diff --git a/arch/arm/src/armv6-m/arm_exception.S b/arch/arm/src/armv6-m/arm_exception.S index 95e5f8c2be007..ed6d7fec521cd 100644 --- a/arch/arm/src/armv6-m/arm_exception.S +++ b/arch/arm/src/armv6-m/arm_exception.S @@ -85,7 +85,8 @@ .syntax unified .type exception_common, function exception_common: - + .cfi_sections .debug_frame + .cfi_startproc /* Complete the context save */ /* Get the current stack pointer. The EXC_RETURN value tells us whether @@ -162,7 +163,11 @@ exception_common: isb sy 3: #endif - + mov fp, r1 + .cfi_def_cfa fp, 0 /* Register in fp, so we just set fp as frame */ + .cfi_offset pc, REG_PC * 4 + .cfi_offset sp, REG_SP * 4 + .cfi_offset lr, REG_LR * 4 bl arm_doirq /* R0=IRQ, R1=register save area on stack */ /* On return from arm_doirq, R0 will hold a pointer to register context @@ -215,7 +220,7 @@ exception_common: */ bx r14 /* And return */ - + .cfi_endproc .size exception_common, .-exception_common /**************************************************************************** diff --git a/arch/arm/src/armv7-a/arm_vectors.S b/arch/arm/src/armv7-a/arm_vectors.S index a64419ac04f9b..1bf4c37228e02 100644 --- a/arch/arm/src/armv7-a/arm_vectors.S +++ b/arch/arm/src/armv7-a/arm_vectors.S @@ -173,6 +173,8 @@ .type arm_vectorirq, %function arm_vectorirq: + .cfi_sections .debug_frame + .cfi_startproc /* Save the LR and SPSR onto the SYS mode stack before switch. */ @@ -234,6 +236,11 @@ arm_vectorirq: #endif bic sp, sp, #7 /* Force 8-byte alignment */ + mov fp, r0 + .cfi_def_cfa fp, 0 /* Register in fp, so we just set fp as frame */ + .cfi_offset pc, REG_PC * 4 + .cfi_offset sp, REG_SP * 4 + .cfi_offset lr, REG_LR * 4 bl arm_decodeirq /* Call the handler */ mov sp, r4 /* Restore the possibly unaligned stack pointer */ @@ -267,6 +274,7 @@ arm_vectorirq: .Lirqstacktop: .word g_intstacktop #endif + .cfi_endproc .size arm_vectorirq, . - arm_vectorirq .align 5 @@ -394,6 +402,8 @@ arm_vectorsvc: .type arm_vectordata, %function arm_vectordata: + .cfi_sections .debug_frame + .cfi_startproc /* Save the LR and SPSR onto the SYS mode stack before switch. */ @@ -437,6 +447,11 @@ arm_vectordata: mrc CP15_DFSR(r2) /* Get r2=DFSR */ mov r4, sp /* Save the SP in a preserved register */ bic sp, sp, #7 /* Force 8-byte alignment */ + mov fp, r0 + .cfi_def_cfa fp, 0 /* Register in fp, so we just set fp as frame */ + .cfi_offset pc, REG_PC * 4 + .cfi_offset sp, REG_SP * 4 + .cfi_offset lr, REG_LR * 4 bl arm_dataabort /* Call the handler */ mov sp, r4 /* Restore the possibly unaligned stack pointer */ @@ -465,6 +480,7 @@ arm_vectordata: /* Restore the CPSR, SYS mode registers and return. */ rfeia r14 + .cfi_endproc .size arm_vectordata, . - arm_vectordata .align 5 @@ -485,6 +501,8 @@ arm_vectordata: .type arm_vectorprefetch, %function arm_vectorprefetch: + .cfi_sections .debug_frame + .cfi_startproc /* Save the LR and SPSR onto the SYS mode stack before switch. */ @@ -522,6 +540,11 @@ arm_vectorprefetch: mrc CP15_IFSR(r2) /* Get r2=IFSR */ mov r4, sp /* Save the SP in a preserved register */ bic sp, sp, #7 /* Force 8-byte alignment */ + mov fp, r0 + .cfi_def_cfa fp, 0 /* Register in fp, so we just set fp as frame */ + .cfi_offset pc, REG_PC * 4 + .cfi_offset sp, REG_SP * 4 + .cfi_offset lr, REG_LR * 4 bl arm_prefetchabort /* Call the handler */ mov sp, r4 /* Restore the possibly unaligned stack pointer */ @@ -550,6 +573,7 @@ arm_vectorprefetch: /* Restore the CPSR, SYS mode registers and return. */ rfeia r14 + .cfi_endproc .size arm_vectorprefetch, . - arm_vectorprefetch .align 5 @@ -568,7 +592,8 @@ arm_vectorprefetch: .type arm_vectorundefinsn, %function arm_vectorundefinsn: - + .cfi_sections .debug_frame + .cfi_startproc /* Save the LR and SPSR onto the SYS mode stack before switch. */ srsdb sp!, #PSR_MODE_SYS @@ -602,6 +627,11 @@ arm_vectorundefinsn: mov r0, sp /* Get r0=xcp */ mov r4, sp /* Save the SP in a preserved register */ bic sp, sp, #7 /* Force 8-byte alignment */ + mov fp, r0 + .cfi_def_cfa fp, 0 /* Register in fp, so we just set fp as frame */ + .cfi_offset pc, REG_PC * 4 + .cfi_offset sp, REG_SP * 4 + .cfi_offset lr, REG_LR * 4 bl arm_undefinedinsn /* Call the handler */ mov sp, r4 /* Restore the possibly unaligned stack pointer */ @@ -630,6 +660,7 @@ arm_vectorundefinsn: /* Restore the CPSR, SYS mode registers and return. */ rfeia r14 + .cfi_endproc .size arm_vectorundefinsn, . - arm_vectorundefinsn .align 5 @@ -650,6 +681,8 @@ arm_vectorundefinsn: .type arm_vectorfiq, %function arm_vectorfiq: + .cfi_sections .debug_frame + .cfi_startproc #if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_HIPRI_INTERRUPT) /* Save the LR and SPSR onto the SYS mode stack before switch. */ @@ -692,6 +725,11 @@ arm_vectorfiq: #endif bic sp, sp, #7 /* Force 8-byte alignment */ + mov fp, r0 + .cfi_def_cfa fp, 0 /* Register in fp, so we just set fp as frame */ + .cfi_offset pc, REG_PC * 4 + .cfi_offset sp, REG_SP * 4 + .cfi_offset lr, REG_LR * 4 bl arm_decodefiq /* Call the handler */ mov sp, r4 /* Restore the possibly unaligned stack pointer */ @@ -731,6 +769,7 @@ arm_vectorfiq: #else subs pc, lr, #4 #endif + .cfi_endproc .size arm_vectorfiq, . - arm_vectorfiq /**************************************************************************** diff --git a/arch/arm/src/armv7-m/arm_exception.S b/arch/arm/src/armv7-m/arm_exception.S index 9da545d0665f0..7afe86a8779cc 100644 --- a/arch/arm/src/armv7-m/arm_exception.S +++ b/arch/arm/src/armv7-m/arm_exception.S @@ -121,7 +121,8 @@ .type exception_common, function #endif exception_common: - + .cfi_sections .debug_frame + .cfi_startproc mrs r0, ipsr /* R0=exception number */ mrs r12, control /* R12=control */ @@ -199,7 +200,11 @@ exception_common: mov sp, r2 /* Instantiate the aligned stack */ 3: #endif - + mov fp, r1 + .cfi_def_cfa r4, 0 /* Register in fp, so we just set fp as frame */ + .cfi_offset pc, REG_PC * 4 + .cfi_offset sp, REG_SP * 4 + .cfi_offset lr, REG_LR * 4 bl arm_doirq /* R0=IRQ, R1=register save (msp) */ /* On return from arm_doirq, R0 will hold a pointer to register context @@ -235,6 +240,7 @@ exception_common: */ bx r14 /* And return */ + .cfi_endproc .size exception_common, .-exception_common diff --git a/arch/arm/src/armv8-m/arm_exception.S b/arch/arm/src/armv8-m/arm_exception.S index b2bc30f876f0c..a24da151915eb 100644 --- a/arch/arm/src/armv8-m/arm_exception.S +++ b/arch/arm/src/armv8-m/arm_exception.S @@ -114,7 +114,8 @@ .thumb_func .type exception_common, function exception_common: - + .cfi_sections .debug_frame + .cfi_startproc mrs r12, control /* R12=control */ /* Complete the context save */ @@ -209,7 +210,11 @@ exception_common: mov sp, r2 /* Instantiate the aligned stack */ 3: #endif - + mov fp, r1 + .cfi_def_cfa fp, 0 /* Register in fp, so we just set fp as frame */ + .cfi_offset pc, REG_PC * 4 + .cfi_offset sp, REG_SP * 4 + .cfi_offset lr, REG_LR * 4 bl arm_doirq /* R0=IRQ, R1=register save (msp) */ /* On return from arm_doirq, R0 will hold a pointer to register context @@ -255,7 +260,7 @@ exception_common: */ bx r14 /* And return */ - + .cfi_endproc .size exception_common, .-exception_common /**************************************************************************** diff --git a/arch/risc-v/src/common/riscv_exception_common.S b/arch/risc-v/src/common/riscv_exception_common.S index b8e99bc32a195..a8326c5eb4686 100644 --- a/arch/risc-v/src/common/riscv_exception_common.S +++ b/arch/risc-v/src/common/riscv_exception_common.S @@ -106,6 +106,8 @@ .align 8 exception_common: + .cfi_sections .debug_frame + .cfi_startproc #ifdef CONFIG_ARCH_KERNEL_STACK /* Take the kernel stack into use */ @@ -200,6 +202,10 @@ handle_irq: mv a0, s2 /* exception cause */ mv a1, sp /* context = sp */ + mv fp, a1 /* Use fp to debug frame */ + .cfi_def_cfa fp, 0 /* Register in fp, so we just set fp as frame */ + .cfi_offset x2, 8 /* Toolchain not support macro, is REG_X2 * 4 */ + .cfi_offset ra, 0 /* Toolchain not support macro, is REG_EPC * 4 */ #if CONFIG_ARCH_INTERRUPTSTACK > 15 @@ -274,6 +280,7 @@ return_from_exception: /* Return from exception */ ERET + .cfi_endproc /**************************************************************************** * Function: riscv_jump_to_user