vc4: Scheduling for register pressure/texture latency in NIR

[anholt]

We have a lot of code in our QIR scheduler, when it's trying to solve a problem that every driver has: Try to reduce register pressure and hide texture latency by moving instructions around at a high level.

Could implement those two things in NIR, and then skip QIR scheduling entirely in favor of just doing QPU scheduling? This would mean a lot less vc4/vc5 compiler code, and could be better at scheduling code than QIR is (since we can't really move our flags updates/condition code usage groups past each other). This would help with #76.