From 5ab40744e15e79a97e50f735ae4d0cbae5835694 Mon Sep 17 00:00:00 2001 From: chao an Date: Mon, 14 Oct 2024 12:27:22 +0800 Subject: [PATCH] arch/armv8-a: new config to set SPIs Configuration to edge-triggered Configure all SPIs(Shared Peripheral Interrupts) as edge-triggered by default Signed-off-by: chao an --- arch/arm64/Kconfig | 10 ++++++++++ arch/arm64/src/common/arm64_gicv3.c | 8 ++++++++ 2 files changed, 18 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 880b42d1bdbaf..6e81f24db5174 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -218,6 +218,16 @@ config ARMV8A_HAVE_GICv3 Selected by the configuration tool if the architecture supports the Generic Interrupt Controller (GIC) +if ARMV8A_HAVE_GICv3 + +config ARMV8A_GIC_SPI_EDGE + bool "Configure all SPIs(Shared Peripheral Interrupts) as edge-triggered by default" + default n + ---help--- + Configure all SPIs(Shared Peripheral Interrupts) as edge-triggered by default. + +endif # ARMV8A_HAVE_GICv3 + config ARCH_CORTEX_A53 bool default n diff --git a/arch/arm64/src/common/arm64_gicv3.c b/arch/arm64/src/common/arm64_gicv3.c index 9a8b77b4c6f45..de56bec9041b8 100644 --- a/arch/arm64/src/common/arm64_gicv3.c +++ b/arch/arm64/src/common/arm64_gicv3.c @@ -607,7 +607,15 @@ static void gicv3_dist_init(void) intid += GIC_NUM_CFG_PER_REG) { idx = intid / GIC_NUM_CFG_PER_REG; +#ifdef CONFIG_ARMV8A_GIC_SPI_EDGE + /* Configure all SPIs as edge-triggered by default */ + + putreg32(0xaaaaaaaa, ICFGR(base, idx)); +#else + /* Configure all SPIs as level-sensitive by default */ + putreg32(0, ICFGR(base, idx)); +#endif } /* TODO: Some arrch64 Cortex-A core maybe without security state