analogdevicesinc · actorreno · Dec 11, 2024 · Dec 12, 2024 · Dec 12, 2024
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+####################################################################################
+## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+include ../scripts/project-toplevel.mk
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+# AD353XR HDL Driver
+
+Here are some pointers to help you:
+  * [Board Product Page] To Be Released
+  * Parts : [ AD353XR Family of Low Power, Buffered Voltage Output, SPI DAC ] To Be Released
+  * Project Doc: https://wiki.analog.com/resources/eval/user-guides/ad353xr
+  * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad353xr
+  * Linux Drivers: To be added after PR and Upstream
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+####################################################################################
+## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+PROJECT_NAME := ad353xR_coraz7s
+
+M_DEPS += ../../scripts/adi_pd.tcl
+M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl
+M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc
+M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl
+M_DEPS += ../../../library/common/ad_iobuf.v
+
+LIB_DEPS += axi_sysid
+LIB_DEPS += sysid_rom
+
+include ../../scripts/project-xilinx.mk
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+###############################################################################
+## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl
+source $ad_hdl_dir/projects/scripts/adi_pd.tcl
+
+#system ID
+ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
+ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
+ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
+
+sysid_gen_sys_init_file 
+
+set sys_dma_clk [get_bd_nets sys_dma_clk]
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+###############################################################################
+## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+# DAC SPI interface
+
+set_property -dict {PACKAGE_PIN H15  IOSTANDARD LVCMOS33} [get_ports spi_sclk]           ; ## ck_sck H15
+set_property -dict {PACKAGE_PIN T12  IOSTANDARD LVCMOS33} [get_ports spi_sdo]            ; ## ck_mosi T12
+set_property -dict {PACKAGE_PIN W15  IOSTANDARD LVCMOS33} [get_ports spi_sdi]            ; ## ck_miso W15
+set_property -dict {PACKAGE_PIN F16  IOSTANDARD LVCMOS33} [get_ports spi_sync_n]         ; ## ck_ss F16
+
+# DAC GPIO interface
+set_property -dict {PACKAGE_PIN V13  IOSTANDARD LVCMOS33} [get_ports dac_reset_n]        ; ## ck_io[1] V13
+set_property -dict {PACKAGE_PIN T14  IOSTANDARD LVCMOS33} [get_ports dac_ldac_n]         ; ## ck_io[2] T14
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+###############################################################################
+## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source ../../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+adi_project ad353xR_coraz7s
+
+adi_project_files ad353xR_coraz7s [list \
+	"$ad_hdl_dir/library/common/ad_iobuf.v" \
+	"system_top.v" \
+	"system_constr.xdc" \
+	"$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc"]
+
+set_property PROCESSING_ORDER LATE [get_files system_constr.xdc]
+
+adi_project_run ad353xR_coraz7s
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+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+  inout   [14:0]  ddr_addr,
+  inout   [ 2:0]  ddr_ba,
+  inout           ddr_cas_n,
+  inout           ddr_ck_n,
+  inout           ddr_ck_p,
+  inout           ddr_cke,
+  inout           ddr_cs_n,
+  inout   [ 3:0]  ddr_dm,
+  inout   [31:0]  ddr_dq,
+  inout   [ 3:0]  ddr_dqs_n,
+  inout   [ 3:0]  ddr_dqs_p,
+  inout           ddr_odt,
+  inout           ddr_ras_n,
+  inout           ddr_reset_n,
+  inout           ddr_we_n,
+
+  inout           fixed_io_ddr_vrn,
+  inout           fixed_io_ddr_vrp,
+  inout   [53:0]  fixed_io_mio,
+  inout           fixed_io_ps_clk,
+  inout           fixed_io_ps_porb,
+  inout           fixed_io_ps_srstb,
+
+  inout   [ 1:0]  btn,
+  inout   [ 5:0]  led,
+
+  inout           iic_ard_scl,
+  inout           iic_ard_sda,
+
+  output          dac_reset_n,
+  output          dac_ldac_n,
+
+  input           spi_sdi,
+  output          spi_sdo,
+  output          spi_sclk,
+  output          spi_sync_n
+);
+
+  // internal signals
+  wire    [63:0]  gpio_i;
+  wire    [63:0]  gpio_o;
+  wire    [63:0]  gpio_t;
+
+  // assignments
+  assign gpio_i[63:32] = gpio_o[63:32];
+  assign gpio_i[31:8] = gpio_o[31:8];
+
+  assign dac_reset_n = gpio_o[33];
+  assign dac_ldac_n = gpio_o[34];
+
+  // instantiations
+  ad_iobuf #(
+    .DATA_WIDTH (2)
+  ) i_iobuf_buttons (
+    .dio_t (gpio_t[1:0]),
+    .dio_i (gpio_o[1:0]),
+    .dio_o (gpio_i[1:0]),
+    .dio_p (btn));
+
+  ad_iobuf #(
+    .DATA_WIDTH (6)
+  ) i_iobuf_leds (
+    .dio_t (gpio_t[7:2]),
+    .dio_i (gpio_o[7:2]),
+    .dio_o (gpio_i[7:2]),
+    .dio_p (led));
+
+  system_wrapper i_system_wrapper (
+    .ddr_addr (ddr_addr),
+    .ddr_ba (ddr_ba),
+    .ddr_cas_n (ddr_cas_n),
+    .ddr_ck_n (ddr_ck_n),
+    .ddr_ck_p (ddr_ck_p),
+    .ddr_cke (ddr_cke),
+    .ddr_cs_n (ddr_cs_n),
+    .ddr_dm (ddr_dm),
+    .ddr_dq (ddr_dq),
+    .ddr_dqs_n (ddr_dqs_n),
+    .ddr_dqs_p (ddr_dqs_p),
+    .ddr_odt (ddr_odt),
+    .ddr_ras_n (ddr_ras_n),
+    .ddr_reset_n (ddr_reset_n),
+    .ddr_we_n (ddr_we_n),
+
+    .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+    .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+    .fixed_io_mio (fixed_io_mio),
+    .fixed_io_ps_clk (fixed_io_ps_clk),
+    .fixed_io_ps_porb (fixed_io_ps_porb),
+    .fixed_io_ps_srstb (fixed_io_ps_srstb),
+
+    .gpio_i (gpio_i),
+    .gpio_o (gpio_o),
+    .gpio_t (gpio_t),
+
+    .spi0_clk_i (1'b0),
+    .spi0_clk_o (spi_sclk),
+    .spi0_csn_0_o (spi_sync_n),
+    .spi0_csn_1_o (),
+    .spi0_csn_2_o (),
+    .spi0_csn_i (1'b1),
+    .spi0_sdi_i (spi_sdi),
+    .spi0_sdo_i (1'b0),
+    .spi0_sdo_o (spi_sdo),
+    .spi1_clk_i (1'b0),
+    .spi1_clk_o (),
+    .spi1_csn_0_o (),
+    .spi1_csn_1_o (),
+    .spi1_csn_2_o (),
+    .spi1_csn_i (1'b1),
+    .spi1_sdi_i (1'b0),
+    .spi1_sdo_i (1'b0),
+    .spi1_sdo_o(),
+    .iic_ard_scl_io (iic_ard_scl),
+    .iic_ard_sda_io (iic_ard_sda));
+
+endmodule
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+####################################################################################
+## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+PROJECT_NAME := ad353xR_de10nano
+
+M_DEPS += ../../scripts/adi_pd.tcl
+M_DEPS += ../../common/de10nano/de10nano_system_qsys.tcl
+M_DEPS += ../../common/de10nano/de10nano_system_assign.tcl
+
+LIB_DEPS += axi_dmac
+LIB_DEPS += axi_hdmi_tx
+LIB_DEPS += axi_sysid
+LIB_DEPS += sysid_rom
+
+include ../../scripts/project-intel.mk
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+###############################################################################
+## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+create_clock -period "20.000 ns" -name sys_clk_50mhz [get_ports {sys_clk}]
+create_clock -period "16.666 ns" -name usb_clk_60mhz [get_ports {usbl_clk}]
+
+derive_pll_clocks
+derive_clock_uncertainty
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+###############################################################################
+## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+set REQUIRED_QUARTUS_VERSION 21.1.0
+set QUARTUS_PRO_ISUSED 0
+source ../../../scripts/adi_env.tcl
+source ../../scripts/adi_project_intel.tcl
+
+adi_project ad353xR_de10nano
+
+source $ad_hdl_dir/projects/common/de10nano/de10nano_system_assign.tcl
+
+# SPI connections
+
+set_location_assignment PIN_AG18 -to spiml_clk      ; ## GPIO1 JP7 [33]
+set_location_assignment PIN_AF18 -to spiml_miso     ; ## GPIO1 JP7 [35]  
+set_location_assignment PIN_AG15 -to spiml_mosi     ; ## GPIO1 JP7 [37]  
+set_location_assignment PIN_AE19 -to spiml_ss0      ; ## GPIO1 JP7 [39]  
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spiml_clk
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spiml_clk_miso
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spiml_clk_mosi
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to spiml_clk_ss0
+
+# GPIO connections
+
+set_location_assignment PIN_AE20 -to dac_reset_n      ; ## GPIO1 JP7 [38]
+set_location_assignment PIN_AE17 -to dac_ldac_n       ; ## GPIO1 JP7 [40]
+
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dac_reset_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to dac_ldac_n
+
+
+
+execute_flow -compile
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+###############################################################################
+## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source $ad_hdl_dir/projects/scripts/adi_pd.tcl
+source $ad_hdl_dir/projects/common/de10nano/de10nano_system_qsys.tcl
+
+#system ID
+set_instance_parameter_value axi_sysid_0 {ROM_ADDR_BITS} {9}
+set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9}
+
+set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "[pwd]/mem_init_sys.txt"
+
+sysid_gen_sys_init_file;
+