diff --git a/cranelift/codegen/src/isa/pulley_shared/lower.isle b/cranelift/codegen/src/isa/pulley_shared/lower.isle
index ea4b4daab670..1ce44d9b6ab8 100644
--- a/cranelift/codegen/src/isa/pulley_shared/lower.isle
+++ b/cranelift/codegen/src/isa/pulley_shared/lower.isle
@@ -644,3 +644,13 @@
 
 (rule (lower (has_type $F32 (sqrt a))) (pulley_fsqrt32 a))
 (rule (lower (has_type $F64 (sqrt a))) (pulley_fsqrt64 a))
+
+;;;; Rules for `fneg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (has_type $F32 (fneg a))) (pulley_fneg32 a))
+(rule (lower (has_type $F64 (fneg a))) (pulley_fneg64 a))
+
+;;;; Rules for `fabs` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+(rule (lower (has_type $F32 (fabs a))) (pulley_fabs32 a))
+(rule (lower (has_type $F64 (fabs a))) (pulley_fabs64 a))
diff --git a/crates/wast-util/src/lib.rs b/crates/wast-util/src/lib.rs
index 7b6f05000ce3..5f986b0dbe84 100644
--- a/crates/wast-util/src/lib.rs
+++ b/crates/wast-util/src/lib.rs
@@ -428,10 +428,6 @@ impl WastTest {
                 "misc_testsuite/winch/_simd_load.wast",
                 "misc_testsuite/winch/_simd_multivalue.wast",
                 "misc_testsuite/winch/_simd_store.wast",
-                "spec_testsuite/f32_bitwise.wast",
-                "spec_testsuite/f64_bitwise.wast",
-                "spec_testsuite/float_exprs.wast",
-                "spec_testsuite/float_misc.wast",
                 "spec_testsuite/proposals/annotations/simd_lane.wast",
                 "spec_testsuite/proposals/multi-memory/simd_memory-multi.wast",
                 "spec_testsuite/proposals/relaxed-simd/i16x8_relaxed_q15mulr_s.wast",
diff --git a/pulley/src/interp.rs b/pulley/src/interp.rs
index eab32042bb7b..4d0f3e11ac8e 100644
--- a/pulley/src/interp.rs
+++ b/pulley/src/interp.rs
@@ -2242,6 +2242,18 @@ impl OpVisitor for Interpreter<'_> {
         ControlFlow::Continue(())
     }
 
+    fn fneg32(&mut self, dst: FReg, src: FReg) -> ControlFlow<Done> {
+        let a = self.state[src].get_f32();
+        self.state[dst].set_f32(-a);
+        ControlFlow::Continue(())
+    }
+
+    fn fabs32(&mut self, dst: FReg, src: FReg) -> ControlFlow<Done> {
+        let a = self.state[src].get_f32();
+        self.state[dst].set_f32(a.wasm_abs());
+        ControlFlow::Continue(())
+    }
+
     fn fadd64(&mut self, operands: BinaryOperands<FReg>) -> ControlFlow<Done> {
         let a = self.state[operands.src1].get_f64();
         let b = self.state[operands.src2].get_f64();
@@ -2313,6 +2325,18 @@ impl OpVisitor for Interpreter<'_> {
         self.state[dst].set_f64(a.wasm_sqrt());
         ControlFlow::Continue(())
     }
+
+    fn fneg64(&mut self, dst: FReg, src: FReg) -> ControlFlow<Done> {
+        let a = self.state[src].get_f64();
+        self.state[dst].set_f64(-a);
+        ControlFlow::Continue(())
+    }
+
+    fn fabs64(&mut self, dst: FReg, src: FReg) -> ControlFlow<Done> {
+        let a = self.state[src].get_f64();
+        self.state[dst].set_f64(a.wasm_abs());
+        ControlFlow::Continue(())
+    }
 }
 
 impl ExtendedOpVisitor for Interpreter<'_> {
diff --git a/pulley/src/lib.rs b/pulley/src/lib.rs
index d692ace51614..7c09fdd82370 100644
--- a/pulley/src/lib.rs
+++ b/pulley/src/lib.rs
@@ -505,6 +505,10 @@ macro_rules! for_each_op {
             fnearest32 = Fnearest32 { dst: FReg, src: FReg };
             /// `low32(dst) = ieee_sqrt(low32(src))`
             fsqrt32 = Fsqrt32 { dst: FReg, src: FReg };
+            /// `low32(dst) = -low32(src)`
+            fneg32 = Fneg32 { dst: FReg, src: FReg };
+            /// `low32(dst) = |low32(src)|`
+            fabs32 = Fabs32 { dst: FReg, src: FReg };
 
             /// `dst = src1 + src2`
             fadd64 = Fadd64 { operands: BinaryOperands<FReg> };
@@ -528,6 +532,10 @@ macro_rules! for_each_op {
             fnearest64 = Fnearest64 { dst: FReg, src: FReg };
             /// `dst = ieee_sqrt(src)`
             fsqrt64 = Fsqrt64 { dst: FReg, src: FReg };
+            /// `dst = -src`
+            fneg64 = Fneg64 { dst: FReg, src: FReg };
+            /// `dst = |src|`
+            fabs64 = Fabs64 { dst: FReg, src: FReg };
         }
     };
 }