.gitmodules

[submodule "Docs/doxygen-awesome-css"]
	path = Docs/doxygen-awesome-css
	url = https://github.com/jothepro/doxygen-awesome-css.git
[submodule "RTL/VexRiscv"]
	path = RTL/ip/VexRiscv
	url = https://github.com/SpinalHDL/VexRiscv
[submodule "ip/verilog-i2c"]
	path = RTL/ip/verilog-i2c
	url = https://github.com/alexforencich/verilog-i2c.git
[submodule "ip/ahb3lite_wb_bridge"]
	path = RTL/ip/ahb3lite_wb_bridge
	url = https://github.com/vfinotti/ahb3lite_wb_bridge.git
[submodule "ip/verilog-axi"]
	path = RTL/ip/verilog-axi
	url = https://github.com/alexforencich/verilog-axi.git
[submodule "ip/wb_intercon"]
	path = RTL/ip/wb_intercon
	url = https://github.com/olofk/wb_intercon.git
[submodule "ip/wb_common"]
	path = RTL/ip/wb_common
	url = https://github.com/fusesoc/wb_common.git
[submodule "ip/cdc_utils"]
	path = RTL/ip/cdc_utils
	url = https://github.com/fusesoc/cdc_utils.git
[submodule "ip/verilog_arbiter"]
	path = RTL/ip/verilog_arbiter
	url = https://github.com/bmartini/verilog-arbiter.git
[submodule "ip/fifo"]
	path = RTL/ip/fifo
	url = https://github.com/olofk/fifo.git
[submodule "ip/wb_ram"]
	path = RTL/ip/wb_ram
	url = https://github.com/fusesoc/wb_ram.git
[submodule "ip/wb2axip"]
	path = RTL/ip/wb2axip
	url = https://github.com/ZipCPU/wb2axip.git
[submodule "RTL/ip/wb_bfm"]
	path = RTL/ip/wb_bfm
	url = https://github.com/olofk/wb_bfm.git
[submodule "RTL/ip/stream_utils"]
	path = RTL/ip/stream_utils
	url = https://github.com/olofk/stream_utils.git