can: m_can: pci: fix iomap_read_fifo() and iomap_write_fifo()

The same fix that was previously done in m_can_platform in commit
99d173f ("can: m_can: fix iomap_read_fifo() and iomap_write_fifo()")
is required in m_can_pci as well to make iomap_read_fifo() and
iomap_write_fifo() work for val_count > 1.

Fixes: 812270e ("can: m_can: Batch FIFO writes during CAN transmit")
Fixes: 1aa6772 ("can: m_can: Batch FIFO reads during CAN receive")
Link: https://lore.kernel.org/all/[email protected]
Cc: [email protected]
Cc: Matt Kline <[email protected]>
Signed-off-by: Matthias Schiffer <[email protected]>
Tested-by: Jarkko Nikula <[email protected]>
Signed-off-by: Marc Kleine-Budde <[email protected]>

drivers/net/can/m_can/m_can_pci.c

@@ -42,8 +42,13 @@ static u32 iomap_read_reg(struct m_can_classdev *cdev, int reg)
 static int iomap_read_fifo(struct m_can_classdev *cdev, int offset, void *val, size_t val_count)
 {
 	struct m_can_pci_priv *priv = cdev_to_priv(cdev);
+	void __iomem *src = priv->base + offset;
 
-	ioread32_rep(priv->base + offset, val, val_count);
+	while (val_count--) {
+		*(unsigned int *)val = ioread32(src);
+		val += 4;
+		src += 4;
+	}
 
 	return 0;
 }
@@ -61,8 +66,13 @@ static int iomap_write_fifo(struct m_can_classdev *cdev, int offset,
 			    const void *val, size_t val_count)
 {
 	struct m_can_pci_priv *priv = cdev_to_priv(cdev);
+	void __iomem *dst = priv->base + offset;
 
-	iowrite32_rep(priv->base + offset, val, val_count);
+	while (val_count--) {
+		iowrite32(*(unsigned int *)val, dst);
+		val += 4;
+		dst += 4;
+	}
 
 	return 0;
 }