diff --git a/qiskit/transpiler/passes/utils/barrier_before_final_measurements.py b/qiskit/transpiler/passes/utils/barrier_before_final_measurements.py
index da70fa6576bd..e510ddc87aeb 100644
--- a/qiskit/transpiler/passes/utils/barrier_before_final_measurements.py
+++ b/qiskit/transpiler/passes/utils/barrier_before_final_measurements.py
@@ -50,10 +50,12 @@ def run(self, dag):
         if not final_ops:
             return dag
 
-        # Create a layer with the barrier and add registers from the original dag.
+        # Create a layer with the barrier and add both bits and registers from the original dag.
         barrier_layer = DAGCircuit()
+        barrier_layer.add_qubits(dag.qubits)
         for qreg in dag.qregs.values():
             barrier_layer.add_qreg(qreg)
+        barrier_layer.add_clbits(dag.clbits)
         for creg in dag.cregs.values():
             barrier_layer.add_creg(creg)
 
diff --git a/releasenotes/notes/fix-barrier-before-final-measurements-loose-1849282c11fc5eb0.yaml b/releasenotes/notes/fix-barrier-before-final-measurements-loose-1849282c11fc5eb0.yaml
new file mode 100644
index 000000000000..354b4a235f45
--- /dev/null
+++ b/releasenotes/notes/fix-barrier-before-final-measurements-loose-1849282c11fc5eb0.yaml
@@ -0,0 +1,7 @@
+---
+fixes:
+  - |
+    Fixed the :class:`.BarrierBeforeFinalMeasurements` transpiler pass when there
+    are conditions on loose :class:`.Clbit`\ s immediately before the final measurement
+    layer.  Previously, this would fail claiming that the bit was not present
+    in an internal temporary circuit.
diff --git a/test/python/transpiler/test_barrier_before_final_measurements.py b/test/python/transpiler/test_barrier_before_final_measurements.py
index 31af21463c98..6edc7b3fa959 100644
--- a/test/python/transpiler/test_barrier_before_final_measurements.py
+++ b/test/python/transpiler/test_barrier_before_final_measurements.py
@@ -15,7 +15,7 @@
 import unittest
 from qiskit.transpiler.passes import BarrierBeforeFinalMeasurements
 from qiskit.converters import circuit_to_dag
-from qiskit import QuantumRegister, QuantumCircuit, ClassicalRegister
+from qiskit.circuit import QuantumRegister, QuantumCircuit, ClassicalRegister, Clbit
 from qiskit.test import QiskitTestCase
 
 
@@ -370,6 +370,28 @@ def test_barrier_doesnt_reorder_gates(self):
 
         self.assertEqual(result, circuit_to_dag(expected))
 
+    def test_conditioned_on_single_bit(self):
+        """Test that the pass can handle cases where there is a loose-bit condition."""
+        circuit = QuantumCircuit(QuantumRegister(3), ClassicalRegister(2), [Clbit()])
+        circuit.h(range(3))
+        circuit.measure(range(3), range(3))
+        circuit.h(0).c_if(circuit.cregs[0], 3)
+        circuit.h(1).c_if(circuit.clbits[-1], True)
+        circuit.h(2).c_if(circuit.clbits[-1], False)
+        circuit.measure(range(3), range(3))
+
+        expected = circuit.copy_empty_like()
+        expected.h(range(3))
+        expected.measure(range(3), range(3))
+        expected.h(0).c_if(expected.cregs[0], 3)
+        expected.h(1).c_if(expected.clbits[-1], True)
+        expected.h(2).c_if(expected.clbits[-1], False)
+        expected.barrier(range(3))
+        expected.measure(range(3), range(3))
+
+        pass_ = BarrierBeforeFinalMeasurements()
+        self.assertEqual(expected, pass_(circuit))
+
 
 if __name__ == "__main__":
     unittest.main()