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AI Engine Debug Walkthrough Tutorial - From Simulation to Hardware

AI Engine Debug with Integrated Logic Analyzer (ILA)

AI Engine Debug with Integrated Logic Analyzer

AI Engine Debug with Integrated Logic Analyzer (ILA)

Adding ChipScope helps debugging AIE PL interfaces in the design running on hardware including checking for AXI protocol violations, hardware kernel issues, data integrity, and performance issues of the design. To debug using ILAs, the design is required to enable ILA in hardware build.

Enable ILA in design

This tutorial uses v++ --debug option to enable ILA IP core insertion to the design. Syntax:

--debug.chipscope <cu_name>[:<interface_name>]

Example:

v++ -g -l --platform ${PLATFORM} ${XOS} ${LIBADF} \
       --debug.chipscope s2mm_v4_1:s0 \
       --debug.chipscope mm2s_v4_1:s0 \
       -t ${TARGET} ${VPP_FLAGS} -o $@

Note: v++ allows multiple --debug.chipscope lines to meet design debug needs.

Step 1. Prepare the ILA enabled Makefile.

Use the provided Makefile.ILA from this tutorial's root directory. Rename Makefile.ILA to Makefile.

cd ${DOWNLOAD_PATH}/AI_Engine_Development/Feature_Tutorials/09-debug-walkthrough
cp Makefile.ILA Makefile

Step 2. Build the ILA enabled design

make clean; make

After the design is built. Inspect the ILA insertion with mm2s_v4_1:s0 and s2mm_v4_1:s0 interfaces.

Step 3. Boot up the design

Flash the SD card with the ILA enabled design, plug in the flashed SD card to VCK190 sd card slot and boot up the board.

Setup the connection with Vivado

Step 4. Setup Connection to the Hardware Board

Step 4.1. Target Connection Setup

Run hardware server from computer that connects to target board. To do so, launch hw_server from the computer that has JTAG connection to the VCK190 board.

Step 4.2. Launch Vivado

Launch Vivado™ from where the to be debugged project is by issue command, vivado.

Step 4.3. Setup Vivado Hardware Manager

After Vivado is up, click on highlighted icon.

Step 4.4. Setup Hardware Target

Step 4.5. Input Hardware Target

Enter hardware server's IP address or hostname to highlighted area and click Next.

Step 4.6. Check Hardware Target

Confirm target's information from JTAG chain then click Next.

Step 4.7. Select probe file

Click the ellipsis (...) to select the generated probe file, ${PROJECT_PATH}/bf_hw.ltx or ${PROJECT_PATH}/_x/link/int/bf_hw.ltx from this design.

Step 4.8. Select ILA to be examined.

Click on hw_ila_1 to examine the design.

Step 4.9. Setup design's signals to be debugged

Click on + to configure the desired signals and their values during run time.

Example below selects TVALID signal from mm2s_v4_1_s0 and vitis_design_s2mm_v4_1_0_so interfaces that capture valid transfers are driven from master. Set value to B (both transition so transitions of valid data signals can be captured.

Step 4.10. Enable ILA to capture the configured signals to debug

Click one of highlighted icons to capture configured signals.

Wait for ILA is ready to capture signals, run the application from vck190 board.

Step 4.11. Expected result

After completing above steps, we are able to see the captured, related AXI signals and data are shown in waveform with timing information from Vivado.

Step 5. Examine captured results

Expand slot_0:mm2s_v4_1_s0:Interface and slot_1:vitis_design_s2mm_v4_1_0_s0:Interface by click on > icon. Review the above captured result. mm2s_v4_1_s0:TVALID shows '1' which indicates a valid data is available at the time marker pointed. Moving time marker across time line, changes of AIX protocol values indicate values changed at what time shown below. For example at clock cycle 4, TVALID is 1 where TDATA is 57f8a5855ea25c52. This is how to determine when and what a valid data is sent/received.

Support

GitHub issues will be used for tracking requests and bugs. For questions go to support.xilinx.com.

License

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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