From 1463a9598ff93d4991419c85939fce331134662d Mon Sep 17 00:00:00 2001
From: Reto Schneider <reto.schneider@husqvarnagroup.com>
Date: Fri, 11 Jun 2021 11:19:51 +0200
Subject: [PATCH 01/11] ramips: mt7628: fix memory controller reset bit
According to MediaTek MT7688 Datasheet v1.4, as well as the MT7628
counterpart, the memory controller reset bit (MC_RST) is 10, not 20.
Reset bit 20 is used for for UART 2 (UART2_RST).
Please note: Due to the lack of hardware, I was not able to test this
change.
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
---
target/linux/ramips/dts/mt7628an.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/linux/ramips/dts/mt7628an.dtsi b/target/linux/ramips/dts/mt7628an.dtsi
index 0dafdc790e1260..02e0c51b3cd17a 100644
--- a/target/linux/ramips/dts/mt7628an.dtsi
+++ b/target/linux/ramips/dts/mt7628an.dtsi
@@ -76,7 +76,7 @@
compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
reg = <0x300 0x100>;
- resets = <&rstctrl 20>;
+ resets = <&rstctrl 10>;
reset-names = "mc";
interrupt-parent = <&intc>;
From 27befb47d9ae938e0d9fa634b202ef74dd4d6bd5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Petr=20=C5=A0tetiar?= <ynezz@true.cz>
Date: Tue, 9 Aug 2022 07:50:19 +0200
Subject: [PATCH 02/11] zlib: backport null dereference fix
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The curl developers found test case that crashed in their testing when
using zlib patched against CVE-2022-37434, same patch we've backported
in commit 7df6795d4c25 ("zlib: backport fix for heap-based buffer
over-read (CVE-2022-37434)"). So we need to backport following patch in
order to fix issue introduced in that previous CVE-2022-37434 fix.
References: https://github.com/curl/curl/issues/9271
Fixes: 7df6795d4c25 ("zlib: backport fix for heap-based buffer over-read (CVE-2022-37434)")
Signed-off-by: Petr Štetiar <ynezz@true.cz>
---
...ll-dereference-in-fix-CVE-2022-37434.patch | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
create mode 100644 package/libs/zlib/patches/007-fix-null-dereference-in-fix-CVE-2022-37434.patch
diff --git a/package/libs/zlib/patches/007-fix-null-dereference-in-fix-CVE-2022-37434.patch b/package/libs/zlib/patches/007-fix-null-dereference-in-fix-CVE-2022-37434.patch
new file mode 100644
index 00000000000000..c5c95a92b28a1d
--- /dev/null
+++ b/package/libs/zlib/patches/007-fix-null-dereference-in-fix-CVE-2022-37434.patch
@@ -0,0 +1,29 @@
+From 1eb7682f845ac9e9bf9ae35bbfb3bad5dacbd91d Mon Sep 17 00:00:00 2001
+From: Mark Adler <fork@madler.net>
+Date: Mon, 8 Aug 2022 10:50:09 -0700
+Subject: [PATCH] Fix extra field processing bug that dereferences NULL
+ state->head.
+
+The recent commit to fix a gzip header extra field processing bug
+introduced the new bug fixed here.
+---
+ inflate.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/inflate.c b/inflate.c
+index 7a7289749..2a3c4fe98 100644
+--- a/inflate.c
++++ b/inflate.c
+@@ -763,10 +763,10 @@ int flush;
+ copy = state->length;
+ if (copy > have) copy = have;
+ if (copy) {
+- len = state->head->extra_len - state->length;
+ if (state->head != Z_NULL &&
+ state->head->extra != Z_NULL &&
+- len < state->head->extra_max) {
++ (len = state->head->extra_len - state->length) <
++ state->head->extra_max) {
+ zmemcpy(state->head->extra + len, next,
+ len + copy > state->head->extra_max ?
+ state->head->extra_max - len : copy);
From 595bf71b390371ed2df689ae455f0a71585a1be6 Mon Sep 17 00:00:00 2001
From: coolsnowwolf <coolsowwolf@gmail.com>
Date: Wed, 10 Aug 2022 04:19:14 +0000
Subject: [PATCH 03/11] rockchip: add FastRhino R66S support in kernel 5.19
---
.../armv8/base-files/etc/board.d/02_network | 2 +
.../dts/rockchip/rk3568-fastrhino-r66s.dts | 531 ++++++++++++++++++
.../devicetree/bindings/rng/rockchip,rng.txt | 45 ++
.../drivers/char/hw_random/rockchip-rng.c | 289 +++++++---
target/linux/rockchip/image/armv8.mk | 11 +
...ip-add-hardware-random-number-genera.patch | 21 +-
.../0900-arm-boot-add-dts-files.patch | 6 +
7 files changed, 837 insertions(+), 68 deletions(-)
create mode 100644 target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts
create mode 100644 target/linux/rockchip/files/Documentation/devicetree/bindings/rng/rockchip,rng.txt
diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network
index 614841e51930cc..bcc5a907c4c6af 100755
--- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network
+++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network
@@ -10,6 +10,7 @@ rockchip_setup_interfaces()
case "$board" in
embedfire,doornet1|\
embedfire,doornet2|\
+ fastrhino,r66s|\
friendlyarm,nanopi-r2c|\
friendlyarm,nanopi-r2s|\
friendlyarm,nanopi-r4s|\
@@ -45,6 +46,7 @@ rockchip_setup_macs()
case "$board" in
embedfire,doornet1|\
embedfire,doornet2|\
+ fastrhino,r66s|\
friendlyarm,nanopi-r2c|\
friendlyarm,nanopi-r2s|\
sharevdi,guangmiao-g4c)
diff --git a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts
new file mode 100644
index 00000000000000..fffdeed7b7f825
--- /dev/null
+++ b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts
@@ -0,0 +1,531 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3568.dtsi"
+
+/ {
+ model = "FastRhino R66S";
+ compatible = "fastrhino,r66s", "rockchip,rk3568";
+
+ aliases {
+ ethernet0 = &rtl8125_1;
+ ethernet1 = &rtl8125_2;
+ led-boot = &power_led;
+ led-failsafe = &power_led;
+ led-running = &power_led;
+ led-upgrade = &power_led;
+ mmc0 = &sdmmc0;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&power_led_pin>;
+
+ power_led: led-power {
+ label = "green:power";
+ gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&reset_button_pin>;
+
+ reset {
+ debounce-interval = <50>;
+ gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ };
+ };
+
+ dc_12v: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc3v3_pcie: gpio-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_pcie";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-name = "vcc5v0_sys";
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_usb_host: vcc5v0-usb-host {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb_host";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc5v0_usb_otg: vcc5v0-usb-otg {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_otg_en>;
+ regulator-name = "vcc5v0_usb_otg";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&combphy0 {
+ status = "okay";
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>;
+ rockchip,system-power-controller;
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ wakeup-source;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <950000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-init-microvolt = <950000>;
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+
+ };
+};
+
+&pcie30phy {
+ data-lanes = <1 2>;
+ status = "okay";
+};
+
+&pcie3x1 {
+ num-lanes = <1>;
+ reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+
+ pcie@10 {
+ reg = <0x00100000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ rtl8125_1: pcie-eth@10,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x000000 0 0 0 0>;
+
+ realtek,led-data = <0x4078>;
+ };
+ };
+};
+
+&pcie3x2 {
+ num-lanes = <1>;
+ reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pcie>;
+ status = "okay";
+
+ pcie@20 {
+ reg = <0x00200000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ rtl8125_2: pcie-eth@20,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x000000 0 0 0 0>;
+
+ realtek,led-data = <0x4078>;
+ };
+ };
+};
+
+&pinctrl {
+ gpio-leds {
+ power_led_pin: power-led-pin {
+ rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic_int {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ rockchip-key {
+ reset_button_pin: reset-button-pin {
+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb {
+ vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&rng {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ max-frequency = <150000000>;
+ no-sdio;
+ no-mmc;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ extcon = <&usb2phy0>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_usb_host>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ phy-supply = <&vcc5v0_usb_otg>;
+ status = "okay";
+};
diff --git a/target/linux/rockchip/files/Documentation/devicetree/bindings/rng/rockchip,rng.txt b/target/linux/rockchip/files/Documentation/devicetree/bindings/rng/rockchip,rng.txt
new file mode 100644
index 00000000000000..d5f41c464fff99
--- /dev/null
+++ b/target/linux/rockchip/files/Documentation/devicetree/bindings/rng/rockchip,rng.txt
@@ -0,0 +1,45 @@
+Rockchip Hardware Random Number Generator
+
+Required properties:
+
+- compatible : should be one of the following.
+ "rockchip,cryptov1-rng" for crypto v1
+ "rockchip,cryptov2-rng" for crypto v2
+ "rockchip,trngv1" for independent trng, such as rk3588.
+- reg : Specifies base physical address and size of the registers map.
+- clocks : Phandle to clock-controller plus clock-specifier pair.
+- clock-names : "clk_crypto", "clk_crypto_apk", "aclk_crypto", "hclk_crypto" as a clock name.
+- assigned-clocks: Main clock, should be <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
+ <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>
+- assigned-clock-rates : The rng core clk frequency, shall be: <150000000>, <150000000>,
+ <200000000>, <100000000>
+- resets : Used for module reset
+- reset-names : Reset names, should be "reset"
+Example:
+
+ rng: rng@100fc000 {
+ compatible = "rockchip,cryptov1-rng";
+ reg = <0x100fc000 0x4000>;
+ clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
+ clock-names = "clk_crypto", "hclk_crypto";
+ assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
+ assigned-clock-rates = <150000000>, <100000000>;
+ resets = <&cru SRST_CRYPTO>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ rng: rng@ff2f0000 {
+ compatible = "rockchip,cryptov2-rng";
+ reg = <0x0 0xff2f0000 0x0 0x4000>;
+ clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
+ <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
+ clock-names = "clk_crypto", "clk_crypto_apk",
+ "aclk_crypto", "hclk_crypto";
+ assigned-clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>,
+ <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>;
+ assigned-clock-rates = <150000000>, <150000000>,
+ <200000000>, <100000000>;
+ resets = <&cru SRST_CRYPTO>;
+ reset-names = "reset";
+ };
diff --git a/target/linux/rockchip/files/drivers/char/hw_random/rockchip-rng.c b/target/linux/rockchip/files/drivers/char/hw_random/rockchip-rng.c
index bdc3578d4de24c..08ad08148d256d 100644
--- a/target/linux/rockchip/files/drivers/char/hw_random/rockchip-rng.c
+++ b/target/linux/rockchip/files/drivers/char/hw_random/rockchip-rng.c
@@ -21,7 +21,7 @@
#define ROCKCHIP_AUTOSUSPEND_DELAY 100
#define ROCKCHIP_POLL_PERIOD_US 100
-#define ROCKCHIP_POLL_TIMEOUT_US 10000
+#define ROCKCHIP_POLL_TIMEOUT_US 50000
#define RK_MAX_RNG_BYTE (32)
/* start of CRYPTO V1 register define */
@@ -37,7 +37,8 @@
/* end of CRYPTO V1 register define */
/* start of CRYPTO V2 register define */
-#define CRYPTO_V2_RNG_CTL 0x0400
+#define CRYPTO_V2_RNG_DEFAULT_OFFSET 0x0400
+#define CRYPTO_V2_RNG_CTL 0x0
#define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00)
#define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01)
#define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02)
@@ -48,13 +49,48 @@
#define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03)
#define CRYPTO_V2_RNG_ENABLE BIT(1)
#define CRYPTO_V2_RNG_START BIT(0)
-#define CRYPTO_V2_RNG_SAMPLE_CNT 0x0404
-#define CRYPTO_V2_RNG_DOUT_0 0x0410
+#define CRYPTO_V2_RNG_SAMPLE_CNT 0x0004
+#define CRYPTO_V2_RNG_DOUT_0 0x0010
/* end of CRYPTO V2 register define */
+/* start of TRNG_V1 register define */
+/* TRNG is no longer subordinate to the Crypto module */
+#define TRNG_V1_CTRL 0x0000
+#define TRNG_V1_CTRL_NOP _SBF(0, 0x00)
+#define TRNG_V1_CTRL_RAND _SBF(0, 0x01)
+#define TRNG_V1_CTRL_SEED _SBF(0, 0x02)
+
+#define TRNG_V1_STAT 0x0004
+#define TRNG_V1_STAT_SEEDED BIT(9)
+#define TRNG_V1_STAT_GENERATING BIT(30)
+#define TRNG_V1_STAT_RESEEDING BIT(31)
+
+#define TRNG_V1_MODE 0x0008
+#define TRNG_V1_MODE_128_BIT _SBF(3, 0x00)
+#define TRNG_V1_MODE_256_BIT _SBF(3, 0x01)
+
+#define TRNG_V1_IE 0x0010
+#define TRNG_V1_IE_GLBL_EN BIT(31)
+#define TRNG_V1_IE_SEED_DONE_EN BIT(1)
+#define TRNG_V1_IE_RAND_RDY_EN BIT(0)
+
+#define TRNG_V1_ISTAT 0x0014
+#define TRNG_V1_ISTAT_RAND_RDY BIT(0)
+
+/* RAND0 ~ RAND7 */
+#define TRNG_V1_RAND0 0x0020
+#define TRNG_V1_RAND7 0x003C
+
+#define TRNG_V1_AUTO_RQSTS 0x0060
+
+#define TRNG_V1_VERSION 0x00F0
+#define TRNG_v1_VERSION_CODE 0x46bc
+/* end of TRNG_V1 register define */
+
struct rk_rng_soc_data {
- const char * const *clks;
- int clks_num;
+ u32 default_offset;
+
+ int (*rk_rng_init)(struct hwrng *rng);
int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait);
};
@@ -63,22 +99,10 @@ struct rk_rng {
struct hwrng rng;
void __iomem *mem;
struct rk_rng_soc_data *soc_data;
- u32 clk_num;
+ int clk_num;
struct clk_bulk_data *clk_bulks;
};
-static const char * const rk_rng_v1_clks[] = {
- "hclk_crypto",
- "clk_crypto",
-};
-
-static const char * const rk_rng_v2_clks[] = {
- "hclk_crypto",
- "aclk_crypto",
- "clk_crypto",
- "clk_crypto_apk",
-};
-
static void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset)
{
__raw_writel(val, rng->mem + offset);
@@ -113,6 +137,38 @@ static void rk_rng_cleanup(struct hwrng *rng)
clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
}
+static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+{
+ int ret;
+ int read_len = 0;
+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
+
+ if (!rk_rng->soc_data->rk_rng_read)
+ return -EFAULT;
+
+ ret = pm_runtime_get_sync(rk_rng->dev);
+ if (ret < 0) {
+ pm_runtime_put_noidle(rk_rng->dev);
+ return ret;
+ }
+
+ ret = 0;
+ while (max > ret) {
+ read_len = rk_rng->soc_data->rk_rng_read(rng, buf + ret,
+ max - ret, wait);
+ if (read_len < 0) {
+ ret = read_len;
+ break;
+ }
+ ret += read_len;
+ }
+
+ pm_runtime_mark_last_busy(rk_rng->dev);
+ pm_runtime_put_sync_autosuspend(rk_rng->dev);
+
+ return ret;
+}
+
static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf,
size_t size)
{
@@ -122,18 +178,12 @@ static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf,
*(u32 *)(buf + i) = be32_to_cpu(rk_rng_readl(rng, offset + i));
}
-static int rk_rng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+static int rk_crypto_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
{
int ret = 0;
u32 reg_ctrl = 0;
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
- ret = pm_runtime_get_sync(rk_rng->dev);
- if (ret < 0) {
- pm_runtime_put_noidle(rk_rng->dev);
- return ret;
- }
-
/* enable osc_ring to get entropy, sample period is set as 100 */
reg_ctrl = CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100);
rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_TRNG_CTRL);
@@ -158,24 +208,15 @@ static int rk_rng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
rk_rng_writel(rk_rng, HIWORD_UPDATE(0, CRYPTO_V1_RNG_START, 0),
CRYPTO_V1_CTRL);
- pm_runtime_mark_last_busy(rk_rng->dev);
- pm_runtime_put_sync_autosuspend(rk_rng->dev);
-
return ret;
}
-static int rk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+static int rk_crypto_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
{
int ret = 0;
u32 reg_ctrl = 0;
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
- ret = pm_runtime_get_sync(rk_rng->dev);
- if (ret < 0) {
- pm_runtime_put_noidle(rk_rng->dev);
- return ret;
- }
-
/* enable osc_ring to get entropy, sample period is set as 100 */
rk_rng_writel(rk_rng, 100, CRYPTO_V2_RNG_SAMPLE_CNT);
@@ -185,7 +226,7 @@ static int rk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
reg_ctrl |= CRYPTO_V2_RNG_START;
rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0),
- CRYPTO_V2_RNG_CTL);
+ CRYPTO_V2_RNG_CTL);
ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V2_RNG_CTL, reg_ctrl,
!(reg_ctrl & CRYPTO_V2_RNG_START),
@@ -202,32 +243,139 @@ static int rk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
/* close TRNG */
rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), CRYPTO_V2_RNG_CTL);
+ return ret;
+}
+
+static int rk_trng_v1_init(struct hwrng *rng)
+{
+ int ret;
+ uint32_t auto_reseed_cnt = 1000;
+ uint32_t reg_ctrl, status, version;
+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
+
+ ret = pm_runtime_get_sync(rk_rng->dev);
+ if (ret < 0) {
+ pm_runtime_put_noidle(rk_rng->dev);
+ return ret;
+ }
+
+ version = rk_rng_readl(rk_rng, TRNG_V1_VERSION);
+ if (version != TRNG_v1_VERSION_CODE) {
+ dev_err(rk_rng->dev,
+ "wrong trng version, expected = %08x, actual = %08x\n",
+ TRNG_V1_VERSION, version);
+ ret = -EFAULT;
+ goto exit;
+ }
+
+ status = rk_rng_readl(rk_rng, TRNG_V1_STAT);
+
+ /* TRNG should wait RAND_RDY triggered if it is busy or not seeded */
+ if (!(status & TRNG_V1_STAT_SEEDED) ||
+ (status & TRNG_V1_STAT_GENERATING) ||
+ (status & TRNG_V1_STAT_RESEEDING)) {
+ uint32_t mask = TRNG_V1_STAT_SEEDED |
+ TRNG_V1_STAT_GENERATING |
+ TRNG_V1_STAT_RESEEDING;
+
+ udelay(10);
+
+ /* wait for GENERATING and RESEEDING flag to clear */
+ readl_poll_timeout(rk_rng->mem + TRNG_V1_STAT, reg_ctrl,
+ (reg_ctrl & mask) == TRNG_V1_STAT_SEEDED,
+ ROCKCHIP_POLL_PERIOD_US,
+ ROCKCHIP_POLL_TIMEOUT_US);
+ }
+
+ /* clear ISTAT flag because trng may auto reseeding when power on */
+ reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
+ rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
+
+ /* auto reseed after (auto_reseed_cnt * 16) byte rand generate */
+ rk_rng_writel(rk_rng, auto_reseed_cnt, TRNG_V1_AUTO_RQSTS);
+
+ ret = 0;
+exit:
pm_runtime_mark_last_busy(rk_rng->dev);
pm_runtime_put_sync_autosuspend(rk_rng->dev);
return ret;
}
-static const struct rk_rng_soc_data rk_rng_v1_soc_data = {
- .clks_num = ARRAY_SIZE(rk_rng_v1_clks),
- .clks = rk_rng_v1_clks,
- .rk_rng_read = rk_rng_v1_read,
+static int rk_trng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
+{
+ int ret = 0;
+ u32 reg_ctrl = 0;
+ struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
+
+ /* clear ISTAT anyway */
+ reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
+ rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
+
+ /* generate 256bit random */
+ rk_rng_writel(rk_rng, TRNG_V1_MODE_256_BIT, TRNG_V1_MODE);
+ rk_rng_writel(rk_rng, TRNG_V1_CTRL_RAND, TRNG_V1_CTRL);
+
+ /*
+ * Generate2 56 bit random data will cost 1024 clock cycles.
+ * Estimated at 150M RNG module frequency, it takes 6.7 microseconds.
+ */
+ udelay(10);
+ reg_ctrl = rk_rng_readl(rk_rng, TRNG_V1_ISTAT);
+ if (!(reg_ctrl & TRNG_V1_ISTAT_RAND_RDY)) {
+ /* wait RAND_RDY triggered */
+ ret = readl_poll_timeout(rk_rng->mem + TRNG_V1_ISTAT, reg_ctrl,
+ (reg_ctrl & TRNG_V1_ISTAT_RAND_RDY),
+ ROCKCHIP_POLL_PERIOD_US,
+ ROCKCHIP_POLL_TIMEOUT_US);
+ if (ret < 0)
+ goto out;
+ }
+
+ ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
+
+ rk_rng_read_regs(rk_rng, TRNG_V1_RAND0, buf, ret);
+
+ /* clear all status flag */
+ rk_rng_writel(rk_rng, reg_ctrl, TRNG_V1_ISTAT);
+out:
+ /* close TRNG */
+ rk_rng_writel(rk_rng, TRNG_V1_CTRL_NOP, TRNG_V1_CTRL);
+
+ return ret;
+}
+
+static const struct rk_rng_soc_data rk_crypto_v1_soc_data = {
+ .default_offset = 0,
+
+ .rk_rng_read = rk_crypto_v1_read,
+};
+
+static const struct rk_rng_soc_data rk_crypto_v2_soc_data = {
+ .default_offset = CRYPTO_V2_RNG_DEFAULT_OFFSET,
+
+ .rk_rng_read = rk_crypto_v2_read,
};
-static const struct rk_rng_soc_data rk_rng_v2_soc_data = {
- .clks_num = ARRAY_SIZE(rk_rng_v2_clks),
- .clks = rk_rng_v2_clks,
- .rk_rng_read = rk_rng_v2_read,
+static const struct rk_rng_soc_data rk_trng_v1_soc_data = {
+ .default_offset = 0,
+
+ .rk_rng_init = rk_trng_v1_init,
+ .rk_rng_read = rk_trng_v1_read,
};
static const struct of_device_id rk_rng_dt_match[] = {
{
.compatible = "rockchip,cryptov1-rng",
- .data = (void *)&rk_rng_v1_soc_data,
+ .data = (void *)&rk_crypto_v1_soc_data,
},
{
.compatible = "rockchip,cryptov2-rng",
- .data = (void *)&rk_rng_v2_soc_data,
+ .data = (void *)&rk_crypto_v2_soc_data,
+ },
+ {
+ .compatible = "rockchip,trngv1",
+ .data = (void *)&rk_trng_v1_soc_data,
},
{ },
};
@@ -236,11 +384,11 @@ MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
static int rk_rng_probe(struct platform_device *pdev)
{
- int i;
int ret;
struct rk_rng *rk_rng;
struct device_node *np = pdev->dev.of_node;
const struct of_device_id *match;
+ resource_size_t map_size;
dev_dbg(&pdev->dev, "probing...\n");
rk_rng = devm_kzalloc(&pdev->dev, sizeof(struct rk_rng), GFP_KERNEL);
@@ -256,33 +404,37 @@ static int rk_rng_probe(struct platform_device *pdev)
rk_rng->rng.init = rk_rng_init;
rk_rng->rng.cleanup = rk_rng_cleanup,
#endif
- rk_rng->rng.read = rk_rng->soc_data->rk_rng_read;
- rk_rng->rng.quality = 1000;
-
- rk_rng->clk_bulks =
- devm_kzalloc(&pdev->dev, sizeof(*rk_rng->clk_bulks) *
- rk_rng->soc_data->clks_num, GFP_KERNEL);
+ rk_rng->rng.read = rk_rng_read;
+ rk_rng->rng.quality = 999;
- rk_rng->clk_num = rk_rng->soc_data->clks_num;
-
- for (i = 0; i < rk_rng->soc_data->clks_num; i++)
- rk_rng->clk_bulks[i].id = rk_rng->soc_data->clks[i];
-
- rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
+ rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, &map_size);
if (IS_ERR(rk_rng->mem))
return PTR_ERR(rk_rng->mem);
- ret = devm_clk_bulk_get(&pdev->dev, rk_rng->clk_num,
- rk_rng->clk_bulks);
- if (ret) {
+ /* compatible with crypto v2 module */
+ /*
+ * With old dtsi configurations, the RNG base was equal to the crypto
+ * base, so both drivers could not be enabled at the same time.
+ * RNG base = CRYPTO base + RNG offset
+ * (Since RK356X, RNG module is no longer belongs to CRYPTO module)
+ *
+ * With new dtsi configurations, CRYPTO regs is divided into two parts
+ * |---cipher---|---rng---|---pka---|, and RNG base is real RNG base.
+ * RNG driver and CRYPTO driver could be enabled at the same time.
+ */
+ if (map_size > rk_rng->soc_data->default_offset)
+ rk_rng->mem += rk_rng->soc_data->default_offset;
+
+ rk_rng->clk_num = devm_clk_bulk_get_all(&pdev->dev, &rk_rng->clk_bulks);
+ if (rk_rng->clk_num < 0) {
dev_err(&pdev->dev, "failed to get clks property\n");
- return ret;
+ return -ENODEV;
}
platform_set_drvdata(pdev, rk_rng);
pm_runtime_set_autosuspend_delay(&pdev->dev,
- ROCKCHIP_AUTOSUSPEND_DELAY);
+ ROCKCHIP_AUTOSUSPEND_DELAY);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_enable(&pdev->dev);
@@ -292,6 +444,10 @@ static int rk_rng_probe(struct platform_device *pdev)
pm_runtime_disable(&pdev->dev);
}
+ /* for some platform need hardware operation when probe */
+ if (rk_rng->soc_data->rk_rng_init)
+ ret = rk_rng->soc_data->rk_rng_init(&rk_rng->rng);
+
return ret;
}
@@ -314,7 +470,7 @@ static int rk_rng_runtime_resume(struct device *dev)
static const struct dev_pm_ops rk_rng_pm_ops = {
SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
- rk_rng_runtime_resume, NULL)
+ rk_rng_runtime_resume, NULL)
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
pm_runtime_force_resume)
};
@@ -337,4 +493,3 @@ module_platform_driver(rk_rng_driver);
MODULE_DESCRIPTION("ROCKCHIP H/W Random Number Generator driver");
MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>");
MODULE_LICENSE("GPL v2");
-
diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk
index 18fed4d2df1420..f7240446640e59 100644
--- a/target/linux/rockchip/image/armv8.mk
+++ b/target/linux/rockchip/image/armv8.mk
@@ -22,6 +22,17 @@ define Device/embedfire_doornet2
endef
TARGET_DEVICES += embedfire_doornet2
+define Device/fastrhino-r66s
+ DEVICE_VENDOR := FastRhino
+ DEVICE_MODEL := R66S
+ SOC := rk3568
+ UBOOT_DEVICE_NAME := fastrhino-r66s-rk3568
+ IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
+ DEVICE_PACKAGES := kmod-r8125
+ SUPPORTED_DEVICES := fastrhino,r66s
+endef
+TARGET_DEVICES += fastrhino-r66s
+
define Device/friendlyarm_nanopi-neo3
DEVICE_VENDOR := FriendlyARM
DEVICE_MODEL := NanoPi NEO3
diff --git a/target/linux/rockchip/patches-5.19/0057-arm64-dts-rockchip-add-hardware-random-number-genera.patch b/target/linux/rockchip/patches-5.19/0057-arm64-dts-rockchip-add-hardware-random-number-genera.patch
index 4e9be328ee462c..5e47bc23e7f8f5 100644
--- a/target/linux/rockchip/patches-5.19/0057-arm64-dts-rockchip-add-hardware-random-number-genera.patch
+++ b/target/linux/rockchip/patches-5.19/0057-arm64-dts-rockchip-add-hardware-random-number-genera.patch
@@ -31,7 +31,7 @@ Signed-off-by: wevsty <ty@wevs.org>
reg = <0x0 0xff100000 0x0 0x1000>;
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-@@ -2042,6 +2042,16 @@
+@@ -1937,6 +1937,16 @@
};
};
@@ -48,3 +48,22 @@ Signed-off-by: wevsty <ty@wevs.org>
gpu: gpu@ff9a0000 {
compatible = "rockchip,rk3399-mali", "arm,mali-t860";
reg = <0x0 0xff9a0000 0x0 0x10000>;
+--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi 2022-08-09 00:09:02.289032224 +0800
++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi 2022-08-09 00:11:01.829992919 +0800
+@@ -89,6 +89,16 @@
+ };
+ };
+
++ rng: rng@fe388000 {
++ compatible = "rockchip,cryptov2-rng";
++ reg = <0x0 0xfe388000 0x0 0x2000>;
++ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
++ clock-names = "clk_trng", "hclk_trng";
++ resets = <&cru SRST_TRNG_NS>;
++ reset-names = "reset";
++ status = "disabled";
++ };
++
+ combphy0: phy@fe820000 {
+ compatible = "rockchip,rk3568-naneng-combphy";
+ reg = <0x0 0xfe820000 0x0 0x100>;
diff --git a/target/linux/rockchip/patches-5.19/0900-arm-boot-add-dts-files.patch b/target/linux/rockchip/patches-5.19/0900-arm-boot-add-dts-files.patch
index 4ccb5cd31afaec..0d20c731b0c07e 100644
--- a/target/linux/rockchip/patches-5.19/0900-arm-boot-add-dts-files.patch
+++ b/target/linux/rockchip/patches-5.19/0900-arm-boot-add-dts-files.patch
@@ -32,3 +32,9 @@
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
+@@ -65,4 +65,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-ro
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
From 34c8edcddc8bbf08b7f79becd74a9d8590a1f876 Mon Sep 17 00:00:00 2001
From: coolsnowwolf <coolsowwolf@gmail.com>
Date: Wed, 10 Aug 2022 04:21:00 +0000
Subject: [PATCH 04/11] rockchip: switch kernel version to 5.19
---
target/linux/rockchip/Makefile | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/linux/rockchip/Makefile b/target/linux/rockchip/Makefile
index 82ac5ef9da12c8..18687abf3c89e8 100644
--- a/target/linux/rockchip/Makefile
+++ b/target/linux/rockchip/Makefile
@@ -7,8 +7,8 @@ BOARDNAME:=Rockchip
FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-part squashfs
SUBTARGETS:=armv8
-KERNEL_PATCHVER=5.15
-KERNEL_TESTING_PATCHVER=5.19
+KERNEL_PATCHVER=5.19
+KERNEL_TESTING_PATCHVER=5.4
define Target/Description
Build firmware image for Rockchip SoC devices.
From 6d08efd7fa786bd14f1c64308aac582a5d110d21 Mon Sep 17 00:00:00 2001
From: breakings <skygmin@gmail.com>
Date: Wed, 10 Aug 2022 13:00:22 +0800
Subject: [PATCH 05/11] armvirt: switch to Kernel 5.10 (#9906)
* armvirt: switch to Kernel 5.10
Armvirt is a development and testing platform and should therefore use
the latest OpenWrt Kernel by default.
Tested via qemu.
Acked-by: Rosen Penev <rosenp@gmail.com>
Acked-by: Yousong Zhou <yszhou4tech@gmail.com>
Signed-off-by: Paul Spooren <mail@aparcar.org>
* armvirt: add 5.15 as testing kernel
Add 5.15 as testing kernel.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Co-authored-by: Paul Spooren <mail@aparcar.org>
Co-authored-by: Aleksander Jan Bajkowski <olek2@wp.pl>
---
target/linux/armvirt/Makefile | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/linux/armvirt/Makefile b/target/linux/armvirt/Makefile
index 6c0d670743f33f..6a2587fb388cfd 100644
--- a/target/linux/armvirt/Makefile
+++ b/target/linux/armvirt/Makefile
@@ -9,8 +9,8 @@ BOARDNAME:=QEMU ARM Virtual Machine
FEATURES:=fpu pci rtc usb
FEATURES+=cpiogz ext4 ramdisk squashfs targz
-KERNEL_PATCHVER:=5.4
-KERNEL_TESTING_PATCHVER:=5.10
+KERNEL_PATCHVER:=5.10
+KERNEL_TESTING_PATCHVER:=5.15
include $(INCLUDE_DIR)/target.mk
From 7d8ea657c6e196ea0a0ff2bfb1e9dcd6e494d382 Mon Sep 17 00:00:00 2001
From: breakings <skygmin@gmail.com>
Date: Wed, 10 Aug 2022 13:00:47 +0800
Subject: [PATCH 06/11] armvirt: enable MMIO_CMDLINE_DEVICES for firecracker
support (#9907)
This Kernel option allows to run OpenWrt witin a `firecracker` micro VM.
Firecracker is a KVM-based tool for superfast booting VMs on x86_64 and
aarch64. It makes rootfs available to the guest as a virtio-mmio device
and passes its address via the kernel cmdline. A kernel without
CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES will not recognize the rootfs
virtio-mmio device.
Suggested-by: Packet Please <pktpls@systemli.org>
Signed-off-by: Paul Spooren <mail@aparcar.org>
Co-authored-by: Paul Spooren <mail@aparcar.org>
---
target/linux/armvirt/config-5.10 | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/linux/armvirt/config-5.10 b/target/linux/armvirt/config-5.10
index 01c201dab1a4c0..9527a9af510ad5 100644
--- a/target/linux/armvirt/config-5.10
+++ b/target/linux/armvirt/config-5.10
@@ -158,6 +158,7 @@ CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_BLK=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
CONFIG_VIRTIO_NET=y
CONFIG_VIRTIO_PCI=y
CONFIG_VIRTIO_PCI_LEGACY=y
From bb83b78e9e8dee0039030115493a69ecf23ff0b1 Mon Sep 17 00:00:00 2001
From: breakings <skygmin@gmail.com>
Date: Wed, 10 Aug 2022 13:01:12 +0800
Subject: [PATCH 07/11] armvirt: refresh 5.10 config (#9908)
This was done by executing these commands:
$ make kernel_oldconfig CONFIG_TARGET=subtarget
$ make kernel_oldconfig CONFIG_TARGET=subtarget_platform
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Co-authored-by: Aleksander Jan Bajkowski <olek2@wp.pl>
---
target/linux/armvirt/64/config-5.10 | 2 +-
target/linux/armvirt/config-5.10 | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/linux/armvirt/64/config-5.10 b/target/linux/armvirt/64/config-5.10
index 51f3c3c95246f2..0a27bab8cf7f32 100644
--- a/target/linux/armvirt/64/config-5.10
+++ b/target/linux/armvirt/64/config-5.10
@@ -41,6 +41,7 @@ CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BLK_PM=y
CONFIG_CAVIUM_TX2_ERRATUM_219=y
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
CONFIG_CLK_SP810=y
CONFIG_CLK_VEXPRESS_OSC=y
# CONFIG_COMPAT_32BIT_TIME is not set
@@ -94,7 +95,6 @@ CONFIG_FRAME_POINTER=y
CONFIG_FSL_ERRATUM_A008585=y
CONFIG_FUJITSU_ERRATUM_010001=y
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_CSUM=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_GENERIC_PLATFORM=y
diff --git a/target/linux/armvirt/config-5.10 b/target/linux/armvirt/config-5.10
index 9527a9af510ad5..85836808ded8cc 100644
--- a/target/linux/armvirt/config-5.10
+++ b/target/linux/armvirt/config-5.10
@@ -57,6 +57,7 @@ CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
From 17fea87fec1352988243e218f19b011e08cf0325 Mon Sep 17 00:00:00 2001
From: breakings <skygmin@gmail.com>
Date: Wed, 10 Aug 2022 13:01:30 +0800
Subject: [PATCH 08/11] armvirt: copy config files from 5.10 (#9910)
* armvirt: copy config files from 5.10
Copy config files from 5.10.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
* armvirt: refresh 5.15 config
This was done by executing these commands:
$ make kernel_oldconfig CONFIG_TARGET=subtarget
$ make kernel_oldconfig CONFIG_TARGET=subtarget_platform
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
* armvirt: move common symbols from subtarget to target config
These new symbols are common for all subtargets and
can be moved into target config.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
Co-authored-by: Aleksander Jan Bajkowski <olek2@wp.pl>
---
target/linux/armvirt/32/config-5.15 | 75 +++++++++++++
target/linux/armvirt/64/config-5.15 | 150 ++++++++++++++++++++++++++
target/linux/armvirt/config-5.15 | 156 ++++++++++++++++++++++++++++
3 files changed, 381 insertions(+)
create mode 100644 target/linux/armvirt/32/config-5.15
create mode 100644 target/linux/armvirt/64/config-5.15
create mode 100644 target/linux/armvirt/config-5.15
diff --git a/target/linux/armvirt/32/config-5.15 b/target/linux/armvirt/32/config-5.15
new file mode 100644
index 00000000000000..d420850ad8a389
--- /dev/null
+++ b/target/linux/armvirt/32/config-5.15
@@ -0,0 +1,75 @@
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_VIRT=y
+CONFIG_ARM=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_ARM_HEAVY_MB=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_LPAE=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_PSCI=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_CACHE_L2X0=y
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DMA_OPS=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HAVE_SMP=y
+CONFIG_HZ_FIXED=0
+CONFIG_HZ_PERIODIC=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_NEON=y
+CONFIG_NR_CPUS=4
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USE_OF=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
diff --git a/target/linux/armvirt/64/config-5.15 b/target/linux/armvirt/64/config-5.15
new file mode 100644
index 00000000000000..5818dcaf704b29
--- /dev/null
+++ b/target/linux/armvirt/64/config-5.15
@@ -0,0 +1,150 @@
+CONFIG_64BIT=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_VEXPRESS=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_ARM64=y
+CONFIG_ARM64_4K_PAGES=y
+CONFIG_ARM64_CNP=y
+CONFIG_ARM64_CRYPTO=y
+CONFIG_ARM64_EPAN=y
+CONFIG_ARM64_ERRATUM_1165522=y
+CONFIG_ARM64_ERRATUM_1286807=y
+CONFIG_ARM64_ERRATUM_819472=y
+CONFIG_ARM64_ERRATUM_824069=y
+CONFIG_ARM64_ERRATUM_826319=y
+CONFIG_ARM64_ERRATUM_827319=y
+CONFIG_ARM64_ERRATUM_832075=y
+CONFIG_ARM64_ERRATUM_843419=y
+CONFIG_ARM64_HW_AFDBM=y
+CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
+CONFIG_ARM64_MODULE_PLTS=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_PAN=y
+CONFIG_ARM64_PA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_PTR_AUTH=y
+CONFIG_ARM64_PTR_AUTH_KERNEL=y
+CONFIG_ARM64_SVE=y
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_ARM64_VA_BITS=39
+CONFIG_ARM64_VA_BITS_39=y
+CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
+CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
+CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
+CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
+CONFIG_ATOMIC64_SELFTEST=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BLK_PM=y
+CONFIG_CAVIUM_TX2_ERRATUM_219=y
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_CLK_SP810=y
+CONFIG_CLK_VEXPRESS_OSC=y
+# CONFIG_COMPAT_32BIT_TIME is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_PM=y
+CONFIG_CRYPTO_AES_ARM64=y
+CONFIG_CRYPTO_AES_ARM64_BS=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
+CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
+CONFIG_CRYPTO_CHACHA20=y
+CONFIG_CRYPTO_CHACHA20_NEON=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA1_ARM64_CE=y
+CONFIG_CRYPTO_SHA256_ARM64=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_SHA512_ARM64=y
+CONFIG_CRYPTO_SIMD=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DRM=y
+CONFIG_DRM_BOCHS=y
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_GEM_SHMEM_HELPER=y
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_QXL=y
+CONFIG_DRM_TTM=y
+CONFIG_DRM_TTM_HELPER=y
+CONFIG_DRM_VIRTIO_GPU=y
+CONFIG_DRM_VRAM_HELPER=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FRAME_POINTER=y
+CONFIG_FSL_ERRATUM_A008585=y
+CONFIG_FUJITSU_ERRATUM_010001=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_FIND_FIRST_BIT=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_HDMI=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=y
+CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_KCMP=y
+CONFIG_LCD_CLASS_DEVICE=m
+# CONFIG_LCD_PLATFORM is not set
+CONFIG_MFD_CORE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MFD_VEXPRESS_SYSREG=y
+CONFIG_MMC=y
+CONFIG_MMC_ARMMMCI=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=64
+CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_VEXPRESS=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_SMC91X=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_VEXPRESS_CONFIG=y
+CONFIG_VIDEOMODE_HELPERS=y
+CONFIG_VIRTIO_DMA_SHARED_BUFFER=y
+CONFIG_VMAP_STACK=y
+CONFIG_ZONE_DMA32=y
diff --git a/target/linux/armvirt/config-5.15 b/target/linux/armvirt/config-5.15
new file mode 100644
index 00000000000000..667efdf70b4a35
--- /dev/null
+++ b/target/linux/armvirt/config-5.15
@@ -0,0 +1,156 @@
+CONFIG_9P_FS=y
+# CONFIG_9P_FS_POSIX_ACL is not set
+# CONFIG_9P_FS_SECURITY is not set
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_V2M=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_GIC_V3_ITS_PCI=y
+CONFIG_ARM_PSCI_FW=y
+CONFIG_BALLOON_COMPACTION=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_MQ_VIRTIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_CPU_RMAP=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_REMAP=y
+CONFIG_DTC=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EXT4_FS=y
+CONFIG_F2FS_FS=y
+CONFIG_FAILOVER=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_PL061=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HVC_DRIVER=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY_BALLOON=y
+CONFIG_MIGRATION=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NET_9P=y
+# CONFIG_NET_9P_DEBUG is not set
+CONFIG_NET_9P_VIRTIO=y
+CONFIG_NET_FAILOVER=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NLS=y
+CONFIG_NVMEM=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_PADATA=y
+CONFIG_PAGE_REPORTING=y
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_ECAM=y
+CONFIG_PCI_HOST_COMMON=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_RATIONAL=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PL031=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SCSI_VIRTIO=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SRCU=y
+CONFIG_SWIOTLB=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_USB_SUPPORT=y
+CONFIG_VIRTIO=y
+CONFIG_VIRTIO_BALLOON=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
+CONFIG_VIRTIO_NET=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_PCI_LEGACY=y
+CONFIG_VIRTIO_PCI_LIB=y
+CONFIG_XPS=y
From 0edc2efdb01cedb112d591f697e0e0422645b269 Mon Sep 17 00:00:00 2001
From: breakings <skygmin@gmail.com>
Date: Wed, 10 Aug 2022 13:32:15 +0800
Subject: [PATCH 09/11] kernel: modules: fix kmod-mdio-devres dependency for
5.15 (#9911)
Fix:
Package kmod-mdio-devres is missing dependencies for the following libraries:
of_mdio.ko
Package kmod-of-mdio is missing dependencies for the following libraries:
fwnode_mdio.ko
Co-authored-by: breakings <breakingstop@gmail.com>
---
package/kernel/linux/modules/netdevices.mk | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/package/kernel/linux/modules/netdevices.mk b/package/kernel/linux/modules/netdevices.mk
index b86ec9c9b97ff2..4299a193ba8c50 100644
--- a/package/kernel/linux/modules/netdevices.mk
+++ b/package/kernel/linux/modules/netdevices.mk
@@ -1027,8 +1027,8 @@ define KernelPackage/of-mdio
KCONFIG:=CONFIG_OF_MDIO
FILES:= \
$(LINUX_DIR)/drivers/net/phy/fixed_phy.ko \
- $(LINUX_DIR)/drivers/of/of_mdio.ko@lt5.10 \
- $(LINUX_DIR)/drivers/net/mdio/of_mdio.ko@ge5.10
+ $(LINUX_DIR)/drivers/net/mdio/of_mdio.ko \
+ $(LINUX_DIR)/drivers/net/mdio/fwnode_mdio.ko@ge5.15
AUTOLOAD:=$(call AutoLoad,41,of_mdio)
endef
From ab90f4fe97b104de934c2cb8051b1c41a83cc8d2 Mon Sep 17 00:00:00 2001
From: breakings <skygmin@gmail.com>
Date: Wed, 10 Aug 2022 15:33:08 +0800
Subject: [PATCH 10/11] kernel: mdio-devres: fix of-mdio dependency (#9912)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
armvirt/64 when compiled with ALL_KMODS=y reports following:
Package kmod-mdio-devres is missing dependencies for the following libraries:
of_mdio.ko
Signed-off-by: Petr Štetiar <ynezz@true.cz>
---
package/kernel/linux/modules/netdevices.mk | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/package/kernel/linux/modules/netdevices.mk b/package/kernel/linux/modules/netdevices.mk
index 4299a193ba8c50..8bba6c63cc1561 100644
--- a/package/kernel/linux/modules/netdevices.mk
+++ b/package/kernel/linux/modules/netdevices.mk
@@ -142,7 +142,7 @@ $(eval $(call KernelPackage,mii))
define KernelPackage/mdio-devres
SUBMENU:=$(NETWORK_DEVICES_MENU)
TITLE:=Supports MDIO device registration
- DEPENDS:=@(LINUX_5_10||LINUX_5_15||LINUX_5_18||LINUX_5_19) +kmod-libphy PACKAGE_kmod-of-mdio:kmod-of-mdio
+ DEPENDS:=@(LINUX_5_10||LINUX_5_15||LINUX_5_18||LINUX_5_19) +kmod-libphy +(TARGET_armvirt||TARGET_bcm27xx_bcm2708||TARGET_tegra):kmod-of-mdio
KCONFIG:=CONFIG_MDIO_DEVRES
HIDDEN:=1
FILES:=$(LINUX_DIR)/drivers/net/phy/mdio_devres.ko
From 114bd4f3322b04bef574c73fe9281c3c5119efc7 Mon Sep 17 00:00:00 2001
From: coolsnowwolf <coolsowwolf@gmail.com>
Date: Wed, 10 Aug 2022 09:40:11 +0000
Subject: [PATCH 11/11] uboot-rockchip: add fastrhino r66s support
---
package/boot/uboot-rockchip/Makefile | 12 +++
...016-uboot-add-FastRhino-R66S-support.patch | 92 ++++++++++++++++++
.../patches/900-arm-boot-add-dts-files.patch | 3 +-
.../configs/fastrhino-r66s-rk3568_defconfig | 97 +++++++++++++++++++
...568-fastrhino-r66s.dts => rk3568-r66s.dts} | 0
target/linux/rockchip/image/armv8.mk | 5 +-
.../0900-arm-boot-add-dts-files.patch | 2 +-
7 files changed, 206 insertions(+), 5 deletions(-)
create mode 100644 package/boot/uboot-rockchip/patches/016-uboot-add-FastRhino-R66S-support.patch
create mode 100644 package/boot/uboot-rockchip/src/configs/fastrhino-r66s-rk3568_defconfig
rename target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/{rk3568-fastrhino-r66s.dts => rk3568-r66s.dts} (100%)
diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile
index fba287827db007..56daf22c526d62 100644
--- a/package/boot/uboot-rockchip/Makefile
+++ b/package/boot/uboot-rockchip/Makefile
@@ -126,6 +126,17 @@ define U-Boot/nanopi-r4se-rk3399
USE_RKBIN:=1
endef
+define U-Boot/fastrhino-r66s-rk3568
+ BUILD_SUBTARGET:=armv8
+ NAME:=FastRhin-R66S
+ BUILD_DEVICES:= \
+ fastrhino_r66s
+ DEPENDS:=+PACKAGE_u-boot-fastrhino-r66s-rk3568:arm-trusted-firmware-rk3568
+ PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor
+ ATF:=rk3568_bl31_v1.34.elf
+ DDR:=rk3568_ddr_1560MHz_v1.13.bin
+endef
+
define U-Boot/nanopi-r5s-rk3568
BUILD_SUBTARGET:=armv8
NAME:=NANOPI-R5S
@@ -159,6 +170,7 @@ endef
UBOOT_TARGETS := \
doornet2-rk3399 \
+ fastrhino-r66s-rk3568 \
guangmiao-g4c-rk3399 \
nanopi-r4s-rk3399 \
nanopi-r4se-rk3399 \
diff --git a/package/boot/uboot-rockchip/patches/016-uboot-add-FastRhino-R66S-support.patch b/package/boot/uboot-rockchip/patches/016-uboot-add-FastRhino-R66S-support.patch
new file mode 100644
index 00000000000000..4e489f0a8f6f2a
--- /dev/null
+++ b/package/boot/uboot-rockchip/patches/016-uboot-add-FastRhino-R66S-support.patch
@@ -0,0 +1,92 @@
+--- /dev/null
++++ b/arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi
+@@ -0,0 +1,25 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
++ */
++
++#include "rk3568-u-boot.dtsi"
++
++/ {
++ chosen {
++ stdout-path = &uart2;
++ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc0;
++ };
++};
++
++&sdmmc0 {
++ bus-width = <4>;
++ u-boot,dm-spl;
++ u-boot,spl-fifo-mode;
++};
++
++&uart2 {
++ clock-frequency = <24000000>;
++ u-boot,dm-spl;
++ status = "okay";
++};
+--- /dev/null
++++ b/arch/arm/dts/rk3568-fastrhino-r66s.dts
+@@ -0,0 +1,9 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++#include "rk3568-evb.dts"
++
++/ {
++ model = "FastRhino R66S";
++ compatible = "fastrhino,r66s", "rockchip,rk3568";
++};
+--- /dev/null
++++ b/board/fastrhino/fastrhino-r66s-rk3568/Kconfig
+@@ -0,0 +1,15 @@
++if TARGET_FASTRHINO_R66S_RK3568
++
++config SYS_BOARD
++ default "fastrhino-r66s-rk3568"
++
++config SYS_VENDOR
++ default "fastrhino"
++
++config SYS_CONFIG_NAME
++ default "fastrhino-r66s-rk3568"
++
++config BOARD_SPECIFIC_OPTIONS # dummy
++ def_bool y
++
++endif
+--- /dev/null
++++ b/board/fastrhino/fastrhino-r66s-rk3568/Makefile
+@@ -0,0 +1,4 @@
++# SPDX-License-Identifier: GPL-2.0+
++#
++
++obj-y += fastrhino-r66s-rk3568.o
+--- /dev/null
++++ b/board/fastrhino/fastrhino-r66s-rk3568/fastrhino-r66s-rk3568.c
+@@ -0,0 +1,4 @@
++ // SPDX-License-Identifier: GPL-2.0+
++/*
++ *
++ */
+--- /dev/null
++++ b/include/configs/fastrhino-r66s-rk3568.h
+@@ -0,0 +1,17 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++
++#ifndef __FASTRHINO_R66S_RK3568_H
++#define __FASTRHINO_R66S_RK3568_H
++
++#include <configs/rk3568_common.h>
++
++#define CONFIG_SUPPORT_EMMC_RPMB
++
++#define ROCKCHIP_DEVICE_SETTINGS \
++ "stdout=serial,vidconsole\0" \
++ "stderr=serial,vidconsole\0"
++
++#define CONFIG_USB_OHCI_NEW
++#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
++
++#endif
diff --git a/package/boot/uboot-rockchip/patches/900-arm-boot-add-dts-files.patch b/package/boot/uboot-rockchip/patches/900-arm-boot-add-dts-files.patch
index 0c80d91316837e..c24ffd30a043e6 100644
--- a/package/boot/uboot-rockchip/patches/900-arm-boot-add-dts-files.patch
+++ b/package/boot/uboot-rockchip/patches/900-arm-boot-add-dts-files.patch
@@ -1,10 +1,11 @@
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
-@@ -157,6 +157,7 @@
+@@ -157,6 +157,8 @@
rk3399-nanopi-m4b.dtb \
rk3399-nanopi-neo4.dtb \
rk3399-nanopi-r4s.dtb \
+ rk3399-nanopi-r4se.dtb \
++ rk3568-fastrhino-r66s.dtb \
rk3399-orangepi.dtb \
rk3399-pinebook-pro.dtb \
rk3399-puma-haikou.dtb \
diff --git a/package/boot/uboot-rockchip/src/configs/fastrhino-r66s-rk3568_defconfig b/package/boot/uboot-rockchip/src/configs/fastrhino-r66s-rk3568_defconfig
new file mode 100644
index 00000000000000..87e73cdc87e142
--- /dev/null
+++ b/package/boot/uboot-rockchip/src/configs/fastrhino-r66s-rk3568_defconfig
@@ -0,0 +1,97 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00a00000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-fastrhino-r66s"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_FASTRHINO_R66S_RK3568=y
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_API=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-fastrhino-r66s.dtb"
+# CONFIG_SYS_DEVICE_NULLDEV is not set
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM_WARN=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_GPIO_V2=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_SPL_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ROCKCHIP_USB2_PHY=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_LAN75XX=y
+CONFIG_USB_ETHER_LAN78XX=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_ERRNO_STR=y
diff --git a/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts b/target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-r66s.dts
similarity index 100%
rename from target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts
rename to target/linux/rockchip/files-5.19/arch/arm64/boot/dts/rockchip/rk3568-r66s.dts
diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk
index f7240446640e59..348e9d73e6b5f9 100644
--- a/target/linux/rockchip/image/armv8.mk
+++ b/target/linux/rockchip/image/armv8.mk
@@ -22,16 +22,15 @@ define Device/embedfire_doornet2
endef
TARGET_DEVICES += embedfire_doornet2
-define Device/fastrhino-r66s
+define Device/fastrhino_r66s
DEVICE_VENDOR := FastRhino
DEVICE_MODEL := R66S
SOC := rk3568
UBOOT_DEVICE_NAME := fastrhino-r66s-rk3568
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
DEVICE_PACKAGES := kmod-r8125
- SUPPORTED_DEVICES := fastrhino,r66s
endef
-TARGET_DEVICES += fastrhino-r66s
+TARGET_DEVICES += fastrhino_r66s
define Device/friendlyarm_nanopi-neo3
DEVICE_VENDOR := FriendlyARM
diff --git a/target/linux/rockchip/patches-5.19/0900-arm-boot-add-dts-files.patch b/target/linux/rockchip/patches-5.19/0900-arm-boot-add-dts-files.patch
index 0d20c731b0c07e..5b0c265a78f6c4 100644
--- a/target/linux/rockchip/patches-5.19/0900-arm-boot-add-dts-files.patch
+++ b/target/linux/rockchip/patches-5.19/0900-arm-boot-add-dts-files.patch
@@ -36,5 +36,5 @@
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-r66s.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb