# Makefile for producing .json from verilog .v incrementally via yosys
# Author Peter Breuer (ptb@ieee.org) 2023
#  following instructions from N. EngelHardt
# (see https://github.com/YosysHQ/yosys/discussions/3602)
# embedded as comments 1-13 below.

# This work is licensed under the Creative Commons Attribution 4.0
# International License. To view a copy of this license, visit
# http://creativecommons.org/licenses/by/4.0/.

# run make in dir with all .v files (with TOP=Foo if not guessed right below)

ALL_V                = $(shell ls *.v)
ALL_PRE_CHECK_IL     = $(patsubst %.v,%.pre-check-il,$(ALL_V))
ALL_POST_IOPADMAP_IL = $(patsubst %.v,%.post-iopadmap-il,$(ALL_V))
ALL_PRE_IOPADMAP_IL  = $(patsubst %.v,%.pre-iopadmap-il,$(ALL_V))
ALL_RAW_IL           = $(patsubst %.v,%.raw-il,$(ALL_V))
ALL_MOD              = $(patsubst %.v,%,$(ALL_V))
# override TOP on command line with TOP=Foo
TOP                  = $(shell basename `pwd` | cut -d. -f 2)

all: top
top: $(TOP).json

.SUFFIXES:
.SUFFIXES: .v .pre-check-il .post-iopadmap-il .pre-iopadmap-il .raw-il .json

# -------------- #
#  RTLIL is the best format for saving intermediate state ...
#   1 load the entire design from verilog, preferably with -defer to
#   avoid having a unused derived module with the default parameter
#   values (read_verilog -defer [A-Z].v Top.v)
#   2 run hierarchy -top Top
#   3 using write_rtlil, dump each module to a separate .il file
#   4 also using write_rtlil, dump the entire design

define run-yosys-1to4 =
  yosys -p \
  "read_verilog -defer $(ALL_V) ; \
   hierarchy -top $(TOP) ; \
   $(foreach mod,$(ALL_MOD),select $(mod) ; write_rtlil -selected $(mod).raw-il ;) ; \
   select * ; \
   write_rtlil all.raw-il ; \
  "
endef

.PHONY: ALL_RAW_IL
ALL_RAW_IL : $(ALL_RAW_IL)
all.raw-il $(ALL_RAW_IL) &: $(ALL_V)
	$(run-yosys-1to4)

# -------------- #
#   5 in separate yosys processes, load an individual module from .il
#   and load blackboxes for all other modules in the design with
#   read_rtlil -nooverwrite -lib (in case any of the non-top modules A-Z
#   have submodules)
#   6 run synth_xilinx -run prepare:map_cells to synthesize the
#   individual module up to the iopadmap call
#   7 use write_rtlil to write out the synthesized-up-to-iopadmap module

define run-yosys-5to7 =
  yosys -p \
  "read_rtlil $(patsubst %.pre-iopadmap-il,%.raw-il,$@); read_rtlil -nooverwrite -lib $(ALL_RAW_IL) ; \
   synth_xilinx -run prepare:map_cells ; \
   select $(@:.pre-iopadmap-il=) ; \
   write_rtlil -selected $@ ; \
  "
endef

.PHONY: ALL_PRE_IOPADMAP_IL
ALL_PRE_IOPADMAP_IL : $(ALL_PRE_IOPADMAP_IL)
$(ALL_PRE_IOPADMAP_IL) : $(ALL_RAW_IL)
	$(run-yosys-5to7)

# -------------- #
#   8 in one common yosys process, load all the
#   synthesized-up-to-iopadmap modules and run the iopadmap step
#     (with run synth_xilinx -run map_cells: )
#   9 dump out each post-iopadmap module to individual .il files again

define run-yosys-8to9 =
  yosys -p \
  "read_rtlil $(ALL_PRE_IOPADMAP_IL) ; \
   read_verilog -lib -specify +/xilinx/cells_sim.v +/xilinx/cells_xtra.v ; \
   iopadmap -bits -outpad OBUF I:O \
                  -inpad IBUF O:I  \
                  -toutpad OBUFT ~T:I:O \
                  -tinoutpad IOBUF ~T:O:I:IO \
                  A:top ; \
   $(foreach mod,$(ALL_MOD), select $(mod) ; write_rtlil -selected $(mod).post-iopadmap-il ; ) \
  "
endef

.PHONY: ALL_POST_IOPADMAP_IL
ALL_POST_IOPADMAP_IL: $(ALL_POST_IOPADMAP_IL)
$(ALL_POST_IOPADMAP_IL) &: $(ALL_PRE_IOPADMAP_IL)
	$(run-yosys-8to9)

# -------------- #
#   10 in separate yosys processes, load the individual modules and the
#   blackboxes again and continue the synth_xilinx run (first run the
#   last 2 steps of map_cells, then synth_xilinx -run map_ffs:check)
#   11 write out the synthesized module to .il again

define run-yosys-10to11 =
  yosys -p \
  "read_rtlil $(patsubst %.pre-check-il,%.post-iopadmap-il,$@) ; \
   read_rtlil -nooverwrite -lib $(filter-out $(patsubst %.pre-check-il,%.post-iopadmap-il,$@),$^) ; \
   read_verilog -lib -specify +/xilinx/cells_sim.v +/xilinx/cells_xtra.v ; \
   techmap -map +/techmap.v -map +/xilinx/cells_map.v ; \
   clean ; \
   synth_xilinx -run map_ffs:check ; \
   write_rtlil $@ ; \
  "
endef

.PHONY: ALL_PRE_CHECK_IL
ALL_PRE_CHECK_IL: $(ALL_PRE_CHECK_IL)
$(ALL_PRE_CHECK_IL) : $(ALL_POST_IOPADMAP_IL)
	$(run-yosys-10to11)

# -------------- #
#   12 in a common yosys process, load all the synthesized modules again
#   13 run the final steps synth_xilinx -run check:

define run-yosys-12to13 =
  yosys -p \
  "read_rtlil $< ; \
   read_rtlil -nooverwrite  $(filter-out $<,$^) ; \
   read_verilog -lib -specify +/xilinx/cells_sim.v +/xilinx/cells_xtra.v ; \
   techmap -map +/techmap.v -map +/xilinx/cells_map.v ; \
   synth_xilinx $(ifeq $(filter $@,$(TOP).json),-top $(TOP)) -run check: ; \
   write_json $@ ; \
  "
endef

%.json : %.pre-check-il $(ALL_PRE_CHECK_IL)
	$(run-yosys-12to13)

# -------------- #
# cleanups

.PHONY: tidy clean veryclean
# remove intermediates
tidy: 
	rm -f $(ALL_PRE_CHECK_IL) \
	      $(ALL_POST_IOPADMAP_IL) \
	      $(ALL_PRE_IOPADMAP_IL) \
	      $(ALL_RAW_IL) 

# remove intermediates and result
clean: tidy
	rm -f $(TOP).json all.json

# get rid of everything except starting .v, hopefully
veryclean: clean
	rm -f *.pre-check-il *.post-iopadmap-il *.pre-iopadmap-il \
        *.raw-il *.json