Synthesizing Ring Oscillator

[tornupnegatives]

I am trying to synthesize a ring oscillator design in OpenFPGA, but I cannot seem to get it passing through the yosys flow.

Benchmark RTL

The benchmark itself is not particularly interesting. Just a chain of inverters.

`timescale 1ns/1ps

module ring_oscillator#(
                        parameter NO_STAGES=3,
                        )(
                            input wire en,
                            output wire clk_out
                        );    
    
    wire [NO_STAGES:0] wi;
    assign wi[0] = en ? wi[NO_STAGES] : 0;
    assign clk_out = en ? wi[NO_STAGES] : 0;
    genvar i;
    generate
        for(i = 0; i < NO_STAGES; i = i+1) begin
            if(i==0) begin
                    not (wi[i+1], wi[0]);
            end
            else if(i>= NO_STAGES) begin
                    not (wi[i+1], wi[i]); 
            end
            else begin
                    not (wi[i+1], wi[i]); 
            end
        end
    endgenerate    
endmodule 

Yosys Output

I run the benchmark through yosys using the following script:

# Yosys synthesis script for ring_oscillator, which allows logic loops
# Read verilog files
read_verilog  ./benchmark/ring_oscillator.v

# Technology mapping
hierarchy -top ring_oscillator
proc
techmap -D NO_LUT -map +/adff2dff.v

# Synthesis
flatten
opt_expr
opt_clean
check
opt -nodffe -nosdff
fsm
opt -nodffe -nosdff
wreduce
peepopt
opt_clean
opt -nodffe -nosdff
memory -nomap
opt_clean
opt -fast -full -nodffe -nosdff
memory_map
opt -full -nodffe -nosdff
techmap
opt -fast -nodffe -nosdff
clean

# LUT mapping
abc -lut 4

# Check
synth -run check

# Clean and output blif
opt_clean -purge
write_blif ring_oscillator_yosys_out.blif

And it fails the CHECK command because of the oscillations, which are of course intentional.

8. Executing CHECK pass (checking for obvious problems).
Checking module ring_oscillator...
Warning: found logic loop in module ring_oscillator:
    cell $not$./benchmark/ring_oscillator.v:0$7 ($not)
    cell $ternary$./benchmark/ring_oscillator.v:13$2 ($mux)
    wire \wi [2]
    wire \wi [3]
Found and reported 1 problems.

Granted, yosys does not throw an error. Interestingly, if I disable the checks entirely, it still never makes it to the yosys re-write stage.

Please advise.

[nakengelhardt]

What do you mean by "passing"? The above script gives me a valid blif file as far as I can tell. Is your problem is that it optimizes any chain of inverters to be either one or zero not operations? There is not really a way to avoid that beyond instantiating directly the target primitives so that they cannot be optimized.