Add big-endian support #172
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Signed-off-by: Marcus Comstedt <[email protected]>
Between draft-20181101-ebe1ca4 and draft-20190622-6993896 of the RISC-V Instruction Set Manual, the wording was changed from requiring "natural endianness" of instruction parcels to require them to be little endian. Update the big endian instruction pipe to reflect the newer requirement. Signed-off-by: Marcus Comstedt <[email protected]>
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I updated the code to follow the latest version of the RISC-V specification which calls for fully little-endian instruction encoding on big-endian RISC-V. Updated toolchains are here: |
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This PR adds an option to picorv32 to build it in big endian mode.
The instruction stream format mandated by UCB for big endian systems can be enabled with a separate option. If this option is not enabled, an instruction stream generated for LE can be used (but note that sub-word rodata, such as string literals, will not be correct) in lieu of a big endian tool chain.
Tested on iCE40 HX8K hardware, including compressed instruction streams in the big endian format.