transmitter-trace.vcd

$version Generated by VerilatedVcd $end
$timescale 1ps $end
 $scope module TOP $end
  $var wire 1 & i_clk $end
  $var wire 1 ' i_tx_start $end
  $var wire 8 ( i_data [7:0] $end
  $var wire 1 ) busy $end
  $var wire 1 * o_data $end
  $scope module transmitter $end
   $var wire 1 & i_clk $end
   $var wire 1 ' i_tx_start $end
   $var wire 8 ( i_data [7:0] $end
   $var wire 1 ) busy $end
   $var wire 1 * o_data $end
   $var wire 1 # continue_tx $end
   $var wire 10 $ s_data [9:0] $end
   $var wire 4 % bit_counter [3:0] $end
  $upscope $end
 $upscope $end
$enddefinitions $end


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