From ef63c61c948af1a42813a43e8e47acdc060d756a Mon Sep 17 00:00:00 2001 From: Xinlong <821408745@qq.com> Date: Mon, 25 Dec 2023 19:40:05 +0800 Subject: [PATCH] make pc point to EXC_BRANCH inst --- src/mono/mono/mini/cpu-riscv64.mdesc | 10 +++++----- src/mono/mono/mini/exceptions-riscv.c | 2 +- src/mono/mono/mini/mini-riscv.c | 19 ++++++++++--------- 3 files changed, 16 insertions(+), 15 deletions(-) diff --git a/src/mono/mono/mini/cpu-riscv64.mdesc b/src/mono/mono/mini/cpu-riscv64.mdesc index dadd203646e6c..5efee20667ef5 100644 --- a/src/mono/mono/mini/cpu-riscv64.mdesc +++ b/src/mono/mono/mini/cpu-riscv64.mdesc @@ -235,11 +235,11 @@ riscv_bge: src1:i src2:i len:8 riscv_bgeu: src1:i src2:i len:8 riscv_blt: src1:i src2:i len:8 riscv_bltu: src1:i src2:i len:8 -riscv_exc_beq: src1:i src2:i len:12 -riscv_exc_bne: src1:i src2:i len:12 -riscv_exc_bgeu: src1:i src2:i len:12 -riscv_exc_blt: src1:i src2:i len:12 -riscv_exc_bltu: src1:i src2:i len:12 +riscv_exc_beq: src1:i src2:i len:16 +riscv_exc_bne: src1:i src2:i len:16 +riscv_exc_bgeu: src1:i src2:i len:16 +riscv_exc_blt: src1:i src2:i len:16 +riscv_exc_bltu: src1:i src2:i len:16 riscv_slt: dest:i src1:i src2:i len:4 riscv_sltu: dest:i src1:i src2:i len:4 riscv_slti: dest:i src1:i len:4 diff --git a/src/mono/mono/mini/exceptions-riscv.c b/src/mono/mono/mini/exceptions-riscv.c index d9a888dd89860..40f65789fb556 100644 --- a/src/mono/mono/mini/exceptions-riscv.c +++ b/src/mono/mono/mini/exceptions-riscv.c @@ -83,7 +83,7 @@ mono_riscv_throw_exception (gpointer arg, host_mgreg_t pc, host_mgreg_t *int_reg } /* Adjust pc so it points into the call instruction */ - pc -= 4; + pc--; /* Initialize a ctx based on the arguments */ memset (&ctx, 0, sizeof (MonoContext)); diff --git a/src/mono/mono/mini/mini-riscv.c b/src/mono/mono/mini/mini-riscv.c index 5676e4e434370..5f714db9d7176 100644 --- a/src/mono/mono/mini/mini-riscv.c +++ b/src/mono/mono/mini/mini-riscv.c @@ -3662,9 +3662,9 @@ mono_riscv_emit_load_regarray (guint8 *code, guint64 regs, int basereg, int offs g_assert (basereg != RISCV_SP); if (!RISCV_VALID_S_IMM (offset)) { - code = mono_riscv_emit_imm (code, RISCV_T6, offset); - riscv_add (code, RISCV_T6, basereg, RISCV_T6); - basereg = RISCV_T6; + code = mono_riscv_emit_imm (code, RISCV_T0, offset); + riscv_add (code, RISCV_T0, basereg, RISCV_T0); + basereg = RISCV_T0; offset = 0; } @@ -3694,9 +3694,9 @@ mono_riscv_emit_store_regarray (guint8 *code, guint64 regs, int basereg, int off g_assert (basereg != RISCV_SP); if (!RISCV_VALID_S_IMM (offset)) { - code = mono_riscv_emit_imm (code, RISCV_T6, offset); - riscv_add (code, RISCV_T6, basereg, RISCV_T6); - basereg = RISCV_T6; + code = mono_riscv_emit_imm (code, RISCV_T0, offset); + riscv_add (code, RISCV_T0, basereg, RISCV_T0); + basereg = RISCV_T0; offset = 0; } @@ -3725,9 +3725,9 @@ mono_riscv_emit_load_stack (guint8 *code, guint64 regs, int basereg, int offset, g_assert (basereg != RISCV_SP); if (!RISCV_VALID_S_IMM (offset)) { - code = mono_riscv_emit_imm (code, RISCV_T6, offset); - riscv_add (code, RISCV_T6, basereg, RISCV_T6); - basereg = RISCV_T6; + code = mono_riscv_emit_imm (code, RISCV_T0, offset); + riscv_add (code, RISCV_T0, basereg, RISCV_T0); + basereg = RISCV_T0; offset = 0; } @@ -3994,6 +3994,7 @@ static guint8 * mono_riscv_emit_branch_exc (MonoCompile *cfg, guint8 *code, int opcode, int sreg1, int sreg2, const char *exc_name) { riscv_auipc (code, MONO_ARCH_EXC_ADDR_REG, 0); + riscv_addi (code, MONO_ARCH_EXC_ADDR_REG, MONO_ARCH_EXC_ADDR_REG,8); switch (opcode) { case OP_RISCV_EXC_BEQ: riscv_bne (code, sreg1, sreg2, 8);