This documents provides an overview of the cmac kernel.
The cmac kernel is an RTL free running kernel which encapsulates the UltraScale+ Integrated 100G Ethernet Subsystem. The kernel uses ap_ctrl_none as hardware control protocol.
This kernel is configured according to the INTERFACE, DEVICE, and PADDING_MODE arguments passed to make. It exposes two 512-bit AXI4-Stream interfaces (S_AXIS and M_AXIS) to the user logic, which run at the same frequency as the kernel, internally it has CDC (clock domain crossing) logic to convert from kernel clock to the 100G Ethernet Subsystem clock. It also provides and AXI4-Lite interface to check the UltraScale+ Integrated 100G Ethernet Subsystem register map.
The 100G Ethernet Subsystem offers an integrated 100 Gigabit per second (Gbps) Ethernet Media Access Controller (MAC), Physical Coding Sublayer (PCS), IEEE 802.3bj Reed-Solomon Forward Error Correction (RS-FEC), and 100GE Auto-Negotiation/Link Training (AN/LT) IP to enable solutions such as KR4, CR4, SR4, CWDM4, PSM4, or ER4f for high performance applications.
Note: Auto-Negotiation/Link Training is not enabled in this kernel.
This IP implements the Core Bring Up Sequence described in the PG203
This IP implements optional frame padding to 60 or 64 bytes. The padding mode is set at compile-time by the PADDING_MODE parameter as follows: mode 0 indicates no padding, mode 1 (default) pads to 60 bytes, and mode 2 pads to 64 bytes.
The Rx and Tx AXI4-Stream interfaces in the UltraScale+ Integrated 100G Ethernet Subsystem operate at 322.265625 MHz. To accommodate for a different frequency in the rest of the design cross domain crossing is included in the Tx path (acc_kernel_tx_cdc and fifo_cmac_tx) and Rx path (fifo_cmac_rx_cdc).
The UltraScale+ Integrated 100G Ethernet Subsystem register map (described in the PG203) is accessible via the AXI4-Lite interface. Many of these registers have been conveniently mapped into the kernel arguments using the template.xml file. If you wish to access a register that is not mapped, you can use the pynq MMIO read and write methods.
For instance:
# Read CONFIGURATION_AN_ABILITY register
cmac.read(0xA8)
# Set ctl_an_ability_1000base_kx in the CONFIGURATION_AN_ABILITY register
cmac.write(0xA8, 0x1)You could also modify the template.xml file to add more registers. Care must be taken when modifying this file, make sure id are properly changed. Once the template.xml file is modified, you will have to rebuild the design for these changes to be included in the xclbin. Remove all *.xo files in this folder after changing template.xml.
| Name | Description |
|---|---|
| ap_clk | Primary clock |
| ap_rst_n | Primary active-Low reset |
| clk_gt_freerun | Free running kernel |
| gt_ref_clk | GT reference clock |
| gt_serial_port | GT serial lanes |
| S_AXILITE | AXI4-Lite subordinate control interface |
| S_AXIS | 512-bit AXI4-Stream Tx interface |
| M_AXIS | 512-bit AXI4-Stream Rx interface |
To target multiple 100 GbE interfaces and Alveo cards a slightly different kernels are generated, the internal structure and interfaces are the same. However, the UltraScale+ Integrated 100G Ethernet Subsystem configuration changes to accommodate each interface and Alveo card. These configurations are cover here.
To generate the an xclbin file that uses the UltraScale+ Integrated 100G Ethernet Subsystem you need a valid license. You can generate a free of charge license following these steps
Note: To enable Auto-Negotiation/Link Training you would need a separate license. Check the documentation for more information.
RS-FEC is enabled by default in the CMAC instance. At runtime RS-FEC is deactivated by default and can be activated by calling the corresponding functions in the Pynq and C++ drivers. When active, the RS-FEC is set to sub-mode 1 (both correction and indication active). Please refer to the UltraScale+ Integrated 100G Ethernet Subsystem documentation for more details.
Note: When active, RS-FEC increases latency.
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