-
Notifications
You must be signed in to change notification settings - Fork 642
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
XVDPU-TRD C64B5 timeout on VCK190-ES #670
Comments
Since this configuration uses more AIE cores than any other, I got suspicious of the ES AIE workaround script. In the script below I tried to modify the outer for loop to run to 49 instead of 39, and now the benchmark runs fine. Vitis-AI/dsa/XVDPU-TRD/README.md Lines 317 to 325 in fc74d40
Please let me know if this is actually a good fix. |
Hi @ksstms |
Great! Thanks! |
|
I've modified the XVDPU-TRD to target the VCK190-ES board, and removed the HDMI and MIPI stuff from the design.
Everything works fine, except for the C64-B5 DPU configuration.
I get setup violations inside the DPU. Unfortunately I don't know how I could provide more info about it, as the path endpoints are
<hidden>
. On the schematic I can see that most of the paths are around URAM instances, and some of them are coming from a NOC AXI port. The clock isclkout1_primitive_1
which is the 150 MHz clock connected tos_axi_aclk
of the DPU.Every other configuration works with the original 150 MHz clock. PG389 page 30 recommends using 100 MHz for
s_axi_aclk
, so I modified that in the Makefile:Now the timing is okay, but when I try to benchmark it, I get the following error:
This is the same error that I got in issue #576. Is the ES AIE workaround script wrong for this configuration?
The text was updated successfully, but these errors were encountered: