From f5f4c29ed4ba3084b72e75528306a48ab9f8968c Mon Sep 17 00:00:00 2001 From: Lukas Lichtl Date: Wed, 12 May 2021 14:51:13 +0200 Subject: [PATCH] add missing initial values on outgoing ports --- vunit/vhdl/verification_components/src/ram_master.vhd | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/vunit/vhdl/verification_components/src/ram_master.vhd b/vunit/vhdl/verification_components/src/ram_master.vhd index 90f942b69..cf544703b 100644 --- a/vunit/vhdl/verification_components/src/ram_master.vhd +++ b/vunit/vhdl/verification_components/src/ram_master.vhd @@ -22,9 +22,9 @@ entity ram_master is port ( clk : in std_logic; en : out std_logic := '0'; - we : out std_logic_vector(byte_enable_length(bus_handle)-1 downto 0); - addr : out std_logic_vector(address_length(bus_handle)-1 downto 0); - wdata : out std_logic_vector(data_length(bus_handle)-1 downto 0); + we : out std_logic_vector(byte_enable_length(bus_handle)-1 downto 0) := (others => '0'); + addr : out std_logic_vector(address_length(bus_handle)-1 downto 0) := (others => '0'); + wdata : out std_logic_vector(data_length(bus_handle)-1 downto 0) := (others => '0'); rdata : in std_logic_vector(data_length(bus_handle)-1 downto 0) ); end entity;