From 6108eb81359a30d13428f0b55c5030539712b7f9 Mon Sep 17 00:00:00 2001
From: TharrmashasthaPV <tharmasasthapv@gmail.com>
Date: Tue, 13 Jul 2021 10:37:13 +0530
Subject: [PATCH] Corrected tests compression and refactored for #6370

---
 qiskit/visualization/text.py                  |  4 +--
 .../visualization/test_circuit_text_drawer.py | 26 +++++++++++--------
 2 files changed, 17 insertions(+), 13 deletions(-)

diff --git a/qiskit/visualization/text.py b/qiskit/visualization/text.py
index 1e2960114c99..c362ec857035 100644
--- a/qiskit/visualization/text.py
+++ b/qiskit/visualization/text.py
@@ -1390,8 +1390,8 @@ def set_cl_multibox(self, creg, val, top_connect="┴"):
         else:
             if isinstance(creg, Clbit):
                 clbit = [creg]
-                label_bool = "= T" if val is True else "= F"
-                self._set_multibox(label_bool, clbits=clbit, top_connect=top_connect)
+                cond_bin = "1" if val is True else "0"
+                self.set_cond_bullets(cond_bin, clbit)
             else:
                 clbit = [
                     bit for bit in self.clbits if self._clbit_locations[bit]["register"] == creg
diff --git a/test/python/visualization/test_circuit_text_drawer.py b/test/python/visualization/test_circuit_text_drawer.py
index 7ed59e47ff48..44e9dac357a2 100644
--- a/test/python/visualization/test_circuit_text_drawer.py
+++ b/test/python/visualization/test_circuit_text_drawer.py
@@ -2920,15 +2920,15 @@ def test_text_bit_conditional(self):
 
         expected = "\n".join(
             [
-                "          ┌───┐        ",
-                "qr_0: |0>─┤ H ├────────",
-                "          └─╥─┘  ┌───┐ ",
-                "qr_1: |0>───╫────┤ H ├─",
-                "         ┌──╨──┐ └─╥─┘ ",
-                " cr_0: 0 ╡ = T ╞═══╬═══",
-                "         └─────┘┌──╨──┐",
-                " cr_1: 0 ═══════╡ = F ╞",
-                "                └─────┘",
+                "         ┌───┐     ",
+                "qr_0: |0>┤ H ├─────",
+                "         └─╥─┘┌───┐",
+                "qr_1: |0>──╫──┤ H ├",
+                "           ║  └─╥─┘",
+                " cr_0: 0 ══■════╬══",
+                "           =1   ║  ",
+                " cr_1: 0 ═══════o══",
+                "                =0 ",
             ]
         )
 
@@ -2949,13 +2949,17 @@ def test_text_bit_conditional_cregbundle(self):
                 "qr_0: |0>───┤ H ├────────────────",
                 "            └─╥─┘       ┌───┐    ",
                 "qr_1: |0>─────╫─────────┤ H ├────",
-                "         ┌────╨─────┐┌──┴─╨─┴───┐",
+                "              ║         └─╥─┘    ",
+                "         ┌────╨─────┐┌────╨─────┐",
                 " cr: 0 2/╡ cr_0 = T ╞╡ cr_1 = F ╞",
                 "         └──────────┘└──────────┘",
             ]
         )
 
-        self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=True)), expected)
+        self.assertEqual(
+            str(_text_circuit_drawer(circuit, cregbundle=True, vertical_compression="medium")),
+            expected,
+        )
 
     def test_text_conditional_reverse_bits_1(self):
         """Classical condition on 2q2c circuit with cregbundle=False and reverse bits"""