From a07eb88b98fb9afc4d34a555fb541cd7f111003f Mon Sep 17 00:00:00 2001 From: Franco Nieddu Date: Wed, 20 Dec 2023 16:28:11 +0100 Subject: [PATCH] added activation tests --- justfile | 2 +- .../components/fixedpoint/log.hpp | 92 ++++++++++++++++++ .../mlir-assigner/parser/evaluator.hpp | 5 + .../Erf/ErfSimple.json | 1 + .../Erf/ErfSimple.mlir} | 4 +- .../Erf/ErfSimple.onnx | 13 +++ .../NeedsBlueprintComponent/Erf/ErfSimple.res | 3 + .../tests/Ops/Onnx/And/AndSimple.mlir | 16 --- .../tests/Ops/Onnx/Div/DivSimple.mlir | 16 --- .../Onnx/HardSigmoid/HardSigmoidSimple.json | 1 + .../Onnx/HardSigmoid/HardSigmoidSimple.onnx | Bin 0 -> 138 bytes .../Onnx/HardSigmoid/HardSigmoidSimple.res | 3 + .../Ops/Onnx/LeakyRelu/LeakyReluSimple.json | 1 + .../Ops/Onnx/LeakyRelu/LeakyReluSimple.onnx | 15 +++ .../Ops/Onnx/LeakyRelu/LeakyReluSimple.res | 3 + .../Onnx/LogSoftmax/LogSoftmaxBasicMnist.json | 1 + .../Onnx/LogSoftmax/LogSoftmaxBasicMnist.onnx | 15 +++ .../Onnx/LogSoftmax/LogSoftmaxBasicMnist.res | 3 + .../tests/Ops/Onnx/PRelu/PReluConst.json | 1 + .../tests/Ops/Onnx/PRelu/PReluConst.onnx | 16 +++ .../tests/Ops/Onnx/PRelu/PReluConst.res | 3 + .../tests/Ops/Onnx/PRelu/PReluSimple.json | 1 + .../tests/Ops/Onnx/PRelu/PReluSimple.onnx | 19 ++++ .../tests/Ops/Onnx/PRelu/PReluSimple.res | 3 + .../tests/Ops/Onnx/Selu/SeluSimple.json | 1 + .../tests/Ops/Onnx/Selu/SeluSimple.onnx | 16 +++ .../tests/Ops/Onnx/Selu/SeluSimple.res | 3 + .../tests/Ops/Onnx/Sigmoid/SigmoidSimple.json | 1 + .../tests/Ops/Onnx/Sigmoid/SigmoidSimple.onnx | 13 +++ .../tests/Ops/Onnx/Sigmoid/SigmoidSimple.res | 3 + .../Ops/Onnx/Softplus/SoftplusBasicMnist.json | 1 + .../Ops/Onnx/Softplus/SoftplusBasicMnist.onnx | 13 +++ .../Ops/Onnx/Softplus/SoftplusBasicMnist.res | 3 + .../Ops/Onnx/Softsign/SoftsignBasicMnist.json | 1 + .../Ops/Onnx/Softsign/SoftsignBasicMnist.onnx | 13 +++ .../Ops/Onnx/Softsign/SoftsignBasicMnist.res | 3 + mlir-assigner/tests/run.py | 8 +- 37 files changed, 277 insertions(+), 39 deletions(-) create mode 100644 mlir-assigner/include/mlir-assigner/components/fixedpoint/log.hpp create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Erf/ErfSimple.json rename mlir-assigner/tests/Ops/{Onnx/Acosh/AcoshSimple.mlir => NeedsBlueprintComponent/Erf/ErfSimple.mlir} (87%) create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Erf/ErfSimple.onnx create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Erf/ErfSimple.res delete mode 100644 mlir-assigner/tests/Ops/Onnx/And/AndSimple.mlir delete mode 100644 mlir-assigner/tests/Ops/Onnx/Div/DivSimple.mlir create mode 100644 mlir-assigner/tests/Ops/Onnx/HardSigmoid/HardSigmoidSimple.json create mode 100644 mlir-assigner/tests/Ops/Onnx/HardSigmoid/HardSigmoidSimple.onnx create mode 100644 mlir-assigner/tests/Ops/Onnx/HardSigmoid/HardSigmoidSimple.res create mode 100644 mlir-assigner/tests/Ops/Onnx/LeakyRelu/LeakyReluSimple.json create mode 100644 mlir-assigner/tests/Ops/Onnx/LeakyRelu/LeakyReluSimple.onnx create mode 100644 mlir-assigner/tests/Ops/Onnx/LeakyRelu/LeakyReluSimple.res create mode 100644 mlir-assigner/tests/Ops/Onnx/LogSoftmax/LogSoftmaxBasicMnist.json create mode 100644 mlir-assigner/tests/Ops/Onnx/LogSoftmax/LogSoftmaxBasicMnist.onnx create mode 100644 mlir-assigner/tests/Ops/Onnx/LogSoftmax/LogSoftmaxBasicMnist.res create mode 100644 mlir-assigner/tests/Ops/Onnx/PRelu/PReluConst.json create mode 100644 mlir-assigner/tests/Ops/Onnx/PRelu/PReluConst.onnx create mode 100644 mlir-assigner/tests/Ops/Onnx/PRelu/PReluConst.res create mode 100644 mlir-assigner/tests/Ops/Onnx/PRelu/PReluSimple.json create mode 100644 mlir-assigner/tests/Ops/Onnx/PRelu/PReluSimple.onnx create mode 100644 mlir-assigner/tests/Ops/Onnx/PRelu/PReluSimple.res create mode 100644 mlir-assigner/tests/Ops/Onnx/Selu/SeluSimple.json create mode 100644 mlir-assigner/tests/Ops/Onnx/Selu/SeluSimple.onnx create mode 100644 mlir-assigner/tests/Ops/Onnx/Selu/SeluSimple.res create mode 100644 mlir-assigner/tests/Ops/Onnx/Sigmoid/SigmoidSimple.json create mode 100644 mlir-assigner/tests/Ops/Onnx/Sigmoid/SigmoidSimple.onnx create mode 100644 mlir-assigner/tests/Ops/Onnx/Sigmoid/SigmoidSimple.res create mode 100644 mlir-assigner/tests/Ops/Onnx/Softplus/SoftplusBasicMnist.json create mode 100644 mlir-assigner/tests/Ops/Onnx/Softplus/SoftplusBasicMnist.onnx create mode 100644 mlir-assigner/tests/Ops/Onnx/Softplus/SoftplusBasicMnist.res create mode 100644 mlir-assigner/tests/Ops/Onnx/Softsign/SoftsignBasicMnist.json create mode 100644 mlir-assigner/tests/Ops/Onnx/Softsign/SoftsignBasicMnist.onnx create mode 100644 mlir-assigner/tests/Ops/Onnx/Softsign/SoftsignBasicMnist.res diff --git a/justfile b/justfile index 079a59c..07d6a23 100644 --- a/justfile +++ b/justfile @@ -1,6 +1,6 @@ # build the mlir-assigner build: - make -C build/ -j 12 + make -C build/ -j 12 zkml-onnx-compiler mlir-assigner # setsup the build folder setup-build: diff --git a/mlir-assigner/include/mlir-assigner/components/fixedpoint/log.hpp b/mlir-assigner/include/mlir-assigner/components/fixedpoint/log.hpp new file mode 100644 index 0000000..33f4d9e --- /dev/null +++ b/mlir-assigner/include/mlir-assigner/components/fixedpoint/log.hpp @@ -0,0 +1,92 @@ +#ifndef CRYPTO3_ASSIGNER_FIXEDPOINT_LOG_HPP +#define CRYPTO3_ASSIGNER_FIXEDPOINT_LOG_HPP + +#include + +#include + +#include +#include +#include +#include // TODO: check if there is a new mechanism for this in nil upstream + +#include +#include +#include + +namespace nil { + namespace blueprint { + namespace detail { + + template + typename components::fix_log< + crypto3::zk::snark::plonk_constraint_system, + BlueprintFieldType, basic_non_native_policy>::result_type + handle_fixedpoint_log_component( + crypto3::zk::snark::plonk_variable + x, + circuit_proxy< + crypto3::zk::snark::plonk_constraint_system> &bp, + assignment_proxy> &assignment, + std::uint32_t start_row) { + + using var = crypto3::zk::snark::plonk_variable; + + using component_type = components::fix_log< + crypto3::zk::snark::plonk_constraint_system, + BlueprintFieldType, basic_non_native_policy>; + const auto p = PolicyManager::get_parameters( + ManifestReader::get_witness(0, 1, 1)); + component_type component_instance( + p.witness, + ManifestReader::get_constants(), + ManifestReader::get_public_inputs(), + 1, 1); + + if constexpr (nil::blueprint::use_custom_lookup_tables()) { + auto lookup_tables = component_instance.component_custom_lookup_tables(); + for (auto &t : lookup_tables) { + bp.register_lookup_table( + std::shared_ptr>(t)); + } + }; + + if constexpr (nil::blueprint::use_lookups()) { + auto lookup_tables = component_instance.component_lookup_tables(); + for (auto &[k, v] : lookup_tables) { + bp.reserve_table(k); + } + }; + + // TACEO_TODO in the previous line I hardcoded 1 for now!!! CHANGE THAT + // TACEO_TODO make an assert that both have the same scale? + // TACEO_TODO we probably have to extract the field element from the type here + + components::generate_circuit(component_instance, bp, assignment, {x}, start_row); + return components::generate_assignments(component_instance, assignment, {x}, start_row); + } + + } // namespace detail + template + void handle_fixedpoint_log_component( + mlir::math::LogOp &operation, + stack_frame> &frame, + circuit_proxy> &bp, + assignment_proxy> + &assignment, + std::uint32_t start_row) { + auto operand = frame.locals.find(mlir::hash_value(operation.getOperand())); + ASSERT(operand != frame.locals.end()); + + auto x = operand->second; + + // TACEO_TODO: check types + + auto result = detail::handle_fixedpoint_log_component(x, bp, assignment, start_row); + frame.locals[mlir::hash_value(operation.getResult())] = result.output; + } + } // namespace blueprint +} // namespace nil + +#endif // CRYPTO3_ASSIGNER_FIXEDPOINT_LOG_HPP diff --git a/mlir-assigner/include/mlir-assigner/parser/evaluator.hpp b/mlir-assigner/include/mlir-assigner/parser/evaluator.hpp index 818afe3..2304e7d 100644 --- a/mlir-assigner/include/mlir-assigner/parser/evaluator.hpp +++ b/mlir-assigner/include/mlir-assigner/parser/evaluator.hpp @@ -39,6 +39,7 @@ #include #include #include +#include #include #include #include @@ -323,6 +324,8 @@ namespace zk_ml_toolchain { std::uint32_t start_row = assignmnt.allocated_rows(); if (math::ExpOp operation = llvm::dyn_cast(op)) { handle_fixedpoint_exp_component(operation, frames.back(), bp, assignmnt, start_row); + } else if (math::LogOp operation = llvm::dyn_cast(op)) { + handle_fixedpoint_log_component(operation, frames.back(), bp, assignmnt, start_row); } else if (math::AbsFOp operation = llvm::dyn_cast(op)) { handle_fixedpoint_abs_component(operation, frames.back(), bp, assignmnt, start_row); } else if (math::CeilOp operation = llvm::dyn_cast(op)) { @@ -336,6 +339,8 @@ namespace zk_ml_toolchain { frames.back().locals[mlir::hash_value(operation.getLhs())]; } else if (math::SqrtOp operation = llvm::dyn_cast(op)) { UNREACHABLE("TODO: sqrt"); + } else if (math::ErfOp operation = llvm::dyn_cast(op)) { + UNREACHABLE("TODO: component for erf not ready"); } else { std::string opName = op->getName().getIdentifier().str(); UNREACHABLE(std::string("unhandled math operation: ") + opName); diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Erf/ErfSimple.json b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Erf/ErfSimple.json new file mode 100644 index 0000000..a53b5f5 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Erf/ErfSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [0.68353271484375, 0.50244140625, 0.590240478515625, 0.337371826171875, 0.681549072265625, 0.1300048828125, 0.109771728515625, 0.8895263671875, 0.0695648193359375, 0.1826171875], "dims": [1, 10], "type": "f32"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/Acosh/AcoshSimple.mlir b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Erf/ErfSimple.mlir similarity index 87% rename from mlir-assigner/tests/Ops/Onnx/Acosh/AcoshSimple.mlir rename to mlir-assigner/tests/Ops/NeedsBlueprintComponent/Erf/ErfSimple.mlir index 8fe551b..ffe7d2b 100644 --- a/mlir-assigner/tests/Ops/Onnx/Acosh/AcoshSimple.mlir +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Erf/ErfSimple.mlir @@ -1,10 +1,10 @@ -module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-linux-gnu", "onnx-mlir.symbol-postfix" = "acoshsimple.0.mlir"} { +module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-pc-linux-gnu", "onnx-mlir.symbol-postfix" = "erfsimple.mlir"} { func.func @main_graph(%arg0: memref<1x10xf32>) -> memref<1x10xf32> attributes {input_names = ["in_a"], llvm.emit_c_interface, output_names = ["out_a"]} { %alloc = memref.alloc() {alignment = 16 : i64} : memref<1x10xf32> affine.for %arg1 = 0 to 1 { affine.for %arg2 = 0 to 10 { %0 = affine.load %arg0[%arg1, %arg2] : memref<1x10xf32> - %1 = "krnl.acosh"(%0) : (f32) -> f32 + %1 = math.erf %0 : f32 affine.store %1, %alloc[%arg1, %arg2] : memref<1x10xf32> } } diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Erf/ErfSimple.onnx b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Erf/ErfSimple.onnx new file mode 100644 index 0000000..28366ef --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Erf/ErfSimple.onnx @@ -0,0 +1,13 @@ + :P + +in_aout_a"Erf ErfSimpleZ +in_a +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Erf/ErfSimple.res b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Erf/ErfSimple.res new file mode 100644 index 0000000..d91c088 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Erf/ErfSimple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xf32>[0.6662865281105042, 0.5226426720619202, 0.596127986907959, 0.3667203485965729, 0.6648818254470825, 0.14587253332138062, 0.12336840480566025, 0.7916010618209839, 0.07836905121803284, 0.2037934958934784] +ADD THE ROWS HERE \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/And/AndSimple.mlir b/mlir-assigner/tests/Ops/Onnx/And/AndSimple.mlir deleted file mode 100644 index 9a8f026..0000000 --- a/mlir-assigner/tests/Ops/Onnx/And/AndSimple.mlir +++ /dev/null @@ -1,16 +0,0 @@ -module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-pc-linux-gnu", "onnx-mlir.symbol-postfix" = "andsimple.mlir"} { - func.func @main_graph(%arg0: memref<1x10xi1>, %arg1: memref<1x10xi1>) -> memref<1x10xi1> attributes {input_names = ["in_a", "in_b"], llvm.emit_c_interface, output_names = ["out_a"]} { - %c0 = arith.constant 0 : index - %alloc = memref.alloc() {alignment = 16 : i64} : memref<1x10xi1> - affine.for %arg2 = 0 to 1 { - affine.for %arg3 = 0 to 10 { - %0 = affine.load %arg0[%c0, %arg3] : memref<1x10xi1> - %1 = affine.load %arg1[%c0, %arg3] : memref<1x10xi1> - %2 = arith.andi %0, %1 : i1 - affine.store %2, %alloc[%arg2, %arg3] : memref<1x10xi1> - } - } - return %alloc : memref<1x10xi1> - } - "krnl.entry_point"() {func = @main_graph, numInputs = 2 : i32, numOutputs = 1 : i32, signature = "[ { \22type\22 : \22i1\22 , \22dims\22 : [1 , 10] , \22name\22 : \22in_a\22 }\0A , { \22type\22 : \22i1\22 , \22dims\22 : [1 , 10] , \22name\22 : \22in_b\22 }\0A\0A]\00@[ { \22type\22 : \22i1\22 , \22dims\22 : [1 , 10] , \22name\22 : \22out_a\22 }\0A\0A]\00"} : () -> () -} diff --git a/mlir-assigner/tests/Ops/Onnx/Div/DivSimple.mlir b/mlir-assigner/tests/Ops/Onnx/Div/DivSimple.mlir deleted file mode 100644 index a188eda..0000000 --- a/mlir-assigner/tests/Ops/Onnx/Div/DivSimple.mlir +++ /dev/null @@ -1,16 +0,0 @@ -module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-unknown-linux-gnu", "onnx-mlir.symbol-postfix" = "divsimple.0.mlir"} { - func.func @main_graph(%arg0: memref<1x10xf32>, %arg1: memref<1x10xf32>) -> memref<1x10xf32> attributes {input_names = ["in_a", "in_b"], llvm.emit_c_interface, output_names = ["out_a"]} { - %c0 = arith.constant 0 : index - %alloc = memref.alloc() {alignment = 16 : i64} : memref<1x10xf32> - affine.for %arg2 = 0 to 1 { - affine.for %arg3 = 0 to 10 { - %0 = affine.load %arg0[%c0, %arg3] : memref<1x10xf32> - %1 = affine.load %arg1[%c0, %arg3] : memref<1x10xf32> - %2 = arith.divf %0, %1 : f32 - affine.store %2, %alloc[%arg2, %arg3] : memref<1x10xf32> - } - } - return %alloc : memref<1x10xf32> - } - "krnl.entry_point"() {func = @main_graph, numInputs = 2 : i32, numOutputs = 1 : i32, signature = "[ { \22type\22 : \22f32\22 , \22dims\22 : [1 , 10] , \22name\22 : \22in_a\22 }\0A , { \22type\22 : \22f32\22 , \22dims\22 : [1 , 10] , \22name\22 : \22in_b\22 }\0A\0A]\00@[ { \22type\22 : \22f32\22 , \22dims\22 : [1 , 10] , \22name\22 : \22out_a\22 }\0A\0A]\00"} : () -> () -} diff --git a/mlir-assigner/tests/Ops/Onnx/HardSigmoid/HardSigmoidSimple.json b/mlir-assigner/tests/Ops/Onnx/HardSigmoid/HardSigmoidSimple.json new file mode 100644 index 0000000..ab4e2d7 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/HardSigmoid/HardSigmoidSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [0.389190673828125, 0.105712890625, 0.56243896484375, 0.2190704345703125, 0.134674072265625, 0.9574127197265625, 0.547149658203125, 0.1509857177734375, 0.1473541259765625, 0.0181121826171875], "dims": [1, 10], "type": "f32"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/HardSigmoid/HardSigmoidSimple.onnx b/mlir-assigner/tests/Ops/Onnx/HardSigmoid/HardSigmoidSimple.onnx new file mode 100644 index 0000000000000000000000000000000000000000..3b92100933212106b5867c3d3351c3a158d3eab6 GIT binary patch literal 138 zcmdK<&Cg8H;^$&b%qhr76g_*!$8G^5 zqZS_*OHyh{q9_9cgFTQhB#5LsI5W2(CpAh8Y91dK4+o[0.577838122844696, 0.5211426019668579, 0.61248779296875, 0.5438140630722046, 0.526934802532196, 0.6914825439453125, 0.6094299554824829, 0.5301971435546875, 0.5294708013534546, 0.5036224126815796] +60 diff --git a/mlir-assigner/tests/Ops/Onnx/LeakyRelu/LeakyReluSimple.json b/mlir-assigner/tests/Ops/Onnx/LeakyRelu/LeakyReluSimple.json new file mode 100644 index 0000000..8738294 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/LeakyRelu/LeakyReluSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [0.2706146240234375, 0.7530059814453125, 0.69873046875, 0.49169921875, 0.7146148681640625, 0.91375732421875, 0.047088623046875, 0.3588714599609375, 0.4225006103515625, 0.7489166259765625], "dims": [1, 10], "type": "f32"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/LeakyRelu/LeakyReluSimple.onnx b/mlir-assigner/tests/Ops/Onnx/LeakyRelu/LeakyReluSimple.onnx new file mode 100644 index 0000000..5df2a88 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/LeakyRelu/LeakyReluSimple.onnx @@ -0,0 +1,15 @@ + :m +) +in_aout_a" LeakyRelu* +alpha +�#<�LeakyReluSimpleZ +in_a +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/LeakyRelu/LeakyReluSimple.res b/mlir-assigner/tests/Ops/Onnx/LeakyRelu/LeakyReluSimple.res new file mode 100644 index 0000000..205b90f --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/LeakyRelu/LeakyReluSimple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xf32>[0.2706146240234375, 0.7530059814453125, 0.69873046875, 0.49169921875, 0.7146148681640625, 0.91375732421875, 0.047088623046875, 0.3588714599609375, 0.4225006103515625, 0.7489166259765625] +30 diff --git a/mlir-assigner/tests/Ops/Onnx/LogSoftmax/LogSoftmaxBasicMnist.json b/mlir-assigner/tests/Ops/Onnx/LogSoftmax/LogSoftmaxBasicMnist.json new file mode 100644 index 0000000..5da168c --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/LogSoftmax/LogSoftmaxBasicMnist.json @@ -0,0 +1 @@ +[{"memref": {"data": [0.9263153076171875, 0.5552978515625, 0.488739013671875, 0.1752166748046875, 0.75836181640625, 0.498870849609375, 0.184600830078125, 0.7884979248046875, 0.725982666015625, 0.805877685546875], "dims": [1, 10], "type": "f32"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/LogSoftmax/LogSoftmaxBasicMnist.onnx b/mlir-assigner/tests/Ops/Onnx/LogSoftmax/LogSoftmaxBasicMnist.onnx new file mode 100644 index 0000000..e600d2a --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/LogSoftmax/LogSoftmaxBasicMnist.onnx @@ -0,0 +1,15 @@ + :o +& +in_aout_a" +LogSoftmax* +axis�LogSoftmaxBasicMnistZ +in_a +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/LogSoftmax/LogSoftmaxBasicMnist.res b/mlir-assigner/tests/Ops/Onnx/LogSoftmax/LogSoftmaxBasicMnist.res new file mode 100644 index 0000000..5b7f37d --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/LogSoftmax/LogSoftmaxBasicMnist.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xf32>[-1.9957325458526611, -2.3667500019073486, -2.4333088397979736, -2.746831178665161, -2.1636860370635986, -2.4231770038604736, -2.7374470233917236, -2.133549928665161, -2.1960651874542236, -2.1161701679229736] +140 diff --git a/mlir-assigner/tests/Ops/Onnx/PRelu/PReluConst.json b/mlir-assigner/tests/Ops/Onnx/PRelu/PReluConst.json new file mode 100644 index 0000000..e3304f0 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/PRelu/PReluConst.json @@ -0,0 +1 @@ +[{"memref": {"data": [0.7888336181640625, 0.274871826171875, 0.862274169921875, 0.5487213134765625, 0.911895751953125, 0.7361602783203125, 0.2882537841796875, 0.3439788818359375, 0.0133514404296875, 0.8032379150390625], "dims": [1, 10], "type": "f32"}}] diff --git a/mlir-assigner/tests/Ops/Onnx/PRelu/PReluConst.onnx b/mlir-assigner/tests/Ops/Onnx/PRelu/PReluConst.onnx new file mode 100644 index 0000000..2091e2a --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/PRelu/PReluConst.onnx @@ -0,0 +1,16 @@ + :� + +in_a +in_bout_a"PRelu +PReluConst*6 +"(���=���=���=���=���=���=���=���=���=���=Bin_bZ +in_a +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/PRelu/PReluConst.res b/mlir-assigner/tests/Ops/Onnx/PRelu/PReluConst.res new file mode 100644 index 0000000..2e0252a --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/PRelu/PReluConst.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xf32>[0.7888336181640625, 0.274871826171875, 0.862274169921875, 0.5487213134765625, 0.911895751953125, 0.7361602783203125, 0.2882537841796875, 0.3439788818359375, 0.0133514404296875, 0.8032379150390625] +30 diff --git a/mlir-assigner/tests/Ops/Onnx/PRelu/PReluSimple.json b/mlir-assigner/tests/Ops/Onnx/PRelu/PReluSimple.json new file mode 100644 index 0000000..e5b51fe --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/PRelu/PReluSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [0.891021728515625, 0.5626983642578125, 0.2191619873046875, 0.7632598876953125, 0.9755706787109375, 0.7555694580078125, 0.72698974609375, 0.3393096923828125, 0.0352630615234375, 0.398712158203125], "dims": [1, 10], "type": "f32"}}, {"memref": {"data": [0.0781097412109375, 0.0261383056640625, 0.6385345458984375, 0.70574951171875, 0.1352691650390625, 0.2262420654296875, 0.101715087890625, 0.2310028076171875, 0.1707611083984375, 0.8590545654296875], "dims": [1, 10], "type": "f32"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/PRelu/PReluSimple.onnx b/mlir-assigner/tests/Ops/Onnx/PRelu/PReluSimple.onnx new file mode 100644 index 0000000..058997a --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/PRelu/PReluSimple.onnx @@ -0,0 +1,19 @@ + :r + +in_a +in_bout_a"PRelu PReluSimpleZ +in_a +  + + +Z +in_b +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/PRelu/PReluSimple.res b/mlir-assigner/tests/Ops/Onnx/PRelu/PReluSimple.res new file mode 100644 index 0000000..c630301 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/PRelu/PReluSimple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xf32>[0.891021728515625, 0.5626983642578125, 0.2191619873046875, 0.7632598876953125, 0.9755706787109375, 0.7555694580078125, 0.72698974609375, 0.3393096923828125, 0.0352630615234375, 0.398712158203125] +30 diff --git a/mlir-assigner/tests/Ops/Onnx/Selu/SeluSimple.json b/mlir-assigner/tests/Ops/Onnx/Selu/SeluSimple.json new file mode 100644 index 0000000..30c81e8 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Selu/SeluSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [0.335845947265625, 0.8036041259765625, 0.855743408203125, 0.6555633544921875, 0.09368896484375, 0.340057373046875, 0.5518798828125, 0.47216796875, 0.814453125, 0.56549072265625], "dims": [1, 10], "type": "f32"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/Selu/SeluSimple.onnx b/mlir-assigner/tests/Ops/Onnx/Selu/SeluSimple.onnx new file mode 100644 index 0000000..39e6cba --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Selu/SeluSimple.onnx @@ -0,0 +1,16 @@ + :t +5 +in_aout_a"Selu* +alphab-�?�* +gammaV}�?� +SeluSimpleZ +in_a +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/Selu/SeluSimple.res b/mlir-assigner/tests/Ops/Onnx/Selu/SeluSimple.res new file mode 100644 index 0000000..756c317 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Selu/SeluSimple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xf32>[0.3528733253479004, 0.844346821308136, 0.8991295695304871, 0.6888003945350647, 0.09843899309635162, 0.35729825496673584, 0.5798601508140564, 0.4961068630218506, 0.8557458519935608, 0.5941610932350159] +60 diff --git a/mlir-assigner/tests/Ops/Onnx/Sigmoid/SigmoidSimple.json b/mlir-assigner/tests/Ops/Onnx/Sigmoid/SigmoidSimple.json new file mode 100644 index 0000000..f77e7b2 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Sigmoid/SigmoidSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [0.420074462890625, 0.58660888671875, 0.7588348388671875, 0.926849365234375, 0.4851531982421875, 0.1836090087890625, 0.9698486328125, 0.407806396484375, 0.208160400390625, 0.3989105224609375], "dims": [1, 10], "type": "f32"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/Sigmoid/SigmoidSimple.onnx b/mlir-assigner/tests/Ops/Onnx/Sigmoid/SigmoidSimple.onnx new file mode 100644 index 0000000..1247677 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Sigmoid/SigmoidSimple.onnx @@ -0,0 +1,13 @@ + :X + +in_aout_a"Sigmoid SigmoidSimpleZ +in_a +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/Sigmoid/SigmoidSimple.res b/mlir-assigner/tests/Ops/Onnx/Sigmoid/SigmoidSimple.res new file mode 100644 index 0000000..7ba2dca --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Sigmoid/SigmoidSimple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xf32>[0.6035010814666748, 0.6425867080688477, 0.6811007261276245, 0.7164356112480164, 0.6189640164375305, 0.5457737445831299, 0.7250893712043762, 0.600561797618866, 0.5518530011177063, 0.5984258651733398] +50 diff --git a/mlir-assigner/tests/Ops/Onnx/Softplus/SoftplusBasicMnist.json b/mlir-assigner/tests/Ops/Onnx/Softplus/SoftplusBasicMnist.json new file mode 100644 index 0000000..18ff5e0 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Softplus/SoftplusBasicMnist.json @@ -0,0 +1 @@ +[{"memref": {"data": [0.0689697265625, 0.609283447265625, 0.095550537109375, 0.4514007568359375, 0.439605712890625, 0.26214599609375, 0.4383544921875, 0.354248046875, 0.21820068359375, 0.04864501953125], "dims": [1, 10], "type": "f32"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/Softplus/SoftplusBasicMnist.onnx b/mlir-assigner/tests/Ops/Onnx/Softplus/SoftplusBasicMnist.onnx new file mode 100644 index 0000000..dcf8b1f --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Softplus/SoftplusBasicMnist.onnx @@ -0,0 +1,13 @@ + :^ + +in_aout_a"SoftplusSoftplusBasicMnistZ +in_a +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/Softplus/SoftplusBasicMnist.res b/mlir-assigner/tests/Ops/Onnx/Softplus/SoftplusBasicMnist.res new file mode 100644 index 0000000..337eeee --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Softplus/SoftplusBasicMnist.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xf32>[0.7282265424728394, 1.0434917211532593, 0.7420632839202881, 0.9441044926643372, 0.9369146823883057, 0.8327857255935669, 0.9361538290977478, 0.8858763575553894, 0.8081871867179871, 0.7177654504776001] +90 diff --git a/mlir-assigner/tests/Ops/Onnx/Softsign/SoftsignBasicMnist.json b/mlir-assigner/tests/Ops/Onnx/Softsign/SoftsignBasicMnist.json new file mode 100644 index 0000000..ffa3a8a --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Softsign/SoftsignBasicMnist.json @@ -0,0 +1 @@ +[{"memref": {"data": [0.293365478515625, 0.330474853515625, 0.533905029296875, 0.4608154296875, 0.0807037353515625, 0.4675445556640625, 0.616790771484375, 0.2982177734375, 0.3966522216796875, 0.8043975830078125], "dims": [1, 10], "type": "f32"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/Softsign/SoftsignBasicMnist.onnx b/mlir-assigner/tests/Ops/Onnx/Softsign/SoftsignBasicMnist.onnx new file mode 100644 index 0000000..e10fd99 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Softsign/SoftsignBasicMnist.onnx @@ -0,0 +1,13 @@ + :^ + +in_aout_a"SoftsignSoftsignBasicMnistZ +in_a +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/Softsign/SoftsignBasicMnist.res b/mlir-assigner/tests/Ops/Onnx/Softsign/SoftsignBasicMnist.res new file mode 100644 index 0000000..ad7b531 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Softsign/SoftsignBasicMnist.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xf32>[0.2268233448266983, 0.2483886480331421, 0.3480691611766815, 0.3154508173465729, 0.07467702031135559, 0.3185896873474121, 0.3814907670021057, 0.22971321642398834, 0.2840021550655365, 0.44579842686653137] +40 diff --git a/mlir-assigner/tests/run.py b/mlir-assigner/tests/run.py index 13ad856..3613b52 100644 --- a/mlir-assigner/tests/run.py +++ b/mlir-assigner/tests/run.py @@ -213,14 +213,14 @@ def test_folder(test_suite, folder, mlir_tests, timeout, verbose, keep_mlir): test_folder("SingleOps E2E", "mlir-assigner/tests/Ops/Onnx", False, 30, args.verbose, args.keep_mlir) test_folder("SingleOps special MLIR", "mlir-assigner/tests/Ops/Mlir", True, 30, args.verbose, args.keep_mlir) -# Rest of your code... -# test_folder("SingleOps", "mlir-assigner/tests/Ops/", 30, args.verbose) if slow_test: test_folder("Models", "mlir-assigner/tests/Models/", False, 500, args.verbose, args.keep_mlir) # cleanup -os.remove("circuit") -os.remove("table") +if isfile("circuit"): + os.remove("circuit") +if isfile("table"): + os.remove("table") print("\n") print(f"Test Report - run {run_tests} tests, {success_tests} success, {failed_tests} failed, {error_tests} errors, {ignored_tests} ignored") for error in errors: