From 61a3597cac8c9ae394228f69beb0071192d83f4a Mon Sep 17 00:00:00 2001 From: fnieddu <118167989+fnieddu@users.noreply.github.com> Date: Wed, 3 Jan 2024 10:13:49 +0100 Subject: [PATCH] Feat/trigonemtric pooling ops (#16) * added AveragePool; int to fix no range check * added sin,sinh,cos,cosh * rest of trigonometric tests --- .../mlir-assigner/components/boolean/and.hpp | 7 +- .../components/fixedpoint/to_fixpoint.hpp | 44 ++++++++++++ .../components/fixedpoint/trigonometric.hpp | 65 ++++++++++++++++++ .../components/handle_component.hpp | 33 +++++++-- .../mlir-assigner/parser/evaluator.hpp | 37 +++++++++- .../Acos/AcosSimple.json | 1 + .../Acos/AcosSimple.mlir | 14 ++++ .../Acos/AcosSimple.onnx | 14 ++++ .../Acos/AcosSimple.res | 3 + .../Acosh/AcoshSimple.json | 1 + .../Acosh/AcoshSimple.mlir | 14 ++++ .../Acosh/AcoshSimple.onnx | 13 ++++ .../Acosh/AcoshSimple.res | 3 + .../Asin/AsinSimple.json | 1 + .../Asin/AsinSimple.mlir | 14 ++++ .../Asin/AsinSimple.onnx | 14 ++++ .../Asin/AsinSimple.res | 3 + .../Asinh/AsinhSimple.json | 1 + .../Asinh/AsinhSimple.mlir | 14 ++++ .../Asinh/AsinhSimple.onnx | 13 ++++ .../Asinh/AsinhSimple.res | 3 + .../Atan/AtanSimple.json | 1 + .../Atan/AtanSimple.mlir | 14 ++++ .../Atan/AtanSimple.onnx | 14 ++++ .../Atan/AtanSimple.res | 3 + .../Atanh/AtanhSimple.json | 1 + .../Atanh/AtanhSimple.mlir | 14 ++++ .../Atanh/AtanhSimple.onnx | 13 ++++ .../Atanh/AtanhSimple.res | 3 + .../Tan/TanSimple.json | 1 + .../Tan/TanSimple.mlir | 14 ++++ .../Tan/TanSimple.onnx | 13 ++++ .../NeedsBlueprintComponent/Tan/TanSimple.res | 3 + .../Tanh/TanhSimple.json | 1 + .../Tanh/TanhSimple.mlir | 14 ++++ .../Tanh/TanhSimple.onnx | 14 ++++ .../Tanh/TanhSimple.res | 3 + .../Onnx/AveragePool/AveragePoolSimple.json | 1 + .../Onnx/AveragePool/AveragePoolSimple.onnx | Bin 0 -> 199 bytes .../Onnx/AveragePool/AveragePoolSimple.res | 3 + .../tests/Ops/Onnx/Cos/CosSimple.json | 1 + .../tests/Ops/Onnx/Cos/CosSimple.onnx | 13 ++++ .../tests/Ops/Onnx/Cos/CosSimple.res | 3 + .../tests/Ops/Onnx/Cosh/CoshSimple.json | 1 + .../tests/Ops/Onnx/Cosh/CoshSimple.onnx | 14 ++++ .../tests/Ops/Onnx/Cosh/CoshSimple.res | 3 + .../tests/Ops/Onnx/Sin/SinSimple.json | 1 + .../tests/Ops/Onnx/Sin/SinSimple.onnx | 13 ++++ .../tests/Ops/Onnx/Sin/SinSimple.res | 3 + .../tests/Ops/Onnx/Sinh/SinhSimple.json | 1 + .../tests/Ops/Onnx/Sinh/SinhSimple.onnx | 14 ++++ .../tests/Ops/Onnx/Sinh/SinhSimple.res | 3 + mlir-assigner/tests/run.py | 13 ++-- 53 files changed, 510 insertions(+), 15 deletions(-) create mode 100644 mlir-assigner/include/mlir-assigner/components/fixedpoint/to_fixpoint.hpp create mode 100644 mlir-assigner/include/mlir-assigner/components/fixedpoint/trigonometric.hpp create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acos/AcosSimple.json create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acos/AcosSimple.mlir create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acos/AcosSimple.onnx create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acos/AcosSimple.res create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acosh/AcoshSimple.json create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acosh/AcoshSimple.mlir create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acosh/AcoshSimple.onnx create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acosh/AcoshSimple.res create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asin/AsinSimple.json create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asin/AsinSimple.mlir create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asin/AsinSimple.onnx create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asin/AsinSimple.res create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asinh/AsinhSimple.json create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asinh/AsinhSimple.mlir create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asinh/AsinhSimple.onnx create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asinh/AsinhSimple.res create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atan/AtanSimple.json create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atan/AtanSimple.mlir create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atan/AtanSimple.onnx create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atan/AtanSimple.res create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atanh/AtanhSimple.json create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atanh/AtanhSimple.mlir create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atanh/AtanhSimple.onnx create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atanh/AtanhSimple.res create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tan/TanSimple.json create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tan/TanSimple.mlir create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tan/TanSimple.onnx create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tan/TanSimple.res create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tanh/TanhSimple.json create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tanh/TanhSimple.mlir create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tanh/TanhSimple.onnx create mode 100644 mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tanh/TanhSimple.res create mode 100644 mlir-assigner/tests/Ops/Onnx/AveragePool/AveragePoolSimple.json create mode 100644 mlir-assigner/tests/Ops/Onnx/AveragePool/AveragePoolSimple.onnx create mode 100644 mlir-assigner/tests/Ops/Onnx/AveragePool/AveragePoolSimple.res create mode 100644 mlir-assigner/tests/Ops/Onnx/Cos/CosSimple.json create mode 100644 mlir-assigner/tests/Ops/Onnx/Cos/CosSimple.onnx create mode 100644 mlir-assigner/tests/Ops/Onnx/Cos/CosSimple.res create mode 100644 mlir-assigner/tests/Ops/Onnx/Cosh/CoshSimple.json create mode 100644 mlir-assigner/tests/Ops/Onnx/Cosh/CoshSimple.onnx create mode 100644 mlir-assigner/tests/Ops/Onnx/Cosh/CoshSimple.res create mode 100644 mlir-assigner/tests/Ops/Onnx/Sin/SinSimple.json create mode 100644 mlir-assigner/tests/Ops/Onnx/Sin/SinSimple.onnx create mode 100644 mlir-assigner/tests/Ops/Onnx/Sin/SinSimple.res create mode 100644 mlir-assigner/tests/Ops/Onnx/Sinh/SinhSimple.json create mode 100644 mlir-assigner/tests/Ops/Onnx/Sinh/SinhSimple.onnx create mode 100644 mlir-assigner/tests/Ops/Onnx/Sinh/SinhSimple.res diff --git a/mlir-assigner/include/mlir-assigner/components/boolean/and.hpp b/mlir-assigner/include/mlir-assigner/components/boolean/and.hpp index 4ae51ff..d52cb8f 100644 --- a/mlir-assigner/include/mlir-assigner/components/boolean/and.hpp +++ b/mlir-assigner/include/mlir-assigner/components/boolean/and.hpp @@ -29,7 +29,6 @@ #include -#include #include #include #include // TODO: check if there is a new mechanism for this in nil upstream @@ -51,7 +50,7 @@ namespace nil { using component_type = components::lookup_logic_and< crypto3::zk::snark::plonk_constraint_system>; - auto input = PREPARE_INPUT(mlir::arith::AndIOp); + auto input = PREPARE_BINARY_INPUT(mlir::arith::AndIOp); const auto p = detail::PolicyManager::get_parameters( detail::ManifestReader::get_witness(0)); @@ -72,7 +71,7 @@ namespace nil { // using component_type = components::lookup_logic_or< // crypto3::zk::snark::plonk_constraint_system>; // - // auto input = PREPARE_INPUT(mlir::arith::OrIOp); + // auto input = PREPARE_BINARY_INPUT(mlir::arith::OrIOp); // const auto p = detail::PolicyManager::get_parameters( // detail::ManifestReader::get_witness(0)); // @@ -91,7 +90,7 @@ namespace nil { using component_type = components::lookup_logic_xor< crypto3::zk::snark::plonk_constraint_system>; - auto input = PREPARE_INPUT(mlir::arith::XOrIOp); + auto input = PREPARE_BINARY_INPUT(mlir::arith::XOrIOp); const auto p = detail::PolicyManager::get_parameters( detail::ManifestReader::get_witness(0)); diff --git a/mlir-assigner/include/mlir-assigner/components/fixedpoint/to_fixpoint.hpp b/mlir-assigner/include/mlir-assigner/components/fixedpoint/to_fixpoint.hpp new file mode 100644 index 0000000..5bce400 --- /dev/null +++ b/mlir-assigner/include/mlir-assigner/components/fixedpoint/to_fixpoint.hpp @@ -0,0 +1,44 @@ +#ifndef CRYPTO3_ASSIGNER_FIXEDPOINT_TO_FIXEDPOINT_HPP +#define CRYPTO3_ASSIGNER_FIXEDPOINT_TO_FIXEDPOINT_HPP + +#include "mlir/Dialect/zkml/IR/DotProduct.h" +#include + +#include + +#include +#include +#include // TODO: check if there is a new mechanism for this in nil upstream + +#include +#include +#include + +namespace nil { + namespace blueprint { + + template + void handle_to_fixedpoint( + mlir::arith::SIToFPOp &operation, + stack_frame> &frame, + circuit_proxy> &bp, + assignment_proxy> + &assignment, + std::uint32_t start_row) { + using component_type = components::int_to_fix< + crypto3::zk::snark::plonk_constraint_system, + BlueprintFieldType, basic_non_native_policy>; + + auto input = PREPARE_UNARY_INPUT(mlir::arith::SIToFPOp); + using manifest_reader = detail::ManifestReader; + const auto p = detail::PolicyManager::get_parameters( + detail::ManifestReader::get_witness(0)); + + component_type component(p.witness, manifest_reader::get_constants(), manifest_reader::get_public_inputs(), + 1); + fill_trace(component, input, operation, frame, bp, assignment, start_row); + } + } // namespace blueprint +} // namespace nil + +#endif // CRYPTO3_ASSIGNER_FIXEDPOINT_TO_FIXEDPOINT_HPP diff --git a/mlir-assigner/include/mlir-assigner/components/fixedpoint/trigonometric.hpp b/mlir-assigner/include/mlir-assigner/components/fixedpoint/trigonometric.hpp new file mode 100644 index 0000000..5eaf4f6 --- /dev/null +++ b/mlir-assigner/include/mlir-assigner/components/fixedpoint/trigonometric.hpp @@ -0,0 +1,65 @@ +#ifndef CRYPTO3_ASSIGNER_FIXEDPOINT_TRIGONOMETRIC_HPP +#define CRYPTO3_ASSIGNER_FIXEDPOINT_TRIGONOMETRIC_HPP + +#include "mlir/Dialect/zkml/IR/DotProduct.h" +#include + +#include + +#include +#include +#include // TODO: check if there is a new mechanism for this in nil upstream + +#include +#include +#include + +namespace nil { + namespace blueprint { + + template + void handle_sin( + mlir::math::SinOp &operation, + stack_frame> &frame, + circuit_proxy> &bp, + assignment_proxy> + &assignment, + std::uint32_t start_row) { + using component_type = components::fix_sin< + crypto3::zk::snark::plonk_constraint_system, + BlueprintFieldType, basic_non_native_policy>; + + auto input = PREPARE_UNARY_INPUT(mlir::math::SinOp); + using manifest_reader = detail::ManifestReader; + const auto p = detail::PolicyManager::get_parameters( + detail::ManifestReader::get_witness(0, 1, 1)); + + component_type component(p.witness, manifest_reader::get_constants(), manifest_reader::get_public_inputs(), + 1, 1); + fill_trace(component, input, operation, frame, bp, assignment, start_row); + } + template + void handle_cos( + mlir::math::CosOp &operation, + stack_frame> &frame, + circuit_proxy> &bp, + assignment_proxy> + &assignment, + std::uint32_t start_row) { + using component_type = components::fix_cos< + crypto3::zk::snark::plonk_constraint_system, + BlueprintFieldType, basic_non_native_policy>; + + auto input = PREPARE_UNARY_INPUT(mlir::math::CosOp); + using manifest_reader = detail::ManifestReader; + const auto p = detail::PolicyManager::get_parameters( + detail::ManifestReader::get_witness(0, 1, 1)); + + component_type component(p.witness, manifest_reader::get_constants(), manifest_reader::get_public_inputs(), + 1, 1); + fill_trace(component, input, operation, frame, bp, assignment, start_row); + } + } // namespace blueprint +} // namespace nil + +#endif // CRYPTO3_ASSIGNER_FIXEDPOINT_TRIGONOMETRIC_HPP diff --git a/mlir-assigner/include/mlir-assigner/components/handle_component.hpp b/mlir-assigner/include/mlir-assigner/components/handle_component.hpp index 602a6eb..036c8d0 100644 --- a/mlir-assigner/include/mlir-assigner/components/handle_component.hpp +++ b/mlir-assigner/include/mlir-assigner/components/handle_component.hpp @@ -26,13 +26,38 @@ #ifndef CRYPTO3_ASSIGNER_HANDLE_COMPONENT_HPP #define CRYPTO3_ASSIGNER_HANDLE_COMPONENT_HPP -#define PREPARE_INPUT(OP) \ +#include +#include +#include +#include +#include + +#define PREPARE_UNARY_INPUT(OP) \ + prepare_unary_operation_input(operation, frame, bp, assignment); +#define PREPARE_BINARY_INPUT(OP) \ prepare_binary_operation_input(operation, frame, bp, assignment); -#include + namespace nil { namespace blueprint { + template + input_type prepare_unary_operation_input( + UnaryOp &operation, + stack_frame> &frame, + circuit_proxy> &bp, + assignment_proxy> + &assignment) { + + assert(operation->getNumOperands() == 1 && "unary operand must have only one operand"); + auto operand = frame.locals.find(mlir::hash_value(operation->getOperand(0))); + ASSERT(operand != frame.locals.end()); + + input_type instance_input; + instance_input.x = operand->second; + return instance_input; + } template input_type prepare_binary_operation_input( BinOp &operation, @@ -80,11 +105,11 @@ namespace nil { } } - template + template void fill_trace( component_type &component, typename component_type::input_type &input, - BinOp &mlir_op, + Op &mlir_op, stack_frame> &frame, circuit_proxy> &bp, assignment_proxy> diff --git a/mlir-assigner/include/mlir-assigner/parser/evaluator.hpp b/mlir-assigner/include/mlir-assigner/parser/evaluator.hpp index 0177c79..75f74ea 100644 --- a/mlir-assigner/include/mlir-assigner/parser/evaluator.hpp +++ b/mlir-assigner/include/mlir-assigner/parser/evaluator.hpp @@ -48,7 +48,9 @@ #include #include #include +#include #include +#include #include #include @@ -347,6 +349,15 @@ namespace zk_ml_toolchain { logger << constantValue; UNREACHABLE("unhandled constant"); } + } else if (arith::IndexCastOp operation = llvm::dyn_cast(op)) { + assert(operation->getNumOperands() == 1 && "IndexCast must have exactly one operand"); + auto index = frames.back().constant_values[mlir::hash_value(operation->getOperand(0))]; + typename BlueprintFieldType::value_type field_constant = index; + auto val = put_into_assignment(field_constant); + frames.back().locals.insert(std::make_pair(mlir::hash_value(operation.getResult()), val)); + } else if (arith::SIToFPOp operation = llvm::dyn_cast(op)) { + // TODO this does not respect negative and no different ranges for ints... + handle_to_fixedpoint(operation, frames.back(), bp, assignmnt, start_row); } else { std::string opName = op->getName().getIdentifier().str(); UNREACHABLE(std::string("unhandled arith operation: ") + opName); @@ -372,6 +383,14 @@ namespace zk_ml_toolchain { frames.back().locals[mlir::hash_value(operation.getLhs())]; } else if (math::SqrtOp operation = llvm::dyn_cast(op)) { UNREACHABLE("TODO: component for sqrt not ready"); + } else if (math::SinOp operation = llvm::dyn_cast(op)) { + handle_sin(operation, frames.back(), bp, assignmnt, start_row); + } else if (math::CosOp operation = llvm::dyn_cast(op)) { + handle_cos(operation, frames.back(), bp, assignmnt, start_row); + } else if (math::AtanOp operation = llvm::dyn_cast(op)) { + UNREACHABLE("TODO: component for atanh not ready"); + } else if (math::TanhOp operation = llvm::dyn_cast(op)) { + UNREACHABLE("TODO: component for tanh not ready"); } else if (math::ErfOp operation = llvm::dyn_cast(op)) { UNREACHABLE("TODO: component for erf not ready"); } else { @@ -414,7 +433,9 @@ namespace zk_ml_toolchain { assert(res != frames.back().constant_values.end()); mapDims.push_back(res->second); } - auto affineMap = castFromAttr(operation->getAttr(affine::AffineLoadOp::getMapAttrStrName())).getAffineMap(); + auto affineMap = + castFromAttr(operation->getAttr(affine::AffineLoadOp::getMapAttrStrName())) + .getAffineMap(); auto value = memref->second.get(evalAffineMap(affineMap, mapDims)); frames.back().locals[mlir::hash_value(operation.getResult())] = value; } else if (affine::AffineStoreOp operation = llvm::dyn_cast(op)) { @@ -437,7 +458,9 @@ namespace zk_ml_toolchain { auto value = frames.back().locals.find(mlir::hash_value(operation.getValue())); assert(value != frames.back().locals.end()); // put the element from the memref using index vector - auto affineMap = castFromAttr(operation->getAttr(affine::AffineStoreOp::getMapAttrStrName())).getAffineMap(); + auto affineMap = + castFromAttr(operation->getAttr(affine::AffineStoreOp::getMapAttrStrName())) + .getAffineMap(); memref->second.put(evalAffineMap(affineMap, mapDims), value->second); } else if (affine::AffineYieldOp operation = llvm::dyn_cast(op)) { @@ -594,8 +617,18 @@ namespace zk_ml_toolchain { return; } else if (KrnlAcosOp operation = llvm::dyn_cast(op)) { UNREACHABLE(std::string("TODO KrnlAcos: link to bluebrint component")); + } else if (KrnlAsinOp operation = llvm::dyn_cast(op)) { + UNREACHABLE(std::string("TODO KrnlSin: link to bluebrint component")); } else if (KrnlAcoshOp operation = llvm::dyn_cast(op)) { UNREACHABLE(std::string("TODO KrnlAcosh: link to bluebrint component")); + } else if (KrnlAsinhOp operation = llvm::dyn_cast(op)) { + UNREACHABLE(std::string("TODO KrnlSinh: link to bluebrint component")); + } else if (KrnlTanOp operation = llvm::dyn_cast(op)) { + UNREACHABLE("TODO: component for tan not ready"); + } else if (KrnlAtanOp operation = llvm::dyn_cast(op)) { + UNREACHABLE("TODO: component for atan not ready"); + } else if (KrnlAtanhOp operation = llvm::dyn_cast(op)) { + UNREACHABLE("TODO: component for atanh not ready"); } else { std::string opName = op->getName().getIdentifier().str(); UNREACHABLE(std::string("unhandled krnl operation: ") + opName); diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acos/AcosSimple.json b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acos/AcosSimple.json new file mode 100644 index 0000000..248de45 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acos/AcosSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [0.6515045166015625, 0.259490966796875, 0.200439453125, 0.084564208984375, 0.223297119140625, 0.867034912109375, 0.0014801025390625, 0.4618377685546875, 0.059051513671875, 0.2735137939453125], "dims": [1, 10], "type": "f32"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acos/AcosSimple.mlir b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acos/AcosSimple.mlir new file mode 100644 index 0000000..dc2b295 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acos/AcosSimple.mlir @@ -0,0 +1,14 @@ +module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-pc-linux-gnu", "onnx-mlir.symbol-postfix" = "acossimple.mlir"} { + func.func @main_graph(%arg0: memref<1x10xf32>) -> memref<1x10xf32> attributes {input_names = ["in_a"], llvm.emit_c_interface, output_names = ["out_a"]} { + %alloc = memref.alloc() {alignment = 16 : i64} : memref<1x10xf32> + affine.for %arg1 = 0 to 1 { + affine.for %arg2 = 0 to 10 { + %0 = affine.load %arg0[%arg1, %arg2] : memref<1x10xf32> + %1 = "krnl.acos"(%0) : (f32) -> f32 + affine.store %1, %alloc[%arg1, %arg2] : memref<1x10xf32> + } + } + return %alloc : memref<1x10xf32> + } + "krnl.entry_point"() {func = @main_graph, numInputs = 1 : i32, numOutputs = 1 : i32, signature = "[ { \22type\22 : \22f32\22 , \22dims\22 : [1 , 10] , \22name\22 : \22in_a\22 }\0A\0A]\00@[ { \22type\22 : \22f32\22 , \22dims\22 : [1 , 10] , \22name\22 : \22out_a\22 }\0A\0A]\00"} : () -> () +} diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acos/AcosSimple.onnx b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acos/AcosSimple.onnx new file mode 100644 index 0000000..f3c71e5 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acos/AcosSimple.onnx @@ -0,0 +1,14 @@ + :R + +in_aout_a"Acos +AcosSimpleZ +in_a +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acos/AcosSimple.res b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acos/AcosSimple.res new file mode 100644 index 0000000..f43f083 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acos/AcosSimple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xf32>[0.8612304329872131, 1.3083012104034424, 1.3689898252487183, 1.486130952835083, 1.3456006050109863, 0.5215762257575989, 1.5693162679672241, 1.0907303094863892, 1.5117104053497314, 1.2937520742416382] +ADD THE ROWS HERE \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acosh/AcoshSimple.json b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acosh/AcoshSimple.json new file mode 100644 index 0000000..ef3e4a7 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acosh/AcoshSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [0.5222625732421875, 0.6072845458984375, 0.3314361572265625, 0.698211669921875, 0.192108154296875, 0.699432373046875, 0.5330963134765625, 0.62982177734375, 0.908538818359375, 0.012664794921875], "dims": [1, 10], "type": "f32"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acosh/AcoshSimple.mlir b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acosh/AcoshSimple.mlir new file mode 100644 index 0000000..edd0071 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acosh/AcoshSimple.mlir @@ -0,0 +1,14 @@ +module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-pc-linux-gnu", "onnx-mlir.symbol-postfix" = "acoshsimple.mlir"} { + func.func @main_graph(%arg0: memref<1x10xf32>) -> memref<1x10xf32> attributes {input_names = ["in_a"], llvm.emit_c_interface, output_names = ["out_a"]} { + %alloc = memref.alloc() {alignment = 16 : i64} : memref<1x10xf32> + affine.for %arg1 = 0 to 1 { + affine.for %arg2 = 0 to 10 { + %0 = affine.load %arg0[%arg1, %arg2] : memref<1x10xf32> + %1 = "krnl.acosh"(%0) : (f32) -> f32 + affine.store %1, %alloc[%arg1, %arg2] : memref<1x10xf32> + } + } + return %alloc : memref<1x10xf32> + } + "krnl.entry_point"() {func = @main_graph, numInputs = 1 : i32, numOutputs = 1 : i32, signature = "[ { \22type\22 : \22f32\22 , \22dims\22 : [1 , 10] , \22name\22 : \22in_a\22 }\0A\0A]\00@[ { \22type\22 : \22f32\22 , \22dims\22 : [1 , 10] , \22name\22 : \22out_a\22 }\0A\0A]\00"} : () -> () +} diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acosh/AcoshSimple.onnx b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acosh/AcoshSimple.onnx new file mode 100644 index 0000000..648f213 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acosh/AcoshSimple.onnx @@ -0,0 +1,13 @@ + :T + +in_aout_a"Acosh AcoshSimpleZ +in_a +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acosh/AcoshSimple.res b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acosh/AcoshSimple.res new file mode 100644 index 0000000..552b0a0 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Acosh/AcoshSimple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xf32>['-nan', '-nan', '-nan', '-nan', '-nan', '-nan', '-nan', '-nan', '-nan', '-nan'] +ADD THE ROWS HERE \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asin/AsinSimple.json b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asin/AsinSimple.json new file mode 100644 index 0000000..517adda --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asin/AsinSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [0.9450225830078125, 0.605438232421875, 0.3217926025390625, 0.98101806640625, 0.3497314453125, 0.0294036865234375, 0.0135650634765625, 0.7371368408203125, 0.589508056640625, 0.6390838623046875], "dims": [1, 10], "type": "f32"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asin/AsinSimple.mlir b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asin/AsinSimple.mlir new file mode 100644 index 0000000..f5d4743 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asin/AsinSimple.mlir @@ -0,0 +1,14 @@ +module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-pc-linux-gnu", "onnx-mlir.symbol-postfix" = "asinsimple.mlir"} { + func.func @main_graph(%arg0: memref<1x10xf32>) -> memref<1x10xf32> attributes {input_names = ["in_a"], llvm.emit_c_interface, output_names = ["out_a"]} { + %alloc = memref.alloc() {alignment = 16 : i64} : memref<1x10xf32> + affine.for %arg1 = 0 to 1 { + affine.for %arg2 = 0 to 10 { + %0 = affine.load %arg0[%arg1, %arg2] : memref<1x10xf32> + %1 = "krnl.asin"(%0) : (f32) -> f32 + affine.store %1, %alloc[%arg1, %arg2] : memref<1x10xf32> + } + } + return %alloc : memref<1x10xf32> + } + "krnl.entry_point"() {func = @main_graph, numInputs = 1 : i32, numOutputs = 1 : i32, signature = "[ { \22type\22 : \22f32\22 , \22dims\22 : [1 , 10] , \22name\22 : \22in_a\22 }\0A\0A]\00@[ { \22type\22 : \22f32\22 , \22dims\22 : [1 , 10] , \22name\22 : \22out_a\22 }\0A\0A]\00"} : () -> () +} diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asin/AsinSimple.onnx b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asin/AsinSimple.onnx new file mode 100644 index 0000000..084cd67 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asin/AsinSimple.onnx @@ -0,0 +1,14 @@ + :R + +in_aout_a"Asin +AsinSimpleZ +in_a +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asin/AsinSimple.res b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asin/AsinSimple.res new file mode 100644 index 0000000..cfacebc --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asin/AsinSimple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xf32>[1.2376636266708374, 0.6503163576126099, 0.3276221752166748, 1.3756436109542847, 0.35728442668914795, 0.02940792590379715, 0.013565479777753353, 0.828823447227478, 0.630449652671814, 0.693306565284729] +ADD THE ROWS HERE \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asinh/AsinhSimple.json b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asinh/AsinhSimple.json new file mode 100644 index 0000000..828489b --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asinh/AsinhSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [0.1416015625, 0.3862457275390625, 0.2863922119140625, 0.447998046875, 0.6417999267578125, 0.0609130859375, 0.6517486572265625, 0.5254974365234375, 0.335479736328125, 0.4817657470703125], "dims": [1, 10], "type": "f32"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asinh/AsinhSimple.mlir b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asinh/AsinhSimple.mlir new file mode 100644 index 0000000..7e6da0c --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asinh/AsinhSimple.mlir @@ -0,0 +1,14 @@ +module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-pc-linux-gnu", "onnx-mlir.symbol-postfix" = "asinhsimple.mlir"} { + func.func @main_graph(%arg0: memref<1x10xf32>) -> memref<1x10xf32> attributes {input_names = ["in_a"], llvm.emit_c_interface, output_names = ["out_a"]} { + %alloc = memref.alloc() {alignment = 16 : i64} : memref<1x10xf32> + affine.for %arg1 = 0 to 1 { + affine.for %arg2 = 0 to 10 { + %0 = affine.load %arg0[%arg1, %arg2] : memref<1x10xf32> + %1 = "krnl.asinh"(%0) : (f32) -> f32 + affine.store %1, %alloc[%arg1, %arg2] : memref<1x10xf32> + } + } + return %alloc : memref<1x10xf32> + } + "krnl.entry_point"() {func = @main_graph, numInputs = 1 : i32, numOutputs = 1 : i32, signature = "[ { \22type\22 : \22f32\22 , \22dims\22 : [1 , 10] , \22name\22 : \22in_a\22 }\0A\0A]\00@[ { \22type\22 : \22f32\22 , \22dims\22 : [1 , 10] , \22name\22 : \22out_a\22 }\0A\0A]\00"} : () -> () +} diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asinh/AsinhSimple.onnx b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asinh/AsinhSimple.onnx new file mode 100644 index 0000000..4fb60ed --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asinh/AsinhSimple.onnx @@ -0,0 +1,13 @@ + :T + +in_aout_a"Asinh AsinhSimpleZ +in_a +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asinh/AsinhSimple.res b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asinh/AsinhSimple.res new file mode 100644 index 0000000..86d042c --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Asinh/AsinhSimple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xf32>[0.14113257825374603, 0.37723469734191895, 0.2826150059700012, 0.43422335386276245, 0.604336142539978, 0.06087547540664673, 0.6126898527145386, 0.5039003491401672, 0.3294857442378998, 0.46484342217445374] +ADD THE ROWS HERE \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atan/AtanSimple.json b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atan/AtanSimple.json new file mode 100644 index 0000000..b32059a --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atan/AtanSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [0.2377166748046875, 0.9100189208984375, 0.345306396484375, 0.606475830078125, 0.2786865234375, 0.1507568359375, 0.5531158447265625, 0.115234375, 0.6790771484375, 0.534637451171875], "dims": [1, 10], "type": "f32"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atan/AtanSimple.mlir b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atan/AtanSimple.mlir new file mode 100644 index 0000000..ffc241d --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atan/AtanSimple.mlir @@ -0,0 +1,14 @@ +module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-pc-linux-gnu", "onnx-mlir.symbol-postfix" = "atansimple.mlir"} { + func.func @main_graph(%arg0: memref<1x10xf32>) -> memref<1x10xf32> attributes {input_names = ["in_a"], llvm.emit_c_interface, output_names = ["out_a"]} { + %alloc = memref.alloc() {alignment = 16 : i64} : memref<1x10xf32> + affine.for %arg1 = 0 to 1 { + affine.for %arg2 = 0 to 10 { + %0 = affine.load %arg0[%arg1, %arg2] : memref<1x10xf32> + %1 = "krnl.atan"(%0) : (f32) -> f32 + affine.store %1, %alloc[%arg1, %arg2] : memref<1x10xf32> + } + } + return %alloc : memref<1x10xf32> + } + "krnl.entry_point"() {func = @main_graph, numInputs = 1 : i32, numOutputs = 1 : i32, signature = "[ { \22type\22 : \22f32\22 , \22dims\22 : [1 , 10] , \22name\22 : \22in_a\22 }\0A\0A]\00@[ { \22type\22 : \22f32\22 , \22dims\22 : [1 , 10] , \22name\22 : \22out_a\22 }\0A\0A]\00"} : () -> () +} diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atan/AtanSimple.onnx b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atan/AtanSimple.onnx new file mode 100644 index 0000000..f627a10 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atan/AtanSimple.onnx @@ -0,0 +1,14 @@ + :R + +in_aout_a"Atan +AtanSimpleZ +in_a +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atan/AtanSimple.res b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atan/AtanSimple.res new file mode 100644 index 0000000..4424eff --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atan/AtanSimple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xf32>[0.2333848923444748, 0.738322913646698, 0.3324873447418213, 0.5451675653457642, 0.2717902958393097, 0.14963003993034363, 0.5052322745323181, 0.11472833901643753, 0.5965453386306763, 0.490972101688385] +ADD THE ROWS HERE \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atanh/AtanhSimple.json b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atanh/AtanhSimple.json new file mode 100644 index 0000000..9e488d2 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atanh/AtanhSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [0.8856964111328125, 0.0599365234375, 0.4793548583984375, 0.5802764892578125, 0.1214447021484375, 0.6031494140625, 0.543914794921875, 0.0394744873046875, 0.1163482666015625, 0.7165069580078125], "dims": [1, 10], "type": "f32"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atanh/AtanhSimple.mlir b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atanh/AtanhSimple.mlir new file mode 100644 index 0000000..a8ff0d0 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atanh/AtanhSimple.mlir @@ -0,0 +1,14 @@ +module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-pc-linux-gnu", "onnx-mlir.symbol-postfix" = "atanhsimple.mlir"} { + func.func @main_graph(%arg0: memref<1x10xf32>) -> memref<1x10xf32> attributes {input_names = ["in_a"], llvm.emit_c_interface, output_names = ["out_a"]} { + %alloc = memref.alloc() {alignment = 16 : i64} : memref<1x10xf32> + affine.for %arg1 = 0 to 1 { + affine.for %arg2 = 0 to 10 { + %0 = affine.load %arg0[%arg1, %arg2] : memref<1x10xf32> + %1 = "krnl.atanh"(%0) : (f32) -> f32 + affine.store %1, %alloc[%arg1, %arg2] : memref<1x10xf32> + } + } + return %alloc : memref<1x10xf32> + } + "krnl.entry_point"() {func = @main_graph, numInputs = 1 : i32, numOutputs = 1 : i32, signature = "[ { \22type\22 : \22f32\22 , \22dims\22 : [1 , 10] , \22name\22 : \22in_a\22 }\0A\0A]\00@[ { \22type\22 : \22f32\22 , \22dims\22 : [1 , 10] , \22name\22 : \22out_a\22 }\0A\0A]\00"} : () -> () +} diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atanh/AtanhSimple.onnx b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atanh/AtanhSimple.onnx new file mode 100644 index 0000000..0506973 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atanh/AtanhSimple.onnx @@ -0,0 +1,13 @@ + :T + +in_aout_a"Atanh AtanhSimpleZ +in_a +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atanh/AtanhSimple.res b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atanh/AtanhSimple.res new file mode 100644 index 0000000..ea7a148 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Atanh/AtanhSimple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xf32>[1.401597261428833, 0.0600084513425827, 0.5221463441848755, 0.662879467010498, 0.12204709649085999, 0.6980827450752258, 0.6096984148025513, 0.03949500992894173, 0.11687757074832916, 0.9004295468330383] +ADD THE ROWS HERE \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tan/TanSimple.json b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tan/TanSimple.json new file mode 100644 index 0000000..9acfadc --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tan/TanSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [0.2104034423828125, 0.4101104736328125, 0.7538604736328125, 0.9796142578125, 0.509368896484375, 0.5928192138671875, 0.80328369140625, 0.6318511962890625, 0.01287841796875, 0.3797607421875], "dims": [1, 10], "type": "f32"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tan/TanSimple.mlir b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tan/TanSimple.mlir new file mode 100644 index 0000000..dad340f --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tan/TanSimple.mlir @@ -0,0 +1,14 @@ +module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-pc-linux-gnu", "onnx-mlir.symbol-postfix" = "tansimple.mlir"} { + func.func @main_graph(%arg0: memref<1x10xf32>) -> memref<1x10xf32> attributes {input_names = ["in_a"], llvm.emit_c_interface, output_names = ["out_a"]} { + %alloc = memref.alloc() {alignment = 16 : i64} : memref<1x10xf32> + affine.for %arg1 = 0 to 1 { + affine.for %arg2 = 0 to 10 { + %0 = affine.load %arg0[%arg1, %arg2] : memref<1x10xf32> + %1 = "krnl.tan"(%0) : (f32) -> f32 + affine.store %1, %alloc[%arg1, %arg2] : memref<1x10xf32> + } + } + return %alloc : memref<1x10xf32> + } + "krnl.entry_point"() {func = @main_graph, numInputs = 1 : i32, numOutputs = 1 : i32, signature = "[ { \22type\22 : \22f32\22 , \22dims\22 : [1 , 10] , \22name\22 : \22in_a\22 }\0A\0A]\00@[ { \22type\22 : \22f32\22 , \22dims\22 : [1 , 10] , \22name\22 : \22out_a\22 }\0A\0A]\00"} : () -> () +} diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tan/TanSimple.onnx b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tan/TanSimple.onnx new file mode 100644 index 0000000..08b77f3 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tan/TanSimple.onnx @@ -0,0 +1,13 @@ + :P + +in_aout_a"Tan TanSimpleZ +in_a +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tan/TanSimple.res b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tan/TanSimple.res new file mode 100644 index 0000000..4c2e324 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tan/TanSimple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xf32>[0.21356424689292908, 0.43476253747940063, 0.9388334155082703, 1.4897156953811646, 0.5585304498672485, 0.6736464500427246, 1.0364264249801636, 0.7319538593292236, 0.01287913043051958, 0.3991353213787079] +ADD THE ROWS HERE \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tanh/TanhSimple.json b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tanh/TanhSimple.json new file mode 100644 index 0000000..9a82438 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tanh/TanhSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [0.3677978515625, 0.4518890380859375, 0.4237213134765625, 0.785888671875, 0.817413330078125, 0.3992156982421875, 0.2161712646484375, 0.1353759765625, 0.528350830078125, 0.5242767333984375], "dims": [1, 10], "type": "f32"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tanh/TanhSimple.mlir b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tanh/TanhSimple.mlir new file mode 100644 index 0000000..79c60f2 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tanh/TanhSimple.mlir @@ -0,0 +1,14 @@ +module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-pc-linux-gnu", "onnx-mlir.symbol-postfix" = "tanhsimple.mlir"} { + func.func @main_graph(%arg0: memref<1x10xf32>) -> memref<1x10xf32> attributes {input_names = ["in_a"], llvm.emit_c_interface, output_names = ["out_a"]} { + %alloc = memref.alloc() {alignment = 16 : i64} : memref<1x10xf32> + affine.for %arg1 = 0 to 1 { + affine.for %arg2 = 0 to 10 { + %0 = affine.load %arg0[%arg1, %arg2] : memref<1x10xf32> + %1 = math.tanh %0 : f32 + affine.store %1, %alloc[%arg1, %arg2] : memref<1x10xf32> + } + } + return %alloc : memref<1x10xf32> + } + "krnl.entry_point"() {func = @main_graph, numInputs = 1 : i32, numOutputs = 1 : i32, signature = "[ { \22type\22 : \22f32\22 , \22dims\22 : [1 , 10] , \22name\22 : \22in_a\22 }\0A\0A]\00@[ { \22type\22 : \22f32\22 , \22dims\22 : [1 , 10] , \22name\22 : \22out_a\22 }\0A\0A]\00"} : () -> () +} diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tanh/TanhSimple.onnx b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tanh/TanhSimple.onnx new file mode 100644 index 0000000..80da2b2 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tanh/TanhSimple.onnx @@ -0,0 +1,14 @@ + :R + +in_aout_a"Tanh +TanhSimpleZ +in_a +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tanh/TanhSimple.res b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tanh/TanhSimple.res new file mode 100644 index 0000000..e4719de --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/Tanh/TanhSimple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xf32>[0.35206401348114014, 0.4234505593776703, 0.4000608026981354, 0.6560736894607544, 0.6736595630645752, 0.37927767634391785, 0.21286578476428986, 0.13455499708652496, 0.4841194152832031, 0.4809940755367279] +ADD THE ROWS HERE \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/AveragePool/AveragePoolSimple.json b/mlir-assigner/tests/Ops/Onnx/AveragePool/AveragePoolSimple.json new file mode 100644 index 0000000..5a3eaf9 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/AveragePool/AveragePoolSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [0.5590057373046875, 0.2895050048828125, 0.8659210205078125, 0.2179107666015625, 0.13983154296875, 0.285003662109375, 0.647857666015625, 0.400665283203125, 0.2336273193359375, 0.773406982421875, 0.4894561767578125, 0.750244140625, 0.0911712646484375, 0.177703857421875, 0.7621002197265625, 0.5656890869140625, 0.5687103271484375, 0.983795166015625, 0.2562255859375, 0.002685546875, 0.967926025390625, 0.9023895263671875, 0.2940826416015625, 0.35479736328125, 0.98907470703125, 0.4078369140625, 0.5491485595703125, 0.6179046630859375, 0.481964111328125, 0.8272705078125, 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0.1280517578125, 0.5208892822265625, 0.5111083984375, 0.453857421875, 0.232086181640625, 0.1649017333984375, 0.2313690185546875, 0.0970916748046875, 0.3879852294921875, 0.24713134765625, 0.8818511962890625, 0.730316162109375, 0.4608306884765625, 0.200042724609375, 0.73870849609375, 0.557861328125, 0.5318145751953125, 0.8816680908203125, 0.5128936767578125, 0.2660675048828125, 0.14410400390625, 0.5460662841796875, 0.1490020751953125, 0.2237548828125, 0.877685546875, 0.806243896484375, 0.2261962890625, 0.555450439453125, 0.905792236328125, 0.20721435546875, 0.7978515625, 0.9395904541015625, 0.19537353515625, 0.3351898193359375, 0.0585479736328125, 0.8310699462890625, 0.98577880859375, 0.5617828369140625, 0.7138671875, 0.7102508544921875, 0.78662109375, 0.1346282958984375, 0.4747161865234375, 0.5204925537109375, 0.522064208984375, 0.4499359130859375, 0.2165374755859375, 0.87255859375, 0.9650421142578125, 0.013763427734375, 0.133453369140625, 0.9371490478515625, 0.274627685546875, 0.1803436279296875, 0.727447509765625, 0.040191650390625, 0.39801025390625, 0.70550537109375, 0.4818878173828125, 0.6094970703125, 0.260009765625, 0.4561767578125, 0.6441802978515625, 0.8063201904296875, 0.3227996826171875, 0.7526092529296875, 0.952117919921875, 0.3965911865234375, 0.832061767578125, 0.228515625, 0.130462646484375, 0.20184326171875, 0.5722808837890625], "dims": [1, 1, 28, 28], "type": "f32"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/AveragePool/AveragePoolSimple.onnx b/mlir-assigner/tests/Ops/Onnx/AveragePool/AveragePoolSimple.onnx new file mode 100644 index 0000000000000000000000000000000000000000..9bb625e2169911d30f9ffcabd42a576f12968a20 GIT binary patch literal 199 zcmd%7Hf`kOP*o#YwGE-8Ep^AhA xk&F(`%q_@Cjgo^}F2*Io!6+oa#l*n~#WFxzCP|(P;w&Ld1$;mSd`?UPA^_5CD&+tG literal 0 HcmV?d00001 diff --git a/mlir-assigner/tests/Ops/Onnx/AveragePool/AveragePoolSimple.res b/mlir-assigner/tests/Ops/Onnx/AveragePool/AveragePoolSimple.res new file mode 100644 index 0000000..c76109d --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/AveragePool/AveragePoolSimple.res @@ -0,0 +1,3 @@ +Result: +memref<1x1x14x14xf32>[0.5394363403320312, 0.4712028503417969, 0.21437835693359375, 0.4114646911621094, 0.5775413513183594, 0.7657814025878906, 0.28823089599609375, 0.7411727905273438, 0.6459312438964844, 0.3773193359375, 0.8365249633789062, 0.3866996765136719, 0.5719490051269531, 0.5062408447265625, 0.38759613037109375, 0.29695892333984375, 0.59033203125, 0.7469978332519531, 0.5867652893066406, 0.670379638671875, 0.4091072082519531, 0.5278167724609375, 0.3641815185546875, 0.5161476135253906, 0.5039215087890625, 0.5983505249023438, 0.47751617431640625, 0.47095489501953125, 0.36246490478515625, 0.6673431396484375, 0.3992195129394531, 0.4020576477050781, 0.6552505493164062, 0.6864280700683594, 0.5408668518066406, 0.65142822265625, 0.7032623291015625, 0.4016151428222656, 0.3031959533691406, 0.78173828125, 0.6719741821289062, 0.5572052001953125, 0.6043243408203125, 0.7353591918945312, 0.5729331970214844, 0.6805458068847656, 0.4591789245605469, 0.5109596252441406, 0.4050941467285156, 0.5183143615722656, 0.3124847412109375, 0.5170326232910156, 0.7779960632324219, 0.5478782653808594, 0.2559928894042969, 0.3593482971191406, 0.5884323120117188, 0.38454437255859375, 0.5208549499511719, 0.3499336242675781, 0.5894050598144531, 0.5909843444824219, 0.4623565673828125, 0.5927162170410156, 0.3062171936035156, 0.19814682006835938, 0.6034126281738281, 0.3755149841308594, 0.27564239501953125, 0.4769706726074219, 0.2569999694824219, 0.5887222290039062, 0.4218902587890625, 0.5553817749023438, 0.852508544921875, 0.6044464111328125, 0.3868370056152344, 0.6036376953125, 0.4734535217285156, 0.3287696838378906, 0.5876922607421875, 0.4459686279296875, 0.5128593444824219, 0.56353759765625, 0.4265708923339844, 0.4687461853027344, 0.4358482360839844, 0.5845108032226562, 0.4886741638183594, 0.39421844482421875, 0.36730194091796875, 0.6597709655761719, 0.3663787841796875, 0.46242523193359375, 0.19101715087890625, 0.4452018737792969, 0.5493354797363281, 0.4221000671386719, 0.6675910949707031, 0.4483299255371094, 0.7252006530761719, 0.475067138671875, 0.5752410888671875, 0.5490226745605469, 0.4223060607910156, 0.4676170349121094, 0.4823875427246094, 0.2901458740234375, 0.5686607360839844, 0.46788787841796875, 0.4866905212402344, 0.6320304870605469, 0.32891845703125, 0.3942108154296875, 0.39887237548828125, 0.293975830078125, 0.3845405578613281, 0.5002632141113281, 0.4890403747558594, 0.476806640625, 0.3865547180175781, 0.7099723815917969, 0.6193008422851562, 0.2971458435058594, 0.6474990844726562, 0.2936058044433594, 0.46205902099609375, 0.40016937255859375, 0.4792022705078125, 0.5056076049804688, 0.24171066284179688, 0.4054069519042969, 0.6818122863769531, 0.5042877197265625, 0.4996604919433594, 0.5294265747070312, 0.702056884765625, 0.42987060546875, 0.4325752258300781, 0.7164993286132812, 0.6866683959960938, 0.4599113464355469, 0.6934776306152344, 0.6852226257324219, 0.29973602294921875, 0.5356178283691406, 0.5708808898925781, 0.5976791381835938, 0.6354484558105469, 0.6656227111816406, 0.45171356201171875, 0.2944183349609375, 0.353546142578125, 0.5468597412109375, 0.7515449523925781, 0.8024330139160156, 0.4825439453125, 0.2822303771972656, 0.23249435424804688, 0.4272422790527344, 0.31919097900390625, 0.46389007568359375, 0.6377944946289062, 0.6670036315917969, 0.5799369812011719, 0.6646919250488281, 0.833221435546875, 0.8069267272949219, 0.5270195007324219, 0.5651321411132812, 0.5850753784179688, 0.5403785705566406, 0.25018310546875, 0.5947303771972656, 0.5947647094726562, 0.4994773864746094, 0.4501800537109375, 0.4654998779296875, 0.4146995544433594, 0.4080047607421875, 0.4835014343261719, 0.4703712463378906, 0.5152587890625, 0.5619430541992188, 0.2105712890625, 0.5783042907714844, 0.4850578308105469, 0.47486114501953125, 0.5481147766113281, 0.5011177062988281, 0.3735237121582031, 0.7364921569824219, 0.7450942993164062, 0.6813812255859375, 0.2420806884765625, 0.45417022705078125] +1372 diff --git a/mlir-assigner/tests/Ops/Onnx/Cos/CosSimple.json b/mlir-assigner/tests/Ops/Onnx/Cos/CosSimple.json new file mode 100644 index 0000000..ea199a2 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Cos/CosSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [0.304473876953125, 0.6345062255859375, 0.330474853515625, 0.9480438232421875, 0.813690185546875, 0.3028411865234375, 0.429534912109375, 0.5058135986328125, 0.5876007080078125, 0.666473388671875], "dims": [1, 10], "type": "f32"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/Cos/CosSimple.onnx b/mlir-assigner/tests/Ops/Onnx/Cos/CosSimple.onnx new file mode 100644 index 0000000..f9aee7a --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Cos/CosSimple.onnx @@ -0,0 +1,13 @@ + :P + +in_aout_a"Cos CosSimpleZ +in_a +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/Cos/CosSimple.res b/mlir-assigner/tests/Ops/Onnx/Cos/CosSimple.res new file mode 100644 index 0000000..d4c860b --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Cos/CosSimple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xf32>[0.9540048241615295, 0.8053644895553589, 0.945888340473175, 0.58327317237854, 0.6868209838867188, 0.95449298620224, 0.9091595411300659, 0.874780535697937, 0.8322731852531433, 0.7860067486763] +12 diff --git a/mlir-assigner/tests/Ops/Onnx/Cosh/CoshSimple.json b/mlir-assigner/tests/Ops/Onnx/Cosh/CoshSimple.json new file mode 100644 index 0000000..feab078 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Cosh/CoshSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [0.1055755615234375, 0.544708251953125, 0.6250457763671875, 0.039825439453125, 0.35162353515625, 0.773223876953125, 0.5823974609375, 0.0647125244140625, 0.04266357421875, 0.5506439208984375], "dims": [1, 10], "type": "f32"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/Cosh/CoshSimple.onnx b/mlir-assigner/tests/Ops/Onnx/Cosh/CoshSimple.onnx new file mode 100644 index 0000000..99b7ab1 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Cosh/CoshSimple.onnx @@ -0,0 +1,14 @@ + :R + +in_aout_a"Cosh +CoshSimpleZ +in_a +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/Cosh/CoshSimple.res b/mlir-assigner/tests/Ops/Onnx/Cosh/CoshSimple.res new file mode 100644 index 0000000..1af5bfa --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Cosh/CoshSimple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xf32>[1.0055782794952393, 1.1520581245422363, 1.2017841339111328, 1.000793218612671, 1.062459111213684, 1.3141316175460815, 1.1744415760040283, 1.0020946264266968, 1.0009102821350098, 1.1554739475250244] +60 diff --git a/mlir-assigner/tests/Ops/Onnx/Sin/SinSimple.json b/mlir-assigner/tests/Ops/Onnx/Sin/SinSimple.json new file mode 100644 index 0000000..4b14792 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Sin/SinSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [0.0673065185546875, 0.84857177734375, 0.3023834228515625, 0.5435638427734375, 0.0666046142578125, 0.1373443603515625, 0.163055419921875, 0.9552001953125, 0.96441650390625, 0.7205963134765625], "dims": [1, 10], "type": "f32"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/Sin/SinSimple.onnx b/mlir-assigner/tests/Ops/Onnx/Sin/SinSimple.onnx new file mode 100644 index 0000000..c26f00b --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Sin/SinSimple.onnx @@ -0,0 +1,13 @@ + :P + +in_aout_a"Sin SinSimpleZ +in_a +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/Sin/SinSimple.res b/mlir-assigner/tests/Ops/Onnx/Sin/SinSimple.res new file mode 100644 index 0000000..a9a17cd --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Sin/SinSimple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xf32>[0.06725571304559708, 0.7503370642662048, 0.2977963387966156, 0.5171894431114197, 0.06655538082122803, 0.1369129717350006, 0.16233384609222412, 0.8164293766021729, 0.8217165470123291, 0.6598328948020935] +12 diff --git a/mlir-assigner/tests/Ops/Onnx/Sinh/SinhSimple.json b/mlir-assigner/tests/Ops/Onnx/Sinh/SinhSimple.json new file mode 100644 index 0000000..865ac37 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Sinh/SinhSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [0.8580322265625, 0.5621490478515625, 0.566253662109375, 0.83184814453125, 0.663787841796875, 0.2048492431640625, 0.304443359375, 0.43353271484375, 0.0232086181640625, 0.235595703125], "dims": [1, 10], "type": "f32"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/Sinh/SinhSimple.onnx b/mlir-assigner/tests/Ops/Onnx/Sinh/SinhSimple.onnx new file mode 100644 index 0000000..b5d61b9 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Sinh/SinhSimple.onnx @@ -0,0 +1,14 @@ + :R + +in_aout_a"Sinh +SinhSimpleZ +in_a +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/Sinh/SinhSimple.res b/mlir-assigner/tests/Ops/Onnx/Sinh/SinhSimple.res new file mode 100644 index 0000000..4806e74 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Sinh/SinhSimple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xf32>[0.9672597050666809, 0.5922280550003052, 0.5970034599304199, 0.9311584234237671, 0.7136188745498657, 0.20628491044044495, 0.30916810035705566, 0.44724133610725403, 0.02321070432662964, 0.23778125643730164] +60 diff --git a/mlir-assigner/tests/run.py b/mlir-assigner/tests/run.py index 320ad17..b8a29d0 100644 --- a/mlir-assigner/tests/run.py +++ b/mlir-assigner/tests/run.py @@ -205,6 +205,7 @@ def test_folder(test_suite, folder, mlir_tests, timeout, verbose, keep_mlir): parser.add_argument('--fast', action='store_true', help='Run fast tests only') parser.add_argument('--verbose', action='store_true', help='Print detailed output') parser.add_argument('--keep-mlir', action='store_true', help='Keep generated mlir files') +parser.add_argument('--current', action='store_true', help='do only the current folder') args = parser.parse_args() @@ -213,11 +214,13 @@ def test_folder(test_suite, folder, mlir_tests, timeout, verbose, keep_mlir): else: slow_test = True -test_folder("SingleOps E2E", "mlir-assigner/tests/Ops/Onnx", False, 30, args.verbose, args.keep_mlir) -test_folder("SingleOps special MLIR", "mlir-assigner/tests/Ops/Mlir", True, 30, args.verbose, args.keep_mlir) -#test_folder("SingleOps E2E", "mlir-assigner/tests/Ops/Current", False, 30, args.verbose, args.keep_mlir) -if slow_test: - test_folder("Models", "mlir-assigner/tests/Models/", False, 500, args.verbose, args.keep_mlir) +if args.current: + test_folder("SingleOps E2E", "mlir-assigner/tests/Ops/Current", False, 30, args.verbose, args.keep_mlir) +else: + test_folder("SingleOps E2E", "mlir-assigner/tests/Ops/Onnx", False, 30, args.verbose, args.keep_mlir) + test_folder("SingleOps special MLIR", "mlir-assigner/tests/Ops/Mlir", True, 30, args.verbose, args.keep_mlir) + if slow_test: + test_folder("Models", "mlir-assigner/tests/Models/", False, 500, args.verbose, args.keep_mlir) # cleanup if isfile("circuit"):