diff --git a/libs/blueprint b/libs/blueprint index ef8edc2..577e409 160000 --- a/libs/blueprint +++ b/libs/blueprint @@ -1 +1 @@ -Subproject commit ef8edc2dff613774eb5266ded434b7ee140034f9 +Subproject commit 577e409518edcf1e29dbb03a36b92b53a0fd003e diff --git a/mlir-assigner/include/mlir-assigner/components/boolean/logic_ops.hpp b/mlir-assigner/include/mlir-assigner/components/boolean/logic_ops.hpp index 2e421f5..578ca2c 100644 --- a/mlir-assigner/include/mlir-assigner/components/boolean/logic_ops.hpp +++ b/mlir-assigner/include/mlir-assigner/components/boolean/logic_ops.hpp @@ -25,6 +25,7 @@ #ifndef CRYPTO3_ASSIGNER_AND_HPP #define CRYPTO3_ASSIGNER_AND_HPP +#include #include #include @@ -51,7 +52,15 @@ namespace nil { using component_type = components::lookup_logic_and< crypto3::zk::snark::plonk_constraint_system>; - auto input = PREPARE_BINARY_INPUT(mlir::arith::AndIOp); + auto lhs = frame.locals.find(mlir::hash_value(operation.getLhs())); + auto rhs = frame.locals.find(mlir::hash_value(operation.getRhs())); + ASSERT(lhs != frame.locals.end()); + ASSERT(rhs != frame.locals.end()); + + typename component_type::input_type input; + input.input[0] = lhs->second; + input.input[1] = rhs->second; + const auto p = detail::PolicyManager::get_parameters( detail::ManifestReader::get_witness(0)); @@ -70,17 +79,8 @@ namespace nil { std::uint32_t start_row) { using component_type = components::logic_or_flag< crypto3::zk::snark::plonk_constraint_system>; - using input_type = typename component_type::input_type; - auto lhs = frame.locals.find(mlir::hash_value(operation.getLhs())); - auto rhs = frame.locals.find(mlir::hash_value(operation.getRhs())); - ASSERT(lhs != frame.locals.end()); - ASSERT(rhs != frame.locals.end()); - - input_type input; - input.x = lhs->second; - input.y = rhs->second; - const auto p = detail::PolicyManager::get_parameters( + auto input = PREPARE_BINARY_INPUT(mlir::arith::OrIOp) const auto p = detail::PolicyManager::get_parameters( detail::ManifestReader::get_witness(0)); using manifest_reader = detail::ManifestReader; component_type component(p.witness, manifest_reader::get_constants(), manifest_reader::get_public_inputs()); @@ -98,7 +98,14 @@ namespace nil { using component_type = components::lookup_logic_xor< crypto3::zk::snark::plonk_constraint_system>; - auto input = PREPARE_BINARY_INPUT(mlir::arith::XOrIOp); + auto lhs = frame.locals.find(mlir::hash_value(operation.getLhs())); + auto rhs = frame.locals.find(mlir::hash_value(operation.getRhs())); + ASSERT(lhs != frame.locals.end()); + ASSERT(rhs != frame.locals.end()); + + typename component_type::input_type input; + input.input[0] = lhs->second; + input.input[1] = rhs->second; const auto p = detail::PolicyManager::get_parameters( detail::ManifestReader::get_witness(0)); @@ -107,6 +114,72 @@ namespace nil { fill_trace(component, input, operation, frame, bp, assignment, start_row); } + template + void handle_bitwise_and( + mlir::arith::AndIOp &operation, + stack_frame> &frame, + circuit_proxy> &bp, + assignment_proxy> + &assignment, + std::uint32_t start_row) { + using component_type = components::bitwise_and< + crypto3::zk::snark::plonk_constraint_system, + BlueprintFieldType, + basic_non_native_policy>; + using manifest_reader = detail::ManifestReader; + + auto input = PREPARE_BINARY_INPUT(mlir::arith::AndIOp); + const auto p = detail::PolicyManager::get_parameters(manifest_reader::get_witness(0, m)); + + component_type component( + p.witness, manifest_reader::get_constants(), manifest_reader::get_public_inputs(), m); + fill_trace(component, input, operation, frame, bp, assignment, start_row); + } + + template + void handle_bitwise_or( + mlir::arith::OrIOp &operation, + stack_frame> &frame, + circuit_proxy> &bp, + assignment_proxy> + &assignment, + std::uint32_t start_row) { + using component_type = components::bitwise_or< + crypto3::zk::snark::plonk_constraint_system, + BlueprintFieldType, + basic_non_native_policy>; + using manifest_reader = detail::ManifestReader; + + auto input = PREPARE_BINARY_INPUT(mlir::arith::OrIOp); + const auto p = detail::PolicyManager::get_parameters(manifest_reader::get_witness(0, m)); + + component_type component( + p.witness, manifest_reader::get_constants(), manifest_reader::get_public_inputs(), m); + fill_trace(component, input, operation, frame, bp, assignment, start_row); + } + + template + void handle_bitwise_xor( + mlir::arith::XOrIOp &operation, + stack_frame> &frame, + circuit_proxy> &bp, + assignment_proxy> + &assignment, + std::uint32_t start_row) { + using component_type = components::bitwise_xor< + crypto3::zk::snark::plonk_constraint_system, + BlueprintFieldType, + basic_non_native_policy>; + using manifest_reader = detail::ManifestReader; + + auto input = PREPARE_BINARY_INPUT(mlir::arith::XOrIOp); + const auto p = detail::PolicyManager::get_parameters(manifest_reader::get_witness(0, m)); + + component_type component( + p.witness, manifest_reader::get_constants(), manifest_reader::get_public_inputs(), m); + fill_trace(component, input, operation, frame, bp, assignment, start_row); + } + } // namespace blueprint } // namespace nil diff --git a/mlir-assigner/include/mlir-assigner/components/handle_component.hpp b/mlir-assigner/include/mlir-assigner/components/handle_component.hpp index 0a6bb08..93c6e1c 100644 --- a/mlir-assigner/include/mlir-assigner/components/handle_component.hpp +++ b/mlir-assigner/include/mlir-assigner/components/handle_component.hpp @@ -37,6 +37,9 @@ #include #include #include +#include +#include +#include #include #include @@ -75,19 +78,17 @@ namespace nil { &assignment) { auto lhs = frame.locals.find(mlir::hash_value(operation.getLhs())); - ASSERT(lhs != frame.locals.end()); auto rhs = frame.locals.find(mlir::hash_value(operation.getRhs())); + ASSERT(lhs != frame.locals.end()); ASSERT(rhs != frame.locals.end()); - auto x = lhs->second; - auto y = rhs->second; - input_type instance_input; - instance_input.input[0] = x; - instance_input.input[1] = y; + instance_input.x = lhs->second; + instance_input.y = rhs->second; return instance_input; } + template void handle_component_input( assignment_proxy> diff --git a/mlir-assigner/include/mlir-assigner/parser/evaluator.hpp b/mlir-assigner/include/mlir-assigner/parser/evaluator.hpp index 0332d4d..30a429a 100644 --- a/mlir-assigner/include/mlir-assigner/parser/evaluator.hpp +++ b/mlir-assigner/include/mlir-assigner/parser/evaluator.hpp @@ -271,6 +271,24 @@ namespace zk_ml_toolchain { // std::cout << toFixpoint(Lhs) << " * " << toFixpoint(Rhs) << " = " << toFixpoint(Result) << "\n"; } +#define BITSWITCHER(func, b) \ + switch (b) { \ + case 8: \ + func<1>(operation, frames.back(), bp, assignmnt, start_row); \ + break; \ + case 16: \ + func<2>(operation, frames.back(), bp, assignmnt, start_row); \ + break; \ + case 32: \ + func<4>(operation, frames.back(), bp, assignmnt, start_row); \ + break; \ + case 64: \ + func<8>(operation, frames.back(), bp, assignmnt, start_row); \ + break; \ + default: \ + UNREACHABLE(std::string("unsupported int bit size for bitwise op: ") + std::to_string(b)); \ + } + void handleArithOperation(Operation *op) { std::uint32_t start_row = assignmnt.allocated_rows(); if (arith::AddFOp operation = llvm::dyn_cast(op)) { @@ -332,10 +350,11 @@ namespace zk_ml_toolchain { mlir::Type LhsType = operation.getLhs().getType(); mlir::Type RhsType = operation.getRhs().getType(); assert(LhsType == RhsType && "must be same type for AndIOp"); - if (LhsType.getIntOrFloatBitWidth() == 1) { + uint8_t bits = LhsType.getIntOrFloatBitWidth(); + if (1 == bits) { handle_logic_and(operation, frames.back(), bp, assignmnt, start_row); } else { - UNREACHABLE("TODO add Bitwise And Gadget"); + BITSWITCHER(handle_bitwise_and, bits); } } else if (arith::OrIOp operation = llvm::dyn_cast(op)) { ASSERT(operation.getNumOperands() == 2 && "Or must have two operands"); @@ -355,10 +374,11 @@ namespace zk_ml_toolchain { mlir::Type LhsType = operation.getLhs().getType(); mlir::Type RhsType = operation.getRhs().getType(); assert(LhsType == RhsType && "must be same type for OrIOp"); - if (LhsType.getIntOrFloatBitWidth() == 1) { + unsigned bits = LhsType.getIntOrFloatBitWidth(); + if (1 == bits) { handle_logic_or(operation, frames.back(), bp, assignmnt, start_row); } else { - UNREACHABLE("TODO add Bitwise Or Gadget"); + BITSWITCHER(handle_bitwise_or, bits); } } } else if (arith::XOrIOp operation = llvm::dyn_cast(op)) { @@ -366,10 +386,11 @@ namespace zk_ml_toolchain { mlir::Type LhsType = operation.getLhs().getType(); mlir::Type RhsType = operation.getRhs().getType(); assert(LhsType == RhsType && "must be same type for XOrIOp"); - if (LhsType.getIntOrFloatBitWidth() == 1) { + unsigned bits = LhsType.getIntOrFloatBitWidth(); + if (1 == bits) { handle_logic_xor(operation, frames.back(), bp, assignmnt, start_row); } else { - UNREACHABLE("TODO add Bitwise XOr Gadget"); + BITSWITCHER(handle_bitwise_xor, bits); } } else if (arith::AddIOp operation = llvm::dyn_cast(op)) { // TODO: ATM, handle only the case where we work on indices that are @@ -524,6 +545,7 @@ namespace zk_ml_toolchain { UNREACHABLE(std::string("unhandled arith operation: ") + opName); } } +#undef BITSWITCHER void handleMathOperation(Operation *op) { std::uint32_t start_row = assignmnt.allocated_rows(); diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseAnd/BitwiseAndSimple.json b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseAnd/BitwiseAndSimple.json deleted file mode 100644 index d6cc240..0000000 --- a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseAnd/BitwiseAndSimple.json +++ /dev/null @@ -1 +0,0 @@ -[{"memref": {"data": [-17364, -5917, 20048, -5966, 26954, -27667, -5752, -18323, -27730, 3267], "dims": [1, 10], "type": "int"}}, {"memref": {"data": [12595, 478, 29202, -11821, -3991, 7786, 14699, 5733, -27202, 14058], "dims": [1, 10], "type": "int"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseAnd/BitwiseAndSimple.res b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseAnd/BitwiseAndSimple.res deleted file mode 100644 index 2de0d62..0000000 --- a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseAnd/BitwiseAndSimple.res +++ /dev/null @@ -1,3 +0,0 @@ -Result: -memref<1x10xint>[12320, 194, 16912, -16238, 24648, 4712, 10504, 4197, -28242, 1218] -ADD THE ROWS HERE \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseOr/BitwiseOrSimple.json b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseOr/BitwiseOrSimple.json deleted file mode 100644 index e2c5c34..0000000 --- a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseOr/BitwiseOrSimple.json +++ /dev/null @@ -1 +0,0 @@ -[{"memref": {"data": [17404, 12269, -2971, -24378, 29836, 52, 11050, 27899, -32318, 8698], "dims": [1, 10], "type": "int"}}, {"memref": {"data": [8593, 11402, -2385, 5229, -18463, 10748, -30730, 25091, 22130, -14765], "dims": [1, 10], "type": "int"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseOr/BitwiseOrSimple.res b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseOr/BitwiseOrSimple.res deleted file mode 100644 index ca35d2a..0000000 --- a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseOr/BitwiseOrSimple.res +++ /dev/null @@ -1,3 +0,0 @@ -Result: -memref<1x10xint>[25597, 12271, -2321, -19217, -2067, 10748, -20482, 28411, -10254, -6149] -ADD THE ROWS HERE \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseXor/BitwiseXorSimple.json b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseXor/BitwiseXorSimple.json deleted file mode 100644 index 54a8f9c..0000000 --- a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseXor/BitwiseXorSimple.json +++ /dev/null @@ -1 +0,0 @@ -[{"memref": {"data": [-11526, 25091, -17049, 22557, -15341, 9387, 6169, -3828, -21288, 22372], "dims": [1, 10], "type": "int"}}, {"memref": {"data": [-7542, -25840, -7075, 23653, 27243, -16232, 32027, 2937, -4794, -7927], "dims": [1, 10], "type": "int"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseXor/BitwiseXorSimple.res b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseXor/BitwiseXorSimple.res deleted file mode 100644 index d427120..0000000 --- a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseXor/BitwiseXorSimple.res +++ /dev/null @@ -1,3 +0,0 @@ -Result: -memref<1x10xint>[12400, -1773, 22842, 1144, -20872, -7117, 25858, -1419, 16798, -18835] -ADD THE ROWS HERE \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI16Simple.json b/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI16Simple.json new file mode 100644 index 0000000..494c51d --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI16Simple.json @@ -0,0 +1 @@ +[{"memref": {"data": [-23105, 19325, 20849, -30787, -28574, 6400, -17468, -25069, -3772, -5585], "dims": [1, 10], "type": "int"}}, {"memref": {"data": [12315, -8527, -15259, -2999, 26965, -9250, -9078, 9823, -13382, -24594], "dims": [1, 10], "type": "int"}}] diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI16Simple.onnx b/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI16Simple.onnx new file mode 100644 index 0000000..2bd174e --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI16Simple.onnx @@ -0,0 +1,20 @@ + : + +in_a +in_bout_a" +BitwiseAndBitwiseAndI16SimpleZ +in_a +  + + +Z +in_b +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI16Simple.res b/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI16Simple.res new file mode 100644 index 0000000..82d501b --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI16Simple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xi16>[8219, 18993, 16481, -31735, 64, 6400, -26496, 1555, -16128, -30162] +22 diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI32Simple.json b/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI32Simple.json new file mode 100644 index 0000000..1b8e863 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI32Simple.json @@ -0,0 +1 @@ +[{"memref": {"data": [-17405, -6334, 17342, -2390, 11827, -4355, 97, 24390, 5832, 21905], "dims": [1, 10], "type": "int"}}, {"memref": {"data": [18283, 12705, -22076, 23371, -15509, -21397, 857, -24556, -30933, -31965], "dims": [1, 10], "type": "int"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseAnd/BitwiseAndSimple.onnx b/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI32Simple.onnx similarity index 71% rename from mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseAnd/BitwiseAndSimple.onnx rename to mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI32Simple.onnx index 95c7b99..b8aac8b 100644 --- a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseAnd/BitwiseAndSimple.onnx +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI32Simple.onnx @@ -1,8 +1,8 @@ - :| + :  in_a in_bout_a" -BitwiseAndBitwiseAndSimpleZ +BitwiseAndBitwiseAndI32SimpleZ in_a   diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI32Simple.res b/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI32Simple.res new file mode 100644 index 0000000..15afe25 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI32Simple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xi32>[1027, 8448, 388, 21002, 547, -21399, 65, 4, 1544, 257] +22 diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI64Simple.json b/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI64Simple.json new file mode 100644 index 0000000..ab36521 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI64Simple.json @@ -0,0 +1 @@ +[{"memref": {"data": [-31058, 24103, 20613, -14245, 30834, -9972, -16062, 24153, 6507, -2612], "dims": [1, 10], "type": "int"}}, {"memref": {"data": [-5647, 8761, -16974, -18729, 26300, -32249, 2301, -19788, 27028, -9132], "dims": [1, 10], "type": "int"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI64Simple.onnx b/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI64Simple.onnx new file mode 100644 index 0000000..6091b5a --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI64Simple.onnx @@ -0,0 +1,20 @@ + : + +in_a +in_bout_a" +BitwiseAndBitwiseAndI64SimpleZ +in_a +  + + +Z +in_b +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI64Simple.res b/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI64Simple.res new file mode 100644 index 0000000..d70e298 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI64Simple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xi64>[-32608, 545, 4224, -32685, 24624, -32764, 64, 4624, 2304, -11196] +22 diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI8Simple.json b/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI8Simple.json new file mode 100644 index 0000000..6e1b58d --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI8Simple.json @@ -0,0 +1 @@ +[{"memref": {"data": [-99, 68, 14, -106, 31, 114, 45, 30, 35, 50], "dims": [1, 10], "type": "int"}}, {"memref": {"data": [51, 77, 19, -123, 102, -44, -103, -7, 84, -105], "dims": [1, 10], "type": "int"}}] diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI8Simple.onnx b/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI8Simple.onnx new file mode 100644 index 0000000..5ba09b1 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI8Simple.onnx @@ -0,0 +1,20 @@ + :~ + +in_a +in_bout_a" +BitwiseAndBitwiseAndI8SimpleZ +in_a +  + + +Z +in_b +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI8Simple.res b/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI8Simple.res new file mode 100644 index 0000000..f0c0d11 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseAnd/BitwiseAndI8Simple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xi8>[17, 68, 2, -124, 6, 80, 9, 24, 0, 18] +22 diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI16Simple.json b/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI16Simple.json new file mode 100644 index 0000000..494c51d --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI16Simple.json @@ -0,0 +1 @@ +[{"memref": {"data": [-23105, 19325, 20849, -30787, -28574, 6400, -17468, -25069, -3772, -5585], "dims": [1, 10], "type": "int"}}, {"memref": {"data": [12315, -8527, -15259, -2999, 26965, -9250, -9078, 9823, -13382, -24594], "dims": [1, 10], "type": "int"}}] diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI16Simple.onnx b/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI16Simple.onnx new file mode 100644 index 0000000..2a43db6 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI16Simple.onnx @@ -0,0 +1,19 @@ + :} + +in_a +in_bout_a" BitwiseOrBitwiseOrI16SimpleZ +in_a +  + + +Z +in_b +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI16Simple.res b/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI16Simple.res new file mode 100644 index 0000000..891d882 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI16Simple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xi16>[-19009, -8195, -10891, -2051, -1673, -9250, -50, -16801, -1026, -17] +22 diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI32Simple.json b/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI32Simple.json new file mode 100644 index 0000000..9eb3ec5 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI32Simple.json @@ -0,0 +1 @@ +[{"memref": {"data": [-21077, -28282, -13936, -25859, 6844, -5718, -31330, 11094, -10612, 16281], "dims": [1, 10], "type": "int"}}, {"memref": {"data": [29882, 22273, -26978, 31387, 28800, 14063, 5075, 8593, -24531, 11358], "dims": [1, 10], "type": "int"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseOr/BitwiseOrSimple.onnx b/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI32Simple.onnx similarity index 61% rename from mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseOr/BitwiseOrSimple.onnx rename to mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI32Simple.onnx index 251f0f1..a8cef11 100644 --- a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseOr/BitwiseOrSimple.onnx +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI32Simple.onnx @@ -1,7 +1,7 @@ - :z + :}  in_a -in_bout_a" BitwiseOrBitwiseOrSimpleZ +in_bout_a" BitwiseOrBitwiseOrI32SimpleZ in_a   diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI32Simple.res b/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI32Simple.res new file mode 100644 index 0000000..f182558 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI32Simple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xi32>[-581, -10361, -8290, -1281, 31420, -17, -26657, 11223, -2387, 16351] +22 diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI64Simple.json b/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI64Simple.json new file mode 100644 index 0000000..1738ec9 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI64Simple.json @@ -0,0 +1 @@ +[{"memref": {"data": [24523, -10783, 15862, 18854, -4117, 15225, 20517, -12891, -4529, 29071], "dims": [1, 10], "type": "int"}}, {"memref": {"data": [17488, 15891, 1551, 8247, -19340, 19990, 8792, -9165, 10042, -32019], "dims": [1, 10], "type": "int"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI64Simple.onnx b/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI64Simple.onnx new file mode 100644 index 0000000..c54a96f --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI64Simple.onnx @@ -0,0 +1,19 @@ + :} + +in_a +in_bout_a" BitwiseOrBitwiseOrI64SimpleZ +in_a +  + + +Z +in_b +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI64Simple.res b/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI64Simple.res new file mode 100644 index 0000000..1475c8a --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI64Simple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xi64>[24539, -13, 16383, 27063, -1, 32639, 29309, -8777, -4225, -3089] +22 diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI8Simple.json b/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI8Simple.json new file mode 100644 index 0000000..6e1b58d --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI8Simple.json @@ -0,0 +1 @@ +[{"memref": {"data": [-99, 68, 14, -106, 31, 114, 45, 30, 35, 50], "dims": [1, 10], "type": "int"}}, {"memref": {"data": [51, 77, 19, -123, 102, -44, -103, -7, 84, -105], "dims": [1, 10], "type": "int"}}] diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI8Simple.onnx b/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI8Simple.onnx new file mode 100644 index 0000000..face160 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI8Simple.onnx @@ -0,0 +1,19 @@ + :| + +in_a +in_bout_a" BitwiseOrBitwiseOrI8SimpleZ +in_a +  + + +Z +in_b +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI8Simple.res b/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI8Simple.res new file mode 100644 index 0000000..aec983f --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseOr/BitwiseOrI8Simple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xi8>[-65, 77, 31, -105, 127, -10, -67, -1, 119, -73] +22 diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI16Simple.json b/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI16Simple.json new file mode 100644 index 0000000..494c51d --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI16Simple.json @@ -0,0 +1 @@ +[{"memref": {"data": [-23105, 19325, 20849, -30787, -28574, 6400, -17468, -25069, -3772, -5585], "dims": [1, 10], "type": "int"}}, {"memref": {"data": [12315, -8527, -15259, -2999, 26965, -9250, -9078, 9823, -13382, -24594], "dims": [1, 10], "type": "int"}}] diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI16Simple.onnx b/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI16Simple.onnx new file mode 100644 index 0000000..fb024a4 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI16Simple.onnx @@ -0,0 +1,20 @@ + : + +in_a +in_bout_a" +BitwiseXorBitwiseXorI16SimpleZ +in_a +  + + +Z +in_b +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI16Simple.res b/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI16Simple.res new file mode 100644 index 0000000..2694f0b --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI16Simple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xi16>[-27228, -27188, -27372, 29684, -1737, -15650, 26446, -18356, 15102, 30145] +22 diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI32Simple.json b/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI32Simple.json new file mode 100644 index 0000000..5b114d2 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI32Simple.json @@ -0,0 +1 @@ +[{"memref": {"data": [-2088, 11489, -10429, -22307, -28558, -21018, -125, 7395, -29350, 32250], "dims": [1, 10], "type": "int"}}, {"memref": {"data": [-32673, 28392, 29021, -22019, 24368, -6239, -8300, -17246, -13522, -28723], "dims": [1, 10], "type": "int"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseXor/BitwiseXorSimple.onnx b/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI32Simple.onnx similarity index 71% rename from mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseXor/BitwiseXorSimple.onnx rename to mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI32Simple.onnx index b792c6e..b218d12 100644 --- a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseXor/BitwiseXorSimple.onnx +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI32Simple.onnx @@ -1,8 +1,8 @@ - :| + :  in_a in_bout_a" -BitwiseXorBitwiseXorSimpleZ +BitwiseXorBitwiseXorI32SimpleZ in_a   diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI32Simple.res b/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI32Simple.res new file mode 100644 index 0000000..dcaeb17 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI32Simple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xi32>[30599, 16905, -23010, 288, -12478, 19015, 8215, -24511, 18036, -3529] +22 diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI64Simple.json b/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI64Simple.json new file mode 100644 index 0000000..68a8e40 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI64Simple.json @@ -0,0 +1 @@ +[{"memref": {"data": [-32300, 2629, 3073, -30492, -6461, 430, 15663, 3460, 7602, -16883], "dims": [1, 10], "type": "int"}}, {"memref": {"data": [11598, 3180, -19196, 17178, 11200, 29567, 18581, 32459, 20509, -12456], "dims": [1, 10], "type": "int"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI64Simple.onnx b/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI64Simple.onnx new file mode 100644 index 0000000..cd87464 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI64Simple.onnx @@ -0,0 +1,20 @@ + : + +in_a +in_bout_a" +BitwiseXorBitwiseXorI64SimpleZ +in_a +  + + +Z +in_b +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI64Simple.res b/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI64Simple.res new file mode 100644 index 0000000..8d720e7 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI64Simple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xi64>[-21350, 1577, -18171, -13314, -13053, 29393, 30138, 29519, 19887, 29013] +22 diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI8Simple.json b/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI8Simple.json new file mode 100644 index 0000000..6e1b58d --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI8Simple.json @@ -0,0 +1 @@ +[{"memref": {"data": [-99, 68, 14, -106, 31, 114, 45, 30, 35, 50], "dims": [1, 10], "type": "int"}}, {"memref": {"data": [51, 77, 19, -123, 102, -44, -103, -7, 84, -105], "dims": [1, 10], "type": "int"}}] diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI8Simple.onnx b/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI8Simple.onnx new file mode 100644 index 0000000..ec272a7 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI8Simple.onnx @@ -0,0 +1,20 @@ + :~ + +in_a +in_bout_a" +BitwiseXorBitwiseXorI8SimpleZ +in_a +  + + +Z +in_b +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI8Simple.res b/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI8Simple.res new file mode 100644 index 0000000..47f8dcc --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/BitwiseXor/BitwiseXorI8Simple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xi8>[-82, 9, 29, 19, 121, -90, -76, -25, 119, -91] +22