diff --git a/mlir-assigner/include/mlir-assigner/components/boolean/and.hpp b/mlir-assigner/include/mlir-assigner/components/boolean/and.hpp new file mode 100644 index 0000000..4ae51ff --- /dev/null +++ b/mlir-assigner/include/mlir-assigner/components/boolean/and.hpp @@ -0,0 +1,105 @@ +//---------------------------------------------------------------------------// +// Copyright (c) 2023 Nikita Kaskov +// +// MIT License +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +// SOFTWARE. +//---------------------------------------------------------------------------// + +#ifndef CRYPTO3_ASSIGNER_AND_HPP +#define CRYPTO3_ASSIGNER_AND_HPP + +#include + +#include + +#include +#include +#include +#include // TODO: check if there is a new mechanism for this in nil upstream + +#include +#include +#include + +namespace nil { + namespace blueprint { + template + void handle_logic_and( + mlir::arith::AndIOp &operation, + stack_frame> &frame, + circuit_proxy> &bp, + assignment_proxy> + &assignment, + std::uint32_t start_row) { + using component_type = components::lookup_logic_and< + crypto3::zk::snark::plonk_constraint_system>; + + auto input = PREPARE_INPUT(mlir::arith::AndIOp); + const auto p = detail::PolicyManager::get_parameters( + detail::ManifestReader::get_witness(0)); + + component_type component(p.witness); + fill_trace(component, input, operation, frame, bp, assignment, start_row); + } + + template + void handle_logic_or( + mlir::arith::OrIOp &operation, + stack_frame> &frame, + circuit_proxy> &bp, + assignment_proxy> + &assignment, + std::uint32_t start_row) { + //FIXME logic_or is commented out. As soon as it is enabled, remove add the liens above and it SHOULD work + UNREACHABLE("LogicOR not enabled in blueprint"); + // using component_type = components::lookup_logic_or< + // crypto3::zk::snark::plonk_constraint_system>; + // + // auto input = PREPARE_INPUT(mlir::arith::OrIOp); + // const auto p = detail::PolicyManager::get_parameters( + // detail::ManifestReader::get_witness(0)); + // + // component_type component(p.witness); + // fill_trace(component, input, operation, frame, bp, assignment, start_row); + } + + template + void handle_logic_xor( + mlir::arith::XOrIOp &operation, + stack_frame> &frame, + circuit_proxy> &bp, + assignment_proxy> + &assignment, + std::uint32_t start_row) { + using component_type = components::lookup_logic_xor< + crypto3::zk::snark::plonk_constraint_system>; + + auto input = PREPARE_INPUT(mlir::arith::XOrIOp); + const auto p = detail::PolicyManager::get_parameters( + detail::ManifestReader::get_witness(0)); + + component_type component(p.witness); + fill_trace(component, input, operation, frame, bp, assignment, start_row); + } + + } // namespace blueprint +} // namespace nil + +#endif // CRYPTO3_ASSIGNER_LOGIC_OPS_HPP diff --git a/mlir-assigner/include/mlir-assigner/components/fixedpoint/dot_product.hpp b/mlir-assigner/include/mlir-assigner/components/fixedpoint/dot_product.hpp index d9895b4..bc1ce59 100644 --- a/mlir-assigner/include/mlir-assigner/components/fixedpoint/dot_product.hpp +++ b/mlir-assigner/include/mlir-assigner/components/fixedpoint/dot_product.hpp @@ -14,8 +14,6 @@ #include #include -#include - namespace nil { namespace blueprint { namespace detail { diff --git a/mlir-assigner/include/mlir-assigner/components/handle_component.hpp b/mlir-assigner/include/mlir-assigner/components/handle_component.hpp new file mode 100644 index 0000000..602a6eb --- /dev/null +++ b/mlir-assigner/include/mlir-assigner/components/handle_component.hpp @@ -0,0 +1,117 @@ + +//---------------------------------------------------------------------------// +// Copyright (c) 2023 Nikita Kaskov +// +// MIT License +// +// Permission is hereby granted, free of charge, to any person obtaining a copy +// of this software and associated documentation files (the "Software"), to deal +// in the Software without restriction, including without limitation the rights +// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +// copies of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all +// copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +// SOFTWARE. +//---------------------------------------------------------------------------// + +#ifndef CRYPTO3_ASSIGNER_HANDLE_COMPONENT_HPP +#define CRYPTO3_ASSIGNER_HANDLE_COMPONENT_HPP + +#define PREPARE_INPUT(OP) \ + prepare_binary_operation_input(operation, frame, bp, assignment); + +#include +namespace nil { + namespace blueprint { + template + input_type prepare_binary_operation_input( + BinOp &operation, + stack_frame> &frame, + circuit_proxy> &bp, + assignment_proxy> + &assignment) { + + auto lhs = frame.locals.find(mlir::hash_value(operation.getLhs())); + ASSERT(lhs != frame.locals.end()); + auto rhs = frame.locals.find(mlir::hash_value(operation.getRhs())); + ASSERT(rhs != frame.locals.end()); + + auto x = lhs->second; + auto y = rhs->second; + + input_type instance_input; + instance_input.input[0] = x; + instance_input.input[1] = y; + return instance_input; + } + + template + void handle_component_input( + assignment_proxy> + &assignment, + typename ComponentType::input_type &instance_input) { + + using var = crypto3::zk::snark::plonk_variable; + + std::vector all_vars = instance_input.all_vars(); + std::vector> input(all_vars.begin(), all_vars.end()); + const auto &used_rows = assignment.get_used_rows(); + + for (auto &v : input) { + bool found = (used_rows.find(v.get().rotation) != used_rows.end()); + if (!found && + (v.get().type == var::column_type::witness || v.get().type == var::column_type::constant)) { + const auto new_v = save_shared_var(assignment, v); + v.get().index = new_v.index; + v.get().rotation = new_v.rotation; + v.get().relative = new_v.relative; + v.get().type = new_v.type; + } + } + } + + template + void fill_trace( + component_type &component, + typename component_type::input_type &input, + BinOp &mlir_op, + stack_frame> &frame, + circuit_proxy> &bp, + assignment_proxy> + &assignment, + std::uint32_t start_row) { + + if constexpr (nil::blueprint::use_custom_lookup_tables()) { + auto lookup_tables = component.component_custom_lookup_tables(); + for (auto &t : lookup_tables) { + bp.register_lookup_table( + std::shared_ptr>(t)); + } + }; + + if constexpr (nil::blueprint::use_lookups()) { + auto lookup_tables = component.component_lookup_tables(); + for (auto &[k, v] : lookup_tables) { + bp.reserve_table(k); + } + }; + + handle_component_input(assignment, input); + + components::generate_circuit(component, bp, assignment, input, start_row); + auto result = components::generate_assignments(component, assignment, input, start_row); + frame.locals[mlir::hash_value(mlir_op.getResult())] = result.output; + } + } // namespace blueprint +} // namespace nil +#endif // CRYPTO3_ASSIGNER_HANDLE_COMPONENT_HPP diff --git a/mlir-assigner/include/mlir-assigner/memory/memref.hpp b/mlir-assigner/include/mlir-assigner/memory/memref.hpp index f6d920d..4d670b0 100644 --- a/mlir-assigner/include/mlir-assigner/memory/memref.hpp +++ b/mlir-assigner/include/mlir-assigner/memory/memref.hpp @@ -100,7 +100,7 @@ namespace nil { template void print( - llvm::raw_ostream &os, + std::ostream& os, const assignment> &assignment) { os << "memref<"; @@ -108,13 +108,29 @@ namespace nil { os << dims[i]; os << "x"; } - os << type << ">["; - for (int i = 0; i < data.size(); i++) { - auto value = var_value(assignment, data[i]).data; - components::FixedPoint out(value, 16); - os << out.to_double(); - if (i != data.size() - 1) - os << ","; + std::string type_str; + llvm::raw_string_ostream ss(type_str); + ss << type << ">["; + os << type_str; + if (type.isa()) { + if (type.getIntOrFloatBitWidth() == 1) { + //bool + for (int i = 0; i < data.size(); i++) { + os << var_value(assignment, data[i]).data; + if (i != data.size() - 1) + os << ","; + } + } else { + //int + } + } else if (type.isa()) { + for (int i = 0; i < data.size(); i++) { + auto value = var_value(assignment, data[i]).data; + components::FixedPoint out(value, 16); + os << out.to_double(); + if (i != data.size() - 1) + os << ","; + } } os << "]\n"; } diff --git a/mlir-assigner/include/mlir-assigner/parser/evaluator.hpp b/mlir-assigner/include/mlir-assigner/parser/evaluator.hpp index 2304e7d..e3a0998 100644 --- a/mlir-assigner/include/mlir-assigner/parser/evaluator.hpp +++ b/mlir-assigner/include/mlir-assigner/parser/evaluator.hpp @@ -1,6 +1,8 @@ #ifndef CRYPTO3_BLUEPRINT_COMPONENT_INSTRUCTION_MLIR_EVALUATOR_HPP #define CRYPTO3_BLUEPRINT_COMPONENT_INSTRUCTION_MLIR_EVALUATOR_HPP +#include +#include #define TEST_WITHOUT_LOOKUP_TABLES #include "mlir-assigner/helper/asserts.hpp" @@ -46,6 +48,7 @@ #include #include #include +#include #include #include @@ -248,7 +251,35 @@ namespace zk_ml_toolchain { } else if (arith::NegFOp operation = llvm::dyn_cast(op)) { handle_fixedpoint_neg_component(operation, frames.back(), bp, assignmnt, start_row); } else if (arith::AndIOp operation = llvm::dyn_cast(op)) { - UNREACHABLE("TODO component not finished at nils side"); + // check if logical and or bitwise and + mlir::Type LhsType = operation.getLhs().getType(); + mlir::Type RhsType = operation.getRhs().getType(); + assert(LhsType == RhsType && "must be same type for AndIOp"); + if (LhsType.getIntOrFloatBitWidth() == 1) { + handle_logic_and(operation, frames.back(), bp, assignmnt, start_row); + } else { + UNREACHABLE("TODO add Bitwise And Gadget"); + } + } else if (arith::OrIOp operation = llvm::dyn_cast(op)) { + // check if logical and or bitwise and + mlir::Type LhsType = operation.getLhs().getType(); + mlir::Type RhsType = operation.getRhs().getType(); + assert(LhsType == RhsType && "must be same type for OrIOp"); + if (LhsType.getIntOrFloatBitWidth() == 1) { + handle_logic_or(operation, frames.back(), bp, assignmnt, start_row); + } else { + UNREACHABLE("TODO add Bitwise Or Gadget"); + } + } else if (arith::XOrIOp operation = llvm::dyn_cast(op)) { + // check if logical and or bitwise and + mlir::Type LhsType = operation.getLhs().getType(); + mlir::Type RhsType = operation.getRhs().getType(); + assert(LhsType == RhsType && "must be same type for XOrIOp"); + if (LhsType.getIntOrFloatBitWidth() == 1) { + handle_logic_xor(operation, frames.back(), bp, assignmnt, start_row); + } else { + UNREACHABLE("TODO add Bitwise XOr Gadget"); + } } else if (arith::AddIOp operation = llvm::dyn_cast(op)) { // TODO: ATM, handle only the case where we work on indices that are @@ -291,12 +322,17 @@ namespace zk_ml_toolchain { } else if (arith::ConstantOp operation = llvm::dyn_cast(op)) { TypedAttr constantValue = operation.getValueAttr(); if (constantValue.isa()) { - int64_t value = llvm::dyn_cast(constantValue).getInt(); // this insert is ok, since this should never change, so we don't // override it if it is already there // TACEO_TODO: better separation of constant values that come from the // loop bounds an normal ones, ATM just do both + int64_t value; + if (constantValue.isa()) { + value = llvm::dyn_cast(constantValue).getValue() ? 1 : 0; + } else { + value = llvm::dyn_cast(constantValue).getInt(); + } frames.back().constant_values.insert( std::make_pair(mlir::hash_value(operation.getResult()), value)); @@ -763,8 +799,8 @@ namespace zk_ml_toolchain { auto retval = frames.back().memrefs.find(mlir::hash_value(ops[0])); assert(retval != frames.back().memrefs.end()); if (PrintCircuitOutput) { - llvm::outs() << "Result:\n"; - retval->second.print(llvm::outs(), assignmnt); + std::cout << "Result:\n"; + retval->second.print(std::cout, assignmnt); } return; } diff --git a/mlir-assigner/include/mlir-assigner/parser/input_reader.hpp b/mlir-assigner/include/mlir-assigner/parser/input_reader.hpp index dbadb9f..b6b4f98 100644 --- a/mlir-assigner/include/mlir-assigner/parser/input_reader.hpp +++ b/mlir-assigner/include/mlir-assigner/parser/input_reader.hpp @@ -27,6 +27,7 @@ #define CRYPTO3_ASSIGNER_PUBLIC_INPUT_HPP #include +#include "mlir-assigner/helper/asserts.hpp" #include #include @@ -80,6 +81,17 @@ namespace nil { return parse_scalar(value, out); } + bool parse_int(const boost::json::value &value, typename BlueprintFieldType::value_type &out) { + switch (value.kind()) { + case boost::json::kind::int64: + case boost::json::kind::uint64: + return parse_scalar(value, out); + default: + std::cerr << "unsupported int type: " << value.as_string() << std::endl; + UNREACHABLE("int must be int64 or uint64"); + }; + } + bool parse_scalar(const boost::json::value &value, typename BlueprintFieldType::value_type &out) { const std::size_t buflen = 256; char buf[buflen]; @@ -240,7 +252,17 @@ namespace nil { } data.put_flat(i, var(0, public_input_idx++, false, var::column_type::public_input)); } - } else if (type == "bool") { + } else if (type == "int") { + //TODO do we have to handle uint? + for (size_t i = 0; i < tensor_arr.size(); ++i) { + if (!parse_int(tensor_arr[i], assignmnt.public_input(0, public_input_idx))) { + llvm::errs() << "expect fixedpoints in tensor\n"; + return false; + } + data.put_flat(i, var(0, public_input_idx++, false, var::column_type::public_input)); + } + } + else if (type == "bool") { for (size_t i = 0; i < tensor_arr.size(); ++i) { if (!parse_bool(tensor_arr[i], assignmnt.public_input(0, public_input_idx))) { llvm::errs() << "expect fixedpoints in tensor\n"; diff --git a/mlir-assigner/include/mlir-assigner/parser/parser.hpp b/mlir-assigner/include/mlir-assigner/parser/parser.hpp index d8c35c8..572c1de 100644 --- a/mlir-assigner/include/mlir-assigner/parser/parser.hpp +++ b/mlir-assigner/include/mlir-assigner/parser/parser.hpp @@ -118,7 +118,7 @@ namespace nil { // return false; // } - llvm::outs() << assignments[0].rows_amount() << " rows\n"; + std::cout << assignments[0].rows_amount() << " rows\n"; return true; } diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseAnd/BitwiseAndSimple.json b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseAnd/BitwiseAndSimple.json new file mode 100644 index 0000000..d6cc240 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseAnd/BitwiseAndSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [-17364, -5917, 20048, -5966, 26954, -27667, -5752, -18323, -27730, 3267], "dims": [1, 10], "type": "int"}}, {"memref": {"data": [12595, 478, 29202, -11821, -3991, 7786, 14699, 5733, -27202, 14058], "dims": [1, 10], "type": "int"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseAnd/BitwiseAndSimple.onnx b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseAnd/BitwiseAndSimple.onnx new file mode 100644 index 0000000..95c7b99 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseAnd/BitwiseAndSimple.onnx @@ -0,0 +1,20 @@ + :| + +in_a +in_bout_a" +BitwiseAndBitwiseAndSimpleZ +in_a +  + + +Z +in_b +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseAnd/BitwiseAndSimple.res b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseAnd/BitwiseAndSimple.res new file mode 100644 index 0000000..2de0d62 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseAnd/BitwiseAndSimple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xint>[12320, 194, 16912, -16238, 24648, 4712, 10504, 4197, -28242, 1218] +ADD THE ROWS HERE \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseOr/BitwiseOrSimple.json b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseOr/BitwiseOrSimple.json new file mode 100644 index 0000000..e2c5c34 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseOr/BitwiseOrSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [17404, 12269, -2971, -24378, 29836, 52, 11050, 27899, -32318, 8698], "dims": [1, 10], "type": "int"}}, {"memref": {"data": [8593, 11402, -2385, 5229, -18463, 10748, -30730, 25091, 22130, -14765], "dims": [1, 10], "type": "int"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseOr/BitwiseOrSimple.onnx b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseOr/BitwiseOrSimple.onnx new file mode 100644 index 0000000..251f0f1 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseOr/BitwiseOrSimple.onnx @@ -0,0 +1,19 @@ + :z + +in_a +in_bout_a" BitwiseOrBitwiseOrSimpleZ +in_a +  + + +Z +in_b +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseOr/BitwiseOrSimple.res b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseOr/BitwiseOrSimple.res new file mode 100644 index 0000000..ca35d2a --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseOr/BitwiseOrSimple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xint>[25597, 12271, -2321, -19217, -2067, 10748, -20482, 28411, -10254, -6149] +ADD THE ROWS HERE \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseXor/BitwiseXorSimple.json b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseXor/BitwiseXorSimple.json new file mode 100644 index 0000000..54a8f9c --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseXor/BitwiseXorSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [-11526, 25091, -17049, 22557, -15341, 9387, 6169, -3828, -21288, 22372], "dims": [1, 10], "type": "int"}}, {"memref": {"data": [-7542, -25840, -7075, 23653, 27243, -16232, 32027, 2937, -4794, -7927], "dims": [1, 10], "type": "int"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseXor/BitwiseXorSimple.onnx b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseXor/BitwiseXorSimple.onnx new file mode 100644 index 0000000..b792c6e --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseXor/BitwiseXorSimple.onnx @@ -0,0 +1,20 @@ + :| + +in_a +in_bout_a" +BitwiseXorBitwiseXorSimpleZ +in_a +  + + +Z +in_b +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseXor/BitwiseXorSimple.res b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseXor/BitwiseXorSimple.res new file mode 100644 index 0000000..d427120 --- /dev/null +++ b/mlir-assigner/tests/Ops/NeedsBlueprintComponent/BitwiseXor/BitwiseXorSimple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xint>[12400, -1773, 22842, 1144, -20872, -7117, 25858, -1419, 16798, -18835] +ADD THE ROWS HERE \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/And/.ignore b/mlir-assigner/tests/Ops/Onnx/And/.ignore deleted file mode 100644 index e69de29..0000000 diff --git a/mlir-assigner/tests/Ops/Onnx/And/AndSimple.json b/mlir-assigner/tests/Ops/Onnx/And/AndSimple.json index bd5827e..ae03ee8 100644 --- a/mlir-assigner/tests/Ops/Onnx/And/AndSimple.json +++ b/mlir-assigner/tests/Ops/Onnx/And/AndSimple.json @@ -1 +1 @@ -[{"memref": {"data": [0, 1, 1, 0, 1, 0, 1, 1, 0, 1], "dims": [1, 10], "type": "bool"}}, {"memref": {"data": [0, 0, 1, 0, 0, 1, 0, 0, 1, 0], "dims": [1, 10], "type": "bool"}}] \ No newline at end of file +[{"memref": {"data": [1, 0, 0, 0, 1, 0, 1, 0, 1, 1], "dims": [1, 10], "type": "bool"}}, {"memref": {"data": [0, 1, 1, 1, 0, 0, 0, 1, 1, 1], "dims": [1, 10], "type": "bool"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/And/AndSimple.res b/mlir-assigner/tests/Ops/Onnx/And/AndSimple.res index 73917a4..3298e87 100644 --- a/mlir-assigner/tests/Ops/Onnx/And/AndSimple.res +++ b/mlir-assigner/tests/Ops/Onnx/And/AndSimple.res @@ -1,3 +1,3 @@ Result: -memref<1x10xbool>[0, 0, 1, 0, 0, 0, 0, 0, 0, 0] -ADD THE ROWS HERE \ No newline at end of file +memref<1x10xi1>[0, 0, 0, 0, 0, 0, 0, 0, 1, 1] +23 diff --git a/mlir-assigner/tests/Ops/Onnx/Not/NotSimple.json b/mlir-assigner/tests/Ops/Onnx/Not/NotSimple.json new file mode 100644 index 0000000..150b5a2 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Not/NotSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [1, 0, 1, 0, 0, 1, 0, 1, 0, 0], "dims": [1, 10], "type": "bool"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/Not/NotSimple.onnx b/mlir-assigner/tests/Ops/Onnx/Not/NotSimple.onnx new file mode 100644 index 0000000..750e688 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Not/NotSimple.onnx @@ -0,0 +1,13 @@ + :P + +in_aout_a"Not NotSimpleZ +in_a +   + + +b +out_a +   + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/Not/NotSimple.res b/mlir-assigner/tests/Ops/Onnx/Not/NotSimple.res new file mode 100644 index 0000000..2d0f31e --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Not/NotSimple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xi1>[0, 1, 0, 1, 1, 0, 1, 0, 1, 1] +13 diff --git a/mlir-assigner/tests/Ops/Onnx/Where/WhereSimple.json b/mlir-assigner/tests/Ops/Onnx/Where/WhereSimple.json new file mode 100644 index 0000000..892b5eb --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Where/WhereSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [0, 0, 1, 1, 0, 0, 1, 1, 1, 1], "dims": [1, 10], "type": "bool"}}, {"memref": {"data": [0.0034637451171875, 0.141265869140625, 0.979644775390625, 0.863555908203125, 0.5037841796875, 0.360443115234375, 0.7198486328125, 0.19195556640625, 0.9474945068359375, 0.8270111083984375], "dims": [1, 10], "type": "f32"}}, {"memref": {"data": [0.8197174072265625, 0.71905517578125, 0.218597412109375, 0.3871612548828125, 0.125091552734375, 0.0448150634765625, 0.9925079345703125, 0.101654052734375, 0.0225982666015625, 0.1092681884765625], "dims": [1, 10], "type": "f32"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/Where/WhereSimple.onnx b/mlir-assigner/tests/Ops/Onnx/Where/WhereSimple.onnx new file mode 100644 index 0000000..602e431 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Where/WhereSimple.onnx @@ -0,0 +1,25 @@ + :� + +in_a +in_b +in_cout_a"Where WhereSimpleZ +in_a +   + + +Z +in_b +  + + +Z +in_c +  + + +b +out_a +  + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/Where/WhereSimple.res b/mlir-assigner/tests/Ops/Onnx/Where/WhereSimple.res new file mode 100644 index 0000000..b1681dd --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Where/WhereSimple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xf32>[0.8197174072265625, 0.71905517578125, 0.979644775390625, 0.863555908203125, 0.125091552734375, 0.0448150634765625, 0.7198486328125, 0.19195556640625, 0.9474945068359375, 0.8270111083984375] +33 diff --git a/mlir-assigner/tests/Ops/Onnx/Xor/XorSimple.json b/mlir-assigner/tests/Ops/Onnx/Xor/XorSimple.json new file mode 100644 index 0000000..7d140c4 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Xor/XorSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [1, 1, 0, 1, 1, 1, 1, 0, 0, 1], "dims": [1, 10], "type": "bool"}}, {"memref": {"data": [0, 0, 0, 0, 1, 1, 1, 1, 0, 1], "dims": [1, 10], "type": "bool"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/Xor/XorSimple.onnx b/mlir-assigner/tests/Ops/Onnx/Xor/XorSimple.onnx new file mode 100644 index 0000000..c9e60a4 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Xor/XorSimple.onnx @@ -0,0 +1,19 @@ + :n + +in_a +in_bout_a"Xor XorSimpleZ +in_a +   + + +Z +in_b +   + + +b +out_a +   + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/Onnx/Xor/XorSimple.res b/mlir-assigner/tests/Ops/Onnx/Xor/XorSimple.res new file mode 100644 index 0000000..8af0cc0 --- /dev/null +++ b/mlir-assigner/tests/Ops/Onnx/Xor/XorSimple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xi1>[1, 1, 0, 1, 0, 0, 0, 1, 0, 0] +23 diff --git a/mlir-assigner/tests/Ops/TheirBluePrintNotWorkingNOTHING_FOR_US/Or/OrSimple.json b/mlir-assigner/tests/Ops/TheirBluePrintNotWorkingNOTHING_FOR_US/Or/OrSimple.json new file mode 100644 index 0000000..dba7bb0 --- /dev/null +++ b/mlir-assigner/tests/Ops/TheirBluePrintNotWorkingNOTHING_FOR_US/Or/OrSimple.json @@ -0,0 +1 @@ +[{"memref": {"data": [1, 1, 0, 0, 1, 1, 0, 1, 1, 1], "dims": [1, 10], "type": "bool"}}, {"memref": {"data": [0, 1, 0, 0, 1, 0, 0, 0, 1, 0], "dims": [1, 10], "type": "bool"}}] \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/TheirBluePrintNotWorkingNOTHING_FOR_US/Or/OrSimple.mlir b/mlir-assigner/tests/Ops/TheirBluePrintNotWorkingNOTHING_FOR_US/Or/OrSimple.mlir new file mode 100644 index 0000000..5a0758d --- /dev/null +++ b/mlir-assigner/tests/Ops/TheirBluePrintNotWorkingNOTHING_FOR_US/Or/OrSimple.mlir @@ -0,0 +1,16 @@ +module attributes {llvm.data_layout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128", llvm.target_triple = "x86_64-pc-linux-gnu", "onnx-mlir.symbol-postfix" = "orsimple.mlir"} { + func.func @main_graph(%arg0: memref<1x10xi1>, %arg1: memref<1x10xi1>) -> memref<1x10xi1> attributes {input_names = ["in_a", "in_b"], llvm.emit_c_interface, output_names = ["out_a"]} { + %c0 = arith.constant 0 : index + %alloc = memref.alloc() {alignment = 16 : i64} : memref<1x10xi1> + affine.for %arg2 = 0 to 1 { + affine.for %arg3 = 0 to 10 { + %0 = affine.load %arg0[%c0, %arg3] : memref<1x10xi1> + %1 = affine.load %arg1[%c0, %arg3] : memref<1x10xi1> + %2 = arith.ori %0, %1 : i1 + affine.store %2, %alloc[%arg2, %arg3] : memref<1x10xi1> + } + } + return %alloc : memref<1x10xi1> + } + "krnl.entry_point"() {func = @main_graph, numInputs = 2 : i32, numOutputs = 1 : i32, signature = "[ { \22type\22 : \22i1\22 , \22dims\22 : [1 , 10] , \22name\22 : \22in_a\22 }\0A , { \22type\22 : \22i1\22 , \22dims\22 : [1 , 10] , \22name\22 : \22in_b\22 }\0A\0A]\00@[ { \22type\22 : \22i1\22 , \22dims\22 : [1 , 10] , \22name\22 : \22out_a\22 }\0A\0A]\00"} : () -> () +} diff --git a/mlir-assigner/tests/Ops/TheirBluePrintNotWorkingNOTHING_FOR_US/Or/OrSimple.onnx b/mlir-assigner/tests/Ops/TheirBluePrintNotWorkingNOTHING_FOR_US/Or/OrSimple.onnx new file mode 100644 index 0000000..c51975d --- /dev/null +++ b/mlir-assigner/tests/Ops/TheirBluePrintNotWorkingNOTHING_FOR_US/Or/OrSimple.onnx @@ -0,0 +1,19 @@ + :l + +in_a +in_bout_a"OrOrSimpleZ +in_a +   + + +Z +in_b +   + + +b +out_a +   + + +B \ No newline at end of file diff --git a/mlir-assigner/tests/Ops/TheirBluePrintNotWorkingNOTHING_FOR_US/Or/OrSimple.res b/mlir-assigner/tests/Ops/TheirBluePrintNotWorkingNOTHING_FOR_US/Or/OrSimple.res new file mode 100644 index 0000000..990b388 --- /dev/null +++ b/mlir-assigner/tests/Ops/TheirBluePrintNotWorkingNOTHING_FOR_US/Or/OrSimple.res @@ -0,0 +1,3 @@ +Result: +memref<1x10xbool>[1, 1, 0, 0, 1, 1, 0, 1, 1, 1] +ADD THE ROWS HERE \ No newline at end of file diff --git a/mlir-assigner/tests/run.py b/mlir-assigner/tests/run.py index 3613b52..320ad17 100644 --- a/mlir-assigner/tests/run.py +++ b/mlir-assigner/tests/run.py @@ -29,16 +29,18 @@ class bcolors: def assert_output(should_output, is_output): global MAX_DELTA - ziped = zip(should_output.splitlines(), is_output.splitlines()) + is_lines = is_output.splitlines() + if len(is_lines) < 3: + return False, "Output incomplete got less than 3 lines" + ziped = zip(should_output.splitlines(), is_lines) #1 First Line Result s,i = next(ziped) if s != i: - print("FAIL") return False, "Cannot get Result (First Line does not match) " s,i = next(ziped) memref_index = s.find('[') if s[0: memref_index] != i[0: memref_index]: - return False + return False, "Type mismatch (should={}; is={})".format(s[0: memref_index], i[0: memref_index]) s_values = ast.literal_eval(s[memref_index:]) i_values = ast.literal_eval(i[memref_index:]) if any(filter(lambda a: a >= MAX_DELTA, map(lambda a: abs(a[0]-a[1]), zip(s_values, i_values)))): @@ -135,14 +137,14 @@ def test_mlir(file, subfolder_path, timeout, verbose): if verbose: print("running: '" + " ".join(args) + "'...", flush=True) try: - is_output = check_output(args, stderr=STDOUT, timeout=timeout).decode().strip() - if is_output == should_output: + valid, error_string = assert_output(should_output, check_output(args, stderr=STDOUT, timeout=timeout).decode().strip()) + if valid: print(f"{bcolors.OKGREEN} success{bcolors.ENDC}") success_tests += 1 else: failed_tests += 1 print(f"{bcolors.FAIL} failed{bcolors.ENDC}") - errors.append(build_error_object(file, f"output mismatch")) + errors.append(build_error_object(file, error_string)) except CalledProcessError: error_tests += 1 print(f"{bcolors.FAIL} error{bcolors.ENDC}") @@ -213,6 +215,7 @@ def test_folder(test_suite, folder, mlir_tests, timeout, verbose, keep_mlir): test_folder("SingleOps E2E", "mlir-assigner/tests/Ops/Onnx", False, 30, args.verbose, args.keep_mlir) test_folder("SingleOps special MLIR", "mlir-assigner/tests/Ops/Mlir", True, 30, args.verbose, args.keep_mlir) +#test_folder("SingleOps E2E", "mlir-assigner/tests/Ops/Current", False, 30, args.verbose, args.keep_mlir) if slow_test: test_folder("Models", "mlir-assigner/tests/Models/", False, 500, args.verbose, args.keep_mlir)