From 61ba0f59414c1fccd8d899ec4ab13008f59d3e9c Mon Sep 17 00:00:00 2001 From: mikee47 Date: Fri, 13 Nov 2020 23:24:01 +0000 Subject: [PATCH] Remove esp32 espinc headers where possible; should use esp-idf soc headers --- .../esp32/include/espinc/eagle_soc.h | 226 ------------ .../esp32/include/espinc/gpio_register.h | 309 ---------------- .../esp32/include/espinc/gpio_struct.h | 92 ----- .../esp32/include/espinc/i2c_bbpll.h | 52 --- .../esp32/include/espinc/i2s_register.h | 128 ------- .../esp32/include/espinc/i2s_struct.h | 144 -------- .../esp32/include/espinc/pin_mux_register.h | 154 -------- .../esp32/include/espinc/slc_register.h | 289 --------------- .../esp32/include/espinc/slc_struct.h | 347 ------------------ .../esp32/include/espinc/spi_register.h | 274 -------------- .../esp32/include/espinc/uart_register.h | 173 --------- .../esp32/src/include/esp_systemapi.h | 3 - 12 files changed, 2191 deletions(-) delete mode 100644 Sming/Arch/Esp32/Components/esp32/include/espinc/eagle_soc.h delete mode 100644 Sming/Arch/Esp32/Components/esp32/include/espinc/gpio_register.h delete mode 100644 Sming/Arch/Esp32/Components/esp32/include/espinc/gpio_struct.h delete mode 100644 Sming/Arch/Esp32/Components/esp32/include/espinc/i2c_bbpll.h delete mode 100644 Sming/Arch/Esp32/Components/esp32/include/espinc/i2s_register.h delete mode 100644 Sming/Arch/Esp32/Components/esp32/include/espinc/i2s_struct.h delete mode 100644 Sming/Arch/Esp32/Components/esp32/include/espinc/pin_mux_register.h delete mode 100644 Sming/Arch/Esp32/Components/esp32/include/espinc/slc_register.h delete mode 100644 Sming/Arch/Esp32/Components/esp32/include/espinc/slc_struct.h delete mode 100644 Sming/Arch/Esp32/Components/esp32/include/espinc/spi_register.h delete mode 100644 Sming/Arch/Esp32/Components/esp32/include/espinc/uart_register.h diff --git a/Sming/Arch/Esp32/Components/esp32/include/espinc/eagle_soc.h b/Sming/Arch/Esp32/Components/esp32/include/espinc/eagle_soc.h deleted file mode 100644 index a58c7b7a40..0000000000 --- a/Sming/Arch/Esp32/Components/esp32/include/espinc/eagle_soc.h +++ /dev/null @@ -1,226 +0,0 @@ -#include - -#define CACHE_FLASH_CTRL_REG (0x3ff00000 + 0x0c) - -#if 0 - -/* - * ESPRSSIF MIT License - * - * Copyright (c) 2015 - * - * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case, - * it is free of charge, to any person obtaining a copy of this software and associated - * documentation files (the "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the Software is furnished - * to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _EAGLE_SOC_H_ -#define _EAGLE_SOC_H_ - -#include -#include - -/* IO definitions (access restrictions to peripheral registers) */ - -#define __RO__ volatile const /*!< Defines 'read only' permissions */ -#define __WO__ volatile /*!< Defines 'write only' permissions */ -#define __RW__ volatile /*!< Defines 'read / write' permissions */ - -//Register Bits{{ -#define BIT31 0x80000000 -#define BIT30 0x40000000 -#define BIT29 0x20000000 -#define BIT28 0x10000000 -#define BIT27 0x08000000 -#define BIT26 0x04000000 -#define BIT25 0x02000000 -#define BIT24 0x01000000 -#define BIT23 0x00800000 -#define BIT22 0x00400000 -#define BIT21 0x00200000 -#define BIT20 0x00100000 -#define BIT19 0x00080000 -#define BIT18 0x00040000 -#define BIT17 0x00020000 -#define BIT16 0x00010000 -#define BIT15 0x00008000 -#define BIT14 0x00004000 -#define BIT13 0x00002000 -#define BIT12 0x00001000 -#define BIT11 0x00000800 -#define BIT10 0x00000400 -#define BIT9 0x00000200 -#define BIT8 0x00000100 -#define BIT7 0x00000080 -#define BIT6 0x00000040 -#define BIT5 0x00000020 -#define BIT4 0x00000010 -#define BIT3 0x00000008 -#define BIT2 0x00000004 -#define BIT1 0x00000002 -#define BIT0 0x00000001 -//}} - -#define BIT(nr) (1UL << (nr)) - -#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) -#define REG_READ(_r) (*(volatile uint32_t *)(_r)) - -#define REG_SET_BIT(_r, _b) (*(volatile uint32_t *)(_r) |= (_b)) -#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t *)(_r) &= ~(_b)) - -//Registers Operation {{ -#define ETS_UNCACHED_ADDR(addr) (addr) -#define ETS_CACHED_ADDR(addr) (addr) - -#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) -#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val) -#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg) & (~(mask)))) -#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg) | (mask))) -#define GET_PERI_REG_BITS(reg, hipos, lowpos) ((READ_PERI_REG(reg) >> (lowpos)) & ((1 << ((hipos) - (lowpos) + 1)) - 1)) -#define SET_PERI_REG_BITS(reg, bit_map, value, shift) (WRITE_PERI_REG((reg), (READ_PERI_REG(reg) & (~((bit_map) << (shift)))) | ((value) << (shift)) )) -//}} - -//Periheral Clock {{ -#define CPU_CLK_FREQ 80 * 1000000 // unit: Hz -#define APB_CLK_FREQ CPU_CLK_FREQ -#define UART_CLK_FREQ APB_CLK_FREQ -#define TIMER_CLK_FREQ (APB_CLK_FREQ >> 8) // divided by 256 - -#define FREQ_1MHZ (1000 * 1000) -#define FREQ_1KHZ (1000) - -#define CPU_FREQ_160MHZ (160 * 1000 * 1000) -#define CPU_FREQ_80MHz (80 * 1000 * 1000) - -#define CPU_160M_TICKS_PRT_MS (CPU_FREQ_160MHZ / FREQ_1KHZ) -#define CPU_80M_TICKS_PRT_MS (CPU_FREQ_80MHz / FREQ_1KHZ) - -#define CPU_160M_TICKS_PRT_US (CPU_FREQ_160MHZ / FREQ_1MHZ) -#define CPU_80M_TICKS_PRT_US (CPU_FREQ_80MHz / FREQ_1MHZ) -//}} - -//Peripheral device base address define{{ -#define PERIPHS_DPORT_BASEADDR 0x3ff00000 -#define PERIPHS_RTC_BASEADDR 0x60000700 -//}} - -//DPORT{{ -#define HOST_INF_SEL (PERIPHS_DPORT_BASEADDR + 0x28) -#define DPORT_LINK_DEVICE_SEL 0x000000FF -#define DPORT_LINK_DEVICE_SEL_S 8 -#define DPORT_PERI_IO_SWAP 0x000000FF -#define DPORT_PERI_IO_SWAP_S 0 -#define PERI_IO_CSPI_OVERLAP (BIT(7)) // two spi masters on cspi -#define PERI_IO_HSPI_OVERLAP (BIT(6)) // two spi masters on hspi -#define PERI_IO_HSPI_PRIO (BIT(5)) // hspi is with the higher prior -#define PERI_IO_UART1_PIN_SWAP (BIT(3)) // swap uart1 pins (u1rxd <-> u1cts), (u1txd <-> u1rts) -#define PERI_IO_UART0_PIN_SWAP (BIT(2)) // swap uart0 pins (u0rxd <-> u0cts), (u0txd <-> u0rts) -#define PERI_IO_SPI_PORT_SWAP (BIT(1)) // swap two spi -#define PERI_IO_UART_PORT_SWAP (BIT(0)) // swap two uart -//}} - -//Interrupt remap control registers define{{ -#define EDGE_INT_ENABLE_REG (PERIPHS_DPORT_BASEADDR + 0x04) -#define WDT_EDGE_INT_ENABLE() SET_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT0) -#define TM1_EDGE_INT_ENABLE() SET_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1) -#define TM1_EDGE_INT_DISABLE() CLEAR_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1) -//}} - -#define DPORT_CTL_REG (PERIPHS_DPORT_BASEADDR + 0x14) -#define DPORT_CTL_DOUBLE_CLK BIT0 - -#define INT_ENA_WDEV 0x3ff20c18 -#define WDEV_TSF0_REACH_INT (BIT(27)) - -#define WDEV_COUNT_REG (0x3ff20c00) - -//Watch dog reg {{ -#define PERIPHS_WDT_BASEADDR 0x60000900 - -#define WDT_CTL_ADDRESS 0 -#define WDT_OP_ADDRESS 0x4 -#define WDT_OP_ND_ADDRESS 0x8 -#define WDT_RST_ADDRESS 0x14 - -#define WDT_CTL_RSTLEN_MASK 0x38 -#define WDT_CTL_RSPMOD_MASK 0x6 -#define WDT_CTL_EN_MASK 0x1 - -#define WDT_CTL_RSTLEN_LSB 0x3 -#define WDT_CTL_RSPMOD_LSB 0x1 -#define WDT_CTL_EN_LSB 0 - -#define WDT_FEED_VALUE 0x73 - -#define WDT_REG_READ(_reg) REG_READ(PERIPHS_WDT_BASEADDR + _reg) -#define WDT_REG_WRITE(_reg, _val) REG_WRITE(PERIPHS_WDT_BASEADDR + _reg, _val) -#define CLEAR_WDT_REG_MASK(_reg, _mask) WDT_REG_WRITE(_reg, WDT_REG_READ(_reg) & (~_mask)) -#define WDT_FEED() WDT_REG_WRITE(WDT_RST_ADDRESS, WDT_FEED_VALUE) - -//}} - -//RTC reg {{ -#define REG_RTC_BASE PERIPHS_RTC_BASEADDR - -#define RTC_SLP_VAL (REG_RTC_BASE + 0x004) // the target value of RTC_COUNTER for wakeup from light-sleep/deep-sleep -#define RTC_SLP_CNT_VAL (REG_RTC_BASE + 0x01C) // the current value of RTC_COUNTER - -#define RTC_SCRATCH0 (REG_RTC_BASE + 0x030) // the register for software to save some values for watchdog reset -#define RTC_SCRATCH1 (REG_RTC_BASE + 0x034) // the register for software to save some values for watchdog reset -#define RTC_SCRATCH2 (REG_RTC_BASE + 0x038) // the register for software to save some values for watchdog reset -#define RTC_SCRATCH3 (REG_RTC_BASE + 0x03C) // the register for software to save some values for watchdog reset - -#define RTC_GPIO_OUT (REG_RTC_BASE + 0x068) // used by gpio16 -#define RTC_GPIO_ENABLE (REG_RTC_BASE + 0x074) -#define RTC_GPIO_IN_DATA (REG_RTC_BASE + 0x08C) -#define RTC_GPIO_CONF (REG_RTC_BASE + 0x090) -#define PAD_XPD_DCDC_CONF (REG_RTC_BASE + 0x0A0) -//}} - -//CACHE{{ -#define CACHE_FLASH_CTRL_REG (0x3ff00000 + 0x0c) -#define CACHE_READ_EN_BIT BIT8 -//}} - -#define DRAM_BASE (0x3FFE8000) -#define DRAM_SIZE (96 * 1024) - -#define IRAM_BASE (0x40100000) -#define IRAM_SIZE (CONFIG_SOC_IRAM_SIZE) - -#define FLASH_BASE (0x40200000) -#define FLASH_SIZE (1 * 1024 * 1024) - -#define RTC_SYS_BASE (0x60001000) -#define RTC_SYS_SIZE (0x200) - -#define RTC_USER_BASE (0x60001200) -#define RTC_USER_SIZE (0x200) - -#define ROM_BASE (0x40000000) -#define ROM_SIZE (0x10000) - -#define IS_DRAM(a) ((size_t)(a) >= DRAM_BASE && (size_t)(a) < (DRAM_BASE + DRAM_SIZE)) -#define IS_IRAM(a) ((size_t)(a) >= IRAM_BASE && (size_t)(a) < (IRAM_BASE + IRAM_SIZE)) -#define IS_FLASH(a) ((size_t)(a) >= FLASH_BASE && (size_t)(a) < (FLASH_BASE + FLASH_SIZE)) -#define IS_USR_RTC(a) ((size_t)(a) >= RTC_USER_BASE && (size_t)(a) < (RTC_USER_BASE + RTC_USER_SIZE)) -#define IS_ROM(a) ((size_t)(a) >= ROM_BASE && (size_t)(a) < (ROM_BASE + ROM_SIZE)) - -#endif //_EAGLE_SOC_H_ - -#endif // 0 diff --git a/Sming/Arch/Esp32/Components/esp32/include/espinc/gpio_register.h b/Sming/Arch/Esp32/Components/esp32/include/espinc/gpio_register.h deleted file mode 100644 index 8552a7fa03..0000000000 --- a/Sming/Arch/Esp32/Components/esp32/include/espinc/gpio_register.h +++ /dev/null @@ -1,309 +0,0 @@ -/* - * ESPRSSIF MIT License - * - * Copyright (c) 2015 - * - * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case, - * it is free of charge, to any person obtaining a copy of this software and associated - * documentation files (the "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the Software is furnished - * to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _GPIO_REGISTER_H_ -#define _GPIO_REGISTER_H_ - -#include - -#include "eagle_soc.h" - -#define PERIPHS_GPIO_BASEADDR 0x60000300 - -#define GPIO_OUT_ADDRESS 0x00 -#define GPIO_OUT_DATA_S 0 - -#define GPIO_OUT_W1TS_ADDRESS 0x04 -#define GPIO_OUT_DATA_W1TS_S 0 - -#define GPIO_OUT_W1TC_ADDRESS 0x08 -#define GPIO_OUT_DATA_W1TC_S 0 -#define GPIO_OUT_DATA_MASK 0x0000ffff - -#define GPIO_ENABLE_ADDRESS 0x0c -#define GPIO_ENABLE_DATA_S 0 - -#define GPIO_ENABLE_W1TS_ADDRESS 0x10 -#define GPIO_ENABLE_DATA_W1TS_s 0 - -#define GPIO_ENABLE_W1TC_ADDRESS 0x14 -#define GPIO_ENABLE_DATA_W1TC_S 0 -#define GPIO_ENABLE_DATA_DATA_MASK 0x0000ffff - -#define GPIO_IN_ADDRESS 0x18 -#define GPIO_IN_DATA_S 0 - -#define GPIO_STATUS_ADDRESS 0x1c -#define GPIO_STATUS_INTERRUPT 0x0000ffff -#define GPIO_STATUS_INTERRUPT_S 0 - -#define GPIO_STATUS_W1TS_ADDRESS 0x20 -#define GPIO_STATUS_INTERRUPT_W1TS 0x0000ffff -#define GPIO_STATUS_INTERRUPT_W1TS_S 0 - -#define GPIO_STATUS_W1TC_ADDRESS 0x24 -#define GPIO_STATUS_INTERRUPT_W1TC 0x0000ffff -#define GPIO_STATUS_INTERRUPT_W1TC_S 0 -#define GPIO_STATUS_INTERRUPT_DATA_MASK 0x0000ffff - -//Region1: used for gpio config for GPIO_PIN0_ADDRESS~GPIO_PIN15_ADDRESS -#define GPIO_ID_PIN0 0 -#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n)) -#define GPIO_LAST_REGISTER_ID GPIO_ID_PIN(15) -#define GPIO_ID_NONE 0xffffffff - -#define GPIO_PIN_CONFIG_MSB 12 -#define GPIO_PIN_CONFIG_LSB 11 -#define GPIO_PIN_CONFIG_MASK (0x00000003<> GPIO_PIN_CONFIG_LSB) -#define GPIO_PIN_CONFIG_SET(x) (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK) - -#define GPIO_WAKEUP_ENABLE 1 -#define GPIO_WAKEUP_DISABLE (~GPIO_WAKEUP_ENABLE) -#define GPIO_PIN_WAKEUP_ENABLE_MSB 10 -#define GPIO_PIN_WAKEUP_ENABLE_LSB 10 -#define GPIO_PIN_WAKEUP_ENABLE_MASK (0x00000001<> GPIO_PIN_CONFIG_LSB) -#define GPIO_PIN_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK) - -#define GPIO_PIN_INT_TYPE_MSB 9 -#define GPIO_PIN_INT_TYPE_LSB 7 -#define GPIO_PIN_INT_TYPE_MASK (0x00000007<> GPIO_PIN_INT_TYPE_LSB) -#define GPIO_PIN_INT_TYPE_SET(x) (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK) - -#define GPIO_PAD_DRIVER_ENABLE 1 -#define GPIO_PAD_DRIVER_DISABLE (~GPIO_PAD_DRIVER_ENABLE) -#define GPIO_PIN_DRIVER_MSB 2 -#define GPIO_PIN_DRIVER_LSB 2 -#define GPIO_PIN_DRIVER_MASK (0x00000001<> GPIO_PIN_INT_TYPE_LSB) -#define GPIO_PIN_PAD_DRIVER_SET(x) (((x) << GPIO_PIN_DRIVER_LSB) & GPIO_PIN_DRIVER_MASK) - -#define GPIO_PIN_SOURCE_MSB 0 -#define GPIO_PIN_SOURCE_LSB 0 -#define GPIO_PIN_SOURCE_MASK (0x00000001<> GPIO_PIN_INT_TYPE_LSB) -#define GPIO_PIN_SOURCE_SET(x) (((x) << GPIO_PIN_SOURCE_LSB) & GPIO_PIN_SOURCE_MASK) -//end of region1 - -#define GPIO_PIN0_ADDRESS 0x28 -#define GPIO_PIN0_CONFIG 0x00000003 -#define GPIO_PIN0_CONFIG_S 11 -#define GPIO_PIN0_WAKEUP_ENABLE_S 10 -#define GPIO_PIN0_INT_TYPE 0x00000007 -#define GPIO_PIN0_INT_TYPE_S 7 -#define GPIO_PIN0_DRIVER BIT2 -#define GPIO_PIN0_DRIVER_S 2 -#define GPIO_PIN0_SOURCE BIT0 -#define GPIO_PIN0_SOURCE_S 0 - -#define GPIO_PIN1_ADDRESS 0x2c -#define GPIO_PIN1_CONFIG 0x00000003 -#define GPIO_PIN1_CONFIG_S 11 -#define GPIO_PIN1_WAKEUP_ENABLE_S 10 -#define GPIO_PIN1_INT_TYPE 0x00000007 -#define GPIO_PIN1_INT_TYPE_S 7 -#define GPIO_PIN1_DRIVER BIT2 -#define GPIO_PIN1_DRIVER_S 2 -#define GPIO_PIN1_SOURCE BIT0 -#define GPIO_PIN1_SOURCE_S 0 - -#define GPIO_PIN2_ADDRESS 0x30 -#define GPIO_PIN2_CONFIG 0x00000003 -#define GPIO_PIN2_CONFIG_S 11 -#define GPIO_PIN2_WAKEUP_ENABLE_S 10 -#define GPIO_PIN2_INT_TYPE 0x00000007 -#define GPIO_PIN2_INT_TYPE_S 7 -#define GPIO_PIN2_DRIVER BIT2 -#define GPIO_PIN2_DRIVER_S 2 -#define GPIO_PIN2_SOURCE BIT0 -#define GPIO_PIN2_SOURCE_S 0 - -#define GPIO_PIN3_ADDRESS 0x34 -#define GPIO_PIN3_CONFIG 0x00000003 -#define GPIO_PIN3_CONFIG_S 11 -#define GPIO_PIN3_WAKEUP_ENABLE_S 10 -#define GPIO_PIN3_INT_TYPE 0x00000007 -#define GPIO_PIN3_INT_TYPE_S 7 -#define GPIO_PIN3_DRIVER BIT2 -#define GPIO_PIN3_DRIVER_S 2 -#define GPIO_PIN3_SOURCE BIT0 -#define GPIO_PIN3_SOURCE_S 0 - -#define GPIO_PIN4_ADDRESS 0x38 -#define GPIO_PIN4_CONFIG 0x00000003 -#define GPIO_PIN4_CONFIG_S 11 -#define GPIO_PIN4_WAKEUP_ENABLE_S 10 -#define GPIO_PIN4_INT_TYPE 0x00000007 -#define GPIO_PIN4_INT_TYPE_S 7 -#define GPIO_PIN4_DRIVER BIT2 -#define GPIO_PIN4_DRIVER_S 2 -#define GPIO_PIN4_SOURCE BIT0 -#define GPIO_PIN4_SOURCE_S 0 - -#define GPIO_PIN5_ADDRESS 0x3c -#define GPIO_PIN5_CONFIG 0x00000003 -#define GPIO_PIN5_CONFIG_S 11 -#define GPIO_PIN5_WAKEUP_ENABLE_S 10 -#define GPIO_PIN5_INT_TYPE 0x00000007 -#define GPIO_PIN5_INT_TYPE_S 7 -#define GPIO_PIN5_DRIVER BIT2 -#define GPIO_PIN5_DRIVER_S 2 -#define GPIO_PIN5_SOURCE BIT0 -#define GPIO_PIN5_SOURCE_S 0 - -#define GPIO_PIN6_ADDRESS 0x40 -#define GPIO_PIN6_CONFIG 0x00000003 -#define GPIO_PIN6_CONFIG_S 11 -#define GPIO_PIN6_WAKEUP_ENABLE_S 10 -#define GPIO_PIN6_INT_TYPE 0x00000007 -#define GPIO_PIN6_INT_TYPE_S 7 -#define GPIO_PIN6_DRIVER BIT2 -#define GPIO_PIN6_DRIVER_S 2 -#define GPIO_PIN6_SOURCE BIT0 -#define GPIO_PIN6_SOURCE_S 0 - -#define GPIO_PIN7_ADDRESS 0x44 -#define GPIO_PIN7_CONFIG 0x00000003 -#define GPIO_PIN7_CONFIG_S 11 -#define GPIO_PIN7_WAKEUP_ENABLE_S 10 -#define GPIO_PIN7_INT_TYPE 0x00000007 -#define GPIO_PIN7_INT_TYPE_S 7 -#define GPIO_PIN7_DRIVER BIT2 -#define GPIO_PIN7_DRIVER_S 2 -#define GPIO_PIN7_SOURCE BIT0 -#define GPIO_PIN7_SOURCE_S 0 - -#define GPIO_PIN8_ADDRESS 0x48 -#define GPIO_PIN8_CONFIG 0x00000003 -#define GPIO_PIN8_CONFIG_S 11 -#define GPIO_PIN8_WAKEUP_ENABLE_S 10 -#define GPIO_PIN8_INT_TYPE 0x00000007 -#define GPIO_PIN8_INT_TYPE_S 7 -#define GPIO_PIN8_DRIVER BIT2 -#define GPIO_PIN8_DRIVER_S 2 -#define GPIO_PIN8_SOURCE BIT0 -#define GPIO_PIN8_SOURCE_S 0 - -#define GPIO_PIN9_ADDRESS 0x4c -#define GPIO_PIN9_CONFIG 0x00000003 -#define GPIO_PIN9_CONFIG_S 11 -#define GPIO_PIN9_WAKEUP_ENABLE_S 10 -#define GPIO_PIN9_INT_TYPE 0x00000007 -#define GPIO_PIN9_INT_TYPE_S 7 -#define GPIO_PIN9_DRIVER BIT2 -#define GPIO_PIN9_DRIVER_S 2 -#define GPIO_PIN9_SOURCE BIT0 -#define GPIO_PIN9_SOURCE_S 0 - -#define GPIO_PIN10_ADDRESS 0x50 -#define GPIO_PIN10_CONFIG 0x00000003 -#define GPIO_PIN10_CONFIG_S 11 -#define GPIO_PIN10_WAKEUP_ENABLE_S 10 -#define GPIO_PIN10_INT_TYPE 0x00000007 -#define GPIO_PIN10_INT_TYPE_S 7 -#define GPIO_PIN10_DRIVER BIT2 -#define GPIO_PIN10_DRIVER_S 2 -#define GPIO_PIN10_SOURCE BIT0 -#define GPIO_PIN10_SOURCE_S 0 - -#define GPIO_PIN11_ADDRESS 0x54 -#define GPIO_PIN11_CONFIG 0x00000003 -#define GPIO_PIN11_CONFIG_S 11 -#define GPIO_PIN11_WAKEUP_ENABLE_S 10 -#define GPIO_PIN11_INT_TYPE 0x00000007 -#define GPIO_PIN11_INT_TYPE_S 7 -#define GPIO_PIN11_DRIVER BIT2 -#define GPIO_PIN11_DRIVER_S 2 -#define GPIO_PIN11_SOURCE BIT0 -#define GPIO_PIN11_SOURCE_S 0 - -#define GPIO_PIN12_ADDRESS 0x58 -#define GPIO_PIN12_CONFIG 0x00000003 -#define GPIO_PIN12_CONFIG_S 11 -#define GPIO_PIN12_WAKEUP_ENABLE_S 10 -#define GPIO_PIN12_INT_TYPE 0x00000007 -#define GPIO_PIN12_INT_TYPE_S 7 -#define GPIO_PIN12_DRIVER BIT2 -#define GPIO_PIN12_DRIVER_S 2 -#define GPIO_PIN12_SOURCE BIT0 -#define GPIO_PIN12_SOURCE_S 0 - -#define GPIO_PIN13_ADDRESS 0x5c -#define GPIO_PIN13_CONFIG 0x00000003 -#define GPIO_PIN13_CONFIG_S 11 -#define GPIO_PIN13_WAKEUP_ENABLE_S 10 -#define GPIO_PIN13_INT_TYPE 0x00000007 -#define GPIO_PIN13_INT_TYPE_S 7 -#define GPIO_PIN13_DRIVER BIT2 -#define GPIO_PIN13_DRIVER_S 2 -#define GPIO_PIN13_SOURCE BIT0 -#define GPIO_PIN13_SOURCE_S 0 - -#define GPIO_PIN14_ADDRESS 0x60 -#define GPIO_PIN14_CONFIG 0x00000003 -#define GPIO_PIN14_CONFIG_S 11 -#define GPIO_PIN14_WAKEUP_ENABLE_S 10 -#define GPIO_PIN14_INT_TYPE 0x00000007 -#define GPIO_PIN14_INT_TYPE_S 7 -#define GPIO_PIN14_DRIVER BIT2 -#define GPIO_PIN14_DRIVER_S 2 -#define GPIO_PIN14_SOURCE BIT0 -#define GPIO_PIN14_SOURCE_S 0 - -#define GPIO_PIN15_ADDRESS 0x64 -#define GPIO_PIN15_CONFIG 0x00000003 -#define GPIO_PIN15_CONFIG_S 11 -#define GPIO_PIN15_WAKEUP_ENABLE_S 10 -#define GPIO_PIN15_INT_TYPE 0x00000007 -#define GPIO_PIN15_INT_TYPE_S 7 -#define GPIO_PIN15_DRIVER BIT2 -#define GPIO_PIN15_DRIVER_S 2 -#define GPIO_PIN15_SOURCE BIT0 -#define GPIO_PIN15_SOURCE_S 0 - -#define GPIO_SIGMA_DELTA_ADDRESS 0x68 -#define SIGMA_DELTA_ENABLE BIT16 -#define SIGMA_DELTA_ENABLE_S 16 -#define SIGMA_DELTA_PRESCALAR 0x000000ff -#define SIGMA_DELTA_PRESCALAR_S 8 -#define SIGMA_DELTA_TARGET 0x000000ff -#define SIGMA_DELTA_TARGET_S 0 - -#define GPIO_RTC_CALIB_SYNC_ADDRESS 0x6c -#define RTC_CALIB_START BIT31 -#define RTC_CALIB_START_S 31 -#define RTC_PERIOD_NUM 0x000003ff -#define RTC_PERIOD_NUM_S 0 - -#define GPIO_RTC_CALIB_VALUE_ADDRESS 0x70 -#define RTC_CALIB_RDY BIT31 -#define RTC_CALIB_RDY_S 31 -#define RTC_CALIB_RDY_REAL BIT30 -#define RTC_CALIB_RDY_REAL_S 30 -#define RTC_CALIB_VALUE 0x000fffff -#define RTC_CALIB_VALUE_S 0 - -#endif diff --git a/Sming/Arch/Esp32/Components/esp32/include/espinc/gpio_struct.h b/Sming/Arch/Esp32/Components/esp32/include/espinc/gpio_struct.h deleted file mode 100644 index aa78c48dae..0000000000 --- a/Sming/Arch/Esp32/Components/esp32/include/espinc/gpio_struct.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright 2018 Espressif Systems (Shanghai) PTE LTD - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - */ - -#ifndef _GPIO_STRUCT_H_ -#define _GPIO_STRUCT_H_ - -#include "../../../esp32/include/espinc/eagle_soc.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ESP8266 GPIO Register Definitions */ - -typedef union { - __RW__ struct { - uint32_t sleep_oe: 1; - uint32_t sleep_sel: 1; - uint32_t reserved1: 1; - uint32_t sleep_pullup: 1; - uint32_t func_low_bit: 2; - uint32_t reserved2: 1; - uint32_t pullup: 1; - uint32_t func_high_bit: 1; - }; - __RW__ struct { - uint32_t func_low_bit: 2; - uint32_t reserved1: 1; - uint32_t pulldown: 1; - uint32_t reserved2: 1; - uint32_t sleep_pulldown: 1; - uint32_t func_high_bit: 1; - } rtc_pin; - __RW__ uint32_t val; -} gpio_pin_reg_t; - -typedef struct { - __RO__ uint32_t out; - __WO__ uint32_t out_w1ts; - __WO__ uint32_t out_w1tc; - - __RO__ uint32_t enable; - __WO__ uint32_t enable_w1ts; - __WO__ uint32_t enable_w1tc; - - __RO__ uint32_t in; - - __RO__ uint32_t status; - __WO__ uint32_t status_w1ts; - __WO__ uint32_t status_w1tc; - - __RW__ union { - struct { - uint32_t source: 1; - uint32_t reserved1: 1; - uint32_t driver: 1; - uint32_t reserved2: 4; - uint32_t int_type: 3; - uint32_t wakeup_enable: 1; - uint32_t reserved3: 21; - }; - uint32_t val; - } pin[16]; - - __RW__ uint32_t sigma_delta; - - __RW__ uint32_t rtc_calib_sync; - __RW__ uint32_t rtc_calib_value; -} gpio_struct_t; - -extern volatile gpio_struct_t GPIO; - -#ifdef __cplusplus -} -#endif /* end of __cplusplus */ - -#endif /* _GPIO_STRUCT_H_ */ diff --git a/Sming/Arch/Esp32/Components/esp32/include/espinc/i2c_bbpll.h b/Sming/Arch/Esp32/Components/esp32/include/espinc/i2c_bbpll.h deleted file mode 100644 index da6f4c2955..0000000000 --- a/Sming/Arch/Esp32/Components/esp32/include/espinc/i2c_bbpll.h +++ /dev/null @@ -1,52 +0,0 @@ -// Copyright 2018-2025 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -/** - * @file i2c_apll.h - * @brief Register definitions for digital PLL (BBPLL) - * - * This file lists register fields of BBPLL, located on an internal configuration bus. - */ - -#pragma once - -#include - -#define i2c_bbpll 0x67 -#define i2c_bbpll_en_audio_clock_out 4 -#define i2c_bbpll_en_audio_clock_out_msb 7 -#define i2c_bbpll_en_audio_clock_out_lsb 7 -#define i2c_bbpll_hostid 4 - -#ifdef __cplusplus -extern "C" { -#endif - -/* ROM functions which read/write internal control bus */ -uint8_t rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add); -uint8_t rom_i2c_readReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb); -void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data); -void rom_i2c_writeReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data); - -#ifdef __cplusplus -} -#endif - -#define i2c_writeReg_Mask(block, host_id, reg_add, Msb, Lsb, indata) \ - rom_i2c_writeReg_Mask(block, host_id, reg_add, Msb, Lsb, indata) -#define i2c_readReg_Mask(block, host_id, reg_add, Msb, Lsb) rom_i2c_readReg_Mask(block, host_id, reg_add, Msb, Lsb) -#define i2c_writeReg_Mask_def(block, reg_add, indata) \ - i2c_writeReg_Mask(block, block##_hostid, reg_add, reg_add##_msb, reg_add##_lsb, indata) -#define i2c_readReg_Mask_def(block, reg_add) \ - i2c_readReg_Mask(block, block##_hostid, reg_add, reg_add##_msb, reg_add##_lsb) diff --git a/Sming/Arch/Esp32/Components/esp32/include/espinc/i2s_register.h b/Sming/Arch/Esp32/Components/esp32/include/espinc/i2s_register.h deleted file mode 100644 index f85b0dc8b5..0000000000 --- a/Sming/Arch/Esp32/Components/esp32/include/espinc/i2s_register.h +++ /dev/null @@ -1,128 +0,0 @@ -// Copyright 2018-2025 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#ifndef _I2S_REGISTER_H_ -#define _I2S_REGISTER_H_ - -#include "../../../esp32/include/espinc/eagle_soc.h" - -#define REG_I2S_BASE (0x60000e00) - -#define I2STXFIFO (REG_I2S_BASE + 0x0000) -#define I2SRXFIFO (REG_I2S_BASE + 0x0004) - -#define I2SCONF (REG_I2S_BASE + 0x0008) -#define I2S_BCK_DIV_NUM 0x0000003F -#define I2S_BCK_DIV_NUM_S 22 -#define I2S_CLKM_DIV_NUM 0x0000003F -#define I2S_CLKM_DIV_NUM_S 16 -#define I2S_BITS_MOD 0x0000000F -#define I2S_BITS_MOD_S 12 -#define I2S_RECE_MSB_SHIFT (BIT(11)) -#define I2S_TRANS_MSB_SHIFT (BIT(10)) -#define I2S_I2S_RX_START (BIT(9)) -#define I2S_I2S_TX_START (BIT(8)) -#define I2S_MSB_RIGHT (BIT(7)) -#define I2S_RIGHT_FIRST (BIT(6)) -#define I2S_RECE_SLAVE_MOD (BIT(5)) -#define I2S_TRANS_SLAVE_MOD (BIT(4)) -#define I2S_I2S_RX_FIFO_RESET (BIT(3)) -#define I2S_I2S_TX_FIFO_RESET (BIT(2)) -#define I2S_I2S_RX_RESET (BIT(1)) -#define I2S_I2S_TX_RESET (BIT(0)) -#define I2S_I2S_RESET_MASK 0xf - -#define I2SINT_RAW (REG_I2S_BASE + 0x000c) -#define I2S_I2S_TX_REMPTY_INT_RAW (BIT(5)) -#define I2S_I2S_TX_WFULL_INT_RAW (BIT(4)) -#define I2S_I2S_RX_REMPTY_INT_RAW (BIT(3)) -#define I2S_I2S_RX_WFULL_INT_RAW (BIT(2)) -#define I2S_I2S_TX_PUT_DATA_INT_RAW (BIT(1)) -#define I2S_I2S_RX_TAKE_DATA_INT_RAW (BIT(0)) - -#define I2SINT_ST (REG_I2S_BASE + 0x0010) -#define I2S_I2S_TX_REMPTY_INT_ST (BIT(5)) -#define I2S_I2S_TX_WFULL_INT_ST (BIT(4)) -#define I2S_I2S_RX_REMPTY_INT_ST (BIT(3)) -#define I2S_I2S_RX_WFULL_INT_ST (BIT(2)) -#define I2S_I2S_TX_PUT_DATA_INT_ST (BIT(1)) -#define I2S_I2S_RX_TAKE_DATA_INT_ST (BIT(0)) - -#define I2SINT_ENA (REG_I2S_BASE + 0x0014) -#define I2S_I2S_TX_REMPTY_INT_ENA (BIT(5)) -#define I2S_I2S_TX_WFULL_INT_ENA (BIT(4)) -#define I2S_I2S_RX_REMPTY_INT_ENA (BIT(3)) -#define I2S_I2S_RX_WFULL_INT_ENA (BIT(2)) -#define I2S_I2S_TX_PUT_DATA_INT_ENA (BIT(1)) -#define I2S_I2S_RX_TAKE_DATA_INT_ENA (BIT(0)) - -#define I2SINT_CLR (REG_I2S_BASE + 0x0018) -#define I2S_I2S_TX_REMPTY_INT_CLR (BIT(5)) -#define I2S_I2S_TX_WFULL_INT_CLR (BIT(4)) -#define I2S_I2S_RX_REMPTY_INT_CLR (BIT(3)) -#define I2S_I2S_RX_WFULL_INT_CLR (BIT(2)) -#define I2S_I2S_PUT_DATA_INT_CLR (BIT(1)) -#define I2S_I2S_TAKE_DATA_INT_CLR (BIT(0)) - -#define I2STIMING (REG_I2S_BASE + 0x001c) -#define I2S_TRANS_BCK_IN_INV (BIT(22)) -#define I2S_RECE_DSYNC_SW (BIT(21)) -#define I2S_TRANS_DSYNC_SW (BIT(20)) -#define I2S_RECE_BCK_OUT_DELAY 0x00000003 -#define I2S_RECE_BCK_OUT_DELAY_S 18 -#define I2S_RECE_WS_OUT_DELAY 0x00000003 -#define I2S_RECE_WS_OUT_DELAY_S 16 -#define I2S_TRANS_SD_OUT_DELAY 0x00000003 -#define I2S_TRANS_SD_OUT_DELAY_S 14 -#define I2S_TRANS_WS_OUT_DELAY 0x00000003 -#define I2S_TRANS_WS_OUT_DELAY_S 12 -#define I2S_TRANS_BCK_OUT_DELAY 0x00000003 -#define I2S_TRANS_BCK_OUT_DELAY_S 10 -#define I2S_RECE_SD_IN_DELAY 0x00000003 -#define I2S_RECE_SD_IN_DELAY_S 8 -#define I2S_RECE_WS_IN_DELAY 0x00000003 -#define I2S_RECE_WS_IN_DELAY_S 6 -#define I2S_RECE_BCK_IN_DELAY 0x00000003 -#define I2S_RECE_BCK_IN_DELAY_S 4 -#define I2S_TRANS_WS_IN_DELAY 0x00000003 -#define I2S_TRANS_WS_IN_DELAY_S 2 -#define I2S_TRANS_BCK_IN_DELAY 0x00000003 -#define I2S_TRANS_BCK_IN_DELAY_S 0 - -#define I2S_FIFO_CONF (REG_I2S_BASE + 0x0020) -#define I2S_I2S_RX_FIFO_MOD 0x00000007 -#define I2S_I2S_RX_FIFO_MOD_S 16 -#define I2S_I2S_TX_FIFO_MOD 0x00000007 -#define I2S_I2S_TX_FIFO_MOD_S 13 -#define I2S_I2S_DSCR_EN (BIT(12)) -#define I2S_I2S_TX_DATA_NUM 0x0000003F -#define I2S_I2S_TX_DATA_NUM_S 6 -#define I2S_I2S_RX_DATA_NUM 0x0000003F -#define I2S_I2S_RX_DATA_NUM_S 0 - -#define I2SRXEOF_NUM (REG_I2S_BASE + 0x0024) -#define I2S_I2S_RX_EOF_NUM 0xFFFFFFFF -#define I2S_I2S_RX_EOF_NUM_S 0 - -#define I2SCONF_SIGLE_DATA (REG_I2S_BASE + 0x0028) -#define I2S_I2S_SIGLE_DATA 0xFFFFFFFF -#define I2S_I2S_SIGLE_DATA_S 0 - -#define I2SCONF_CHAN (REG_I2S_BASE + 0x002c) -#define I2S_RX_CHAN_MOD 0x00000003 -#define I2S_RX_CHAN_MOD_S 3 -#define I2S_TX_CHAN_MOD 0x00000007 -#define I2S_TX_CHAN_MOD_S 0 - -#endif diff --git a/Sming/Arch/Esp32/Components/esp32/include/espinc/i2s_struct.h b/Sming/Arch/Esp32/Components/esp32/include/espinc/i2s_struct.h deleted file mode 100644 index 462af31bdc..0000000000 --- a/Sming/Arch/Esp32/Components/esp32/include/espinc/i2s_struct.h +++ /dev/null @@ -1,144 +0,0 @@ -// Copyright 2018-2025 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -#include "eagle_soc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* ESP8266 I2S Register Definitions */ - -typedef volatile struct { - uint32_t tx_fifo; - uint32_t rx_fifo; - union { - struct { - uint32_t tx_reset: 1; - uint32_t rx_reset: 1; - uint32_t tx_fifo_reset: 1; - uint32_t rx_fifo_reset: 1; - uint32_t tx_slave_mod: 1; - uint32_t rx_slave_mod: 1; - uint32_t right_first: 1; - uint32_t msb_right: 1; - uint32_t tx_start: 1; - uint32_t rx_start: 1; - uint32_t tx_msb_shift: 1; - uint32_t rx_msb_shift: 1; - uint32_t bits_mod: 4; - uint32_t clkm_div_num: 6; - uint32_t bck_div_num: 6; - uint32_t reserved28: 4; - }; - uint32_t val; - } conf; - union { - struct { - uint32_t rx_take_data: 1; - uint32_t tx_put_data: 1; - uint32_t rx_wfull: 1; - uint32_t rx_rempty: 1; - uint32_t tx_wfull: 1; - uint32_t tx_rempty: 1; - uint32_t reserved6: 26; - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t rx_take_data: 1; - uint32_t tx_put_data: 1; - uint32_t rx_wfull: 1; - uint32_t rx_rempty: 1; - uint32_t tx_wfull: 1; - uint32_t tx_rempty: 1; - uint32_t reserved6: 26; - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t rx_take_data: 1; - uint32_t tx_put_data: 1; - uint32_t rx_wfull: 1; - uint32_t rx_rempty: 1; - uint32_t tx_wfull: 1; - uint32_t tx_rempty: 1; - uint32_t reserved6: 26; - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t rx_take_data: 1; - uint32_t tx_put_data: 1; - uint32_t rx_wfull: 1; - uint32_t rx_rempty: 1; - uint32_t tx_wfull: 1; - uint32_t tx_rempty: 1; - uint32_t reserved6: 26; - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t tx_bck_in_delay: 2; - uint32_t tx_ws_in_delay: 2; - uint32_t rx_bck_in_delay: 2; - uint32_t rx_ws_in_delay: 2; - uint32_t rx_sd_in_delay: 2; - uint32_t tx_bck_out_delay: 2; - uint32_t tx_ws_out_delay: 2; - uint32_t tx_sd_out_delay: 2; - uint32_t rx_ws_out_delay: 2; - uint32_t rx_bck_out_delay: 2; - uint32_t tx_dsync_sw: 1; - uint32_t rx_dsync_sw: 1; - uint32_t tx_bck_in_inv: 1; - uint32_t reserved23: 9; - }; - uint32_t val; - } timing; - union { - struct { - uint32_t rx_data_num: 6; - uint32_t tx_data_num: 6; - uint32_t dscr_en: 1; - uint32_t tx_fifo_mod: 3; - uint32_t rx_fifo_mod: 3; - uint32_t reserved19: 13; - }; - uint32_t val; - } fifo_conf; - uint32_t rx_eof_num; - uint32_t conf_single_data; - union { - struct { - uint32_t tx_chan_mod: 3; - uint32_t rx_chan_mod: 2; - uint32_t reserved5: 27; - }; - uint32_t val; - } conf_chan; -} i2s_struct_t; - -extern volatile i2s_struct_t I2S0; - -#ifdef __cplusplus -} -#endif /* end of __cplusplus */ - diff --git a/Sming/Arch/Esp32/Components/esp32/include/espinc/pin_mux_register.h b/Sming/Arch/Esp32/Components/esp32/include/espinc/pin_mux_register.h deleted file mode 100644 index 0e48f7ef6a..0000000000 --- a/Sming/Arch/Esp32/Components/esp32/include/espinc/pin_mux_register.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - * ESPRSSIF MIT License - * - * Copyright (c) 2015 - * - * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case, - * it is free of charge, to any person obtaining a copy of this software and associated - * documentation files (the "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the Software is furnished - * to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all copies or - * substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _PIN_MUX_H_ -#define _PIN_MUX_H_ - -#include - -#define PERIPHS_IO_MUX 0x60000800 - -#define PERIPHS_IO_MUX_FUNC 0x13 -#define PERIPHS_IO_MUX_FUNC_S 4 -#define PERIPHS_IO_MUX_PULLUP BIT7 -#define PERIPHS_IO_MUX_PULLDWN BIT6 -#define PERIPHS_IO_MUX_SLEEP_PULLUP BIT3 -#define PERIPHS_IO_MUX_SLEEP_PULLDWN BIT2 -#define PERIPHS_IO_MUX_SLEEP_OE BIT1 -#define PERIPHS_IO_MUX_OE BIT0 - -#define PERIPHS_IO_MUX_CONF_U (PERIPHS_IO_MUX + 0x00) -#define SPI0_CLK_EQU_SYS_CLK BIT8 -#define SPI1_CLK_EQU_SYS_CLK BIT9 - -#define FUNC_MTDI 0 -#define FUNC_I2SI_DATA 1 -#define FUNC_HSPIQ_MISO 2 -#define FUNC_GPIO12 3 -#define FUNC_UART0_DTR 4 - -#define FUNC_MTCK 0 -#define FUNC_I2SI_BCK 1 -#define FUNC_HSPID_MOSI 2 -#define FUNC_GPIO13 3 -#define FUNC_UART0_CTS 4 - -#define FUNC_MTMS 0 -#define FUNC_I2SI_WS 1 -#define FUNC_HSPI_CLK 2 -#define FUNC_GPIO14 3 -#define FUNC_UART0_DSR 4 - -#define FUNC_MTDO 0 -#define FUNC_I2SO_BCK 1 -#define FUNC_HSPI_CS0 2 -#define FUNC_GPIO15 3 -#define FUNC_U0RTS 4 -#define FUNC_UART0_RTS 4 - -#define FUNC_U0RXD 0 -#define FUNC_UART0_RXD 0 -#define FUNC_I2SO_DATA 1 -#define FUNC_GPIO3 3 -#define FUNC_CLK_XTAL_BK 4 - -#define FUNC_U0TXD 0 -#define FUNC_UART0_TXD 0 -#define FUNC_SPICS1 1 -#define FUNC_GPIO1 3 -#define FUNC_CLK_RTC_BK 4 - -#define FUNC_SDCLK 0 -#define FUNC_SPICLK 1 -#define FUNC_GPIO6 3 -#define UART1_CTS 4 - -#define FUNC_SDDATA0 0 -#define FUNC_SPIQ_MISO 1 -#define FUNC_GPIO7 3 -#define FUNC_U1TXD 4 -#define FUNC_UART1_TXD 4 - -#define FUNC_SDDATA1 0 -#define FUNC_SPID_MOSI 1 -#define FUNC_GPIO8 3 -#define FUNC_U1RXD 4 -#define FUNC_UART1_RXD 4 - -#define FUNC_SDDATA2 0 -#define FUNC_SPIHD 1 -#define FUNC_GPIO9 3 -#define UFNC_HSPIHD 4 - -#define FUNC_SDDATA3 0 -#define FUNC_SPIWP 1 -#define FUNC_GPIO10 3 -#define FUNC_HSPIWP 4 - -#define FUNC_SDCMD 0 -#define FUNC_SPICS0 1 -#define FUNC_GPIO11 3 -#define U1RTS 4 -#define UART1_RTS 4 - -#define FUNC_GPIO0 0 -#define FUNC_SPICS2 1 -#define FUNC_CLK_OUT 4 - -#define FUNC_GPIO2 0 -#define FUNC_I2SO_WS 1 -#define FUNC_U1TXD_BK 2 -#define FUNC_UART1_TXD_BK 2 -#define FUNC_U0TXD_BK 4 -#define FUNC_UART0_TXD_BK 4 - -#define FUNC_GPIO4 0 -#define FUNC_CLK_XTAL 1 - -#define FUNC_GPIO5 0 -#define FUNC_CLK_RTC 1 - -#define PIN_PULLUP_DIS(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLUP) -#define PIN_PULLUP_EN(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLUP) - -#define PERIPHS_GPIO_MUX_REG(i) \ - (i==0) ? PERIPHS_IO_MUX_GPIO0_U: \ - (i==1) ? PERIPHS_IO_MUX_U0TXD_U: \ - (i==2) ? PERIPHS_IO_MUX_GPIO2_U: \ - (i==3) ? PERIPHS_IO_MUX_U0RXD_U: \ - (i==4) ? PERIPHS_IO_MUX_GPIO4_U: \ - (i==5) ? PERIPHS_IO_MUX_GPIO5_U: \ - (i==6) ? PERIPHS_IO_MUX_SD_CLK_U: \ - (i==7) ? PERIPHS_IO_MUX_SD_DATA0_U: \ - (i==8) ? PERIPHS_IO_MUX_SD_DATA1_U: \ - (i==9) ? PERIPHS_IO_MUX_SD_DATA2_U: \ - (i==10)? PERIPHS_IO_MUX_SD_DATA3_U: \ - (i==11)? PERIPHS_IO_MUX_SD_CMD_U: \ - (i==12)? PERIPHS_IO_MUX_MTDI_U: \ - (i==13)? PERIPHS_IO_MUX_MTCK_U: \ - (i==14)? PERIPHS_IO_MUX_MTMS_U: \ - (i==15)? PERIPHS_IO_MUX_MTDO_U: \ - PAD_XPD_DCDC_CONF - -#endif //_PIN_MUX_H_ diff --git a/Sming/Arch/Esp32/Components/esp32/include/espinc/slc_register.h b/Sming/Arch/Esp32/Components/esp32/include/espinc/slc_register.h deleted file mode 100644 index 7564c81680..0000000000 --- a/Sming/Arch/Esp32/Components/esp32/include/espinc/slc_register.h +++ /dev/null @@ -1,289 +0,0 @@ -// Copyright 2018-2025 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#ifndef _SLC_REGISTER_H_ -#define _SLC_REGISTER_H_ - -#include "../../../esp32/include/espinc/eagle_soc.h" - -#define REG_SLC_BASE 0x60000B00 -//version value:32'h091700 - -#define SLC_CONF0 (REG_SLC_BASE + 0x0) -#ifndef ESP_MAC_5 -#define SLC_MODE 0x00000003 -#define SLC_MODE_S 12 -#endif -#define SLC_DATA_BURST_EN (BIT(9)) -#define SLC_DSCR_BURST_EN (BIT(8)) -#define SLC_RX_NO_RESTART_CLR (BIT(7)) -#define SLC_RX_AUTO_WRBACK (BIT(6)) -#define SLC_RX_LOOP_TEST (BIT(5)) -#define SLC_TX_LOOP_TEST (BIT(4)) -#define SLC_AHBM_RST (BIT(3)) -#define SLC_AHBM_FIFO_RST (BIT(2)) -#define SLC_RXLINK_RST (BIT(1)) -#define SLC_TXLINK_RST (BIT(0)) - -#define SLC_INT_RAW (REG_SLC_BASE + 0x4) -#define SLC_TX_DSCR_EMPTY_INT_RAW (BIT(21)) -#define SLC_RX_DSCR_ERR_INT_RAW (BIT(20)) -#define SLC_TX_DSCR_ERR_INT_RAW (BIT(19)) -#define SLC_TOHOST_INT_RAW (BIT(18)) -#define SLC_RX_EOF_INT_RAW (BIT(17)) -#define SLC_RX_DONE_INT_RAW (BIT(16)) -#define SLC_TX_EOF_INT_RAW (BIT(15)) -#define SLC_TX_DONE_INT_RAW (BIT(14)) -#define SLC_TOKEN1_1TO0_INT_RAW (BIT(13)) -#define SLC_TOKEN0_1TO0_INT_RAW (BIT(12)) -#define SLC_TX_OVF_INT_RAW (BIT(11)) -#define SLC_RX_UDF_INT_RAW (BIT(10)) -#define SLC_TX_START_INT_RAW (BIT(9)) -#define SLC_RX_START_INT_RAW (BIT(8)) -#define SLC_FRHOST_BIT7_INT_RAW (BIT(7)) -#define SLC_FRHOST_BIT6_INT_RAW (BIT(6)) -#define SLC_FRHOST_BIT5_INT_RAW (BIT(5)) -#define SLC_FRHOST_BIT4_INT_RAW (BIT(4)) -#define SLC_FRHOST_BIT3_INT_RAW (BIT(3)) -#define SLC_FRHOST_BIT2_INT_RAW (BIT(2)) -#define SLC_FRHOST_BIT1_INT_RAW (BIT(1)) -#define SLC_FRHOST_BIT0_INT_RAW (BIT(0)) - -#define SLC_INT_STATUS (REG_SLC_BASE + 0x8) -#define SLC_TX_DSCR_EMPTY_INT_ST (BIT(21)) -#define SLC_RX_DSCR_ERR_INT_ST (BIT(20)) -#define SLC_TX_DSCR_ERR_INT_ST (BIT(19)) -#define SLC_TOHOST_INT_ST (BIT(18)) -#define SLC_RX_EOF_INT_ST (BIT(17)) -#define SLC_RX_DONE_INT_ST (BIT(16)) -#define SLC_TX_EOF_INT_ST (BIT(15)) -#define SLC_TX_DONE_INT_ST (BIT(14)) -#define SLC_TOKEN1_1TO0_INT_ST (BIT(13)) -#define SLC_TOKEN0_1TO0_INT_ST (BIT(12)) -#define SLC_TX_OVF_INT_ST (BIT(11)) -#define SLC_RX_UDF_INT_ST (BIT(10)) -#define SLC_TX_START_INT_ST (BIT(9)) -#define SLC_RX_START_INT_ST (BIT(8)) -#define SLC_FRHOST_BIT7_INT_ST (BIT(7)) -#define SLC_FRHOST_BIT6_INT_ST (BIT(6)) -#define SLC_FRHOST_BIT5_INT_ST (BIT(5)) -#define SLC_FRHOST_BIT4_INT_ST (BIT(4)) -#define SLC_FRHOST_BIT3_INT_ST (BIT(3)) -#define SLC_FRHOST_BIT2_INT_ST (BIT(2)) -#define SLC_FRHOST_BIT1_INT_ST (BIT(1)) -#define SLC_FRHOST_BIT0_INT_ST (BIT(0)) - -#define SLC_INT_ENA (REG_SLC_BASE + 0xC) -#define SLC_TX_DSCR_EMPTY_INT_ENA (BIT(21)) -#define SLC_RX_DSCR_ERR_INT_ENA (BIT(20)) -#define SLC_TX_DSCR_ERR_INT_ENA (BIT(19)) -#define SLC_TOHOST_INT_ENA (BIT(18)) -#define SLC_RX_EOF_INT_ENA (BIT(17)) -#define SLC_RX_DONE_INT_ENA (BIT(16)) -#define SLC_TX_EOF_INT_ENA (BIT(15)) -#define SLC_TX_DONE_INT_ENA (BIT(14)) -#define SLC_TOKEN1_1TO0_INT_ENA (BIT(13)) -#define SLC_TOKEN0_1TO0_INT_ENA (BIT(12)) -#define SLC_TX_OVF_INT_ENA (BIT(11)) -#define SLC_RX_UDF_INT_ENA (BIT(10)) -#define SLC_TX_START_INT_ENA (BIT(9)) -#define SLC_RX_START_INT_ENA (BIT(8)) -#define SLC_FRHOST_BIT7_INT_ENA (BIT(7)) -#define SLC_FRHOST_BIT6_INT_ENA (BIT(6)) -#define SLC_FRHOST_BIT5_INT_ENA (BIT(5)) -#define SLC_FRHOST_BIT4_INT_ENA (BIT(4)) -#define SLC_FRHOST_BIT3_INT_ENA (BIT(3)) -#define SLC_FRHOST_BIT2_INT_ENA (BIT(2)) -#define SLC_FRHOST_BIT1_INT_ENA (BIT(1)) -#define SLC_FRHOST_BIT0_INT_ENA (BIT(0)) - -#define SLC_FRHOST_BIT_INT_ENA_ALL 0xff - -#define SLC_INT_CLR (REG_SLC_BASE + 0x10) -#define SLC_TX_DSCR_EMPTY_INT_CLR (BIT(21)) -#define SLC_RX_DSCR_ERR_INT_CLR (BIT(20)) -#define SLC_TX_DSCR_ERR_INT_CLR (BIT(19)) -#define SLC_TOHOST_INT_CLR (BIT(18)) -#define SLC_RX_EOF_INT_CLR (BIT(17)) -#define SLC_RX_DONE_INT_CLR (BIT(16)) -#define SLC_TX_EOF_INT_CLR (BIT(15)) -#define SLC_TX_DONE_INT_CLR (BIT(14)) -#define SLC_TOKEN1_1TO0_INT_CLR (BIT(13)) -#define SLC_TOKEN0_1TO0_INT_CLR (BIT(12)) -#define SLC_TX_OVF_INT_CLR (BIT(11)) -#define SLC_RX_UDF_INT_CLR (BIT(10)) -#define SLC_TX_START_INT_CLR (BIT(9)) -#define SLC_RX_START_INT_CLR (BIT(8)) -#define SLC_FRHOST_BIT7_INT_CLR (BIT(7)) -#define SLC_FRHOST_BIT6_INT_CLR (BIT(6)) -#define SLC_FRHOST_BIT5_INT_CLR (BIT(5)) -#define SLC_FRHOST_BIT4_INT_CLR (BIT(4)) -#define SLC_FRHOST_BIT3_INT_CLR (BIT(3)) -#define SLC_FRHOST_BIT2_INT_CLR (BIT(2)) -#define SLC_FRHOST_BIT1_INT_CLR (BIT(1)) -#define SLC_FRHOST_BIT0_INT_CLR (BIT(0)) - -#define SLC_RX_STATUS (REG_SLC_BASE + 0x14) -#define SLC_RX_EMPTY (BIT(1)) -#define SLC_RX_FULL (BIT(0)) - -#define SLC_RX_FIFO_PUSH (REG_SLC_BASE + 0x18) -#define SLC_RXFIFO_PUSH (BIT(16)) -#define SLC_RXFIFO_WDATA 0x000001FF -#define SLC_RXFIFO_WDATA_S 0 - -#define SLC_TX_STATUS (REG_SLC_BASE + 0x1C) -#define SLC_TX_EMPTY (BIT(1)) -#define SLC_TX_FULL (BIT(0)) - -#define SLC_TX_FIFO_POP (REG_SLC_BASE + 0x20) -#define SLC_TXFIFO_POP (BIT(16)) -#define SLC_TXFIFO_RDATA 0x000007FF -#define SLC_TXFIFO_RDATA_S 0 - -#define SLC_RX_LINK (REG_SLC_BASE + 0x24) -#define SLC_RXLINK_PARK (BIT(31)) -#define SLC_RXLINK_RESTART (BIT(30)) -#define SLC_RXLINK_START (BIT(29)) -#define SLC_RXLINK_STOP (BIT(28)) -#define SLC_RXLINK_DESCADDR_MASK 0x000FFFFF -#define SLC_RXLINK_ADDR_S 0 - -#define SLC_TX_LINK (REG_SLC_BASE + 0x28) -#define SLC_TXLINK_PARK (BIT(31)) -#define SLC_TXLINK_RESTART (BIT(30)) -#define SLC_TXLINK_START (BIT(29)) -#define SLC_TXLINK_STOP (BIT(28)) -#define SLC_TXLINK_DESCADDR_MASK 0x000FFFFF -#define SLC_TXLINK_ADDR_S 0 - -#define SLC_INTVEC_TOHOST (REG_SLC_BASE + 0x2C) -#define SLC_TOHOST_INTVEC 0x000000FF -#define SLC_TOHOST_INTVEC_S 0 - -#define SLC_TOKEN0 (REG_SLC_BASE + 0x30) -#define SLC_TOKEN0_MASK 0x00000FFF -#define SLC_TOKEN0_S 16 -#define SLC_TOKEN0_LOCAL_INC_MORE (BIT(14)) -#define SLC_TOKEN0_LOCAL_INC (BIT(13)) -#define SLC_TOKEN0_LOCAL_WR (BIT(12)) -#define SLC_TOKEN0_LOCAL_WDATA_MASK 0x00000FFF -#define SLC_TOKEN0_LOCAL_WDATA_S 0 - -#define SLC_TOKEN1 (REG_SLC_BASE + 0x34) -#define SLC_TOKEN1_MASK 0x00000FFF -#define SLC_TOKEN1_S 16 -#define SLC_TOKEN1_LOCAL_INC_MORE (BIT(14)) -#define SLC_TOKEN1_LOCAL_INC (BIT(13)) -#define SLC_TOKEN1_LOCAL_WR (BIT(12)) -#define SLC_TOKEN1_LOCAL_WDATA 0x00000FFF -#define SLC_TOKEN1_LOCAL_WDATA_S 0 - -#define SLC_CONF1 (REG_SLC_BASE + 0x38) -#define SLC_STATE0 (REG_SLC_BASE + 0x3C) -#define SLC_STATE1 (REG_SLC_BASE + 0x40) - -#define SLC_BRIDGE_CONF (REG_SLC_BASE + 0x44) -#ifndef ESP_MAC_5 -#define SLC_TX_PUSH_IDLE_NUM 0x0000FFFF -#define SLC_TX_PUSH_IDLE_NUM_S 16 -#define SLC_TX_DUMMY_MODE (BIT(12)) -#endif -#define SLC_FIFO_MAP_ENA 0x0000000F -#define SLC_FIFO_MAP_ENA_S 8 -#define SLC_TXEOF_ENA 0x0000003F -#define SLC_TXEOF_ENA_S 0 - -#define SLC_RX_EOF_DES_ADDR (REG_SLC_BASE + 0x48) -#define SLC_TX_EOF_DES_ADDR (REG_SLC_BASE + 0x4C) -#define SLC_FROM_HOST_LAST_DESC SLC_TX_EOF_DES_ADDR -#define SLC_TO_HOST_LAST_DESC SLC_RX_EOF_DES_ADDR - -#define SLC_RX_EOF_BFR_DES_ADDR (REG_SLC_BASE + 0x50) -#define SLC_AHB_TEST (REG_SLC_BASE + 0x54) -#define SLC_AHB_TESTADDR 0x00000003 -#define SLC_AHB_TESTADDR_S 4 -#define SLC_AHB_TESTMODE 0x00000007 -#define SLC_AHB_TESTMODE_S 0 - -#define SLC_SDIO_ST (REG_SLC_BASE + 0x58) -#define SLC_BUS_ST 0x00000007 -#define SLC_BUS_ST_S 12 -#define SLC_SDIO_WAKEUP (BIT(8)) -#define SLC_FUNC_ST 0x0000000F -#define SLC_FUNC_ST_S 4 -#define SLC_CMD_ST 0x00000007 -#define SLC_CMD_ST_S 0 - -#define SLC_RX_DSCR_CONF (REG_SLC_BASE + 0x5C) -#ifdef ESP_MAC_5 -#define SLC_INFOR_NO_REPLACE (BIT(9)) -#define SLC_TOKEN_NO_REPLACE (BIT(8)) -#define SLC_POP_IDLE_CNT 0x000000FF -#else -#define SLC_RX_FILL_EN (BIT(20)) -#define SLC_RX_EOF_MODE (BIT(19)) -#define SLC_RX_FILL_MODE (BIT(18)) -#define SLC_INFOR_NO_REPLACE (BIT(17)) -#define SLC_TOKEN_NO_REPLACE (BIT(16)) // -#define SLC_POP_IDLE_CNT 0x0000FFFF -#endif -#define SLC_POP_IDLE_CNT_S 0 - -#define SLC_TXLINK_DSCR (REG_SLC_BASE + 0x60) -#define SLC_TXLINK_DSCR_BF0 (REG_SLC_BASE + 0x64) -#define SLC_TXLINK_DSCR_BF1 (REG_SLC_BASE + 0x68) -#define SLC_RXLINK_DSCR (REG_SLC_BASE + 0x6C) -#define SLC_RXLINK_DSCR_BF0 (REG_SLC_BASE + 0x70) -#define SLC_RXLINK_DSCR_BF1 (REG_SLC_BASE + 0x74) -#define SLC_DATE (REG_SLC_BASE + 0x78) -#define SLC_ID (REG_SLC_BASE + 0x7C) - -#define SLC_HOST_CONF_W0 (REG_SLC_BASE + 0x80 + 0x14) -#define SLC_HOST_CONF_W1 (REG_SLC_BASE + 0x80 + 0x18) -#define SLC_HOST_CONF_W2 (REG_SLC_BASE + 0x80 + 0x20) -#define SLC_HOST_CONF_W3 (REG_SLC_BASE + 0x80 + 0x24) -#define SLC_HOST_CONF_W4 (REG_SLC_BASE + 0x80 + 0x28) - -#define SLC_HOST_INTR_ST (REG_SLC_BASE + 0x80 + 0x1c) -#define SLC_HOST_INTR_CLR (REG_SLC_BASE + 0x80 + 0x30) -#define SLC_HOST_INTR_SOF_BIT (BIT(12)) - -#define SLC_HOST_INTR_ENA (REG_SLC_BASE + 0x80 + 0x34) -#define SLC_RX_NEW_PACKET_INT_ENA (BIT23) -#define SLC_HOST_TOHOST_BIT0_INT_ENA (BIT0) -#define SLC_HOST_CONF_W5 (REG_SLC_BASE + 0x80 + 0x3C) -#define SLC_HOST_INTR_RAW (REG_SLC_BASE + 0x80 + 0x8) -#define SLC_HOST_INTR_ENA_BIT (BIT(23)) -//[15:12]: 0x3ff9xxxx -- 0b01 from_host -// 0x3ffaxxxx -- 0b10 general -// 0x3ffbxxxx -- 0b11 to_host -#define SLC_DATA_ADDR_CLEAR_MASK (~(0xf<<12)) -#define SLC_FROM_HOST_ADDR_MASK (0x1<<12) -#define SLC_TO_HOST_ADDR_MASK (0x3<<12) - -#define SLC_SET_FROM_HOST_ADDR_MASK(v) do { \ - (v) &= SLC_DATA_ADDR_CLEAR_MASK; \ - (v) |= SLC_FROM_HOST_ADDR_MASK; \ - } while(0); - -#define SLC_SET_TO_HOST_ADDR_MASK(v) do { \ - (v) &= SLC_DATA_ADDR_CLEAR_MASK; \ - (v) |= SLC_TO_HOST_ADDR_MASK; \ - } while(0); - - -#define SLC_TX_DESC_DEBUG_REG 0x3ff0002c //[15:0] set to 0xcccc - -#endif diff --git a/Sming/Arch/Esp32/Components/esp32/include/espinc/slc_struct.h b/Sming/Arch/Esp32/Components/esp32/include/espinc/slc_struct.h deleted file mode 100644 index 4f9e519743..0000000000 --- a/Sming/Arch/Esp32/Components/esp32/include/espinc/slc_struct.h +++ /dev/null @@ -1,347 +0,0 @@ -// Copyright 2018-2025 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -#include "../../../esp32/include/espinc/eagle_soc.h" - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ESP8266 SLC Register Definitions */ - -typedef struct { - union { - struct { - uint32_t tx_rst: 1; - uint32_t rx_rst: 1; - uint32_t ahbm_fifo_rst: 1; - uint32_t ahbm_rst: 1; - uint32_t tx_loop_test: 1; - uint32_t rx_loop_test: 1; - uint32_t rx_auto_wrback: 1; - uint32_t rx_no_restart_clr: 1; - uint32_t rxdscr_burst_en: 1; - uint32_t rxdata_burst_en: 1; - uint32_t rxlink_auto_ret: 1; - uint32_t txlink_auto_ret: 1; - uint32_t txdscr_burst_en: 1; - uint32_t txdata_burst_en: 1; - uint32_t reserved14: 18; - }; - uint32_t val; - } conf0; - union { - struct { - uint32_t frhost_bit0: 1; - uint32_t frhost_bit1: 1; - uint32_t frhost_bit2: 1; - uint32_t frhost_bit3: 1; - uint32_t frhost_bit4: 1; - uint32_t frhost_bit5: 1; - uint32_t frhost_bit6: 1; - uint32_t frhost_bit7: 1; - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_udf: 1; - uint32_t tx_ovf: 1; - uint32_t token0_1to0: 1; - uint32_t token1_1to0: 1; - uint32_t tx_done: 1; - uint32_t tx_suc_eof: 1; - uint32_t rx_done: 1; - uint32_t rx_eof: 1; - uint32_t tohost: 1; - uint32_t tx_dscr_err: 1; - uint32_t rx_dscr_err: 1; - uint32_t tx_dscr_empty: 1; - uint32_t reserved22: 10; - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t frhost_bit0: 1; - uint32_t frhost_bit1: 1; - uint32_t frhost_bit2: 1; - uint32_t frhost_bit3: 1; - uint32_t frhost_bit4: 1; - uint32_t frhost_bit5: 1; - uint32_t frhost_bit6: 1; - uint32_t frhost_bit7: 1; - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_udf: 1; - uint32_t tx_ovf: 1; - uint32_t token0_1to0: 1; - uint32_t token1_1to0: 1; - uint32_t tx_done: 1; - uint32_t tx_suc_eof: 1; - uint32_t rx_done: 1; - uint32_t rx_eof: 1; - uint32_t tohost: 1; - uint32_t tx_dscr_err: 1; - uint32_t rx_dscr_err: 1; - uint32_t tx_dscr_empty: 1; - uint32_t reserved22: 10; - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t frhost_bit0: 1; - uint32_t frhost_bit1: 1; - uint32_t frhost_bit2: 1; - uint32_t frhost_bit3: 1; - uint32_t frhost_bit4: 1; - uint32_t frhost_bit5: 1; - uint32_t frhost_bit6: 1; - uint32_t frhost_bit7: 1; - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_udf: 1; - uint32_t tx_ovf: 1; - uint32_t token0_1to0: 1; - uint32_t token1_1to0: 1; - uint32_t tx_done: 1; - uint32_t tx_suc_eof: 1; - uint32_t rx_done: 1; - uint32_t rx_eof: 1; - uint32_t tohost: 1; - uint32_t tx_dscr_err: 1; - uint32_t rx_dscr_err: 1; - uint32_t tx_dscr_empty: 1; - uint32_t reserved22: 10; - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t frhost_bit0: 1; - uint32_t frhost_bit1: 1; - uint32_t frhost_bit2: 1; - uint32_t frhost_bit3: 1; - uint32_t frhost_bit4: 1; - uint32_t frhost_bit5: 1; - uint32_t frhost_bit6: 1; - uint32_t frhost_bit7: 1; - uint32_t rx_start: 1; - uint32_t tx_start: 1; - uint32_t rx_udf: 1; - uint32_t tx_ovf: 1; - uint32_t token0_1to0: 1; - uint32_t token1_1to0: 1; - uint32_t tx_done: 1; - uint32_t tx_suc_eof: 1; - uint32_t rx_done: 1; - uint32_t rx_eof: 1; - uint32_t tohost: 1; - uint32_t tx_dscr_err: 1; - uint32_t rx_dscr_err: 1; - uint32_t tx_dscr_empty: 1; - uint32_t reserved22: 10; - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t rx_full: 1; - uint32_t rx_empty: 1; - uint32_t reserved2: 30; - }; - uint32_t val; - } rx_status; - union { - struct { - uint32_t rxfifo_wdata: 9; - uint32_t reserved9: 7; - uint32_t rxfifo_push: 1; - uint32_t reserved17: 15; - }; - uint32_t val; - } rxfifo_push; - union { - struct { - uint32_t tx_full: 1; - uint32_t tx_empty: 1; - uint32_t reserved2: 30; - }; - uint32_t val; - } tx_status; - union { - struct { - uint32_t txfifo_rdata: 11; - uint32_t reserved11: 5; - uint32_t txfifo_pop: 1; - uint32_t reserved17: 15; - }; - uint32_t val; - } txfifo_pop; - union { - struct { - uint32_t addr: 20; - uint32_t reserved20: 8; - uint32_t stop: 1; - uint32_t start: 1; - uint32_t restart: 1; - uint32_t park: 1; - }; - uint32_t val; - } rx_link; - union { - struct { - uint32_t addr: 20; - uint32_t reserved20: 8; - uint32_t stop: 1; - uint32_t start: 1; - uint32_t restart: 1; - uint32_t park: 1; - }; - uint32_t val; - } tx_link; - union { - struct { - uint32_t intvec: 8; - uint32_t reserved8: 24; - }; - uint32_t val; - } intvec_tohost; - union { - struct { - uint32_t wdata: 12; - uint32_t wr: 1; - uint32_t inc: 1; - uint32_t inc_more: 1; - uint32_t reserved15: 1; - uint32_t token0: 12; - uint32_t reserved28: 4; - }; - uint32_t val; - } token0; - union { - struct { - uint32_t wdata: 12; - uint32_t wr: 1; - uint32_t inc: 1; - uint32_t inc_more: 1; - uint32_t reserved15: 1; - uint32_t token1: 12; - uint32_t reserved28: 4; - }; - uint32_t val; - } token1; - uint32_t conf1; - uint32_t state0; - uint32_t state1; - union { - struct { - uint32_t txeof_ena: 6; - uint32_t reserved6: 2; - uint32_t fifo_map_ena: 4; - uint32_t tx_dummy_mode: 1; - uint32_t reserved13: 3; - uint32_t tx_push_idle_num: 16; - }; - uint32_t val; - } bridge_conf; - uint32_t rx_eof_des_addr; - uint32_t tx_eof_des_addr; - uint32_t to_eof_bfr_des_addr; - union { - struct { - uint32_t mode: 3; - uint32_t reserved3: 1; - uint32_t addr: 2; - uint32_t reserved6: 26; - }; - uint32_t val; - } ahb_test; - union { - struct { - uint32_t cmd_st: 3; - uint32_t reserved3: 1; - uint32_t func_st: 4; - uint32_t sdio_wakeup: 1; - uint32_t reserved9: 3; - uint32_t bus_st: 3; - uint32_t reserved15: 17; - }; - uint32_t val; - } sdio_st; - union { - struct { - uint32_t pop_idle_cnt: 16; - uint32_t token_no_replace: 1; - uint32_t infor_no_replace: 1; - uint32_t rx_fill_mode: 1; - uint32_t rx_eof_mode: 1; - uint32_t rx_fill_en: 1; - uint32_t reserved21: 11; - }; - uint32_t val; - } rx_dscr_conf; - uint32_t txlink_dscr; - uint32_t txlink_dscr_bf0; - uint32_t txlink_dscr_bf1; - uint32_t rxlink_dscr; - uint32_t rxlink_dscr_bf0; - uint32_t rxlink_dscr_bf1; - uint32_t date; - uint32_t id; - uint32_t reserved_80[2]; - union { - struct { - uint32_t reserved0: 23; - uint32_t intr_ena: 1; - uint32_t reserved24: 8; - }; - uint32_t val; - } host_intr_raw; - uint32_t reserved_8C[2]; - uint32_t host_conf_w0; - uint32_t host_conf_w1; - uint32_t host_intr_status; - uint32_t host_conf_w2; - uint32_t host_conf_w3; - uint32_t host_conf_w4; - uint32_t reserved_AC[1]; - union { - struct { - uint32_t reserved0: 12; - uint32_t sof_bit: 1; - uint32_t reserved13: 19; - }; - uint32_t val; - } host_intr_clr; - union { - struct { - uint32_t tohost_bit0: 1; - uint32_t reserved1: 22; - uint32_t rx_new_packet: 1; - uint32_t reserved24: 8; - }; - uint32_t val; - } host_intr_ena; - uint32_t reserved_BC[1]; - uint32_t host_conf_w5; -} slc_struct_t; - -extern volatile slc_struct_t SLC0; - -#ifdef __cplusplus -} -#endif /* end of __cplusplus */ - diff --git a/Sming/Arch/Esp32/Components/esp32/include/espinc/spi_register.h b/Sming/Arch/Esp32/Components/esp32/include/espinc/spi_register.h deleted file mode 100644 index 687ebe5db3..0000000000 --- a/Sming/Arch/Esp32/Components/esp32/include/espinc/spi_register.h +++ /dev/null @@ -1,274 +0,0 @@ -/* - * Copyright (c) 2010 - 2011 Espressif System - * Modified by David Ogilvy (MetalPhreak) - * Based on original file included in SDK 1.0.0 - * - * Missing defines from previous SDK versions have - * been added and are noted with comments. The - * names of these defines are likely to change. - */ - -#pragma once - -#include - -#define SPI_CMD(i) (REG_SPI_BASE(i) + 0x0) -#define SPI_FLASH_READ (BIT(31)) //From previous SDK -#define SPI_FLASH_WREN (BIT(30)) //From previous SDK -#define SPI_FLASH_WRDI (BIT(29)) //From previous SDK -#define SPI_FLASH_RDID (BIT(28)) //From previous SDK -#define SPI_FLASH_RDSR (BIT(27)) //From previous SDK -#define SPI_FLASH_WRSR (BIT(26)) //From previous SDK -#define SPI_FLASH_PP (BIT(25)) //From previous SDK -#define SPI_FLASH_SE (BIT(24)) //From previous SDK -#define SPI_FLASH_BE (BIT(23)) //From previous SDK -#define SPI_FLASH_CE (BIT(22)) //From previous SDK -#define SPI_FLASH_DP (BIT(21)) //From previous SDK -#define SPI_FLASH_RES (BIT(20)) //From previous SDK -#define SPI_FLASH_HPM (BIT(19)) //From previous SDK -#define SPI_USR (BIT(18)) - -#define SPI_ADDR(i) (REG_SPI_BASE(i) + 0x4) - -#define SPI_CTRL(i) (REG_SPI_BASE(i) + 0x8) -#define SPI_WR_BIT_ORDER (BIT(26)) -#define SPI_RD_BIT_ORDER (BIT(25)) -#define SPI_QIO_MODE (BIT(24)) -#define SPI_DIO_MODE (BIT(23)) -#define SPI_TWO_BYTE_STATUS_EN (BIT(22)) //From previous SDK -#define SPI_WP_REG (BIT(21)) //From previous SDK -#define SPI_QOUT_MODE (BIT(20)) -#define SPI_SHARE_BUS (BIT(19)) //From previous SDK -#define SPI_HOLD_MODE (BIT(18)) //From previous SDK -#define SPI_ENABLE_AHB (BIT(17)) //From previous SDK -#define SPI_SST_AAI (BIT(16)) //From previous SDK -#define SPI_RESANDRES (BIT(15)) //From previous SDK -#define SPI_DOUT_MODE (BIT(14)) -#define SPI_FASTRD_MODE (BIT(13)) - -#define SPI_CTRL1(i) (REG_SPI_BASE (i) + 0xC) //From previous SDK. Removed _FLASH_ from name to match other registers. -#define SPI_CS_HOLD_DELAY 0x0000000F //Espressif BBS -#define SPI_CS_HOLD_DELAY_S 28 //Espressif BBS -#define SPI_CS_HOLD_DELAY_RES 0x00000FFF //Espressif BBS -#define SPI_CS_HOLD_DELAY_RES_S 16 //Espressif BBS -#define SPI_BUS_TIMER_LIMIT 0x0000FFFF //From previous SDK -#define SPI_BUS_TIMER_LIMIT_S 0 //From previous SDK - - -#define SPI_RD_STATUS(i) (REG_SPI_BASE(i) + 0x10) -#define SPI_STATUS_EXT 0x000000FF //From previous SDK -#define SPI_STATUS_EXT_S 24 //From previous SDK -#define SPI_WB_MODE 0x000000FF //From previous SDK -#define SPI_WB_MODE_S 16 //From previous SDK -#define SPI_FLASH_STATUS_PRO_FLAG (BIT(7)) //From previous SDK -#define SPI_FLASH_TOP_BOT_PRO_FLAG (BIT(5)) //From previous SDK -#define SPI_FLASH_BP2 (BIT(4)) //From previous SDK -#define SPI_FLASH_BP1 (BIT(3)) //From previous SDK -#define SPI_FLASH_BP0 (BIT(2)) //From previous SDK -#define SPI_FLASH_WRENABLE_FLAG (BIT(1)) //From previous SDK -#define SPI_FLASH_BUSY_FLAG (BIT(0)) //From previous SDK - -#define SPI_CTRL2(i) (REG_SPI_BASE(i) + 0x14) -#define SPI_CS_DELAY_NUM 0x0000000F -#define SPI_CS_DELAY_NUM_S 28 -#define SPI_CS_DELAY_MODE 0x00000003 -#define SPI_CS_DELAY_MODE_S 26 -#define SPI_MOSI_DELAY_NUM 0x00000007 -#define SPI_MOSI_DELAY_NUM_S 23 -#define SPI_MOSI_DELAY_MODE 0x00000003 //mode 0 : posedge; data set at positive edge of clk - //mode 1 : negedge + 1 cycle delay, only if freq<10MHz ; data set at negitive edge of clk - //mode 2 : Do not use this mode. -#define SPI_MOSI_DELAY_MODE_S 21 -#define SPI_MISO_DELAY_NUM 0x00000007 -#define SPI_MISO_DELAY_NUM_S 18 -#define SPI_MISO_DELAY_MODE 0x00000003 -#define SPI_MISO_DELAY_MODE_S 16 -#define SPI_CK_OUT_HIGH_MODE 0x0000000F -#define SPI_CK_OUT_HIGH_MODE_S 12 -#define SPI_CK_OUT_LOW_MODE 0x0000000F -#define SPI_CK_OUT_LOW_MODE_S 8 -#define SPI_HOLD_TIME 0x0000000F -#define SPI_HOLD_TIME_S 4 -#define SPI_SETUP_TIME 0x0000000F -#define SPI_SETUP_TIME_S 0 - -#define SPI_CLOCK(i) (REG_SPI_BASE(i) + 0x18) -#define SPI_CLK_EQU_SYSCLK (BIT(31)) -#define SPI_CLKDIV_PRE 0x00001FFF -#define SPI_CLKDIV_PRE_S 18 -#define SPI_CLKCNT_N 0x0000003F -#define SPI_CLKCNT_N_S 12 -#define SPI_CLKCNT_H 0x0000003F -#define SPI_CLKCNT_H_S 6 -#define SPI_CLKCNT_L 0x0000003F -#define SPI_CLKCNT_L_S 0 - -#define SPI_USER(i) (REG_SPI_BASE(i) + 0x1C) -#define SPI_USR_COMMAND (BIT(31)) -#define SPI_USR_ADDR (BIT(30)) -#define SPI_USR_DUMMY (BIT(29)) -#define SPI_USR_MISO (BIT(28)) -#define SPI_USR_MOSI (BIT(27)) -#define SPI_USR_DUMMY_IDLE (BIT(26)) //From previous SDK -#define SPI_USR_MOSI_HIGHPART (BIT(25)) -#define SPI_USR_MISO_HIGHPART (BIT(24)) -#define SPI_USR_PREP_HOLD (BIT(23)) //From previous SDK -#define SPI_USR_CMD_HOLD (BIT(22)) //From previous SDK -#define SPI_USR_ADDR_HOLD (BIT(21)) //From previous SDK -#define SPI_USR_DUMMY_HOLD (BIT(20)) //From previous SDK -#define SPI_USR_DIN_HOLD (BIT(19)) //From previous SDK -#define SPI_USR_DOUT_HOLD (BIT(18)) //From previous SDK -#define SPI_USR_HOLD_POL (BIT(17)) //From previous SDK -#define SPI_SIO (BIT(16)) -#define SPI_FWRITE_QIO (BIT(15)) -#define SPI_FWRITE_DIO (BIT(14)) -#define SPI_FWRITE_QUAD (BIT(13)) -#define SPI_FWRITE_DUAL (BIT(12)) -#define SPI_WR_BYTE_ORDER (BIT(11)) -#define SPI_RD_BYTE_ORDER (BIT(10)) -#define SPI_AHB_ENDIAN_MODE 0x00000003 //From previous SDK -#define SPI_AHB_ENDIAN_MODE_S 8 //From previous SDK -#define SPI_CK_OUT_EDGE (BIT(7)) -#define SPI_CK_I_EDGE (BIT(6)) -#define SPI_CS_SETUP (BIT(5)) -#define SPI_CS_HOLD (BIT(4)) -#define SPI_AHB_USR_COMMAND (BIT(3)) //From previous SDK -#define SPI_FLASH_MODE (BIT(2)) -#define SPI_AHB_USR_COMMAND_4BYTE (BIT(1)) //From previous SDK -#define SPI_DOUTDIN (BIT(0)) //From previous SDK - -//AHB = http://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture ? - - -#define SPI_USER1(i) (REG_SPI_BASE(i) + 0x20) -#define SPI_USR_ADDR_BITLEN 0x0000003F -#define SPI_USR_ADDR_BITLEN_S 26 -#define SPI_USR_MOSI_BITLEN 0x000001FF -#define SPI_USR_MOSI_BITLEN_S 17 -#define SPI_USR_MISO_BITLEN 0x000001FF -#define SPI_USR_MISO_BITLEN_S 8 -#define SPI_USR_DUMMY_CYCLELEN 0x000000FF -#define SPI_USR_DUMMY_CYCLELEN_S 0 - -#define SPI_USER2(i) (REG_SPI_BASE(i) + 0x24) -#define SPI_USR_COMMAND_BITLEN 0x0000000F -#define SPI_USR_COMMAND_BITLEN_S 28 -#define SPI_USR_COMMAND_VALUE 0x0000FFFF -#define SPI_USR_COMMAND_VALUE_S 0 - -#define SPI_WR_STATUS(i) (REG_SPI_BASE(i) + 0x28) - //previously defined as SPI_FLASH_USER3. No further info available. - -#define SPI_PIN(i) (REG_SPI_BASE(i) + 0x2C) -#define SPI_IDLE_EDGE (BIT(29)) -#define SPI_CS2_DIS (BIT(2)) -#define SPI_CS1_DIS (BIT(1)) -#define SPI_CS0_DIS (BIT(0)) - -#define SPI_SLAVE(i) (REG_SPI_BASE(i) + 0x30) -#define SPI_SYNC_RESET (BIT(31)) -#define SPI_SLAVE_MODE (BIT(30)) -#define SPI_SLV_WR_RD_BUF_EN (BIT(29)) -#define SPI_SLV_WR_RD_STA_EN (BIT(28)) -#define SPI_SLV_CMD_DEFINE (BIT(27)) -#define SPI_TRANS_CNT 0x0000000F -#define SPI_TRANS_CNT_S 23 -#define SPI_SLV_LAST_STATE 0x00000007 //From previous SDK -#define SPI_SLV_LAST_STATE_S 20 //From previous SDK -#define SPI_SLV_LAST_COMMAND 0x00000007 //From previous SDK -#define SPI_SLV_LAST_COMMAND_S 17 //From previous SDK -#define SPI_CS_I_MODE 0x00000003 //From previous SDK -#define SPI_CS_I_MODE_S 10 //From previous SDK -#define SPI_TRANS_DONE_EN (BIT(9)) -#define SPI_SLV_WR_STA_DONE_EN (BIT(8)) -#define SPI_SLV_RD_STA_DONE_EN (BIT(7)) -#define SPI_SLV_WR_BUF_DONE_EN (BIT(6)) -#define SPI_SLV_RD_BUF_DONE_EN (BIT(5)) -#define SLV_SPI_INT_EN 0x0000001f -#define SLV_SPI_INT_EN_S 5 -#define SPI_TRANS_DONE (BIT(4)) -#define SPI_SLV_WR_STA_DONE (BIT(3)) -#define SPI_SLV_RD_STA_DONE (BIT(2)) -#define SPI_SLV_WR_BUF_DONE (BIT(1)) -#define SPI_SLV_RD_BUF_DONE (BIT(0)) - -#define SPI_SLAVE1(i) (REG_SPI_BASE(i) + 0x34) -#define SPI_SLV_STATUS_BITLEN 0x0000001F -#define SPI_SLV_STATUS_BITLEN_S 27 -#define SPI_SLV_STATUS_FAST_EN (BIT(26)) //From previous SDK -#define SPI_SLV_STATUS_READBACK (BIT(25)) //From previous SDK -#define SPI_SLV_BUF_BITLEN 0x000001FF -#define SPI_SLV_BUF_BITLEN_S 16 -#define SPI_SLV_RD_ADDR_BITLEN 0x0000003F -#define SPI_SLV_RD_ADDR_BITLEN_S 10 -#define SPI_SLV_WR_ADDR_BITLEN 0x0000003F -#define SPI_SLV_WR_ADDR_BITLEN_S 4 -#define SPI_SLV_WRSTA_DUMMY_EN (BIT(3)) -#define SPI_SLV_RDSTA_DUMMY_EN (BIT(2)) -#define SPI_SLV_WRBUF_DUMMY_EN (BIT(1)) -#define SPI_SLV_RDBUF_DUMMY_EN (BIT(0)) - - - -#define SPI_SLAVE2(i) (REG_SPI_BASE(i) + 0x38) -#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24 -#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16 -#define SPI_SLV_WRSTR_DUMMY_CYCLELEN 0X000000FF -#define SPI_SLV_WRSTR_DUMMY_CYCLELEN_S 8 -#define SPI_SLV_RDSTR_DUMMY_CYCLELEN 0x000000FF -#define SPI_SLV_RDSTR_DUMMY_CYCLELEN_S 0 - -#define SPI_SLAVE3(i) (REG_SPI_BASE(i) + 0x3C) -#define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF -#define SPI_SLV_WRSTA_CMD_VALUE_S 24 -#define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF -#define SPI_SLV_RDSTA_CMD_VALUE_S 16 -#define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF -#define SPI_SLV_WRBUF_CMD_VALUE_S 8 -#define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF -#define SPI_SLV_RDBUF_CMD_VALUE_S 0 - -//Previous SDKs referred to these following registers as SPI_C0 etc. - -#define SPI_W0(i) (REG_SPI_BASE(i) +0x40) -#define SPI_W1(i) (REG_SPI_BASE(i) +0x44) -#define SPI_W2(i) (REG_SPI_BASE(i) +0x48) -#define SPI_W3(i) (REG_SPI_BASE(i) +0x4C) -#define SPI_W4(i) (REG_SPI_BASE(i) +0x50) -#define SPI_W5(i) (REG_SPI_BASE(i) +0x54) -#define SPI_W6(i) (REG_SPI_BASE(i) +0x58) -#define SPI_W7(i) (REG_SPI_BASE(i) +0x5C) -#define SPI_W8(i) (REG_SPI_BASE(i) +0x60) -#define SPI_W9(i) (REG_SPI_BASE(i) +0x64) -#define SPI_W10(i) (REG_SPI_BASE(i) +0x68) -#define SPI_W11(i) (REG_SPI_BASE(i) +0x6C) -#define SPI_W12(i) (REG_SPI_BASE(i) +0x70) -#define SPI_W13(i) (REG_SPI_BASE(i) +0x74) -#define SPI_W14(i) (REG_SPI_BASE(i) +0x78) -#define SPI_W15(i) (REG_SPI_BASE(i) +0x7C) - - // +0x80 to +0xBC could be SPI_W16 through SPI_W31? - - // +0xC0 to +0xEC not currently defined. - -#define SPI_EXT0(i) (REG_SPI_BASE(i) + 0xF0) //From previous SDK. Removed _FLASH_ from name to match other registers. -#define SPI_T_PP_ENA (BIT(31)) //From previous SDK -#define SPI_T_PP_SHIFT 0x0000000F //From previous SDK -#define SPI_T_PP_SHIFT_S 16 //From previous SDK -#define SPI_T_PP_TIME 0x00000FFF //From previous SDK -#define SPI_T_PP_TIME_S 0 //From previous SDK - -#define SPI_EXT1(i) (REG_SPI_BASE(i) + 0xF4) //From previous SDK. Removed _FLASH_ from name to match other registers. -#define SPI_T_ERASE_ENA (BIT(31)) //From previous SDK -#define SPI_T_ERASE_SHIFT 0x0000000F //From previous SDK -#define SPI_T_ERASE_SHIFT_S 16 //From previous SDK -#define SPI_T_ERASE_TIME 0x00000FFF //From previous SDK -#define SPI_T_ERASE_TIME_S 0 //From previous SDK - -#define SPI_EXT2(i) (REG_SPI_BASE(i) + 0xF8) //From previous SDK. Removed _FLASH_ from name to match other registers. -#define SPI_ST 0x00000007 //From previous SDK -#define SPI_ST_S 0 //From previous SDK - -#define SPI_EXT3(i) (REG_SPI_BASE(i) + 0xFC) -#define SPI_INT_HOLD_ENA 0x00000003 -#define SPI_INT_HOLD_ENA_S 0 diff --git a/Sming/Arch/Esp32/Components/esp32/include/espinc/uart_register.h b/Sming/Arch/Esp32/Components/esp32/include/espinc/uart_register.h deleted file mode 100644 index c35ca56936..0000000000 --- a/Sming/Arch/Esp32/Components/esp32/include/espinc/uart_register.h +++ /dev/null @@ -1,173 +0,0 @@ -// Copyright 2018-2025 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -#include - -#define UART_FIFO(i) (REG_UART_BASE(i) + 0x0) -#define UART_RXFIFO_RD_BYTE 0x000000FF -#define UART_RXFIFO_RD_BYTE_S 0 - -#define UART_INT_RAW(i) (REG_UART_BASE(i) + 0x4) -#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) -#define UART_BRK_DET_INT_RAW (BIT(7)) -#define UART_CTS_CHG_INT_RAW (BIT(6)) -#define UART_DSR_CHG_INT_RAW (BIT(5)) -#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) -#define UART_FRM_ERR_INT_RAW (BIT(3)) -#define UART_PARITY_ERR_INT_RAW (BIT(2)) -#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) -#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) - -#define UART_INT_ST(i) (REG_UART_BASE(i) + 0x8) -#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) -#define UART_BRK_DET_INT_ST (BIT(7)) -#define UART_CTS_CHG_INT_ST (BIT(6)) -#define UART_DSR_CHG_INT_ST (BIT(5)) -#define UART_RXFIFO_OVF_INT_ST (BIT(4)) -#define UART_FRM_ERR_INT_ST (BIT(3)) -#define UART_PARITY_ERR_INT_ST (BIT(2)) -#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) -#define UART_RXFIFO_FULL_INT_ST (BIT(0)) - -#define UART_INT_ENA(i) (REG_UART_BASE(i) + 0xC) -#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) -#define UART_BRK_DET_INT_ENA (BIT(7)) -#define UART_CTS_CHG_INT_ENA (BIT(6)) -#define UART_DSR_CHG_INT_ENA (BIT(5)) -#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) -#define UART_FRM_ERR_INT_ENA (BIT(3)) -#define UART_PARITY_ERR_INT_ENA (BIT(2)) -#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) -#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) - -#define UART_INT_CLR(i) (REG_UART_BASE(i) + 0x10) -#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) -#define UART_BRK_DET_INT_CLR (BIT(7)) -#define UART_CTS_CHG_INT_CLR (BIT(6)) -#define UART_DSR_CHG_INT_CLR (BIT(5)) -#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) -#define UART_FRM_ERR_INT_CLR (BIT(3)) -#define UART_PARITY_ERR_INT_CLR (BIT(2)) -#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) -#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) - -#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) -#define UART_RXFIFO_FULL_INT_ENA_M (BIT(0)) -#define UART_RXFIFO_FULL_INT_ST_M (BIT(0)) -#define UART_RXFIFO_FULL_INT_CLR_M (BIT(0)) - -#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_ENA_M (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_ST_M (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_CLR_M (BIT(1)) - -#define UART_PARITY_ERR_INT_ENA (BIT(2)) -#define UART_PARITY_ERR_INT_ENA_M (BIT(2)) -#define UART_PARITY_ERR_INT_ST_M (BIT(2)) -#define UART_PARITY_ERR_INT_CLR_M (BIT(2)) - -#define UART_FRM_ERR_INT_ENA (BIT(3)) -#define UART_FRM_ERR_INT_ENA_M (BIT(3)) -#define UART_FRM_ERR_INT_ST_M (BIT(3)) -#define UART_FRM_ERR_INT_CLR_M (BIT(3)) - -#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) -#define UART_RXFIFO_OVF_INT_ENA_M (BIT(4)) -#define UART_RXFIFO_OVF_INT_ST_M (BIT(4)) -#define UART_RXFIFO_OVF_INT_CLR_M (BIT(4)) - -#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) -#define UART_RXFIFO_TOUT_INT_ENA_M (BIT(8)) -#define UART_RXFIFO_TOUT_INT_ST_M (BIT(8)) -#define UART_RXFIFO_TOUT_INT_CLR_M (BIT(8)) - -#define UART_CLKDIV_CNT 0x000FFFFF -#define UART_CLKDIV_S 0 - -#define UART_AUTOBAUD(i) (REG_UART_BASE(i) + 0x18) -#define UART_GLITCH_FILT 0x000000FF -#define UART_GLITCH_FILT_S 8 -#define UART_AUTOBAUD_EN (BIT(0)) - -#define UART_STATUS(i) (REG_UART_BASE(i) + 0x1C) -#define UART_TXD (BIT(31)) -#define UART_RTSN (BIT(30)) -#define UART_DTRN (BIT(29)) -#define UART_TXFIFO_CNT 0x000000FF -#define UART_TXFIFO_CNT_S 16 -#define UART_RXD (BIT(15)) -#define UART_CTSN (BIT(14)) -#define UART_DSRN (BIT(13)) -#define UART_RXFIFO_CNT 0x000000FF -#define UART_RXFIFO_CNT_S 0 - -#define UART_CONF0(i) (REG_UART_BASE(i) + 0x20) -#define UART_DTR_INV (BIT(24)) -#define UART_RTS_INV (BIT(23)) -#define UART_TXD_INV (BIT(22)) -#define UART_DSR_INV (BIT(21)) -#define UART_CTS_INV (BIT(20)) -#define UART_RXD_INV (BIT(19)) -#define UART_TXFIFO_RST (BIT(18)) -#define UART_RXFIFO_RST (BIT(17)) -#define UART_IRDA_EN (BIT(16)) -#define UART_TX_FLOW_EN (BIT(15)) -#define UART_LOOPBACK (BIT(14)) -#define UART_IRDA_RX_INV (BIT(13)) -#define UART_IRDA_TX_INV (BIT(12)) -#define UART_IRDA_WCTL (BIT(11)) -#define UART_IRDA_TX_EN (BIT(10)) -#define UART_IRDA_DPLX (BIT(9)) -#define UART_TXD_BRK (BIT(8)) -#define UART_SW_DTR (BIT(7)) -#define UART_SW_RTS (BIT(6)) -#define UART_STOP_BIT_NUM 0x00000003 -#define UART_STOP_BIT_NUM_S 4 -#define UART_BIT_NUM 0x00000003 -#define UART_BIT_NUM_S 2 -#define UART_PARITY_EN (BIT(1)) -#define UART_PARITY_EN_S 1 -#define UART_PARITY (BIT(0)) -#define UART_PARITY_S 0 - -#define UART_CONF1(i) (REG_UART_BASE(i) + 0x24) -#define UART_RX_TOUT_EN (BIT(31)) -#define UART_RX_TOUT_THRHD 0x0000007F -#define UART_RX_TOUT_THRHD_S 24 -#define UART_RX_FLOW_EN (BIT(23)) -#define UART_RX_FLOW_THRHD 0x0000007F -#define UART_RX_FLOW_THRHD_S 16 -#define UART_TXFIFO_EMPTY_THRHD 0x0000007F -#define UART_TXFIFO_EMPTY_THRHD_S 8 -#define UART_RXFIFO_FULL_THRHD 0x0000007F -#define UART_RXFIFO_FULL_THRHD_S 0 - -#define UART_LOWPULSE(i) (REG_UART_BASE(i) + 0x28) -#define UART_LOWPULSE_MIN_CNT 0x000FFFFF -#define UART_LOWPULSE_MIN_CNT_S 0 - -#define UART_HIGHPULSE(i) (REG_UART_BASE(i) + 0x2C) -#define UART_HIGHPULSE_MIN_CNT 0x000FFFFF -#define UART_HIGHPULSE_MIN_CNT_S 0 - -#define UART_PULSE_NUM(i) (REG_UART_BASE(i) + 0x30) -#define UART_PULSE_NUM_CNT 0x0003FF -#define UART_PULSE_NUM_CNT_S 0 - -#define UART_SWAP_REG 0x3FF00028 -#define UART_SWAP BIT(0) //Swaps UART -#define UART_SWAP0 BIT(2) //Swaps UART 0 pins (u0rxd <-> u0cts), (u0txd <-> u0rts) -#define UART_SWAP1 BIT(3) //Swaps UART 1 pins (u1rxd <-> u1cts), (u1txd <-> u1rts) diff --git a/Sming/Arch/Esp32/Components/esp32/src/include/esp_systemapi.h b/Sming/Arch/Esp32/Components/esp32/src/include/esp_systemapi.h index ff0dfe2d62..25e620cd37 100644 --- a/Sming/Arch/Esp32/Components/esp32/src/include/esp_systemapi.h +++ b/Sming/Arch/Esp32/Components/esp32/src/include/esp_systemapi.h @@ -27,9 +27,6 @@ #include "esp_tasks.h" #include #include -#include -#include -#include #include #include #include