1.2_Computer_system_organization_Interrupts

Interrupts are used for many other purposes as well and are a key part of how operating systems and hardware interact.

Hardware may trigger any time by sending a signal to the CPU, usually by way of the system bus.

There may be many buses within a computer system, but the system bus is the main communications path between the major components

When the CPU is interrupted, it stops what it is doing and immediately transfers execution to a fixed location. 

The fixed location usually contains the starting address where the service routine for the interrupt is located.

The interrupt service routine executes; on completion, the CPU resumes the interrupted computation.

===>  Interrupt -> Interrupt service routine -> Interrupt-specific handler. 

A table of pointers to interrupt routines can be used instead to provide the necessary speed. The interrupt routine is called indirectly through the table, with no intermediate routine needed.

Generally, the table of pointers is stored in low memory (the first hundread or so locations). These locations hold the addresses of the interrupt service for the various devices. This array or interrupt vector, of addresses is then indexed by a unique number, given with interrupt request to provide the address of the interrupt service routine for the interrupting device.

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The basic interrupt mechanism:
   
    - CPU hardware has a wire called the `interrupt-rquest line` that CPU senses after executing every instruction
    - When the CPU detects that a controller has asserted a signal on interrupt-request line, it reads the interrupt number and jumps to the 
  `interrupt-handler routine` by using that interrupt number as an index into the interrupt vector
    - It then starts execution at the address associated with that index
    - The interrupt hadler saves any state it will be changing during its operation, determines the cause of the interrupt, performs the necessary processing, performs a state restore, and executes a return_from_interrupt instruction to return the CPU to the execution state prior to the interrupt.
    
    
    Device Controller RAISES an interrupt by asserting a signal on the interrupt request line
    CPU CATCHES the interrupt and DISPATCHES it to the interrupt handler
    Handler CLEARS the interrupt by servicing the device
    
    
 ==> Sophisticated interrupt handling features:
 
1. We need the ability to defer interrupt handling during critical processing.
2. We need an efficient way to dispatch to the proper interrupt handler for
a device.
3. We need multilevel interrupts, so that the operating system can distin-
guish between high- and low-priority interrupts and can respond with
the appropriate degree of urgency.

In modern computer hardware, these three features are provided by the CPU
and the interrupt-controller hardware.


==> Most CPUs have two interrupt lines.
	- nonmaskable interrupt: Reserved for events such as unrecoverable memory errors
	- maskable interrupt: It can be turned off by the CPU before the execution of critical instruction sequences that must not be interrupted
	
	The maskable interrupt is used by device controllers to request service.