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opcode.h
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/* OPCODE.H (C) Copyright Jan Jaeger, 2000-2012 */
/* (C) and others 2013-2023 */
/* Instruction decoding macros and prototypes */
/* */
/* Released under "The Q Public License Version 1" */
/* (http://www.hercules-390.org/herclic.html) as modifications to */
/* Hercules. */
/* Interpretive Execution - (C) Copyright Jan Jaeger, 1999-2012 */
/* z/Architecture support - (C) Copyright Jan Jaeger, 1999-2012 */
#ifndef _OPCODE_H
#define _OPCODE_H
/*-------------------------------------------------------------------*/
/* (delineates ARCH_DEP from non-arch_dep) */
/*-------------------------------------------------------------------*/
/*-------------------------------------------------------------------*/
/* Architecture *INDEPENDENT* macros */
/*-------------------------------------------------------------------*/
/* The following macros are defined ONE TIME (due to the above */
/* "#ifndef _OPCODE_H" guard) and thus are the same for ALL */
/* build architectures. */
/*-------------------------------------------------------------------*/
/*-------------------------------------------------------------------*/
/* helper macros to define an opcode table instruction function name */
/*-------------------------------------------------------------------*/
#if defined( _370 )
#define _GEN370( _ifunc_name ) &s370_ ## _ifunc_name,
#else
#define _GEN370( _ifunc_name )
#endif
#if defined( _390 )
#define _GEN390( _ifunc_name ) &s390_ ## _ifunc_name,
#else
#define _GEN390( _ifunc_name )
#endif
#if defined( _900 )
#define _GEN900( _ifunc_name ) &z900_ ## _ifunc_name,
#else
#define _GEN900( _ifunc_name )
#endif
/*-------------------------------------------------------------------*/
/* Macros for defining opcode table entries */
/*-------------------------------------------------------------------*/
/* */
/* The below GENx...macros are used to define the NON-archdep master */
/* opcode table entries in opcode.c. Each entry defines a separate */
/* pointer to an architecture DEPENDENT instruction function for all */
/* three of our supported build architectures, as well as a common */
/* instruction tracing function (based on the instruction's format) */
/* and a string used during tracing containing the instruction's */
/* mnemonic and instruction function's name, because each opcode is */
/* expected to define the same instruction for each architecture if */
/* that opcode is defined in the given architecture. */
/* */
/* That is to say, using the below macros, it is NOT possible to de- */
/* fine a table entry for a given opcode for an instruction that is */
/* completely different in one architecture than it is in the other */
/* architectures. Opcode 'D2' for example, is expected to be the op- */
/* code for the "MVC" instruction in all three architectures. */
/* */
/* With later versions of z/Architecture however, this is not neces- */
/* sarily always true. In later versions of z/Architecture, IBM has */
/* begun re-using opcodes for older S/370-only instructions. In such */
/* type of situations you need to define an architecture DEPENDENT */
/* opcode table instead, using the new 'AD_GENx...' macros defined */
/* further below in the architecture-DEPENDENT section of opcode.h */
/* (which immediately follows the "#endif" for _OPCODE_H). */
/* */
/*-------------------------------------------------------------------*/
/* */
/* PROGRAMMING NOTE */
/* */
/* PROGRAMMING NOTE: the '_ifmt' argument in the below "GENx" macros */
/* is currently ignored since it is not being used for anything at */
/* the moment. At some point in the near future however, if things */
/* work out, it will actually be used as a function call to decode */
/* the instruction before being dispatched to the actual function */
/* that executes the instruction, relieving each instruction from */
/* having to decode the instruction itself each time (as well as */
/* relieving the instruction 'iprint' (tracing) functions from also */
/* having to decode the instruction too!) After all, if there are */
/* 57 instructions defined that use the 'RR' format and 220 defined */
/* that use the 'RRE' format, etc, why should they each have to do */
/* the same thing themselves each time? There needs to be a common */
/* instruction format decoding function that is called before each */
/* instruction function is ever reached so that all the instruction */
/* itself has to do is whatever its purpose is. After all, decoding */
/* an instruction is LOGICALLY part of the instruction decoding and */
/* dispatching logic, NOT something that each instruction (or each */
/* 'iprint' tracing function!) should be doing themselves. This is */
/* what I intend to (hope to) fix at some point in the near future. */
/* */
/*-------------------------------------------------------------------*/
#define GENx___x___x___ \
{ \
&operation_exception, \
&operation_exception, \
&operation_exception, \
(void*) &iprint_ASMFMT_none, \
(void*) &"?????" "\0" "?" \
}
#define GENx370x___x___( _mnemonic, _ifmt, _asmfmt, _ifunc_name ) \
{ \
_GEN370( _ifunc_name ) \
&operation_exception, \
&operation_exception, \
(void*) &iprint_ ## _asmfmt, \
(void*) & _mnemonic "\0" #_ifunc_name \
}
#define GENx___x390x___( _mnemonic, _ifmt, _asmfmt, _ifunc_name ) \
{ \
&operation_exception, \
_GEN390( _ifunc_name ) \
&operation_exception, \
(void*) &iprint_ ## _asmfmt, \
(void*) & _mnemonic "\0" #_ifunc_name \
}
#define GENx370x390x___( _mnemonic, _ifmt, _asmfmt, _ifunc_name ) \
{ \
_GEN370( _ifunc_name ) \
_GEN390( _ifunc_name ) \
&operation_exception, \
(void*) &iprint_ ## _asmfmt, \
(void*) & _mnemonic "\0" #_ifunc_name \
}
#define GENx___x___x900( _mnemonic, _ifmt, _asmfmt, _ifunc_name ) \
{ \
&operation_exception, \
&operation_exception, \
_GEN900( _ifunc_name ) \
(void*) &iprint_ ## _asmfmt, \
(void*) & _mnemonic "\0" #_ifunc_name \
}
#define GENx370x___x900( _mnemonic, _ifmt, _asmfmt, _ifunc_name ) \
{ \
_GEN370( _ifunc_name ) \
&operation_exception, \
_GEN900( _ifunc_name ) \
(void*) &iprint_ ## _asmfmt, \
(void*) & _mnemonic "\0" #_ifunc_name \
}
#define GENx___x390x900( _mnemonic, _ifmt, _asmfmt, _ifunc_name ) \
{ \
&operation_exception, \
_GEN390( _ifunc_name ) \
_GEN900( _ifunc_name ) \
(void*) &iprint_ ## _asmfmt, \
(void*) & _mnemonic "\0" #_ifunc_name \
}
#define GENx370x390x900( _mnemonic, _ifmt, _asmfmt, _ifunc_name ) \
{ \
_GEN370( _ifunc_name ) \
_GEN390( _ifunc_name ) \
_GEN900( _ifunc_name ) \
(void*) &iprint_ ## _asmfmt, \
(void*) & _mnemonic "\0" #_ifunc_name \
}
/*-------------------------------------------------------------------*/
/* PROGRAMMING NOTE */
/*-------------------------------------------------------------------*/
/* The following set of macros identifies those instructions which */
/* are a part of the FEATURE_370_EXTENSION backport of some S/390 */
/* and z/Architecture instructions to System/370 mode (refer to the */
/* the feat370.h header). All instructions so identified will have */
/* their instruction generated also for the S/370 architecture mode */
/* as well, even though such instruction are not formally a part of */
/* the System/370 architecture. */
/* */
/* Whether or not such instructions cause a Program Check Operation */
/* Exception to occur when executed in S/370 mode is controlled via */
/* enabling or disabling the 'HERC_370_EXTENSION' archlvl facility. */
/* */
/* When the facility is disabled (default), all such instructions */
/* will properly Program Check (Operation Exception) when attempted */
/* to be executed in S/370 mode. When the facility enabled however, */
/* then all such "37X" instructions are instead allowed to execute. */
/*-------------------------------------------------------------------*/
#define GENx37Xx390x___ GENx370x390x___
#define GENx37Xx___x900 GENx370x___x900
#define GENx37Xx390x900 GENx370x390x900
#define AD_GENx37Xx390x___ AD_GENx370x390x___
#define AD_GENx37Xx___x900 AD_GENx370x___x900
#define AD_GENx37Xx390x900 AD_GENx370x390x900
/*-------------------------------------------------------------------*/
#define ILC(_b) ((_b) < 0x40 ? 2 : (_b) < 0xc0 ? 4 : 6)
#define REAL_ILC(_regs) \
(likely(!(_regs)->execflag) ? (_regs)->psw.ilc : (_regs)->exrl ? 6 : 4)
#define ILC_FROM_PIID( piid ) (((piid) & 0x00070000) >> 16)
#define CODE_FROM_PIID( piid ) (((piid) & 0x0000FFFF) )
/*-------------------------------------------------------------------*/
/* Instruction tracing helper function to print the instruction */
/*-------------------------------------------------------------------*/
#define PRINT_INST( _arch_mode, _inst, _prtbuf ) \
\
iprint_router_func( (_arch_mode), (_inst), 0, (_prtbuf) )
OPCD_DLL_IMPORT int iprint_router_func( int arch_mode, BYTE inst[], char mnemonic[], char* prtbuf );
/*-------------------------------------------------------------------*/
/* Individual instruction counting */
/*-------------------------------------------------------------------*/
#if defined( OPTION_INSTR_COUNT_AND_TIME )
#define BEG_COUNT_INSTR( _inst, _regs ) \
do \
{ \
if (sysblk.icount) \
{ \
U64 used; \
gettimeofday(&sysblk.start_time, NULL); \
switch ((_inst)[0]) { \
case 0x01: \
used = sysblk.imaps.imap01[(_inst)[1]]++; \
break; \
case 0xA4: \
used = sysblk.imaps.imapa4[(_inst)[1]]++; \
break; \
case 0xA5: \
used = sysblk.imaps.imapa5[(_inst)[1] & 0x0F]++; \
break; \
case 0xA6: \
used = sysblk.imaps.imapa6[(_inst)[1]]++; \
break; \
case 0xA7: \
used = sysblk.imaps.imapa7[(_inst)[1] & 0x0F]++; \
break; \
case 0xB2: \
used = sysblk.imaps.imapb2[(_inst)[1]]++; \
break; \
case 0xB3: \
used = sysblk.imaps.imapb3[(_inst)[1]]++; \
break; \
case 0xB9: \
used = sysblk.imaps.imapb9[(_inst)[1]]++; \
break; \
case 0xC0: \
used = sysblk.imaps.imapc0[(_inst)[1] & 0x0F]++; \
break; \
case 0xC2: \
used = sysblk.imaps.imapc2[(_inst)[1] & 0x0F]++; \
break; \
case 0xC4: \
used = sysblk.imaps.imapc4[(_inst)[1] & 0x0F]++; \
break; \
case 0xC6: \
used = sysblk.imaps.imapc6[(_inst)[1] & 0x0F]++; \
break; \
case 0xC8: \
used = sysblk.imaps.imapc8[(_inst)[1] & 0x0F]++; \
break; \
case 0xE3: \
used = sysblk.imaps.imape3[(_inst)[5]]++; \
break; \
case 0xE4: \
used = sysblk.imaps.imape4[(_inst)[1]]++; \
break; \
case 0xE5: \
used = sysblk.imaps.imape5[(_inst)[1]]++; \
break; \
case 0xE7: \
used = sysblk.imaps.imape7[(_inst)[5]]++; \
break; \
case 0xEB: \
used = sysblk.imaps.imapeb[(_inst)[5]]++; \
break; \
case 0xEC: \
used = sysblk.imaps.imapec[(_inst)[5]]++; \
break; \
case 0xED: \
used = sysblk.imaps.imaped[(_inst)[5]]++; \
break; \
default: \
used = sysblk.imaps.imapxx[(_inst)[0]]++; \
} \
\
if (!used) \
{ \
/* "%s" */ \
WRMSG( HHC02292, "I", "First use" ); \
ARCH_DEP( display_inst )( (_regs), (_inst) ); \
} \
} \
} while (0)
#else // !defined( OPTION_INSTR_COUNT_AND_TIME )
#define BEG_COUNT_INSTR(_inst, _regs)
#endif // defined( OPTION_INSTR_COUNT_AND_TIME )
#if defined( OPTION_INSTR_COUNT_AND_TIME )
#define END_COUNT_INSTR(_inst, _regs) \
do \
{ \
if (sysblk.icount) \
{ \
struct timeval end_time; \
struct timeval dur; \
U64 elapsed_usecs; \
\
gettimeofday(&end_time, NULL); \
timeval_subtract(&sysblk.start_time, &end_time, &dur); \
elapsed_usecs = (dur.tv_sec * 1000000) + dur.tv_usec; \
\
switch ((_inst)[0]) { \
case 0x01: \
sysblk.imaps.imap01T[(_inst)[1]]+=elapsed_usecs; \
break; \
case 0xA4: \
sysblk.imaps.imapa4T[(_inst)[1]]+=elapsed_usecs; \
break; \
case 0xA5: \
sysblk.imaps.imapa5T[(_inst)[1] & 0x0F]+=elapsed_usecs; \
break; \
case 0xA6: \
sysblk.imaps.imapa6T[(_inst)[1]]+=elapsed_usecs; \
break; \
case 0xA7: \
sysblk.imaps.imapa7T[(_inst)[1] & 0x0F]+=elapsed_usecs; \
break; \
case 0xB2: \
sysblk.imaps.imapb2T[(_inst)[1]]+=elapsed_usecs; \
break; \
case 0xB3: \
sysblk.imaps.imapb3T[(_inst)[1]]+=elapsed_usecs; \
break; \
case 0xB9: \
sysblk.imaps.imapb9T[(_inst)[1]]+=elapsed_usecs; \
break; \
case 0xC0: \
sysblk.imaps.imapc0T[(_inst)[1] & 0x0F]+=elapsed_usecs; \
break; \
case 0xC2: \
sysblk.imaps.imapc2T[(_inst)[1] & 0x0F]+=elapsed_usecs; \
break; \
case 0xC4: \
sysblk.imaps.imapc4T[(_inst)[1] & 0x0F]+=elapsed_usecs; \
break; \
case 0xC6: \
sysblk.imaps.imapc6T[(_inst)[1] & 0x0F]+=elapsed_usecs; \
break; \
case 0xC8: \
sysblk.imaps.imapc8T[(_inst)[1] & 0x0F]+=elapsed_usecs; \
break; \
case 0xE3: \
sysblk.imaps.imape3T[(_inst)[5]]+=elapsed_usecs; \
break; \
case 0xE4: \
sysblk.imaps.imape4T[(_inst)[1]]+=elapsed_usecs; \
break; \
case 0xE5: \
sysblk.imaps.imape5T[(_inst)[1]]+=elapsed_usecs; \
break; \
case 0xE7: \
sysblk.imaps.imape7T[(_inst)[5]]+=elapsed_usecs; \
break; \
case 0xEB: \
sysblk.imaps.imapebT[(_inst)[5]]+=elapsed_usecs; \
break; \
case 0xEC: \
sysblk.imaps.imapecT[(_inst)[5]]+=elapsed_usecs; \
break; \
case 0xED: \
sysblk.imaps.imapedT[(_inst)[5]]+=elapsed_usecs; \
break; \
default: \
sysblk.imaps.imapxxT[(_inst)[0]]+=elapsed_usecs; \
} \
} \
} while (0)
#else // !defined( OPTION_INSTR_COUNT_AND_TIME )
#define END_COUNT_INSTR(_inst, _regs)
#endif // defined( OPTION_INSTR_COUNT_AND_TIME )
/*-------------------------------------------------------------------*/
/* SIE macros */
/* (architecture INDEPENDENT) */
/*-------------------------------------------------------------------*/
#if defined( _FEATURE_SIE )
#define SIE_MODE( _regs ) ((_regs)->sie_mode)
#define SIE_STATE( _regs ) ((_regs)->sie_state)
#define SIE_FEAT_BIT_ON( _regs, _byte, _bit ) ((_regs)->siebk->SIE_ ## _byte & SIE_ ## _byte ## _ ## _bit)
#define SIE_EC_BIT_ON( _regs, _byte, _bit ) ((_regs)->siebk->SIE_ ## _byte & SIE_ ## _byte ## _ ## _bit)
#define SIE_FEAT_BIT_OFF( _regs, _byte, _bit ) !SIE_FEAT_BIT_ON( _regs, _byte, _bit )
#define SIE_EC_BIT_OFF( _regs, _byte, _bit ) !SIE_EC_BIT_ON( _regs, _byte, _bit )
#define SIE_STATE_BIT_ON( _regs, _byte, _bit ) (SIE_MODE((_regs)) && SIE_FEAT_BIT_ON( (_regs), _byte, _bit ))
#define SIE_STATE_BIT_OFF( _regs, _byte, _bit ) (SIE_MODE((_regs)) && SIE_FEAT_BIT_OFF( (_regs), _byte, _bit ))
#define TXF_SIE_INTERCEPT( _regs, _name ) \
do \
{ \
/* Only allow direct execution of TXF instructions \
if the z/VM host says to allow it. Otherwise let \
the z/VM host intercept this instruction so it \
can simulate it, throw a PIC001, or at least be \
informed that we are executing this instruction. \
*/ \
if (1 \
&& SIE_MODE( (_regs) ) \
&& SIE_EC_BIT_OFF( (_regs), ECB0, TXF ) \
) \
{ \
if (TXF_TRACING()) \
{ \
/* "TXF: %s%02X: SIE: Intercepting \
%s instruction" */ \
WRMSG( HHC17715, "D", \
TXF_CPUAD( _regs ), #_name ); \
} \
longjmp( (_regs)->progjmp, SIE_INTERCEPT_INST ); \
} \
} \
while (0)
#else // !defined( _FEATURE_SIE )
#define SIE_MODE( _regs ) (0)
#define SIE_STATE( _regs ) (0)
#define SIE_FEAT_BIT_ON( _regs, _byte, _bit ) (0)
#define SIE_EC_BIT_ON( _regs, _byte, _bit ) (0)
#define SIE_STATE_BIT_ON( _regs, _byte, _bit ) (0)
#define SIE_FEAT_BIT_OFF( _regs, _byte, _bit ) (1)
#define SIE_EC_BIT_OFF( _regs, _byte, _bit ) (1)
#define SIE_STATE_BIT_OFF( _regs, _byte, _bit ) (1)
#define TXF_SIE_INTERCEPT( _regs, _name ) /* (do nothing) */
#endif // defined( _FEATURE_SIE )
#if defined( _FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE )
#undef MULTIPLE_CONTROLLED_DATA_SPACE
#define MULTIPLE_CONTROLLED_DATA_SPACE( _regs ) \
(SIE_FEAT_BIT_ON( (_regs), MX, XC ) && AR_BIT( &(_regs)->psw ))
#else
#undef MULTIPLE_CONTROLLED_DATA_SPACE
#define MULTIPLE_CONTROLLED_DATA_SPACE( _regs ) (0)
#endif
#if defined( FEATURE_SIE )
#undef SIE_ACTIVE
#define SIE_ACTIVE( _regs ) ((_regs)->sie_active)
#else
#undef SIE_ACTIVE
#define SIE_ACTIVE( _regs ) (0)
#endif
/*-------------------------------------------------------------------*/
/* Instruction "FOOTPRINT" */
/*-------------------------------------------------------------------*/
/* The footprint_buffer option saves a copy of the register context */
/* every time an instruction is executed. This is for problem */
/* determination only, as it SEVERELY impacts performance. *JJ */
/*-------------------------------------------------------------------*/
#if defined( OPTION_FOOTPRINT_BUFFER )
#define FOOTPRINT(_ip, _regs) \
do { \
sysblk.footprregs[(_regs)->cpuad][sysblk.footprptr[(_regs)->cpuad]] = *(_regs); \
memcpy(&sysblk.footprregs[(_regs)->cpuad][sysblk.footprptr[(_regs)->cpuad]++].inst,(_ip),6); \
sysblk.footprptr[(_regs)->cpuad] &= OPTION_FOOTPRINT_BUFFER - 1; \
} while(0)
#endif
#if !defined( FOOTPRINT )
#define FOOTPRINT(_ip, _regs)
#endif
/*-------------------------------------------------------------------*/
/* CPU Stepping or Tracing */
/*-------------------------------------------------------------------*/
#define TXF_INSTR_TRACING() \
(sysblk.txf_tracing & TXF_TR_INSTR)
#define TXF_CONSTRAINED_TRANS_INSTR( _regs ) \
((sysblk.txf_tracing & TXF_TR_C) \
&& (_regs)->txf_tnd && (_regs)->txf_contran)
#define TXF_UNCONSTRAINED_TRANS_INSTR( _regs ) \
((sysblk.txf_tracing & TXF_TR_U) \
&& (_regs)->txf_tnd && !(_regs)->txf_contran)
#define TXF_TRACE_THIS_INSTR( _regs ) \
(1 \
&& TXF_TRACE_CPU( _regs ) \
&& TXF_TRACE_TND( _regs ) \
&& (0 \
|| TXF_CONSTRAINED_TRANS_INSTR( _regs ) \
|| TXF_UNCONSTRAINED_TRANS_INSTR( _regs ) \
) \
)
#define _CPU_STEP_OR_TRACE(_breakaddr_or_traceaddr, _regs, _ilc) \
(0 \
|| !TXF_INSTR_TRACING() \
|| TXF_TRACE_THIS_INSTR( _regs ) \
) \
&& \
( \
(sysblk._breakaddr_or_traceaddr[0] == 0 && \
sysblk._breakaddr_or_traceaddr[1] == 0) \
\
|| (sysblk._breakaddr_or_traceaddr[0] <= \
sysblk._breakaddr_or_traceaddr[1] \
\
&& PSW_IA_FROM_IP((_regs), -(_ilc)) >= \
sysblk._breakaddr_or_traceaddr[0] \
&& PSW_IA_FROM_IP((_regs), -(_ilc)) <= \
sysblk._breakaddr_or_traceaddr[1] \
) \
\
|| (sysblk._breakaddr_or_traceaddr[0] > \
sysblk._breakaddr_or_traceaddr[1] \
\
&& PSW_IA_FROM_IP((_regs), -(_ilc)) >= \
sysblk._breakaddr_or_traceaddr[1] \
&& PSW_IA_FROM_IP((_regs), -(_ilc)) <= \
sysblk._breakaddr_or_traceaddr[0] \
) \
) \
#define CPU_STEPPING(_regs, _ilc) \
(sysblk.instbreak && _CPU_STEP_OR_TRACE(breakaddr,(_regs),(_ilc)))
#define CPU_TRACING(_regs, _ilc) \
(1 \
&& sysblk.insttrace \
&& (_regs)->insttrace \
&& _CPU_STEP_OR_TRACE( traceaddr, (_regs), (_ilc) ) \
)
#define CPU_STEPPING_OR_TRACING(_regs, _ilc) \
( unlikely((_regs)->breakortrace) && \
(CPU_STEPPING((_regs), (_ilc)) || CPU_TRACING((_regs), (_ilc))) \
)
#define _CPU_TRACE_ALL \
(sysblk.traceaddr[0] == 0 && \
sysblk.traceaddr[1] == 0 && \
/*sysblk.insttrace*/ insttrace_all())
#define _CPU_STEP_ALL \
(sysblk.breakaddr[0] == 0 && \
sysblk.breakaddr[1] == 0 && \
sysblk.instbreak)
#define CPU_STEPPING_OR_TRACING_ALL (_CPU_STEP_ALL || _CPU_TRACE_ALL)
#define PROCESS_TRACE( _regs, _ip, _goto ) \
do \
{ \
/* If stepping or tracing, trace this instruction */ \
if ((_regs)->breakortrace) \
{ \
ARCH_DEP( process_trace )( (_regs), (_ip) ); \
\
/* If the aie was invalidated, re-fetch the instruction. \
Another CPU executing e.g. a IPTE instruction during \
instruction stepping while process_trace was waiting \
for the user to press the enter key can allow this to \
occur. Otherwise it is impossible to occur. */ \
if (1 \
&& (_regs)->stepping \
&& !VALID_AIE( _regs ) \
) \
{ \
/* "Processor %s%02X: aie invalidated; instruction refetched" */ \
WRMSG( HHC00835, "W", PTYPSTR( (_regs)->cpuad ), (_regs)->cpuad ); \
goto _goto; \
} \
} \
} \
while (0)
/*-------------------------------------------------------------------*/
/* Simple helper macro that instructions can use */
/* to force an immediate check for interrupts. */
/*-------------------------------------------------------------------*/
#define RETURN_INTCHECK(_regs) \
longjmp((_regs)->progjmp, SIE_NO_INTERCEPT)
/*-------------------------------------------------------------------*/
/* Instruction validity checking */
/*-------------------------------------------------------------------*/
#define ODD_CHECK(_r, _regs) \
if( (_r) & 1 ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
#define ODD2_CHECK(_r1, _r2, _regs) \
if( ((_r1) & 1) || ((_r2) & 1) ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
#define HW_CHECK(_value, _regs) \
if( (_value) & 1 ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
#define FW_CHECK(_value, _regs) \
if( (_value) & 3 ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
#define DW_CHECK(_value, _regs) \
if( (_value) & 7 ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
#define QW_CHECK(_value, _regs) \
if( (_value) & 15 ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
/* Program check if m is not 0, 1, or 4 to 7 */
#define HFPM_CHECK(_m, _regs) \
if (((_m) == 2) || ((_m) == 3) || ((_m) & 8)) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
#define PRIV_CHECK(_regs) \
if( PROBSTATE(&(_regs)->psw) ) \
(_regs)->program_interrupt( (_regs), PGM_PRIVILEGED_OPERATION_EXCEPTION)
/* Program check if r is not 0,1,4,5,8,9,12, or 13 (designating
the lower-numbered register of a floating-point register pair) */
#define BFPREGPAIR_CHECK(_r, _regs) \
if( ((_r) & 2) ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
/* Program check if r1 and r2 are not both 0,1,4,5,8,9,12, or 13
(lower-numbered register of a floating-point register pair) */
#define BFPREGPAIR2_CHECK(_r1, _r2, _regs) \
if( ((_r1) & 2) || ((_r2) & 2) ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
/* Program check if r is not 0,1,4,5,8,9,12, or 13 (designating
the lower-numbered register of a floating-point register pair) */
#define DFPREGPAIR_CHECK(_r, _regs) \
if( ((_r) & 2) ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
/* Program check if r1 and r2 are not both 0,1,4,5,8,9,12, or 13
(lower-numbered register of a floating-point register pair) */
#define DFPREGPAIR2_CHECK(_r1, _r2, _regs) \
if( ((_r1) & 2) || ((_r2) & 2) ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
/* Program check if r1, r2, r3 are not all 0,1,4,5,8,9,12, or 13
(lower-numbered register of a floating-point register pair) */
#define DFPREGPAIR3_CHECK(_r1, _r2, _r3, _regs) \
if( ((_r1) & 2) || ((_r2) & 2) || ((_r3) & 2) ) \
(_regs)->program_interrupt( (_regs), PGM_SPECIFICATION_EXCEPTION)
#define SSID_CHECK(_regs) \
if((!((_regs)->GR_LHH(1) & 0x0001)) \
|| (_regs)->GR_LHH(1) > (0x0001|(FEATURE_LCSS_MAX-1))) \
(_regs)->program_interrupt( (_regs), PGM_OPERAND_EXCEPTION)
#if defined( _FEATURE_S370_S390_VECTOR_FACILITY )
#ifndef _VFDEFS
#define _VFDEFS
#define VOP_CHECK( _regs ) if (!((_regs)->CR(0) & CR0_VOP) || !(_regs)->vf->online) \
(_regs)->program_interrupt( (_regs), PGM_VECTOR_OPERATION_EXCEPTION )
#define VR_INUSE( _vr, _regs ) ((_regs)->vf->vsr & (VSR_VIU0 >> ((_vr) >> 1)))
#define VR_CHANGED( _vr, _regs ) ((_regs)->vf->vsr & (VSR_VCH0 >> ((_vr) >> 1)))
#define SET_VR_INUSE( _vr, _regs ) (_regs)->vf->vsr |= (VSR_VIU0 >> ((_vr) >> 1))
#define SET_VR_CHANGED( _vr, _regs ) (_regs)->vf->vsr |= (VSR_VCH0 >> ((_vr) >> 1))
#define RESET_VR_INUSE( _vr, _regs ) (_regs)->vf->vsr &= ~(VSR_VIU0 >> ((_vr) >> 1))
#define RESET_VR_CHANGED( _vr, _regs ) (_regs)->vf->vsr &= ~(VSR_VCH0 >> ((_vr) >> 1))
#define VMR_SET( _section, _regs ) ((_regs)->vf->vmr[(_section) >> 3] & (0x80 >> ((_section) & 7)))
#define MASK_MODE( _regs ) ((_regs)->vf->vsr & VSR_M)
#define VECTOR_COUNT( _regs ) (((_regs)->vf->vsr & VSR_VCT) >> 32)
#define VECTOR_IX( _regs ) (((_regs)->vf->vsr & VSR_VIX) >> 16)
#endif /* _VFDEFS */
#endif /* defined( _FEATURE_S370_S390_VECTOR_FACILITY ) */
/*-------------------------------------------------------------------*/
/* Device IOID / SSID / LCSS macros */
/*-------------------------------------------------------------------*/
#define IOID_TO_SSID( _ioid ) ((_ioid) >> 16)
#define IOID_TO_LCSS( _ioid ) ((_ioid) >> 17)
#define SSID_TO_LCSS( _ssid ) ((_ssid) >> 1 )
#define LCSS_TO_SSID( _lcss ) (((_lcss) << 1 ) | 1)
/*-------------------------------------------------------------------*/
/* Virtual Architecture Level Set Facility */
/*-------------------------------------------------------------------*/
#define FACILITY_ENABLED(_faci, _regs) \
(((_regs)->facility_list [ ((STFL_ ## _faci)/8) ]) & (0x80 >> ((STFL_ ## _faci) % 8)))
#define FACILITY_ENABLED_DEV(_faci) \
((sysblk.facility_list[ sysblk.arch_mode ][ ((STFL_ ## _faci)/8) ]) & (0x80 >> ((STFL_ ## _faci) % 8)))
#define FACILITY_ENABLED_ARCH( _faci, _arch ) \
((sysblk.facility_list[ (_arch) ][ ((STFL_ ## _faci)/8) ]) & (0x80 >> ((STFL_ ## _faci) % 8)))
#define FACILITY_CHECK(_faci, _regs) \
do { \
if(!FACILITY_ENABLED( _faci, _regs ) ) \
(_regs)->program_interrupt( (_regs), PGM_OPERATION_EXCEPTION); \
} while (0)
/*-------------------------------------------------------------------*/
/* PER range checking */
/*-------------------------------------------------------------------*/
#define PER_RANGE_CHECK(_addr, _low, _high) \
( (((_high) & MAXADDRESS) >= ((_low) & MAXADDRESS)) ? \
(((_addr) >= ((_low) & MAXADDRESS)) && (_addr) <= ((_high) & MAXADDRESS)) : \
(((_addr) >= ((_low) & MAXADDRESS)) || (_addr) <= ((_high) & MAXADDRESS)) )
#define PER_RANGE_CHECK2(_addr1, _addr2, _low, _high) \
( (((_high) & MAXADDRESS) >= ((_low) & MAXADDRESS)) ? \
(((_addr1) >= ((_low) & MAXADDRESS)) && (_addr1) <= ((_high) & MAXADDRESS)) || \
(((_addr2) >= ((_low) & MAXADDRESS)) && (_addr2) <= ((_high) & MAXADDRESS)) || \
(((_addr1) <= ((_low) & MAXADDRESS)) && (_addr2) >= ((_high) & MAXADDRESS)) : \
(((_addr2) >= ((_low) & MAXADDRESS)) || (_addr1) <= ((_high) & MAXADDRESS)) )
/*-------------------------------------------------------------------*/
/* Byte swapping macros */
/*-------------------------------------------------------------------*/
/* The "CSWAPxx()" macros CONDITIONALLY swap the endianness of the */
/* given argument depending on the endianness of the current host, */
/* much like the "htonl()" networking API functions. If this build */
/* of Hercules is for running on a big endian host, then CSWAPxx() */
/* will do absolutely nothing since the argument should already be */
/* in big endian format. If this build of Hercules is for running */
/* on a little endian host however, it will perform the byte swap */
/* so that the result is a big endian value (since z/Architecture */
/* is big endian). */
/* */
/* The SWAPxx() macros however, UNCONDITIONALLY swap the endianness */
/* of the specified value REGARDLESS of the endianness Hercules was */
/* built for or the endianness of the host it is running on. It is */
/* designed for situations such as what might exist when a number */
/* is read or written to/from disk in a format different from the */
/* format of the Hercules build or the host it is running on (such */
/* as what occurs with Hercules's emulated dasd files). In such a */
/* situation the device driver detects the endianness of the system */
/* it is running on differs from the endianness that the DASD file */
/* was written in, thereby requiring it to *UNCONDITIONALLY* swap */
/* the value that was read from disk, REGARDLESS of the endianness */
/* of the Hercules build or the host it is currently running on. */
/*-------------------------------------------------------------------*/
#ifdef WORDS_BIGENDIAN
#define CSWAP16(_x) (_x) // (result ALWAYS big endian)
#define CSWAP32(_x) (_x) // (result ALWAYS big endian)
#define CSWAP64(_x) (_x) // (result ALWAYS big endian)
#else
#define CSWAP16(_x) bswap_16(_x) // (result ALWAYS big endian)
#define CSWAP32(_x) bswap_32(_x) // (result ALWAYS big endian)
#define CSWAP64(_x) bswap_64(_x) // (result ALWAYS big endian)
#endif
#define SWAP16(_x) bswap_16(_x) // (result OPPOSITE of input)
#define SWAP32(_x) bswap_32(_x) // (result OPPOSITE of input)
#define SWAP64(_x) bswap_64(_x) // (result OPPOSITE of input)
#define SWAP_OFF_T(o) (sizeof(o) <= 4 ? SWAP32((U32)o) : SWAP64(o))
/*-------------------------------------------------------------------*/
/* Guest storage FETCH/STORE macros */
/*-------------------------------------------------------------------*/
/* The following macros fetch a value from emulated guest storage */
/* into a local work variable or store a local work variable into */
/* emulated guest storage, performing a CONDITIONAL swap in between */
/* (via the "CSWAPxx()" macro) to ensure the value placed into guest */
/* storage is always big endian or that the local work variable is */
/* always in the expected big or little endian format (depending on */
/* which endianness Hercules was built for). */
/*-------------------------------------------------------------------*/
#define FETCH_HW( _val, _stor ) (_val) = fetch_hw( _stor )
#define FETCH_FW( _val, _stor ) (_val) = fetch_fw( _stor )
#define FETCH_F3( _val, _stor ) (_val) = fetch_f3( _stor )
#define FETCH_DW( _val, _stor ) (_val) = fetch_dw( _stor )
#define STORE_HW( _stor, _val ) store_hw( _stor, _val )
#define STORE_FW( _stor, _val ) store_fw( _stor, _val )
#define STORE_F3( _stor, _val ) store_f3( _stor, _val )
#define STORE_DW( _stor, _val ) store_dw( _stor, _val )
/*-------------------------------------------------------------------*/
/* CKD/CCKD header field FETCH/STORE macros */
/*-------------------------------------------------------------------*/
/* The following macros fetch a value from a CCKD dasd header field */
/* into a local work variable or store a local work variable into */
/* a CCKD dasd header field (e.g. CKD_DEVHDR, CCKD_DEVHDR) doing an */
/* UNCONDITIONAL "SWAPxx()" in between to ensure the numeric value */
/* stored into, or fetched from, the CCKD header field is always in */
/* LITTLE endian format, accomplishing the complete opposite of the */
/* above "FETCH_FW/STORE_FW/etc" macros. */
/*-------------------------------------------------------------------*/
#define FETCH_LE_HW( _val, _stor ) (_val) = SWAP16( fetch_hw( _stor ))
#define FETCH_LE_FW( _val, _stor ) (_val) = SWAP32( fetch_fw( _stor ))
#define FETCH_LE_DW( _val, _stor ) (_val) = SWAP64( fetch_dw( _stor ))
#define STORE_LE_HW( _stor, _val ) store_hw( _stor, SWAP16( _val ))
#define STORE_LE_FW( _stor, _val ) store_fw( _stor, SWAP32( _val ))
#define STORE_LE_DW( _stor, _val ) store_dw( _stor, SWAP64( _val ))
#include "machdep.h"
#endif /* !defined( _OPCODE_H ) */
/*-------------------------------------------------------------------*/
/* (delineates ARCH_DEP from non-arch_dep) */
/*-------------------------------------------------------------------*/
/*-------------------------------------------------------------------*/
/* Architecture *DEPENDENT* macros */
/*-------------------------------------------------------------------*/
/* The below macros (due to being outside of the above "#endif" */
/* for "_OPCODE_H") are undef'ed and then re-defined differently */
/* for each subsequent new build architecture. */
/*-------------------------------------------------------------------*/
/*-------------------------------------------------------------------*/
/* Macros for defining ARCH_DEP master opcode table entries */
/*-------------------------------------------------------------------*/
#undef AD_GENx___x___x___
#undef AD_GENx370x___x___
#undef AD_GENx___x390x___
#undef AD_GENx370x390x___
#undef AD_GENx___x___x900
#undef AD_GENx370x___x900
#undef AD_GENx___x390x900
#undef AD_GENx370x390x900
#if __GEN_ARCH == 370
#define AD_GENx___x___x___ \
{ \
&operation_exception, \
&operation_exception, \
&operation_exception, \
(void*) &iprint_ASMFMT_none, \
(void*) &"?????" "\0" "?" \
}
#define AD_GENx370x___x___( _mnemonic, _ifmt, _asmfmt, _ifunc_name ) \
{ \
_GEN370( _ifunc_name ) \
&operation_exception, \
&operation_exception, \
(void*) &iprint_ ## _asmfmt, \
(void*) & _mnemonic "\0" #_ifunc_name \
}
#define AD_GENx___x390x___( _mnemonic, _ifmt, _asmfmt, _ifunc_name ) \
{ \
&operation_exception, \
&operation_exception, \
&operation_exception, \
(void*) &iprint_ ## _asmfmt, \
(void*) & _mnemonic "\0" #_ifunc_name \
}
#define AD_GENx370x390x___( _mnemonic, _ifmt, _asmfmt, _ifunc_name ) \
{ \
_GEN370( _ifunc_name ) \
&operation_exception, \
&operation_exception, \
(void*) &iprint_ ## _asmfmt, \
(void*) & _mnemonic "\0" #_ifunc_name \
}
#define AD_GENx___x___x900( _mnemonic, _ifmt, _asmfmt, _ifunc_name ) \
{ \
&operation_exception, \
&operation_exception, \
&operation_exception, \
(void*) &iprint_ ## _asmfmt, \
(void*) & _mnemonic "\0" #_ifunc_name \
}
#define AD_GENx370x___x900( _mnemonic, _ifmt, _asmfmt, _ifunc_name ) \
{ \
_GEN370( _ifunc_name ) \
&operation_exception, \
&operation_exception, \
(void*) &iprint_ ## _asmfmt, \
(void*) & _mnemonic "\0" #_ifunc_name \
}
#define AD_GENx___x390x900( _mnemonic, _ifmt, _asmfmt, _ifunc_name ) \
{ \
&operation_exception, \
&operation_exception, \
&operation_exception, \
(void*) &iprint_ ## _asmfmt, \
(void*) & _mnemonic "\0" #_ifunc_name \
}
#define AD_GENx370x390x900( _mnemonic, _ifmt, _asmfmt, _ifunc_name ) \
{ \
_GEN370( _ifunc_name ) \
&operation_exception, \
&operation_exception, \
(void*) &iprint_ ## _asmfmt, \
(void*) & _mnemonic "\0" #_ifunc_name \
}
#elif __GEN_ARCH == 390
#define AD_GENx___x___x___ \
{ \
&operation_exception, \
&operation_exception, \
&operation_exception, \
(void*) &iprint_ASMFMT_none, \
(void*) &"?????" "\0" "?" \
}
#define AD_GENx370x___x___( _mnemonic, _ifmt, _asmfmt, _ifunc_name ) \
{ \
&operation_exception, \
&operation_exception, \
&operation_exception, \
(void*) &iprint_ ## _asmfmt, \
(void*) & _mnemonic "\0" #_ifunc_name \
}
#define AD_GENx___x390x___( _mnemonic, _ifmt, _asmfmt, _ifunc_name ) \
{ \
&operation_exception, \
_GEN390( _ifunc_name ) \
&operation_exception, \
(void*) &iprint_ ## _asmfmt, \
(void*) & _mnemonic "\0" #_ifunc_name \
}
#define AD_GENx370x390x___( _mnemonic, _ifmt, _asmfmt, _ifunc_name ) \
{ \
&operation_exception, \
_GEN390( _ifunc_name ) \
&operation_exception, \
(void*) &iprint_ ## _asmfmt, \
(void*) & _mnemonic "\0" #_ifunc_name \
}
#define AD_GENx___x___x900( _mnemonic, _ifmt, _asmfmt, _ifunc_name ) \
{ \
&operation_exception, \
&operation_exception, \
&operation_exception, \