Pipeline_Logic.txt

IF/ID: instruction, PC+2

ID/EX: control signals, data read from two registers, sign-extended immediate, RegisterRs, RegisterRt, PC+2

EX/MEM: ALU's reult, mem-write data, writeRegister(Rt/Rd), control signals, PC+2

MEM/WB: dataout, ALU's result, writeRegister(Rt/Rd), PC+2(for PCS), control signals


Note:
1): NOP for flush: LLB $0, 0x00		-> 1010 0000 0000 0000
2): NOP for stall: insert NOP (mux of instruction?) / clear control signals not ALUOp + Rd
3): hlt asserted in the write back stage; Need to consider halt fetched in IF stage and branch is not taken. Thus assign pc_reg_hlt = (instr[15:12] == 4'hf && branchNotTaken); to hinder future instructions from being fetched.
4):  Branch taken --> flush used as a selecting signal for NOP instruction and instruciton fetched


Bugs:
1: first RegWrite is always 1
2: cycle count