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ms.c
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/* Driver for Realtek PCI-Express card reader
*
* Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2, or (at your option) any
* later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http:
*
* Author:
* wwang ([email protected])
* No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
*/
#include <linux/blkdev.h>
#include <linux/kthread.h>
#include <linux/sched.h>
#include <linux/vmalloc.h>
#include "rtsx.h"
#include "rtsx_transport.h"
#include "rtsx_scsi.h"
#include "rtsx_card.h"
#include "ms.h"
static inline void ms_set_err_code(struct rtsx_chip *chip, u8 err_code)
{
struct ms_info *ms_card = &(chip->ms_card);
ms_card->err_code = err_code;
#if DBG
if (err_code != MS_NO_ERROR) {
int i;
for (i = 0; i < 4; i++) {
rtsx_readl(chip, RTSX_HCBAR + i * 4);
}
CATCH_TRIGGER1(chip);
}
#endif
}
static inline int ms_check_err_code(struct rtsx_chip *chip, u8 err_code)
{
struct ms_info *ms_card = &(chip->ms_card);
return (ms_card->err_code == err_code);
}
static int ms_parse_err_code(struct rtsx_chip *chip)
{
TRACE_RET(chip, STATUS_FAIL);
}
static int ms_transfer_tpc(struct rtsx_chip *chip, u8 trans_mode, u8 tpc, u8 cnt, u8 cfg)
{
struct ms_info *ms_card = &(chip->ms_card);
int retval;
u8 *ptr;
RTSX_DEBUGP(("ms_transfer_tpc: tpc = 0x%x\n", tpc));
rtsx_init_cmd(chip);
rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, MS_TRANSFER_START | trans_mode);
rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
rtsx_add_cmd(chip, READ_REG_CMD, MS_TRANS_CFG, 0, 0);
retval = rtsx_send_cmd(chip, MS_CARD, 5000);
if (retval < 0) {
rtsx_clear_ms_error(chip);
ms_set_err_code(chip, MS_TO_ERROR);
TRACE_RET(chip, ms_parse_err_code(chip));
}
ptr = rtsx_get_cmd_data(chip) + 1;
if (!(tpc & 0x08)) {
if (*ptr & MS_CRC16_ERR) {
ms_set_err_code(chip, MS_CRC16_ERROR);
TRACE_RET(chip, ms_parse_err_code(chip));
}
} else {
if (CHK_MSPRO(ms_card) && !(*ptr & 0x80)) {
if (*ptr & (MS_INT_ERR | MS_INT_CMDNK)) {
ms_set_err_code(chip, MS_CMD_NK);
TRACE_RET(chip, ms_parse_err_code(chip));
}
}
}
if (*ptr & MS_RDY_TIMEOUT) {
rtsx_clear_ms_error(chip);
ms_set_err_code(chip, MS_TO_ERROR);
TRACE_RET(chip, ms_parse_err_code(chip));
}
return STATUS_SUCCESS;
}
static int ms_transfer_data(struct rtsx_chip *chip, u8 trans_mode, u8 tpc, u16 sec_cnt,
u8 cfg, int mode_2k, int use_sg, void *buf, int buf_len)
{
int retval;
u8 val, err_code = 0;
enum dma_data_direction dir;
if (!buf || !buf_len) {
TRACE_RET(chip, STATUS_FAIL);
}
if (trans_mode == MS_TM_AUTO_READ) {
dir = DMA_FROM_DEVICE;
err_code = MS_FLASH_READ_ERROR;
} else if (trans_mode == MS_TM_AUTO_WRITE) {
dir = DMA_TO_DEVICE;
err_code = MS_FLASH_WRITE_ERROR;
} else {
TRACE_RET(chip, STATUS_FAIL);
}
rtsx_init_cmd(chip);
rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
rtsx_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_H, 0xFF, (u8)(sec_cnt >> 8));
rtsx_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF, (u8)sec_cnt);
rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
if (mode_2k) {
rtsx_add_cmd(chip, WRITE_REG_CMD, MS_CFG, MS_2K_SECTOR_MODE, MS_2K_SECTOR_MODE);
} else {
rtsx_add_cmd(chip, WRITE_REG_CMD, MS_CFG, MS_2K_SECTOR_MODE, 0);
}
trans_dma_enable(dir, chip, sec_cnt * 512, DMA_512);
rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, MS_TRANSFER_START | trans_mode);
rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
rtsx_send_cmd_no_wait(chip);
retval = rtsx_transfer_data(chip, MS_CARD, buf, buf_len, use_sg, dir, chip->mspro_timeout);
if (retval < 0) {
ms_set_err_code(chip, err_code);
if (retval == -ETIMEDOUT) {
retval = STATUS_TIMEDOUT;
} else {
retval = STATUS_FAIL;
}
TRACE_RET(chip, retval);
}
RTSX_READ_REG(chip, MS_TRANS_CFG, &val);
if (val & (MS_INT_CMDNK | MS_INT_ERR | MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
TRACE_RET(chip, STATUS_FAIL);
}
return STATUS_SUCCESS;
}
static int ms_write_bytes(struct rtsx_chip *chip, u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len)
{
struct ms_info *ms_card = &(chip->ms_card);
int retval, i;
if (!data || (data_len < cnt)) {
TRACE_RET(chip, STATUS_ERROR);
}
rtsx_init_cmd(chip);
for (i = 0; i < cnt; i++) {
rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF, data[i]);
}
if (cnt % 2) {
rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF, 0xFF);
}
rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, MS_TRANSFER_START | MS_TM_WRITE_BYTES);
rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
retval = rtsx_send_cmd(chip, MS_CARD, 5000);
if (retval < 0) {
u8 val = 0;
rtsx_read_register(chip, MS_TRANS_CFG, &val);
RTSX_DEBUGP(("MS_TRANS_CFG: 0x%02x\n", val));
rtsx_clear_ms_error(chip);
if (!(tpc & 0x08)) {
if (val & MS_CRC16_ERR) {
ms_set_err_code(chip, MS_CRC16_ERROR);
TRACE_RET(chip, ms_parse_err_code(chip));
}
} else {
if (CHK_MSPRO(ms_card) && !(val & 0x80)) {
if (val & (MS_INT_ERR | MS_INT_CMDNK)) {
ms_set_err_code(chip, MS_CMD_NK);
TRACE_RET(chip, ms_parse_err_code(chip));
}
}
}
if (val & MS_RDY_TIMEOUT) {
ms_set_err_code(chip, MS_TO_ERROR);
TRACE_RET(chip, ms_parse_err_code(chip));
}
ms_set_err_code(chip, MS_TO_ERROR);
TRACE_RET(chip, ms_parse_err_code(chip));
}
return STATUS_SUCCESS;
}
static int ms_read_bytes(struct rtsx_chip *chip, u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len)
{
struct ms_info *ms_card = &(chip->ms_card);
int retval, i;
u8 *ptr;
if (!data) {
TRACE_RET(chip, STATUS_ERROR);
}
rtsx_init_cmd(chip);
rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, MS_TRANSFER_START | MS_TM_READ_BYTES);
rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
for (i = 0; i < data_len - 1; i++) {
rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0);
}
if (data_len % 2) {
rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len, 0, 0);
} else {
rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len - 1, 0, 0);
}
retval = rtsx_send_cmd(chip, MS_CARD, 5000);
if (retval < 0) {
u8 val = 0;
rtsx_read_register(chip, MS_TRANS_CFG, &val);
rtsx_clear_ms_error(chip);
if (!(tpc & 0x08)) {
if (val & MS_CRC16_ERR) {
ms_set_err_code(chip, MS_CRC16_ERROR);
TRACE_RET(chip, ms_parse_err_code(chip));
}
} else {
if (CHK_MSPRO(ms_card) && !(val & 0x80)) {
if (val & (MS_INT_ERR | MS_INT_CMDNK)) {
ms_set_err_code(chip, MS_CMD_NK);
TRACE_RET(chip, ms_parse_err_code(chip));
}
}
}
if (val & MS_RDY_TIMEOUT) {
ms_set_err_code(chip, MS_TO_ERROR);
TRACE_RET(chip, ms_parse_err_code(chip));
}
ms_set_err_code(chip, MS_TO_ERROR);
TRACE_RET(chip, ms_parse_err_code(chip));
}
ptr = rtsx_get_cmd_data(chip) + 1;
for (i = 0; i < data_len; i++) {
data[i] = ptr[i];
}
if ((tpc == PRO_READ_SHORT_DATA) && (data_len == 8)) {
RTSX_DEBUGP(("Read format progress:\n"));
RTSX_DUMP(ptr, cnt);
}
return STATUS_SUCCESS;
}
static int ms_set_rw_reg_addr(struct rtsx_chip *chip,
u8 read_start, u8 read_cnt, u8 write_start, u8 write_cnt)
{
int retval, i;
u8 data[4];
data[0] = read_start;
data[1] = read_cnt;
data[2] = write_start;
data[3] = write_cnt;
for (i = 0; i < MS_MAX_RETRY_COUNT; i ++) {
retval = ms_write_bytes(chip, SET_RW_REG_ADRS, 4, NO_WAIT_INT, data, 4);
if (retval == STATUS_SUCCESS) {
return STATUS_SUCCESS;
}
rtsx_clear_ms_error(chip);
}
TRACE_RET(chip, STATUS_FAIL);
}
static int ms_send_cmd(struct rtsx_chip *chip, u8 cmd, u8 cfg)
{
u8 data[2];
data[0] = cmd;
data[1] = 0;
return ms_write_bytes(chip, PRO_SET_CMD, 1, cfg, data, 1);
}
static int ms_set_init_para(struct rtsx_chip *chip)
{
struct ms_info *ms_card = &(chip->ms_card);
int retval;
if (CHK_HG8BIT(ms_card)) {
if (chip->asic_code) {
ms_card->ms_clock = chip->asic_ms_hg_clk;
} else {
ms_card->ms_clock = chip->fpga_ms_hg_clk;
}
} else if (CHK_MSPRO(ms_card) || CHK_MS4BIT(ms_card)) {
if (chip->asic_code) {
ms_card->ms_clock = chip->asic_ms_4bit_clk;
} else {
ms_card->ms_clock = chip->fpga_ms_4bit_clk;
}
} else {
if (chip->asic_code) {
ms_card->ms_clock = chip->asic_ms_1bit_clk;
} else {
ms_card->ms_clock = chip->fpga_ms_1bit_clk;
}
}
retval = switch_clock(chip, ms_card->ms_clock);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
retval = select_card(chip, MS_CARD);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
return STATUS_SUCCESS;
}
static int ms_switch_clock(struct rtsx_chip *chip)
{
struct ms_info *ms_card = &(chip->ms_card);
int retval;
retval = select_card(chip, MS_CARD);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
retval = switch_clock(chip, ms_card->ms_clock);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
return STATUS_SUCCESS;
}
static int ms_pull_ctl_disable(struct rtsx_chip *chip)
{
RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x65);
RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);
RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0x95);
RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x09);
RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF, 0x05);
RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, 0x04);
return STATUS_SUCCESS;
}
static int ms_pull_ctl_enable(struct rtsx_chip *chip)
{
int retval;
/* MS CD: pull up
* others: pull down
*/
rtsx_init_cmd(chip);
rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x65);
rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x05);
rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x05);
rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x04);
retval = rtsx_send_cmd(chip, MS_CARD, 100);
if (retval < 0) {
TRACE_RET(chip, STATUS_FAIL);
}
return STATUS_SUCCESS;
}
static int ms_prepare_reset(struct rtsx_chip *chip)
{
struct ms_info *ms_card = &(chip->ms_card);
int retval;
u8 oc_mask = 0;
ms_card->ms_type = 0;
ms_card->check_ms_flow = 0;
ms_card->switch_8bit_fail = 0;
ms_card->delay_write.delay_write_flag = 0;
ms_card->pro_under_formatting = 0;
retval = ms_power_off_card3v3(chip);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
if (!chip->ft2_fast_mode) {
wait_timeout(250);
}
retval = enable_card_clock(chip, MS_CARD);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
if (chip->asic_code) {
retval = ms_pull_ctl_enable(chip);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
} else {
RTSX_WRITE_REG(chip, FPGA_PULL_CTL,
FPGA_SD_CD_PULL_CTL_MASK | FPGA_MS_CD_PULL_CTL_MASK | FPGA_MS_PULL_CTL_MASK,
FPGA_SD_CD_PULL_CTL_DIS | FPGA_MS_CD_PULL_CTL_EN | FPGA_MS_PULL_CTL_EN);
}
if (!chip->ft2_fast_mode) {
retval = card_power_on(chip, MS_CARD);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
wait_timeout(150);
#ifdef SUPPORT_OCP
oc_mask = SD_OC_NOW | SD_OC_EVER;
if (chip->ocp_stat & oc_mask) {
RTSX_DEBUGP(("Over current, OCPSTAT is 0x%x\n", chip->ocp_stat));
TRACE_RET(chip, STATUS_FAIL);
}
#endif
}
RTSX_WRITE_REG(chip, CARD_OE, MS_OUTPUT_EN, MS_OUTPUT_EN);
#ifdef LDO_USING_CARD3V3
RTSX_WRITE_REG(chip, CD_PAD_CTL, FORCE_CD_LOW_MASK, 0);
#endif
if (chip->asic_code) {
RTSX_WRITE_REG(chip, MS_CFG, 0xFF,
SAMPLE_TIME_RISING | PUSH_TIME_DEFAULT | NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);
} else {
RTSX_WRITE_REG(chip, MS_CFG, 0xFF,
SAMPLE_TIME_FALLING | PUSH_TIME_DEFAULT | NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);
}
RTSX_WRITE_REG(chip, MS_TRANS_CFG, 0xFF, NO_WAIT_INT | NO_AUTO_READ_INT_REG);
RTSX_WRITE_REG(chip, CARD_STOP, MS_STOP | MS_CLR_ERR, MS_STOP | MS_CLR_ERR);
retval = ms_set_init_para(chip);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
return STATUS_SUCCESS;
}
static int ms_identify_media_type(struct rtsx_chip *chip, int switch_8bit_bus)
{
struct ms_info *ms_card = &(chip->ms_card);
int retval, i;
u8 val;
retval = ms_set_rw_reg_addr(chip, Pro_StatusReg, 6, SystemParm, 1);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, READ_REG, 6, NO_WAIT_INT);
if (retval == STATUS_SUCCESS) {
break;
}
}
if (i == MS_MAX_RETRY_COUNT) {
TRACE_RET(chip, STATUS_FAIL);
}
RTSX_READ_REG(chip, PPBUF_BASE2 + 2, &val);
RTSX_DEBUGP(("Type register: 0x%x\n", val));
if (val != 0x01) {
if (val != 0x02) {
ms_card->check_ms_flow = 1;
}
TRACE_RET(chip, STATUS_FAIL);
}
RTSX_READ_REG(chip, PPBUF_BASE2 + 4, &val);
RTSX_DEBUGP(("Category register: 0x%x\n", val));
if (val != 0) {
ms_card->check_ms_flow = 1;
TRACE_RET(chip, STATUS_FAIL);
}
RTSX_READ_REG(chip, PPBUF_BASE2 + 5, &val);
RTSX_DEBUGP(("Class register: 0x%x\n", val));
if (val == 0) {
RTSX_READ_REG(chip, PPBUF_BASE2, &val);
if (val & WRT_PRTCT) {
chip->card_wp |= MS_CARD;
} else {
chip->card_wp &= ~MS_CARD;
}
} else if ((val == 0x01) || (val == 0x02) ||(val == 0x03)) {
chip->card_wp |= MS_CARD;
} else {
ms_card->check_ms_flow = 1;
TRACE_RET(chip, STATUS_FAIL);
}
ms_card->ms_type |= TYPE_MSPRO;
RTSX_READ_REG(chip, PPBUF_BASE2 + 3, &val);
RTSX_DEBUGP(("IF Mode register: 0x%x\n", val));
if (val == 0) {
ms_card->ms_type &= 0x0F;
} else if (val == 7) {
if (switch_8bit_bus) {
ms_card->ms_type |= MS_HG;
} else {
ms_card->ms_type &= 0x0F;
}
} else {
TRACE_RET(chip, STATUS_FAIL);
}
return STATUS_SUCCESS;
}
static int ms_confirm_cpu_startup(struct rtsx_chip *chip)
{
int retval, i, k;
u8 val;
k = 0;
do {
if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
ms_set_err_code(chip, MS_NO_CARD);
TRACE_RET(chip, STATUS_FAIL);
}
for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
if (retval == STATUS_SUCCESS) {
break;
}
}
if (i == MS_MAX_RETRY_COUNT) {
TRACE_RET(chip, STATUS_FAIL);
}
if (k > 100) {
TRACE_RET(chip, STATUS_FAIL);
}
k++;
wait_timeout(100);
} while (!(val & INT_REG_CED));
for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
if (retval == STATUS_SUCCESS) {
break;
}
}
if (i == MS_MAX_RETRY_COUNT) {
TRACE_RET(chip, STATUS_FAIL);
}
if (val & INT_REG_ERR) {
if (val & INT_REG_CMDNK) {
chip->card_wp |= (MS_CARD);
} else {
TRACE_RET(chip, STATUS_FAIL);
}
}
return STATUS_SUCCESS;
}
static int ms_switch_parallel_bus(struct rtsx_chip *chip)
{
int retval, i;
u8 data[2];
data[0] = PARALLEL_4BIT_IF;
data[1] = 0;
for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
retval = ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT, data, 2);
if (retval == STATUS_SUCCESS) {
break;
}
}
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
return STATUS_SUCCESS;
}
static int ms_switch_8bit_bus(struct rtsx_chip *chip)
{
struct ms_info *ms_card = &(chip->ms_card);
int retval, i;
u8 data[2];
data[0] = PARALLEL_8BIT_IF;
data[1] = 0;
for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
retval = ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT, data, 2);
if (retval == STATUS_SUCCESS) {
break;
}
}
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
RTSX_WRITE_REG(chip, MS_CFG, 0x98, MS_BUS_WIDTH_8 | SAMPLE_TIME_FALLING);
ms_card->ms_type |= MS_8BIT;
retval = ms_set_init_para(chip);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 1, NO_WAIT_INT);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
}
return STATUS_SUCCESS;
}
static int ms_pro_reset_flow(struct rtsx_chip *chip, int switch_8bit_bus)
{
struct ms_info *ms_card = &(chip->ms_card);
int retval, i;
for (i = 0; i < 3; i++) {
retval = ms_prepare_reset(chip);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
retval = ms_identify_media_type(chip, switch_8bit_bus);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
retval = ms_confirm_cpu_startup(chip);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
retval = ms_switch_parallel_bus(chip);
if (retval != STATUS_SUCCESS) {
if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
ms_set_err_code(chip, MS_NO_CARD);
TRACE_RET(chip, STATUS_FAIL);
}
continue;
} else {
break;
}
}
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
RTSX_WRITE_REG(chip, MS_CFG, 0x18, MS_BUS_WIDTH_4);
RTSX_WRITE_REG(chip, MS_CFG, PUSH_TIME_ODD, PUSH_TIME_ODD);
retval = ms_set_init_para(chip);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
if (CHK_MSHG(ms_card) && switch_8bit_bus) {
retval = ms_switch_8bit_bus(chip);
if (retval != STATUS_SUCCESS) {
ms_card->switch_8bit_fail = 1;
TRACE_RET(chip, STATUS_FAIL);
}
}
return STATUS_SUCCESS;
}
#ifdef XC_POWERCLASS
static int msxc_change_power(struct rtsx_chip *chip, u8 mode)
{
int retval;
u8 buf[6];
ms_cleanup_work(chip);
retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
buf[0] = 0;
buf[1] = mode;
buf[2] = 0;
buf[3] = 0;
buf[4] = 0;
buf[5] = 0;
retval = ms_write_bytes(chip, PRO_WRITE_REG , 6, NO_WAIT_INT, buf, 6);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
retval = ms_send_cmd(chip, XC_CHG_POWER, WAIT_INT);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
RTSX_READ_REG(chip, MS_TRANS_CFG, buf);
if (buf[0] & (MS_INT_CMDNK | MS_INT_ERR)) {
TRACE_RET(chip, STATUS_FAIL);
}
return STATUS_SUCCESS;
}
#endif
static int ms_read_attribute_info(struct rtsx_chip *chip)
{
struct ms_info *ms_card = &(chip->ms_card);
int retval, i;
u8 val, *buf, class_code, device_type, sub_class, data[16];
u16 total_blk = 0, blk_size = 0;
#ifdef SUPPORT_MSXC
u32 xc_total_blk = 0, xc_blk_size = 0;
#endif
u32 sys_info_addr = 0, sys_info_size;
#ifdef SUPPORT_PCGL_1P18
u32 model_name_addr = 0, model_name_size;
int found_sys_info = 0, found_model_name = 0;
#endif
retval = ms_set_rw_reg_addr(chip, Pro_IntReg, 2, Pro_SystemParm, 7);
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
if (CHK_MS8BIT(ms_card)) {
data[0] = PARALLEL_8BIT_IF;
} else {
data[0] = PARALLEL_4BIT_IF;
}
data[1] = 0;
data[2] = 0x40;
data[3] = 0;
data[4] = 0;
data[5] = 0;
data[6] = 0;
data[7] = 0;
for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
retval = ms_write_bytes(chip, PRO_WRITE_REG, 7, NO_WAIT_INT, data, 8);
if (retval == STATUS_SUCCESS) {
break;
}
}
if (retval != STATUS_SUCCESS) {
TRACE_RET(chip, STATUS_FAIL);
}
buf = (u8 *)rtsx_alloc_dma_buf(chip, 64 * 512, GFP_KERNEL);
if (buf == NULL) {
TRACE_RET(chip, STATUS_ERROR);
}
for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
retval = ms_send_cmd(chip, PRO_READ_ATRB, WAIT_INT);
if (retval != STATUS_SUCCESS) {
continue;
}
retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
if (retval != STATUS_SUCCESS) {
rtsx_free_dma_buf(chip, buf);
TRACE_RET(chip, STATUS_FAIL);
}
if (!(val & MS_INT_BREQ)) {
rtsx_free_dma_buf(chip, buf);
TRACE_RET(chip, STATUS_FAIL);
}
retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA,
0x40, WAIT_INT, 0, 0, buf, 64 * 512);
if (retval == STATUS_SUCCESS) {
break;
} else {
rtsx_clear_ms_error(chip);
}
}
if (retval != STATUS_SUCCESS) {
rtsx_free_dma_buf(chip, buf);
TRACE_RET(chip, STATUS_FAIL);
}
i = 0;
do {
retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
if (retval != STATUS_SUCCESS) {
rtsx_free_dma_buf(chip, buf);
TRACE_RET(chip, STATUS_FAIL);
}
if ((val & MS_INT_CED) || !(val & MS_INT_BREQ)) {
break;
}
retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, PRO_READ_LONG_DATA, 0, WAIT_INT);
if (retval != STATUS_SUCCESS) {
rtsx_free_dma_buf(chip, buf);
TRACE_RET(chip, STATUS_FAIL);
}
i++;
} while (i < 1024);
if (retval != STATUS_SUCCESS) {
rtsx_free_dma_buf(chip, buf);
TRACE_RET(chip, STATUS_FAIL);
}
if ((buf[0] != 0xa5) && (buf[1] != 0xc3)) {
rtsx_free_dma_buf(chip, buf);
TRACE_RET(chip, STATUS_FAIL);
}
if ((buf[4] < 1) || (buf[4] > 12)) {
rtsx_free_dma_buf(chip, buf);
TRACE_RET(chip, STATUS_FAIL);
}
for (i = 0; i < buf[4]; i ++) {
int cur_addr_off = 16 + i * 12;
#ifdef SUPPORT_MSXC
if ((buf[cur_addr_off + 8] == 0x10) || (buf[cur_addr_off + 8] == 0x13))
#else
if (buf[cur_addr_off + 8] == 0x10)
#endif
{
sys_info_addr = ((u32)buf[cur_addr_off + 0] << 24) |
((u32)buf[cur_addr_off + 1] << 16) |
((u32)buf[cur_addr_off + 2] << 8) | buf[cur_addr_off + 3];
sys_info_size = ((u32)buf[cur_addr_off + 4] << 24) |
((u32)buf[cur_addr_off + 5] << 16) |
((u32)buf[cur_addr_off + 6] << 8) | buf[cur_addr_off + 7];
RTSX_DEBUGP(("sys_info_addr = 0x%x, sys_info_size = 0x%x\n",
sys_info_addr, sys_info_size));
if (sys_info_size != 96) {
rtsx_free_dma_buf(chip, buf);
TRACE_RET(chip, STATUS_FAIL);
}
if (sys_info_addr < 0x1A0) {
rtsx_free_dma_buf(chip, buf);
TRACE_RET(chip, STATUS_FAIL);
}
if ((sys_info_size + sys_info_addr) > 0x8000) {
rtsx_free_dma_buf(chip, buf);
TRACE_RET(chip, STATUS_FAIL);
}
#ifdef SUPPORT_MSXC
if (buf[cur_addr_off + 8] == 0x13) {
ms_card->ms_type |= MS_XC;
}
#endif
#ifdef SUPPORT_PCGL_1P18
found_sys_info = 1;
#else
break;
#endif
}
#ifdef SUPPORT_PCGL_1P18
if (buf[cur_addr_off + 8] == 0x15) {
model_name_addr = ((u32)buf[cur_addr_off + 0] << 24) |
((u32)buf[cur_addr_off + 1] << 16) |
((u32)buf[cur_addr_off + 2] << 8) | buf[cur_addr_off + 3];
model_name_size = ((u32)buf[cur_addr_off + 4] << 24) |
((u32)buf[cur_addr_off + 5] << 16) |
((u32)buf[cur_addr_off + 6] << 8) | buf[cur_addr_off + 7];
RTSX_DEBUGP(("model_name_addr = 0x%x, model_name_size = 0x%x\n",
model_name_addr, model_name_size));
if (model_name_size != 48) {
rtsx_free_dma_buf(chip, buf);
TRACE_RET(chip, STATUS_FAIL);
}
if (model_name_addr < 0x1A0) {
rtsx_free_dma_buf(chip, buf);
TRACE_RET(chip, STATUS_FAIL);
}
if ((model_name_size + model_name_addr) > 0x8000) {
rtsx_free_dma_buf(chip, buf);
TRACE_RET(chip, STATUS_FAIL);
}
found_model_name = 1;
}
if (found_sys_info && found_model_name) {
break;
}
#endif
}
if (i == buf[4]) {
rtsx_free_dma_buf(chip, buf);
TRACE_RET(chip, STATUS_FAIL);
}
class_code = buf[sys_info_addr + 0];
device_type = buf[sys_info_addr + 56];
sub_class = buf[sys_info_addr + 46];
#ifdef SUPPORT_MSXC
if (CHK_MSXC(ms_card)) {
xc_total_blk = ((u32)buf[sys_info_addr + 6] << 24) |
((u32)buf[sys_info_addr + 7] << 16) |
((u32)buf[sys_info_addr + 8] << 8) |
buf[sys_info_addr + 9];
xc_blk_size = ((u32)buf[sys_info_addr + 32] << 24) |
((u32)buf[sys_info_addr + 33] << 16) |
((u32)buf[sys_info_addr + 34] << 8) |
buf[sys_info_addr + 35];
RTSX_DEBUGP(("xc_total_blk = 0x%x, xc_blk_size = 0x%x\n", xc_total_blk, xc_blk_size));
} else {
total_blk = ((u16)buf[sys_info_addr + 6] << 8) | buf[sys_info_addr + 7];
blk_size = ((u16)buf[sys_info_addr + 2] << 8) | buf[sys_info_addr + 3];
RTSX_DEBUGP(("total_blk = 0x%x, blk_size = 0x%x\n", total_blk, blk_size));
}
#else
total_blk = ((u16)buf[sys_info_addr + 6] << 8) | buf[sys_info_addr + 7];
blk_size = ((u16)buf[sys_info_addr + 2] << 8) | buf[sys_info_addr + 3];
RTSX_DEBUGP(("total_blk = 0x%x, blk_size = 0x%x\n", total_blk, blk_size));
#endif
RTSX_DEBUGP(("class_code = 0x%x, device_type = 0x%x, sub_class = 0x%x\n",