diff --git a/patch/kernel/archive/rockchip64-6.13/rk356x-fix-pcie2-reset.patch b/patch/kernel/archive/rockchip64-6.13/rk356x-fix-pcie2-reset.patch new file mode 100644 index 000000000000..f6ae45b39408 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.13/rk356x-fix-pcie2-reset.patch @@ -0,0 +1,45 @@ +Subject: [PATCH 1/2] arm64: dts: rockchip: rk3568: add reset-names for combphy +Date: Fri, 22 Nov 2024 15:30:05 +0800 + +The reset-names of combphy are missing, add it. + +Signed-off-by: Chukun Pan +--- + arch/arm64/boot/dts/rockchip/rk3568.dtsi | 1 + + arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 2 ++ + 2 files changed, 3 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +index ecaefe208e3e..695cccbdab0f 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi +@@ -350,6 +350,7 @@ combphy0: phy@fe820000 { + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY0>; ++ reset-names = "phy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; + #phy-cells = <1>; +diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +index 62be06f3b863..e55390629114 100644 +--- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +@@ -1681,6 +1681,7 @@ combphy1: phy@fe830000 { + assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY1>; ++ reset-names = "phy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf1>; + #phy-cells = <1>; +@@ -1697,6 +1698,7 @@ combphy2: phy@fe840000 { + assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PIPEPHY2>; ++ reset-names = "phy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf2>; + #phy-cells = <1>; +-- +2.25.1