diff --git a/bsp/mm32f526x/.config b/bsp/mm32f526x/.config index 82cf339290c..1c39d7ad25c 100644 --- a/bsp/mm32f526x/.config +++ b/bsp/mm32f526x/.config @@ -117,7 +117,7 @@ CONFIG_RT_ALIGN_SIZE=8 CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=100 +CONFIG_RT_TICK_PER_SECOND=1000 CONFIG_RT_USING_OVERFLOW_CHECK=y CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y @@ -125,7 +125,10 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=256 -# CONFIG_RT_USING_TIMER_SOFT is not set +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set # CONFIG_RT_USING_CPU_USAGE_TRACER is not set # @@ -158,9 +161,7 @@ CONFIG_RT_USING_MESSAGEQUEUE=y CONFIG_RT_USING_MEMPOOL=y CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set -CONFIG_RT_USING_MEMHEAP=y -CONFIG_RT_MEMHEAP_FAST_MODE=y -# CONFIG_RT_MEMHEAP_BEST_MODE is not set +# CONFIG_RT_USING_MEMHEAP is not set CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y # CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set # CONFIG_RT_USING_SLAB_AS_HEAP is not set @@ -188,7 +189,7 @@ CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 # CONFIG_RT_USING_COMPONENTS_INIT=y CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=1024 +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 CONFIG_RT_MAIN_THREAD_PRIORITY=10 # CONFIG_RT_USING_LEGACY is not set CONFIG_RT_USING_MSH=y @@ -196,7 +197,7 @@ CONFIG_RT_USING_FINSH=y CONFIG_FINSH_USING_MSH=y CONFIG_FINSH_THREAD_NAME="tshell" CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=1024 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 CONFIG_FINSH_USING_HISTORY=y CONFIG_FINSH_HISTORY_LINES=5 CONFIG_FINSH_USING_SYMTAB=y @@ -227,19 +228,15 @@ CONFIG_RT_UNAMED_PIPE_NUMBER=64 CONFIG_RT_USING_SERIAL=y CONFIG_RT_USING_SERIAL_V1=y # CONFIG_RT_USING_SERIAL_V2 is not set -# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_USING_DMA=y CONFIG_RT_SERIAL_RB_BUFSZ=64 # CONFIG_RT_USING_SERIAL_BYPASS is not set # CONFIG_RT_USING_CAN is not set # CONFIG_RT_USING_CPUTIME is not set -CONFIG_RT_USING_I2C=y -# CONFIG_RT_I2C_DEBUG is not set -CONFIG_RT_USING_I2C_BITOPS=y -# CONFIG_RT_I2C_BITOPS_DEBUG is not set -# CONFIG_RT_USING_SOFT_I2C is not set +# CONFIG_RT_USING_I2C is not set # CONFIG_RT_USING_PHY is not set # CONFIG_RT_USING_PHY_V2 is not set -# CONFIG_RT_USING_ADC is not set +CONFIG_RT_USING_ADC=y # CONFIG_RT_USING_DAC is not set # CONFIG_RT_USING_NULL is not set # CONFIG_RT_USING_ZERO is not set @@ -860,10 +857,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_MULTI_INFRARED is not set # CONFIG_PKG_USING_AGILE_BUTTON is not set # CONFIG_PKG_USING_AGILE_LED is not set -CONFIG_PKG_USING_AT24CXX=y -CONFIG_PKG_AT24CXX_PATH="/packages/peripherals/at24cxx" -CONFIG_PKG_USING_AT24CXX_LATEST_VERSION=y -CONFIG_PKG_AT24CXX_VER="latest" +# CONFIG_PKG_USING_AT24CXX is not set # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set # CONFIG_PKG_USING_PCA9685 is not set # CONFIG_PKG_USING_ILI9341 is not set @@ -1280,11 +1274,9 @@ CONFIG_BSP_USING_GPIO=y CONFIG_BSP_USING_UART3=y # end of UART Drivers -# CONFIG_BSP_USING_ADC is not set -CONFIG_BSP_USING_I2C1=y -CONFIG_BSP_I2C1_SCL_PIN=40 -CONFIG_BSP_I2C1_SDA_PIN=39 -# CONFIG_BSP_USING_I2C2 is not set +CONFIG_BSP_USING_ADC=y +CONFIG_BSP_USING_ADC1=y +# CONFIG_BSP_USING_ADC2 is not set # # Flash Drivers diff --git a/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/hal_common.h b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/hal_common.h new file mode 100644 index 00000000000..f1c3f3af776 --- /dev/null +++ b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/hal_common.h @@ -0,0 +1,17 @@ +/* + * Copyright 2021 MindMotion Microelectronics Co., Ltd. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef __HAL_COMMON_H__ +#define __HAL_COMMON_H__ + +#include +#include +#include + +#include "hal_conf.h" + +#endif /* __HAL_COMMON_H__ */ + diff --git a/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/hal_device.h b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/hal_device.h deleted file mode 100644 index ff21337025b..00000000000 --- a/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/hal_device.h +++ /dev/null @@ -1,41 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -/// @file hal_device.h -/// @author AE team -/// @brief CMSIS Cortex-M Peripheral Access Layer for MindMotion -/// microcontroller devices -//////////////////////////////////////////////////////////////////////////////// -/// @attention -/// -/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE -/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE -/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR -/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH -/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN -/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. -/// -///

© COPYRIGHT MINDMOTION

-//////////////////////////////////////////////////////////////////////////////// - - -// Define to prevent recursive inclusion -#ifndef __HAL_DEVICE_H -#define __HAL_DEVICE_H - - - - - -#include "mm32_device.h" - - -#endif // __HAL_device_H - -/// @} - - -/// @} - -/// @} - - - diff --git a/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/hal_flexcan.h b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/hal_flexcan.h index 4bc03598a2b..01c1e6692b5 100644 --- a/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/hal_flexcan.h +++ b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/hal_flexcan.h @@ -44,13 +44,13 @@ */ /* FLEXCAN module features */ -/** - * @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message - * that is enabled to be transmitted in a specific moment during the arbitration process). +/** + * @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message + * that is enabled to be transmitted in a specific moment during the arbitration process). */ #define FLEXCAN_HAS_ERRATA_5829 (0) -/** +/** * @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode * or the Low-Power Mode are entered during a Bus-Off state) */ @@ -67,7 +67,7 @@ #define FLEXCAN_HAS_RX_FIFO_DMA (0) /** - *@brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus + *@brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus * when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */ #define FLEXCAN_HAS_ERRATA_6032 (0) @@ -131,10 +131,10 @@ ((id << FLEXCAN_ID_EXT_Pos) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */ #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */ \ (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ - (((id << FLEXCAN_ID_EXT_Pos) & 0x1FFF8000) << 1)) + (((id << FLEXCAN_ID_EXT_Pos) & 0x1FFF8000) << 1)) #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide) /*!< Extend Rx FIFO Mask helper macro Type B lower part helper macro. */ \ (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \ - (((id << FLEXCAN_ID_EXT_Pos) & 0x1FFF8000) >> 15)) + (((id << FLEXCAN_ID_EXT_Pos) & 0x1FFF8000) >> 15)) #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id) \ (((id << FLEXCAN_ID_EXT_Pos) & 0x1FE00000) << 3) /*!< Extend Rx FIFO Mask helper macro Type C upper part helper macro. */ #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH(id) \ @@ -180,34 +180,34 @@ /** * @brief Generic status return codes. */ -#define Status_Flexcan_Success 0 /*!< Generic status for Success. */ -#define Status_Flexcan_Fail 1 /*!< Generic status for Fail. */ -#define Status_Flexcan_ReadOnly 2 /*!< Generic status for read only failure. */ -#define Status_Flexcan_OutOfRange 3 /*!< Generic status for out of range access. */ -#define Status_Flexcan_InvalidArgument 4 /*!< Generic status for invalid argument check. */ -#define Status_Flexcan_Timeout 5 /*!< Generic status for timeout. */ -#define Status_Flexcan_NoTransferInProgress 6 /*!< Generic status for no transfer in progress. */ +#define Status_Flexcan_Success 0x00000000 /*!< Generic status for Success. */ +#define Status_Flexcan_Fail 0x00000001 /*!< Generic status for Fail. */ +#define Status_Flexcan_ReadOnly 0x00000002 /*!< Generic status for read only failure. */ +#define Status_Flexcan_OutOfRange 0x00000003 /*!< Generic status for out of range access. */ +#define Status_Flexcan_InvalidArgument 0x00000004 /*!< Generic status for invalid argument check. */ +#define Status_Flexcan_Timeout 0x00000005 /*!< Generic status for timeout. */ +#define Status_Flexcan_NoTransferInProgress 0x00000006 /*!< Generic status for no transfer in progress. */ /** * @brief FlexCAN transfer status. */ -#define Status_Flexcan_TxBusy 0 /*!< Tx Message Buffer is Busy. */ -#define Status_Flexcan_TxIdle 1 /*!< Tx Message Buffer is Idle. */ -#define Status_Flexcan_TxSwitchToRx 2 /*!< Remote Message is send out and Message buffer changed to Receive one. */ -#define Status_Flexcan_RxBusy 3 /*!< Rx Message Buffer is Busy. */ -#define Status_Flexcan_RxIdle 4 /*!< Rx Message Buffer is Idle. */ -#define Status_Flexcan_RxOverflow 5 /*!< Rx Message Buffer is Overflowed. */ -#define Status_Flexcan_RxFifoBusy 6 /*!< Rx Message FIFO is Busy. */ -#define Status_Flexcan_RxFifoIdle 7 /*!< Rx Message FIFO is Idle. */ -#define Status_Flexcan_RxFifoOverflow 8 /*!< Rx Message FIFO is overflowed. */ -#define Status_Flexcan_RxFifoWarning 9 /*!< Rx Message FIFO is almost overflowed. */ -#define Status_Flexcan_RxFifoDisabled 10 /*!< Rx Message FIFO is disabled during reading. */ -#define Status_Flexcan_ErrorStatus 11 /*!< FlexCAN Module Error and Status. */ -#define Status_Flexcan_WakeUp 12 /*!< FlexCAN is waken up from STOP mode. */ -#define Status_Flexcan_UnHandled 13 /*!< UnHadled Interrupt asserted. */ -#define Status_Flexcan_RxRemote 14 /*!< Rx Remote Message Received in Mail box. */ -#define Status_Flexcan_RxFifoUnderflow 15 /*!< Enhanced Rx Message FIFO is underflow. */ +#define Status_Flexcan_TxBusy 0x00010000 /*!< Tx Message Buffer is Busy. */ +#define Status_Flexcan_TxIdle 0x00010001 /*!< Tx Message Buffer is Idle. */ +#define Status_Flexcan_TxSwitchToRx 0x00010002 /*!< Remote Message is send out and Message buffer changed to Receive one. */ +#define Status_Flexcan_RxBusy 0x00010003 /*!< Rx Message Buffer is Busy. */ +#define Status_Flexcan_RxIdle 0x00010004 /*!< Rx Message Buffer is Idle. */ +#define Status_Flexcan_RxOverflow 0x00010005 /*!< Rx Message Buffer is Overflowed. */ +#define Status_Flexcan_RxFifoBusy 0x00010006 /*!< Rx Message FIFO is Busy. */ +#define Status_Flexcan_RxFifoIdle 0x00010007 /*!< Rx Message FIFO is Idle. */ +#define Status_Flexcan_RxFifoOverflow 0x00010008 /*!< Rx Message FIFO is overflowed. */ +#define Status_Flexcan_RxFifoWarning 0x00010009 /*!< Rx Message FIFO is almost overflowed. */ +#define Status_Flexcan_RxFifoDisabled 0x0001000A /*!< Rx Message FIFO is disabled during reading. */ +#define Status_Flexcan_ErrorStatus 0x0001000B /*!< FlexCAN Module Error and Status. */ +#define Status_Flexcan_WakeUp 0x0001000C /*!< FlexCAN is waken up from STOP mode. */ +#define Status_Flexcan_UnHandled 0x0001000D /*!< UnHadled Interrupt asserted. */ +#define Status_Flexcan_RxRemote 0x0001000E /*!< Rx Remote Message Received in Mail box. */ +#define Status_Flexcan_RxFifoUnderflow 0x0001000F /*!< Enhanced Rx Message FIFO is underflow. */ /** * @brief FlexCAN frame format. @@ -256,18 +256,6 @@ typedef enum _flexcan_rx_fifo_filter_type Enum_Flexcan_RxFifoFilterTypeD = 0x3U /*!< All frames rejected. */ } flexcan_rx_fifo_filter_type_t; -/** - * @brief FlexCAN Message Buffer Payload size. - */ -typedef enum _flexcan_mb_size -{ - FLEXCAN_8BperMB = 0x0U, /*!< Selects 8 bytes per Message Buffer. */ - FLEXCAN_16BperMB = 0x1U, /*!< Selects 16 bytes per Message Buffer. */ - FLEXCAN_32BperMB = 0x2U, /*!< Selects 32 bytes per Message Buffer. */ - FLEXCAN_64BperMB = 0x3U /*!< Selects 64 bytes per Message Buffer. */ -} flexcan_mb_size_t; - - /** * @brief FlexCAN Rx FIFO priority. * The matching process starts from the Rx MB(or Rx FIFO) with higher priority. @@ -302,7 +290,7 @@ enum _flexcan_interrupt_enable * * This provides constants for the FlexCAN status flags for use in the FlexCAN functions. * Note: The CPU read action clears FlEXCAN_ErrorFlag, therefore user need to - * read FlEXCAN_ErrorFlag and distinguish which error is occur using + * read FlEXCAN_ErrorFlag and distinguish which error is occur using * @ref _flexcan_error_flags enumerations. */ enum _flexcan_flags @@ -400,106 +388,6 @@ typedef struct _flexcan_frame }; } flexcan_frame_t; -/** - * @brief FlexCAN FD message frame structure. - */ -typedef struct _flexcan_fd_frame -{ - struct - { - uint32_t timestamp : 16; /*!< FlexCAN internal Free-Running Counter Time Stamp. */ - uint32_t length : 4; /*!< CAN frame data length in bytes, range see @ref _flexcan_fd_frame_length. */ - uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */ - uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */ - uint32_t srr : 1; /*!< Substitute Remote request. */ - uint32_t RESERVED_0 : 1; - uint32_t code : 4; /*!< Message Buffer Code. */ - uint32_t RESERVED_1 : 1; - uint32_t esi : 1; /*!< Error State Indicator. */ - uint32_t brs : 1; /*!< Bit Rate Switch. */ - uint32_t edl : 1; /*!< Extended Data Length. */ - }; - struct - { - uint32_t id : 29; /*!< CAN Frame Identifier. */ - uint32_t RESERVED_3 : 3; /*!< Reserved. */ - }; - union - { - struct - { - uint32_t dataWord[16]; /*!< CAN FD Frame payload, 16 double word maximum. */ - }; - struct - { - uint8_t dataByte3; /*!< CAN Frame payload byte3. */ - uint8_t dataByte2; /*!< CAN Frame payload byte2. */ - uint8_t dataByte1; /*!< CAN Frame payload byte1. */ - uint8_t dataByte0; /*!< CAN Frame payload byte0. */ - uint8_t dataByte7; /*!< CAN Frame payload byte7. */ - uint8_t dataByte6; /*!< CAN Frame payload byte6. */ - uint8_t dataByte5; /*!< CAN Frame payload byte5. */ - uint8_t dataByte4; /*!< CAN Frame payload byte4. */ - uint8_t dataByte11; /*!< CAN Frame payload byte11. */ - uint8_t dataByte10; /*!< CAN Frame payload byte10. */ - uint8_t dataByte9; /*!< CAN Frame payload byte9. */ - uint8_t dataByte8; /*!< CAN Frame payload byte8. */ - uint8_t dataByte15; /*!< CAN Frame payload byte15. */ - uint8_t dataByte14; /*!< CAN Frame payload byte14. */ - uint8_t dataByte13; /*!< CAN Frame payload byte13. */ - uint8_t dataByte12; /*!< CAN Frame payload byte12. */ - uint8_t dataByte19; /*!< CAN Frame payload byte19. */ - uint8_t dataByte18; /*!< CAN Frame payload byte18. */ - uint8_t dataByte17; /*!< CAN Frame payload byte17. */ - uint8_t dataByte16; /*!< CAN Frame payload byte16. */ - uint8_t dataByte23; /*!< CAN Frame payload byte23. */ - uint8_t dataByte22; /*!< CAN Frame payload byte22. */ - uint8_t dataByte21; /*!< CAN Frame payload byte21. */ - uint8_t dataByte20; /*!< CAN Frame payload byte20. */ - uint8_t dataByte27; /*!< CAN Frame payload byte27. */ - uint8_t dataByte26; /*!< CAN Frame payload byte26. */ - uint8_t dataByte25; /*!< CAN Frame payload byte25. */ - uint8_t dataByte24; /*!< CAN Frame payload byte24. */ - uint8_t dataByte31; /*!< CAN Frame payload byte31. */ - uint8_t dataByte30; /*!< CAN Frame payload byte30. */ - uint8_t dataByte29; /*!< CAN Frame payload byte29. */ - uint8_t dataByte28; /*!< CAN Frame payload byte28. */ - uint8_t dataByte35; /*!< CAN Frame payload byte35. */ - uint8_t dataByte34; /*!< CAN Frame payload byte34. */ - uint8_t dataByte33; /*!< CAN Frame payload byte33. */ - uint8_t dataByte32; /*!< CAN Frame payload byte32. */ - uint8_t dataByte39; /*!< CAN Frame payload byte39. */ - uint8_t dataByte38; /*!< CAN Frame payload byte38. */ - uint8_t dataByte37; /*!< CAN Frame payload byte37. */ - uint8_t dataByte36; /*!< CAN Frame payload byte36. */ - uint8_t dataByte43; /*!< CAN Frame payload byte43. */ - uint8_t dataByte42; /*!< CAN Frame payload byte42. */ - uint8_t dataByte41; /*!< CAN Frame payload byte41. */ - uint8_t dataByte40; /*!< CAN Frame payload byte40. */ - uint8_t dataByte47; /*!< CAN Frame payload byte47. */ - uint8_t dataByte46; /*!< CAN Frame payload byte46. */ - uint8_t dataByte45; /*!< CAN Frame payload byte45. */ - uint8_t dataByte44; /*!< CAN Frame payload byte44. */ - uint8_t dataByte51; /*!< CAN Frame payload byte51. */ - uint8_t dataByte50; /*!< CAN Frame payload byte50. */ - uint8_t dataByte49; /*!< CAN Frame payload byte49. */ - uint8_t dataByte48; /*!< CAN Frame payload byte48. */ - uint8_t dataByte55; /*!< CAN Frame payload byte55. */ - uint8_t dataByte54; /*!< CAN Frame payload byte54. */ - uint8_t dataByte53; /*!< CAN Frame payload byte53. */ - uint8_t dataByte52; /*!< CAN Frame payload byte52. */ - uint8_t dataByte59; /*!< CAN Frame payload byte59. */ - uint8_t dataByte58; /*!< CAN Frame payload byte58. */ - uint8_t dataByte57; /*!< CAN Frame payload byte57. */ - uint8_t dataByte56; /*!< CAN Frame payload byte56. */ - uint8_t dataByte63; /*!< CAN Frame payload byte63. */ - uint8_t dataByte62; /*!< CAN Frame payload byte62. */ - uint8_t dataByte61; /*!< CAN Frame payload byte61. */ - uint8_t dataByte60; /*!< CAN Frame payload byte60. */ - }; - }; -} flexcan_fd_frame_t; - /** * @brief FlexCAN protocol timing characteristic configuration structure. */ @@ -526,7 +414,6 @@ typedef struct _flexcan_timing_config typedef struct _flexcan_config { uint32_t baudRate; /*!< FlexCAN baud rate in bps. */ - uint32_t baudRateFD; /*!< FlexCAN FD baud rate in bps. */ flexcan_clock_source_t clkSrc; /*!< Clock source for FlexCAN Protocol Engine. */ flexcan_wake_up_source_t wakeupSrc; /*!< Wake up source selection. */ uint8_t maxMbNum; /*!< The maximum number of Message Buffers used by user. */ @@ -572,7 +459,6 @@ typedef struct _flexcan_rx_fifo_config */ typedef struct _flexcan_mb_transfer { - flexcan_fd_frame_t *framefd; /*!< The buffer of CAN FD Message to be transfer. */ flexcan_frame_t *frame; /*!< The buffer of CAN Message to be transfer. */ uint8_t mbIdx; /*!< The index of Message buffer used to transfer Message. */ } flexcan_mb_transfer_t; @@ -582,7 +468,6 @@ typedef struct _flexcan_mb_transfer */ typedef struct _flexcan_fifo_transfer { - flexcan_fd_frame_t *framefd; /*!< The buffer of CAN Message to be received from Enhanced Rx FIFO. */ flexcan_frame_t *frame; /*!< The buffer of CAN Message to be received from Rx FIFO. */ uint32_t frameNum; /*!< Number of CAN Message need to be received from Legacy or Ehanced Rx FIFO. */ } flexcan_fifo_transfer_t; @@ -613,7 +498,6 @@ struct _flexcan_handle flexcan_transfer_callback_t callback; /*!< Callback function. */ void *userData; /*!< FlexCAN callback function parameter. */ flexcan_frame_t *volatile mbFrameBuf[CAN_WORD1_COUNT]; - flexcan_fd_frame_t *volatile mbFDFrameBuf[CAN_WORD1_COUNT]; /*!< The buffer for received data from Message Buffers. ------------------*/ flexcan_frame_t *volatile rxFifoFrameBuf; /*!< The buffer for received data from Rx FIFO. */ uint32_t rxFifoFrameNum; /*!< The number of CAN messages remaining to be received from Rx FIFO. */ @@ -623,29 +507,6 @@ struct _flexcan_handle volatile uint32_t timestamp[CAN_WORD1_COUNT]; /*!< Mailbox transfer timestamp. */ }; -/** - * @brief FlexCAN FD Message Buffer Size. - */ -typedef enum -{ - FlexCANFD_TX_0Byte_DataLen = 0, /* FlexCANFD sends 0 byte of data length per frame */ - FlexCANFD_TX_1Byte_DataLen = 1, /* FlexCANFD sends 1 byte of data length per frame */ - FlexCANFD_TX_2Bytes_DataLen = 2, /* FlexCANFD sends 2 bytes of data length per frame */ - FlexCANFD_TX_3Bytes_DataLen = 3, /* FlexCANFD sends 3 bytes of data length per frame */ - FlexCANFD_TX_4Bytes_DataLen = 4, /* FlexCANFD sends 4 bytes of data length per frame */ - FlexCANFD_TX_5Bytes_DataLen = 5, /* FlexCANFD sends 5 bytes of data length per frame */ - FlexCANFD_TX_6Bytes_DataLen = 6, /* FlexCANFD sends 6 bytes of data length per frame */ - FlexCANFD_TX_7Bytes_DataLen = 7, /* FlexCANFD sends 7 bytes of data length per frame */ - FlexCANFD_TX_8Bytes_DataLen = 8, /* FlexCANFD sends 8 bytes of data length per frame */ - FlexCANFD_TX_12Bytes_DataLen = 9, /* FlexCANFD sends 12 bytes of data length per frame */ - FlexCANFD_TX_16Bytes_DataLen = 10, /* FlexCANFD sends 16 bytes of data length per frame */ - FlexCANFD_TX_20Bytes_DataLen = 11, /* FlexCANFD sends 20 bytes of data length per frame */ - FlexCANFD_TX_24Bytes_DataLen = 12, /* FlexCANFD sends 24 bytes of data length per frame */ - FlexCANFD_TX_32Bytes_DataLen = 13, /* FlexCANFD sends 32 bytes of data length per frame */ - FlexCANFD_TX_48Bytes_DataLen = 14, /* FlexCANFD sends 48 bytes of data length per frame */ - FlexCANFD_TX_64Bytes_DataLen = 15 /* FlexCANFD sends 64 bytes of data length per frame */ -} FLEXCANFD_Tx_DataLen_Type; - /** * @} */ @@ -851,14 +712,7 @@ __STATIC_INLINE void FLEXCAN_Cmd(FLEXCAN_TypeDef *flex_can, FunctionalState stat int32_t FLEXCAN_WriteTxMb(FLEXCAN_TypeDef *flex_can, uint8_t mbIdx, const flexcan_frame_t *pTxFrame); int32_t FLEXCAN_ReadRxMb(FLEXCAN_TypeDef *flex_can, uint8_t mbIdx, flexcan_frame_t *pRxFrame); -int32_t FLEXCAN_WriteFDTxMb(FLEXCAN_TypeDef *flex_can, uint8_t mbIdx, const flexcan_fd_frame_t *pTxFrame); -int32_t FLEXCAN_ReadFDRxMb(FLEXCAN_TypeDef *flex_can, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame); int32_t FLEXCAN_ReadRxFifo(FLEXCAN_TypeDef *flex_can, flexcan_frame_t *pRxFrame); -int32_t FLEXCAN_TransferFDSendBlocking(FLEXCAN_TypeDef *flex_can, uint8_t mbIdx, flexcan_fd_frame_t *pTxFrame); -int32_t FLEXCAN_TransferFDReceiveBlocking(FLEXCAN_TypeDef *flex_can, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame); -int32_t FLEXCAN_TransferFDReceiveNonBlocking(FLEXCAN_TypeDef *flex_can, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer); -int32_t FLEXCAN_TransferFDSendNonBlocking(FLEXCAN_TypeDef *flex_can, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer); -void FLEXCAN_TransferFDAbortReceive(FLEXCAN_TypeDef *flex_can, flexcan_handle_t *handle, uint8_t mbIdx); int32_t FLEXCAN_TransferSendBlocking(FLEXCAN_TypeDef *flex_can, uint8_t mbIdx, flexcan_frame_t *pTxFrame); int32_t FLEXCAN_TransferReceiveBlocking(FLEXCAN_TypeDef *flex_can, uint8_t mbIdx, flexcan_frame_t *pRxFrame); int32_t FLEXCAN_TransferReceiveFifoBlocking(FLEXCAN_TypeDef *flex_can, flexcan_frame_t *pRxFrame); @@ -871,14 +725,7 @@ void FLEXCAN_TransferAbortSend(FLEXCAN_TypeDef *flex_can, flexcan_handle_t *hand void FLEXCAN_TransferAbortReceive(FLEXCAN_TypeDef *flex_can, flexcan_handle_t *handle, uint8_t mbIdx); void FLEXCAN_TransferAbortReceiveFifo(FLEXCAN_TypeDef *flex_can, flexcan_handle_t *handle); void FLEXCAN_TransferHandleIRQ(FLEXCAN_TypeDef *flex_can, flexcan_handle_t *handle); -ErrorStatus FLEXCAN_FDCalculateImprovedTimingValues(uint32_t baudRate, uint32_t baudRateFD, uint32_t sourceClock_Hz, flexcan_timing_config_t *pTimingConfig); -void FLEXCAN_FDTxMbConfig(FLEXCAN_TypeDef *flex_can, uint8_t mbIdx, FunctionalState enable); -void FLEXCAN_FDRxMbConfig(FLEXCAN_TypeDef *flex_can, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, FunctionalState state); -void FLEXCAN_SetFDTimingConfig(FLEXCAN_TypeDef *flex_can, const flexcan_timing_config_t *pConfig); -void FLEXCAN_FDInit(FLEXCAN_TypeDef *flex_can, const flexcan_config_t *pConfig, flexcan_mb_size_t dataSize, FunctionalState brs); void FLEXCAN_SetBaudRate(FLEXCAN_TypeDef *flex_can, flexcan_timing_config_t timingConfig); -void FLEXCAN_SetFDBaudRate(FLEXCAN_TypeDef *flex_can, flexcan_timing_config_t timingConfig); -uint32_t FLEXCAN_GetFDMailboxOffset(FLEXCAN_TypeDef *flex_can, uint8_t mbIdx); @@ -895,4 +742,3 @@ uint32_t FLEXCAN_GetFDMailboxOffset(FLEXCAN_TypeDef *flex_can, uint8_t mbIdx); /** * @} */ - diff --git a/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/hal_gpio.h b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/hal_gpio.h index d6a5a426bef..07809cdc70f 100644 --- a/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/hal_gpio.h +++ b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/hal_gpio.h @@ -135,10 +135,10 @@ typedef struct #define GPIO_AF_13 (0x0DU) #define GPIO_AF_14 (0x0EU) #define GPIO_AF_15 (0x0FU) -#define GPIO_PortSourceGPIOA (0x00U) -#define GPIO_PortSourceGPIOB (0x01U) -#define GPIO_PortSourceGPIOC (0x02U) -#define GPIO_PortSourceGPIOD (0x03U) +#define GPIO_PortSourceGPIOA (0x00U) +#define GPIO_PortSourceGPIOB (0x01U) +#define GPIO_PortSourceGPIOC (0x02U) +#define GPIO_PortSourceGPIOD (0x03U) #define GPIO_PinSource0 (0x00U) #define GPIO_PinSource1 (0x01U) @@ -157,6 +157,13 @@ typedef struct #define GPIO_PinSource14 (0x0EU) #define GPIO_PinSource15 (0x0FU) +/** + * @brief The port pull-up or pull-down mode + */ +#define GPIO_OD_NoPull 0x00 +#define GPIO_OD_PullDown 0x01 +#define GPIO_OD_PullUp 0x03 + /** * @} */ @@ -186,6 +193,7 @@ void GPIO_WriteBit(GPIO_TypeDef *gpio, uint16_t pin, BitAction value); void GPIO_Write(GPIO_TypeDef *gpio, uint16_t value); void GPIO_PinLockConfig(GPIO_TypeDef *gpio, uint16_t pin, uint16_t lock); void GPIO_PinAFConfig(GPIO_TypeDef *gpio, uint8_t pin, uint8_t alternate_function); +void GPIO_PinODConfig(GPIO_TypeDef *gpio, uint16_t pin, uint32_t od_mode); /** * @} diff --git a/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/hal_rcc.h b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/hal_rcc.h index 8f4bfaa83fe..1e5b8cf6df1 100644 --- a/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/hal_rcc.h +++ b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/hal_rcc.h @@ -205,12 +205,10 @@ typedef struct #define RCC_APB1Periph_BKP (0x01U << RCC_APB1ENR_BKP_Pos) #define RCC_APB1Periph_PWRDBG (0x01U << RCC_APB1ENR_PWRDBG_Pos) #define RCC_APB1Periph_DAC (0x01U << RCC_APB1ENR_DAC_Pos) -#define RCC_APB1Periph_UART7 (0x01U << RCC_APB1ENR_UART7_Pos) #define RCC_APB2Periph_TIM1 (0x01U << RCC_APB2ENR_TIM1_Pos) #define RCC_APB2Periph_TIM8 (0x01U << RCC_APB2ENR_TIM8_Pos) #define RCC_APB2Periph_UART1 (0x01U << RCC_APB2ENR_UART1_Pos) -#define RCC_APB2Periph_UART6 (0x01U << RCC_APB2ENR_UART6_Pos) #define RCC_APB2Periph_ADC1 (0x01U << RCC_APB2ENR_ADC1_Pos) #define RCC_APB2Periph_ADC2 (0x01U << RCC_APB2ENR_ADC2_Pos) #define RCC_APB2Periph_SPI1 (0x01U << RCC_APB2ENR_SPI1_Pos) diff --git a/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/hal_syscfg.h b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/hal_syscfg.h index dc45a25e244..58f5e11f02c 100644 --- a/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/hal_syscfg.h +++ b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/hal_syscfg.h @@ -165,18 +165,6 @@ extern "C" { #define SYSCFG_UART4_TX_RMP_DMA2_CH5 ((0x00 << 5U) | SYSCFG_DMARMP_UART4_TX_RMP_Pos) #define SYSCFG_UART4_TX_RMP_DMA2_CH8 ((0x01 << 5U) | SYSCFG_DMARMP_UART4_TX_RMP_Pos) -#define SYSCFG_UART6_RX_RMP_DMA1_CH1 ((0x00 << 5U) | SYSCFG_DMARMP_UART6_RX_RMP_Pos) -#define SYSCFG_UART6_RX_RMP_DMA2_CH6 ((0x01 << 5U) | SYSCFG_DMARMP_UART6_RX_RMP_Pos) - -#define SYSCFG_UART6_TX_RMP_DMA2_CH4 ((0x00 << 5U) | SYSCFG_DMARMP_UART6_TX_RMP_Pos) -#define SYSCFG_UART6_TX_RMP_DMA1_CH8 ((0x01 << 5U) | SYSCFG_DMARMP_UART6_TX_RMP_Pos) - -#define SYSCFG_UART7_RX_RMP_DMA2_CH1 ((0x00 << 5U) | SYSCFG_DMARMP_UART7_RX_RMP_Pos) -#define SYSCFG_UART7_RX_RMP_DMA2_CH7 ((0x01 << 5U) | SYSCFG_DMARMP_UART7_RX_RMP_Pos) - -#define SYSCFG_UART7_TX_RMP_DMA2_CH2 ((0x00 << 5U) | SYSCFG_DMARMP_UART7_TX_RMP_Pos) -#define SYSCFG_UART7_TX_RMP_DMA2_CH8 ((0x01 << 5U) | SYSCFG_DMARMP_UART7_TX_RMP_Pos) - #define SYSCFG_DAC_CH1_RMP_DMA2_CH3 ((0x00 << 5U) | SYSCFG_DMARMP_DAC_CH1_RMP_Pos) #define SYSCFG_DAC_CH1_RMP_DMA2_CH7 ((0x01 << 5U) | SYSCFG_DMARMP_DAC_CH1_RMP_Pos) diff --git a/bsp/mm32f526x/Libraries/MM32F526x/Include/mm32_device.h b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/mm32_device.h similarity index 100% rename from bsp/mm32f526x/Libraries/MM32F526x/Include/mm32_device.h rename to bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/mm32_device.h diff --git a/bsp/mm32f526x/Libraries/MM32F526x/Include/mm32f5260.h b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/mm32f5260.h similarity index 97% rename from bsp/mm32f526x/Libraries/MM32F526x/Include/mm32f5260.h rename to bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/mm32f5260.h index d311f3b6d43..cf38ee74bba 100644 --- a/bsp/mm32f526x/Libraries/MM32F526x/Include/mm32f5260.h +++ b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Inc/mm32f5260.h @@ -51,19 +51,19 @@ extern "C" { extern void SystemInit(void); -/* MM32 Library version is V0.10 --------------------------------------------*/ +/* MM32 Library version is V0.11 --------------------------------------------*/ #define __MM32_LIB_VERSION_MAIN (0x00U) /*!< [15:8] main version */ -#define __MM32_LIB_VERSION_SUB (0x10U) /*!< [7:0] sub version */ +#define __MM32_LIB_VERSION_SUB (0x11U) /*!< [7:0] sub version */ #define __MM32_LIB_VERSION \ ((__MM32_LIB_VERSION_MAIN << 8U) \ | (__MM32_LIB_VERSION_SUB << 0U)) -/* MM32 Library release date is 2024-09-27 -----------------------------------*/ +/* MM32 Library release date is 2024-12-20 -----------------------------------*/ #define __MM32_LIB_RELESE_YEARH (0x20U) /*!< [31:24] release year high */ #define __MM32_LIB_RELESE_YEARL (0x24U) /*!< [23:16] release year low */ -#define __MM32_LIB_RELESE_MONTH (0x09U) /*!< [15:8] release month */ -#define __MM32_LIB_RELESE_DAY (0x27U) /*!< [7:0] release day */ +#define __MM32_LIB_RELESE_MONTH (0x12U) /*!< [15:8] release month */ +#define __MM32_LIB_RELESE_DAY (0x20U) /*!< [7:0] release day */ #define __MM32_LIB_RELESE_DATE \ ((__MM32_LIB_RELESE_YEARH << 24U) \ | (__MM32_LIB_RELESE_YEARL << 16U) \ @@ -177,8 +177,6 @@ typedef enum IRQn DMA2_CH6_IRQn = 68, /*!< DMA2 Channel 6 */ DMA2_CH7_IRQn = 69, /*!< DMA2 Channel 7 */ DMA2_CH8_IRQn = 70, /*!< DMA2 Channel 8 */ - UART6_IRQn = 71, /*!< UART6 */ - UART7_IRQn = 82, /*!< UART7 */ QSPI_IRQn = 95, /*!< QSPI */ LPTIM_IRQn = 102, /*!< LPTIM */ LPUART_IRQn = 104 /*!< LPUART */ @@ -321,6 +319,7 @@ typedef enum #include "reg_usb_fs.h" #include "reg_wwdg.h" +#define USE_STDPERIPH_DRIVER #ifdef USE_STDPERIPH_DRIVER #include "hal_conf.h" #endif diff --git a/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_flexcan.c b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_flexcan.c index d2d45c8612a..737cd88573a 100644 --- a/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_flexcan.c +++ b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_flexcan.c @@ -70,8 +70,6 @@ #define MAX_FPSEG2 (FLEXCAN_FDCBT_FPSEG2_Msk >> FLEXCAN_FDCBT_FPSEG2_Pos) #define MAX_FRJW (FLEXCAN_FDCBT_FRJW_Msk >> FLEXCAN_FDCBT_FRJW_Pos) #define MAX_FPRESDIV (FLEXCAN_FDCBT_FPRESDIV_Msk >> FLEXCAN_FDCBT_FPRESDIV_Pos) -#define FDCBT_MAX_TIME_QUANTA (1U + MAX_FPROPSEG + 0U + MAX_FPSEG1 + 1U + MAX_FPSEG2 + 1U) -#define FDCBT_MIN_TIME_QUANTA (5U) #define MAX_TDCOFF ((uint32_t)FLEXCAN_FDCTRL_TDCOFF_Msk >> FLEXCAN_FDCTRL_TDCOFF_Pos) @@ -95,8 +93,7 @@ #define MIN_TIME_SEGMENT1 (2U) #define MIN_TIME_SEGMENT2 (2U) -/* Define maximum CAN and CAN FD bit rate supported by FLEXCAN. */ -#define MAX_CANFD_BITRATE (8000000U) +/* Define maximum CAN bit rate supported by FLEXCAN. */ #define MAX_CAN_BITRATE (1000000U) #if (defined(FLEXCAN_HAS_ERRATA_9595) && FLEXCAN_HAS_ERRATA_9595) @@ -392,102 +389,6 @@ void FLEXCAN_Init(FLEXCAN_TypeDef *flex_can, const flexcan_config_t *pConfig) FLEXCAN_SetBaudRate(flex_can, pConfig->timingConfig); } -/** - * @brief Initializes a FlexCAN FD instance. - * - * This function initializes the FlexCAN module with user-defined settings. - * This example shows how to set up the flexcan_config_t parameters and how - * to call the FLEXCAN_FDInit function by passing in these parameters. - * code - * flexcan_config_t flexcanConfig; - * flexcanConfig.clkSrc = kFLEXCAN_ClkSrc0; - * flexcanConfig.baudRate = 1000000U; - * flexcanConfig.baudRateFD = 2000000U; - * flexcanConfig.maxMbNum = 16; - * flexcanConfig.enableLoopBack = false; - * flexcanConfig.enableSelfWakeup = false; - * flexcanConfig.enableIndividMask = false; - * flexcanConfig.disableSelfReception = false; - * flexcanConfig.enableListenOnlyMode = false; - * flexcanConfig.enableDoze = false; - * flexcanConfig.timingConfig = timingConfig; - * FLEXCAN_FDInit(CAN0, &flexcanConfig, kFLEXCAN_16BperMB, false); - * endcode - * - * @param flex_can FlexCAN peripheral base address. - * @param pConfig Pointer to the user-defined configuration structure. - * @param dataSize FlexCAN FD frame payload size. - * @param brs If bitrate switch is enabled in FD mode. - */ -void FLEXCAN_FDInit(FLEXCAN_TypeDef *flex_can, const flexcan_config_t *pConfig, flexcan_mb_size_t dataSize, FunctionalState brs) -{ - uint32_t fdctrl = 0U; - - /* Extra bitrate setting for CANFD. */ - FLEXCAN_SetFDBaudRate(flex_can, pConfig->timingConfig); - - /* read FDCTRL register. */ - fdctrl = flex_can->FDCTRL; - - /* Enable FD operation and set bitrate switch. */ - if (brs) - { - fdctrl |= FLEXCAN_FDCTRL_FDRATE_Msk; - } - else - { - fdctrl &= ~FLEXCAN_FDCTRL_FDRATE_Msk; - } - -// /* Before use "|=" operation for multi-bits field, CPU should clean previous Setting. */ -// fdctrl = (fdctrl & ~FLEXCAN_FDCTRL_MBDSR0_Msk) | (dataSize << FLEXCAN_FDCTRL_MBDSR0_Pos); - -// /* Enter Freeze Mode. */ -// FLEXCAN_EnterFreezeMode(flex_can); - -// /* Enable CAN FD operation. */ -// flex_can->MCR |= FLEXCAN_MCR_FDEN_Msk; - -// /* Clear SMP bit when CAN FD is enabled (CAN FD only can use one regular sample point plus one optional secondary -// * sampling point). */ -// flex_can->CTRL1 &= ~FLEXCAN_CTRL1_SMP_Msk; - - if (brs && !(pConfig->enableLoopBack)) - { - /* The TDC offset should be configured as shown in this equation : offset = PSEG1 + PROPSEG + 2 */ - if (((uint32_t)pConfig->timingConfig.fphaseSeg1 + pConfig->timingConfig.fpropSeg + 2U) < MAX_TDCOFF) - { - fdctrl = (fdctrl & ~FLEXCAN_FDCTRL_TDCOFF_Msk) | (((uint32_t)pConfig->timingConfig.fphaseSeg1 + - pConfig->timingConfig.fpropSeg + 2U) << FLEXCAN_FDCTRL_TDCOFF_Pos); - } - else - { - fdctrl = (fdctrl & ~FLEXCAN_FDCTRL_TDCOFF_Msk) | (MAX_TDCOFF << FLEXCAN_FDCTRL_TDCOFF_Pos); - } - - /* Enable the Transceiver Delay Compensation */ - fdctrl = (fdctrl & ~FLEXCAN_FDCTRL_TDCEN_Msk) | (1 << FLEXCAN_FDCTRL_TDCEN_Pos); - } - - /* Before use "|=" operation for multi-bits field, CPU should clean previous Setting. */ - fdctrl = (fdctrl & ~FLEXCAN_FDCTRL_MBDSR0_Msk) | (dataSize << FLEXCAN_FDCTRL_MBDSR0_Pos); - - /* Enter Freeze Mode. */ - FLEXCAN_EnterFreezeMode(flex_can); - - /* Enable CAN FD operation. */ - flex_can->MCR |= FLEXCAN_MCR_FDEN_Msk; - - /* update the FDCTL register. */ - flex_can->FDCTRL = fdctrl; - - /* Enable CAN FD ISO mode by default. */ - flex_can->CTRL2 |= FLEXCAN_CTRL2_ISOCANFDEN_Msk; - - /* Exit Freeze Mode. */ - FLEXCAN_ExitFreezeMode(flex_can); -} - /** * @brief De-initializes a FlexCAN instance. * @@ -512,7 +413,6 @@ void FLEXCAN_Deinit(FLEXCAN_TypeDef *flex_can) * values are as follows. * flexcanConfig->clkSrc = Enum_Flexcan_ClkSrc0; * flexcanConfig->baudRate = 1000000U; - * flexcanConfig->baudRateFD = 2000000U; * flexcanConfig->maxMbNum = 16; * flexcanConfig->enableLoopBack = false; * flexcanConfig->enableSelfWakeup = false; @@ -533,8 +433,6 @@ void FLEXCAN_GetDefaultConfig(flexcan_config_t *pConfig) pConfig->clkSrc = Enum_Flexcan_ClkSrc0; pConfig->baudRate = 1000000U; /* FlexCAN baud rate. */ - pConfig->baudRateFD = 2000000U; /* FlexCAN FD baud rate. */ - pConfig->maxMbNum = 16; pConfig->enableLoopBack = false; pConfig->enableTimerSync = true; @@ -588,49 +486,6 @@ void FLEXCAN_SetTimingConfig(FLEXCAN_TypeDef *flex_can, const flexcan_timing_con FLEXCAN_ExitFreezeMode(flex_can); } -/** - * brief Sets the FlexCAN FD protocol timing characteristic. - * - * This function gives user settings to CAN bus timing characteristic. - * The function is for an experienced user. For less experienced users, call - * the FLEXCAN_FDInit() and fill the baud rate field with a desired value. - * This provides the default timing characteristics to the module. - * - * Note that calling FLEXCAN_SetFDTimingConfig() overrides the baud rate set - * in FLEXCAN_FDInit(). - * - * param flex_can FlexCAN peripheral base address. - * param pConfig Pointer to the timing configuration structure. - */ -void FLEXCAN_SetFDTimingConfig(FLEXCAN_TypeDef *flex_can, const flexcan_timing_config_t *pConfig) -{ - /* Enter Freeze Mode. */ - FLEXCAN_EnterFreezeMode(flex_can); - - flex_can->CBT |= ((uint32_t)1 << FLEXCAN_CBT_BTF_Pos); - - /* Cleaning previous Timing Setting. */ - flex_can->CBT &= ~(FLEXCAN_CBT_EPRESDIV_Msk | FLEXCAN_CBT_ERJW_Msk | FLEXCAN_CBT_EPSEG1_Msk | FLEXCAN_CBT_EPSEG2_Msk | - FLEXCAN_CBT_EPROPSEG_Msk); - - /* Updating Timing Setting according to configuration structure. */ - flex_can->CBT |= ((pConfig->preDivider << FLEXCAN_CBT_EPRESDIV_Pos) | (pConfig->rJumpwidth << FLEXCAN_CBT_ERJW_Pos) | - (pConfig->phaseSeg1 << FLEXCAN_CBT_EPSEG1_Pos) | (pConfig->phaseSeg2 << FLEXCAN_CBT_EPSEG2_Pos) | - (pConfig->propSeg << FLEXCAN_CBT_EPROPSEG_Pos)); - - /* Cleaning previous Timing Setting. */ - flex_can->FDCBT &= ~(FLEXCAN_FDCBT_FPRESDIV_Msk | FLEXCAN_FDCBT_FRJW_Msk | FLEXCAN_FDCBT_FPSEG1_Msk | FLEXCAN_FDCBT_FPSEG2_Msk | - FLEXCAN_FDCBT_FPROPSEG_Msk); - - /* Updating Timing Setting according to configuration structure. */ - flex_can->FDCBT |= ((pConfig->fpreDivider << FLEXCAN_FDCBT_FPRESDIV_Pos) | (pConfig->frJumpwidth << FLEXCAN_FDCBT_FRJW_Pos) | - (pConfig->fphaseSeg1 << FLEXCAN_FDCBT_FPSEG1_Pos) | (pConfig->fphaseSeg2 << FLEXCAN_FDCBT_FPSEG2_Pos) | - (pConfig->fpropSeg << FLEXCAN_FDCBT_FPROPSEG_Pos)); - - /* Exit Freeze Mode. */ - FLEXCAN_ExitFreezeMode(flex_can); -} - /** * @brief Sets the FlexCAN receive message buffer global mask. * @@ -850,415 +705,6 @@ ErrorStatus FLEXCAN_CalculateImprovedTimingValues(uint32_t baudRate, uint32_t so return (fgRet); } -/*! - * brief Get Mailbox offset number by dword. - * - * This function gets the offset number of the specified mailbox. - * Mailbox is not consecutive between memory regions when payload is not 8 bytes - * so need to calculate the specified mailbox address. - * For example, in the first memory region, MB[0].CS address is 0x4002_4080. For 32 bytes - * payload frame, the second mailbox is ((1/12)*512 + 1%12*40)/4 = 10, meaning 10 dword - * after the 0x4002_4080, which is actually the address of mailbox MB[1].CS. - * - * param base FlexCAN peripheral base address. - * param mbIdx Mailbox index. - */ -uint32_t FLEXCAN_GetFDMailboxOffset(FLEXCAN_TypeDef *flex_can, uint8_t mbIdx) -{ - uint32_t offset = 0; - uint32_t dataSize = (flex_can->FDCTRL & FLEXCAN_FDCTRL_MBDSR0_Msk) >> FLEXCAN_FDCTRL_MBDSR0_Pos; - - switch (dataSize) - { - case (uint32_t)FLEXCAN_8BperMB: - offset = (((uint32_t)mbIdx / 32U) * 512U + ((uint32_t)mbIdx % 32U) * 16U); - break; - - case (uint32_t)FLEXCAN_16BperMB: - offset = (((uint32_t)mbIdx / 21U) * 512U + ((uint32_t)mbIdx % 21U) * 24U); - break; - - case (uint32_t)FLEXCAN_32BperMB: - offset = (((uint32_t)mbIdx / 12U) * 512U + ((uint32_t)mbIdx % 12U) * 40U); - break; - - case (uint32_t)FLEXCAN_64BperMB: - offset = (((uint32_t)mbIdx / 7U) * 512U + ((uint32_t)mbIdx % 7U) * 72U); - break; - - default: - /* All the cases have been listed above, the default clause should not be reached. */ - break; - } - - /* To get the dword aligned offset, need to divide by 4. */ - offset = offset / 4U; - return (offset); -} - -/** - * @brief Calculates the segment values for a single bit time for CANFD bus control baud Rate - * - * @param baudRate The canfd bus control speed in bps - * @param tqNum Number of time quanta per bit - * @param pTimingConfig Pointer to the FlexCAN timing configuration structure. - * - * @return TRUE if Calculates the segment success, FALSE if Calculates the segment success - */ -static ErrorStatus FLEXCAN_FDGetSegments(uint32_t baudRate, uint32_t tqNum, flexcan_timing_config_t *pTimingConfig) -{ - uint32_t ideal_sp; - uint32_t p1; - ErrorStatus fgRet = ERROR; - - /* Get ideal sample point. */ - if (baudRate >= 1000000U) - { - ideal_sp = IDEAL_SP_LOW; - } - else if (baudRate >= 800000U) - { - ideal_sp = IDEAL_SP_MID; - } - else - { - ideal_sp = IDEAL_SP_HIGH; - } - - /* distribute time quanta. */ - p1 = tqNum * (uint32_t)ideal_sp; - pTimingConfig->propSeg = (uint8_t)(p1 / (uint32_t)IDEAL_SP_FACTOR - 3U); - - if (pTimingConfig->propSeg <= (MAX_EPSEG1 + MAX_EPROPSEG)) - { - if (pTimingConfig->propSeg > MAX_EPROPSEG) - { - pTimingConfig->phaseSeg1 = pTimingConfig->propSeg - MAX_EPROPSEG; - pTimingConfig->propSeg = MAX_EPROPSEG; - } - else - { - pTimingConfig->phaseSeg1 = 0; - } - - if (pTimingConfig->phaseSeg1 <= MAX_EPSEG1) - { - /* The value of prog Seg should be not larger than tqNum -4U. */ - if ((pTimingConfig->propSeg + pTimingConfig->phaseSeg1) < ((uint8_t)tqNum - 4U)) - { - pTimingConfig->phaseSeg2 = (uint8_t)tqNum - (pTimingConfig->phaseSeg1 + pTimingConfig->propSeg + 4U); - - if (pTimingConfig->phaseSeg2 <= MAX_EPSEG2) - { - if ((pTimingConfig->phaseSeg1 < pTimingConfig->phaseSeg2) && (pTimingConfig->propSeg > (pTimingConfig->phaseSeg2 - pTimingConfig->phaseSeg1))) - { - pTimingConfig->propSeg -= (pTimingConfig->phaseSeg2 - pTimingConfig->phaseSeg1); - pTimingConfig->phaseSeg1 = pTimingConfig->phaseSeg2; - } - - /* subtract one TQ for sync seg. */ - /* sjw is 20% of total TQ, rounded to nearest int. */ - pTimingConfig->rJumpwidth = ((uint8_t)tqNum + 4U) / 5U - 1U; - - /* The max tqNum for CBT will reach to 129, ERJW would not be larger than 26. */ - /* Considering that max ERJW is 31, rJumpwidth will always be smaller than MAX_ERJW. */ - if (pTimingConfig->rJumpwidth > MAX_ERJW) - { - pTimingConfig->rJumpwidth = MAX_ERJW; - } - - fgRet = SUCCESS; - } - } - } - } - - return (fgRet); -} - -/** - * @brief Calculates the segment values for a single bit time for CANFD bus data baud Rate - * - * @param baudRatebrs The canfd bus data speed in bps - * @param tqNum Number of time quanta per bit - * @param pTimingConfig Pointer to the FlexCAN timing configuration structure. - * - * @return SUCCESS if Calculates the segment success, ERROR if Calculates the segment success - */ -static ErrorStatus FLEXCAN_FDGetSegmentswithBRS(uint32_t baudRatebrs, uint32_t tqNum, flexcan_timing_config_t *pTimingConfig) -{ - uint32_t ideal_sp; - uint32_t p1; - ErrorStatus fgRet = ERROR; - - /* get ideal sample point. */ - if (baudRatebrs >= 1000000U) - { - ideal_sp = IDEAL_SP_LOW; - } - else if (baudRatebrs >= 800000U) - { - ideal_sp = IDEAL_SP_MID; - } - else - { - ideal_sp = IDEAL_SP_HIGH; - } - - /* distribute time quanta. */ - p1 = tqNum * (uint32_t)ideal_sp; - pTimingConfig->fpropSeg = (uint8_t)(p1 / (uint32_t)IDEAL_SP_FACTOR - 2U); - - if (pTimingConfig->fpropSeg <= (MAX_FPSEG1 + MAX_FPROPSEG)) - { - if (pTimingConfig->fpropSeg > MAX_FPROPSEG) - { - pTimingConfig->fphaseSeg1 = pTimingConfig->fpropSeg - MAX_FPROPSEG; - pTimingConfig->fpropSeg = MAX_FPROPSEG; - } - else - { - pTimingConfig->fphaseSeg1 = 0; - } - - if (pTimingConfig->fphaseSeg1 <= MAX_PSEG1) - { - if ((pTimingConfig->fpropSeg + pTimingConfig->fphaseSeg1) < ((uint8_t)tqNum - 3U)) - { - pTimingConfig->fphaseSeg2 = (uint8_t)tqNum - (pTimingConfig->fphaseSeg1 + pTimingConfig->fpropSeg + 3U); - - if (pTimingConfig->fphaseSeg2 <= MAX_PSEG2) - { - if ((pTimingConfig->fphaseSeg1 < pTimingConfig->fphaseSeg2) && (pTimingConfig->fpropSeg > (pTimingConfig->fphaseSeg2 - pTimingConfig->fphaseSeg1))) - { - pTimingConfig->fpropSeg -= (pTimingConfig->fphaseSeg2 - pTimingConfig->fphaseSeg1); - pTimingConfig->fphaseSeg1 = pTimingConfig->fphaseSeg2; - } - - /* subtract one TQ for sync seg. */ - /* sjw is 20% of total TQ, rounded to nearest int. */ - pTimingConfig->frJumpwidth = ((uint8_t)tqNum + 4U) / 5U - 1U; - - if (pTimingConfig->frJumpwidth > MAX_FRJW) - { - pTimingConfig->frJumpwidth = MAX_FRJW; - } - - fgRet = SUCCESS; - } - } - } - } - - return (fgRet); -} - -/** - * @brief Calculates the improved timing values by specific baudrates for CAN by CBT register - * - * @param baudRate The classical CAN speed in bps defined by user - * @param sourceClock_Hz The Source clock data speed in bps. Zero to disable baudrate switching - * @param pTimingConfig Pointer to the FlexCAN timing configuration structure. - * - * @return SUCCESS if timing configuration found, ERROR if failed to find configuration - */ -static ErrorStatus FLEXCAN_CalculateImprovedTimingValuesByCBT(uint32_t baudRate, uint32_t sourceClock_Hz, flexcan_timing_config_t *pTimingConfig) -{ - uint32_t clk; /* the clock is tqNumb x baudRateFD. */ - uint32_t tqNum; /* Numbers of TQ. */ - ErrorStatus fgRet = ERROR; - - tqNum = CBT_MAX_TIME_QUANTA; - - /* Auto Improved Protocal timing. */ - do - { - clk = baudRate * tqNum; - - if (clk > sourceClock_Hz) - { - continue; /* tqNum too large, clk has been exceed sourceClock_Hz. */ - } - - if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) - { - continue; /* Non-supporting: the frequency of clock source is not divisible by target baud rate, the user - should change a divisible baud rate. */ - } - - /* Make sure the new calculated divider value is greater than the previous one. */ - if (pTimingConfig->preDivider > ((uint16_t)(sourceClock_Hz / clk) - 1U)) - { - continue; - } - else - { - pTimingConfig->preDivider = (uint16_t)(sourceClock_Hz / clk) - 1U; - } - - /* To minimize errors when processing FD frames, try to calculate the same value for FPRESDIV and PRESDIV (in CBT). */ - if (pTimingConfig->preDivider != pTimingConfig->fpreDivider) - { - continue; - } - - if (pTimingConfig->preDivider > MAX_EPRESDIV) - { - break; /* The frequency of source clock is too large or the baud rate is too small, the pre-divider could - not handle it. */ - } - - /* Try to get the best timing configuration. */ - if (FLEXCAN_FDGetSegments(baudRate, tqNum, pTimingConfig)) - { - fgRet = SUCCESS; - break; - } - } - while(--tqNum >= CBT_MIN_TIME_QUANTA); - - return (fgRet); -} - -/** - * @brief Calculates the improved timing values by specific baudrates for CAN by FDCBT register - * - * @param baudRate The CANFD speed in bps defined by user - * @param sourceClock_Hz The Source clock data speed in bps. Zero to disable baudrate switching - * @param pTimingConfig Pointer to the FlexCAN timing configuration structure. - * - * @return SUCCESS if timing configuration found, ERROR if failed to find configuration - */ -static ErrorStatus FLEXCAN_CalculateImprovedTimingValuesByFDCBT(uint32_t baudRate, uint32_t sourceClock_Hz, flexcan_timing_config_t *pTimingConfig) -{ - uint32_t clk; /* the clock is tqNumb x baudRateFD. */ - uint32_t tqNum; /* Numbers of TQ. */ - ErrorStatus fgRet = ERROR; - - tqNum = FDCBT_MAX_TIME_QUANTA; - - /* Auto Improved Protocal timing. */ - do - { - clk = baudRate * tqNum; - - if (clk > sourceClock_Hz) - { - continue; /* tqNum too large, clk has been exceed sourceClock_Hz. */ - } - - if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) - { - continue; /* Non-supporting: the frequency of clock source is not divisible by target baud rate, the user - should change a divisible baud rate. */ - } - - /* Make sure the new calculated divider value is greater than the previous one. */ - if (pTimingConfig->fpreDivider > ((uint16_t)(sourceClock_Hz / clk) - 1U)) - { - continue; - } - else - { - pTimingConfig->fpreDivider = (uint16_t)(sourceClock_Hz / clk) - 1U; - } - - if (pTimingConfig->fpreDivider > MAX_FPRESDIV) - { - break; /* The frequency of source clock is too large or the baud rate is too small, the pre-divider could - not handle it. */ - } - - /* Try to get the best timing configuration. */ - if (FLEXCAN_FDGetSegmentswithBRS(baudRate, tqNum, pTimingConfig)) - { - fgRet = SUCCESS; - break; - } - } - while(--tqNum >= FDCBT_MIN_TIME_QUANTA); - - return (fgRet); -} - -/** - * @brief Calculates the improved timing values by specific baudrates for CANFD - * - * @param baudRate The CANFD bus control speed in bps defined by user - * @param baudRateFD The CANFD bus data speed in bps defined by user - * @param sourceClock_Hz The Source clock data speed in bps. Zero to disable baudrate switching - * @param pTimingConfig Pointer to the FlexCAN timing configuration structure. - * - * @return SUCCESS if timing configuration found, ERROR if failed to find configuration - */ -ErrorStatus FLEXCAN_FDCalculateImprovedTimingValues(uint32_t baudRate, uint32_t baudRateFD, uint32_t sourceClock_Hz, flexcan_timing_config_t *pTimingConfig) -{ - ErrorStatus fgRet = ERROR; - - pTimingConfig->preDivider = 0U; - pTimingConfig->fpreDivider = 0U; - - if (FLEXCAN_CalculateImprovedTimingValuesByFDCBT(baudRateFD, sourceClock_Hz, pTimingConfig)) - { - if (FLEXCAN_CalculateImprovedTimingValuesByCBT(baudRate, sourceClock_Hz, pTimingConfig)) - { - fgRet = SUCCESS; - } - } - - return (fgRet); -} - -/** - * brief Configures a FlexCAN transmit message buffer. - * - * This function aborts the previous transmission, cleans the Message Buffer, and - * configures it as a Transmit Message Buffer. - * - * param flex_can FlexCAN peripheral base address. - * param mbIdx The Message Buffer index. - * param enable Enable/disable Tx Message Buffer. - * - ENABLE: Enable Tx Message Buffer. - * - DISABLE: Disable Tx Message Buffer. - */ -void FLEXCAN_FDTxMbConfig(FLEXCAN_TypeDef *flex_can, uint8_t mbIdx, FunctionalState enable) -{ - uint8_t cnt = 0; - uint8_t payload_dword = 1; - uint32_t dataSize; - - dataSize = (flex_can->FDCTRL & FLEXCAN_FDCTRL_MBDSR0_Msk) >> FLEXCAN_FDCTRL_MBDSR0_Pos; - - volatile uint32_t *mbAddr = &(flex_can->MB[0].CS); - uint32_t offset = FLEXCAN_GetFDMailboxOffset(flex_can, mbIdx); - - /* Inactivate Message Buffer. */ - if (enable) - { - /* Inactivate by writing CS. */ - mbAddr[offset] = (Enum_Flexcan_TxMbInactive << FLEXCAN_CS_CODE_Pos); - } - else - { - mbAddr[offset] = 0x0; - } - - /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 - Bytes payload. */ - for (cnt = 0; cnt < (dataSize + 1U); cnt++) - { - payload_dword *= 2U; - } - - /* Clean ID. */ - mbAddr[offset + 1U] = 0x0U; - - /* Clean Message Buffer content, DWORD by DWORD. */ - for (cnt = 0; cnt < payload_dword; cnt++) - { - mbAddr[offset + 2U + cnt] = 0x0U; - } -} /** * @brief Configures a FlexCAN Receive Message Buffer. @@ -1306,65 +752,6 @@ void FLEXCAN_RxMbConfig(FLEXCAN_TypeDef *flex_can, uint8_t mbIdx, const flexcan_ } } -/** - * @brief Configures a FlexCAN Receive Message Buffer. - * - * This function cleans a FlexCAN build-in Message Buffer and configures it - * as a Receive Message Buffer. - * - * @param flex_can FlexCAN peripheral base address. - * @param mbIdx The Message Buffer index. - * @param pRxMbConfig Pointer to the FlexCAN Message Buffer configuration structure. - * @param enable Enable/disable Rx Message Buffer. - * - ENABLE: Enable Rx Message Buffer. - * - DISABLE: Disable Rx Message Buffer. - */ -void FLEXCAN_FDRxMbConfig(FLEXCAN_TypeDef *flex_can, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, FunctionalState state) -{ - uint32_t cs_temp = 0; - uint8_t cnt = 0; - volatile uint32_t *mbAddr = &(flex_can->MB[0].CS); - uint32_t offset = FLEXCAN_GetFDMailboxOffset(flex_can, mbIdx); - uint8_t payload_dword; - uint32_t dataSize = (flex_can->FDCTRL & FLEXCAN_FDCTRL_MBDSR0_Msk) >> FLEXCAN_FDCTRL_MBDSR0_Pos; - - /* Inactivate Message Buffer. */ - mbAddr[offset] = 0U; - - /* Clean Message Buffer content. */ - mbAddr[offset + 1U] = 0U; - /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 - Bytes payload. */ - payload_dword = (2U << dataSize); - - for (cnt = 0; cnt < payload_dword; cnt++) - { - mbAddr[offset + 2U + cnt] = 0x0; - } - - if (state) - { - /* Setup Message Buffer ID. */ - mbAddr[offset + 1U] = pRxMbConfig->id; - - /* Setup Message Buffer format. */ - if (Enum_Flexcan_FrameFormatExtend == pRxMbConfig->format) - { - cs_temp |= FLEXCAN_CS_IDE_Msk; - } - - /* Setup Message Buffer type. */ - if (Enum_Flexcan_FrameTypeRemote == pRxMbConfig->type) - { - cs_temp |= FLEXCAN_CS_RTR_Msk; - } - - /* Activate Rx Message Buffer. */ - cs_temp |= ((Enum_Flexcan_RxMbEmpty << FLEXCAN_CS_CODE_Pos) & FLEXCAN_CS_CODE_Msk); - mbAddr[offset] = cs_temp; - } -} - /** * @brief Configures the FlexCAN Rx FIFO. * @@ -1681,108 +1068,14 @@ int32_t FLEXCAN_WriteTxMb(FLEXCAN_TypeDef *flex_can, uint8_t mbIdx, const flexca #if (defined (FLEXCAN_HAS_ERRATA_5829) && FLEXCAN_HAS_ERRATA_5829) flex_can->MB[FLEXCAN_GetFirstValidMb(flex_can)].CS = (Enum_Flexcan_TxMbInactive << FLEXCAN_CS_CODE_Pos); - flex_can->MB[FLEXCAN_GetFirstValidMb(flex_can)].CS = (Enum_Flexcan_TxMbInactive << FLEXCAN_CS_CODE_Pos); -#endif - - status = Status_Flexcan_Success; - } - else - { - /* Tx Message Buffer is activated, return immediately. */ - status = Status_Flexcan_Fail; - } - - return (status); -} - -/*! - * @brief Writes a FlexCAN FD Message to the Transmit Message Buffer. - * - * This function writes a CAN FD Message to the specified Transmit Message Buffer - * and changes the Message Buffer state to start CAN FD Message transmit. After - * that the function returns immediately. - * - * @param flex_can FlexCAN peripheral base address. - * @param mbIdx The FlexCAN FD Message Buffer index. - * @param pTxFrame Pointer to CAN FD message frame to be sent. - * @retval Status_Success - Write Tx Message Buffer Successfully. - * @retval Status_Fail - Tx Message Buffer is currently in use. - */ -int32_t FLEXCAN_WriteFDTxMb(FLEXCAN_TypeDef *flex_can, uint8_t mbIdx, const flexcan_fd_frame_t *pTxFrame) -{ - int32_t status; - uint32_t cs_temp = 0; - uint8_t cnt = 0; - uint32_t can_cs = 0; - uint8_t payload_dword = 1; - uint32_t dataSize = (flex_can->FDCTRL & FLEXCAN_FDCTRL_MBDSR0_Msk) >> FLEXCAN_FDCTRL_MBDSR0_Pos; - -#if (defined (FLEXCAN_HAS_ERRATA_5829) && FLEXCAN_HAS_ERRATA_5829) - uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(flex_can, FLEXCAN_GetFirstValidMb(flex_can)); -#endif - volatile uint32_t *mbAddr = &(flex_can->MB[0].CS); - uint32_t offset = FLEXCAN_GetFDMailboxOffset(flex_can, mbIdx); - -#if (defined (FLEXCAN_HAS_ERRATA_6032) && FLEXCAN_HAS_ERRATA_6032) - FLEXCAN_ERRATA_6032(flex_can, &(mbAddr[offset])); -#endif - - can_cs = mbAddr[offset]; - - /* Check if Message Buffer is available. */ - if ((Enum_Flexcan_TxMbDataOrRemote << FLEXCAN_CS_CODE_Pos) != (can_cs & FLEXCAN_CS_CODE_Msk)) - { - /* Inactive Tx Message Buffer and Fill Message ID field. */ - mbAddr[offset] = (can_cs & ~FLEXCAN_CS_CODE_Msk) | (Enum_Flexcan_TxMbInactive << FLEXCAN_CS_CODE_Pos); - - /* Fill Message Format field. */ - if ((uint32_t)Enum_Flexcan_FrameFormatExtend == pTxFrame->format) - { - mbAddr[offset + 1U] = pTxFrame->id; - cs_temp |= FLEXCAN_CS_SRR_Msk | FLEXCAN_CS_IDE_Msk; - } - else - { - mbAddr[offset + 1U] = (pTxFrame->id << FLEXCAN_ID_STD_Pos); - cs_temp &= ~(FLEXCAN_CS_SRR_Msk | FLEXCAN_CS_IDE_Msk); - } - - /* Fill Message Type field. */ - if ((uint32_t)Enum_Flexcan_FrameTypeRemote == pTxFrame->type) - { - cs_temp |= FLEXCAN_CS_RTR_Msk; - } - else - { - cs_temp &= ~FLEXCAN_CS_RTR_Msk; - } - - cs_temp |= (Enum_Flexcan_TxMbDataOrRemote << FLEXCAN_CS_CODE_Pos) | (pTxFrame->length << FLEXCAN_CS_DLC_Pos) | (pTxFrame->edl << FLEXCAN_CS_EDL_Pos) | (pTxFrame->brs << FLEXCAN_CS_BRS_Pos); - - /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 - Bytes payload. */ - for (cnt = 0; cnt < (dataSize + 1U); cnt++) - { - payload_dword *= 2U; - } - - /* Load Message Payload and Activate Tx Message Buffer. */ - for (cnt = 0; cnt < payload_dword; cnt++) - { - mbAddr[offset + 2U + cnt] = pTxFrame->dataWord[cnt]; - } - - mbAddr[offset] = cs_temp; - -#if (defined (FLEXCAN_HAS_ERRATA_5829) && FLEXCAN_HAS_ERRATA_5829) - mbAddr[availoffset] = (Enum_Flexcan_TxMbInactive << FLEXCAN_CS_CODE_Pos); - mbAddr[availoffset] = (Enum_Flexcan_TxMbInactive << FLEXCAN_CS_CODE_Pos); + flex_can->MB[FLEXCAN_GetFirstValidMb(flex_can)].CS = (Enum_Flexcan_TxMbInactive << FLEXCAN_CS_CODE_Pos); #endif + status = Status_Flexcan_Success; } else { - /* Tx Message Buffer is activated, return immediately. */ + /* Tx Message Buffer is activated, return immediately. */ status = Status_Flexcan_Fail; } @@ -1862,99 +1155,6 @@ int32_t FLEXCAN_ReadRxMb(FLEXCAN_TypeDef *flex_can, uint8_t mbIdx, flexcan_frame return (status); } -/** - * @brief Reads a FlexCAN FD Message from Receive Message Buffer. - * - * This function reads a CAN FD message from a specified Receive Message Buffer. - * The function fills a receive CAN FD message frame structure with - * just received data and activates the Message Buffer again. - * The function returns immediately. - * - * @param flex_can FlexCAN peripheral base address. - * @param mbIdx The FlexCAN FD Message Buffer index. - * @param pRxFrame Pointer to CAN FD message frame structure for reception. - * @retval Status_Success - Rx Message Buffer is full and has been read successfully. - * @retval Status_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. - * @retval Status_Fail - Rx Message Buffer is empty. - */ -int32_t FLEXCAN_ReadFDRxMb(FLEXCAN_TypeDef *flex_can, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame) -{ - int32_t status; - uint32_t cs_temp; - uint8_t rx_code; - uint8_t cnt = 0; - uint32_t can_id = 0; - uint32_t dataSize; - - dataSize = (flex_can->FDCTRL & FLEXCAN_FDCTRL_MBDSR0_Msk) >> FLEXCAN_FDCTRL_MBDSR0_Pos; - - uint8_t payload_dword = 1; - volatile uint32_t *mbAddr = &(flex_can->MB[0].CS); - uint32_t offset = FLEXCAN_GetFDMailboxOffset(flex_can, mbIdx); - - /* Read CS field of Rx Message Buffer to lock Message Buffer. */ - cs_temp = mbAddr[offset]; - can_id = mbAddr[offset + 1U]; - - /* Get Rx Message Buffer Code field. */ - rx_code = (uint8_t)((cs_temp & FLEXCAN_CS_CODE_Msk) >> FLEXCAN_CS_CODE_Pos); - - /* Check to see if Rx Message Buffer is full. */ - if (((uint8_t)Enum_Flexcan_RxMbFull == rx_code) || ((uint8_t)Enum_Flexcan_RxMbOverrun == rx_code)) - { - /* Store Message ID. */ - pRxFrame->id = can_id & (FLEXCAN_ID_EXT_Msk | FLEXCAN_ID_STD_Msk); - - /* Get the message ID and format. */ - pRxFrame->format = (cs_temp & FLEXCAN_CS_IDE_Msk) != 0U ? (uint8_t)Enum_Flexcan_FrameFormatExtend : - (uint8_t)Enum_Flexcan_FrameFormatStandard; - - /* Get the message type. */ - pRxFrame->type = - (cs_temp & FLEXCAN_CS_RTR_Msk) != 0U ? (uint8_t)Enum_Flexcan_FrameTypeRemote : (uint8_t)Enum_Flexcan_FrameTypeData; - - /* Get the message length. */ - pRxFrame->length = (uint8_t)((cs_temp & FLEXCAN_CS_DLC_Msk) >> FLEXCAN_CS_DLC_Pos); - - /* Get the time stamp. */ - pRxFrame->timestamp = (uint16_t)((cs_temp & FLEXCAN_CS_TIME_STAMP_Msk) >> FLEXCAN_CS_TIME_STAMP_Pos); - - /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 - Bytes payload. */ - for (cnt = 0; cnt < (dataSize + 1U); cnt++) - { - payload_dword *= 2U; - } - - /* Store Message Payload. */ - for (cnt = 0; cnt < payload_dword; cnt++) - { - pRxFrame->dataWord[cnt] = mbAddr[offset + 2U + cnt]; - } - - /* Read free-running timer to unlock Rx Message Buffer. */ - (void)flex_can->TIMER; - - if ((uint32_t)Enum_Flexcan_RxMbFull == rx_code) - { - status = Status_Flexcan_Success; - } - else - { - status = Status_Flexcan_RxOverflow; - } - } - else - { - /* Read free-running timer to unlock Rx Message Buffer. */ - (void)flex_can->TIMER; - - status = Status_Flexcan_Fail; - } - - return (status); -} - /** * @brief Reads a FlexCAN Message from Rx FIFO. * @@ -2083,78 +1283,6 @@ int32_t FLEXCAN_TransferReceiveBlocking(FLEXCAN_TypeDef *flex_can, uint8_t mbIdx return (FLEXCAN_ReadRxMb(flex_can, mbIdx, pRxFrame)); } -/** - * @brief Performs a polling send transaction on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * @param flex_can FlexCAN peripheral base pointer. - * @param mbIdx The FlexCAN FD Message Buffer index. - * @param pTxFrame Pointer to CAN FD message frame to be sent. - * @retval Status_Success - Write Tx Message Buffer Successfully. - * @retval Status_Fail - Tx Message Buffer is currently in use. - */ -int32_t FLEXCAN_TransferFDSendBlocking(FLEXCAN_TypeDef *flex_can, uint8_t mbIdx, flexcan_fd_frame_t *pTxFrame) -{ - int32_t status; - - /* Write Tx Message Buffer to initiate a data sending. */ - if (Status_Flexcan_Success == FLEXCAN_WriteFDTxMb(flex_can, mbIdx, (const flexcan_fd_frame_t *)(uint32_t)pTxFrame)) - { - /* Wait until CAN Message send out. */ - uint32_t uint32_tflag = 1; - - while (0U == FLEXCAN_GetMbStatusFlags(flex_can, uint32_tflag << mbIdx)) - { - } - - /* Clean Tx Message Buffer Flag. */ - FLEXCAN_ClearMbStatusFlags(flex_can, uint32_tflag << mbIdx); - - /*After TX MB tranfered success, update the Timestamp from flex_can->MB[offset for CANFD].CS register*/ - volatile uint32_t *mbAddr = &(flex_can->MB[0].CS); - uint32_t offset = FLEXCAN_GetFDMailboxOffset(flex_can, mbIdx); - - pTxFrame->timestamp = (uint16_t)((mbAddr[offset] & FLEXCAN_CS_TIME_STAMP_Msk) >> FLEXCAN_CS_TIME_STAMP_Pos); - - status = Status_Flexcan_Success; - } - else - { - status = Status_Flexcan_Fail; - } - - return (status); -} - -/** - * @brief Performs a polling receive transaction on the CAN bus. - * - * Note that a transfer handle does not need to be created before calling this API. - * - * @param flex_can FlexCAN peripheral base pointer. - * @param mbIdx The FlexCAN FD Message Buffer index. - * @param pRxFrame Pointer to CAN FD message frame structure for reception. - * @retval Status_Success - Rx Message Buffer is full and has been read successfully. - * @retval Status_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. - * @retval Status_Fail - Rx Message Buffer is empty. - */ -int32_t FLEXCAN_TransferFDReceiveBlocking(FLEXCAN_TypeDef *flex_can, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame) -{ - /* Wait until Rx Message Buffer non-empty. */ - uint32_t uint32_tflag = 1; - - while (0U == FLEXCAN_GetMbStatusFlags(flex_can, uint32_tflag << mbIdx)) - { - } - - /* Clean Rx Message Buffer Flag. */ - FLEXCAN_ClearMbStatusFlags(flex_can, uint32_tflag << mbIdx); - - /* Read Received CAN Message. */ - return (FLEXCAN_ReadFDRxMb(flex_can, mbIdx, pRxFrame)); -} - /** * @brief Performs a polling receive transaction from Rx FIFO on the CAN bus. * @@ -2319,98 +1447,6 @@ int32_t FLEXCAN_TransferReceiveNonBlocking(FLEXCAN_TypeDef *flex_can, flexcan_ha return (status); } -/** - * @brief Sends a message using IRQ. - * - * This function sends a message using IRQ. This is a non-blocking function, which returns - * right away. When messages have been sent out, the send callback function is called. - * - * @param flex_can FlexCAN peripheral base address. - * @param handle FlexCAN handle pointer. - * @param pMbXfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. - * @retval kStatus_Success Start Tx Message Buffer sending process successfully. - * @retval kStatus_Fail Write Tx Message Buffer failed. - * @retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. - */ -int32_t FLEXCAN_TransferFDSendNonBlocking(FLEXCAN_TypeDef *flex_can, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer) -{ - int32_t status; - - /* Check if Message Buffer is idle. */ - if ((uint8_t)Enum_Flexcan_StateIdle == handle->mbState[pMbXfer->mbIdx]) - { - /* Distinguish transmit type. */ - if ((uint32_t)Enum_Flexcan_FrameTypeRemote == pMbXfer->framefd->type) - { - handle->mbState[pMbXfer->mbIdx] = (uint8_t)Enum_Flexcan_StateTxRemote; - } - else - { - handle->mbState[pMbXfer->mbIdx] = (uint8_t)Enum_Flexcan_StateTxData; - } - - if (Status_Flexcan_Success == FLEXCAN_WriteFDTxMb(flex_can, pMbXfer->mbIdx, (const flexcan_fd_frame_t *)(uint32_t)pMbXfer->framefd)) - { - /* Enable Message Buffer Interrupt. */ - uint32_t uint32_tmask = 1; - - FLEXCAN_EnableMbInterrupts(flex_can, uint32_tmask << pMbXfer->mbIdx); - - status = Status_Flexcan_Success; - } - else - { - handle->mbState[pMbXfer->mbIdx] = (uint8_t)Enum_Flexcan_StateIdle; - status = Status_Flexcan_Fail; - } - } - else - { - status = Status_Flexcan_TxBusy; - } - - return (status); -} - -/** - * @brief Receives a message using IRQ. - * - * This function receives a message using IRQ. This is non-blocking function, which returns - * right away. When the message has been received, the receive callback function is called. - * - * @param flex_can FlexCAN peripheral base address. - * @param handle FlexCAN handle pointer. - * @param pMbXfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. - * @retval kStatus_Success - Start Rx Message Buffer receiving process successfully. - * @retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. - */ -int32_t FLEXCAN_TransferFDReceiveNonBlocking(FLEXCAN_TypeDef *flex_can, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer) -{ - int32_t status; - - /* Check if Message Buffer is idle. */ - if ((uint8_t)Enum_Flexcan_StateIdle == handle->mbState[pMbXfer->mbIdx]) - { - handle->mbState[pMbXfer->mbIdx] = (uint8_t)Enum_Flexcan_StateRxData; - - /* Register Message Buffer. */ - handle->mbFDFrameBuf[pMbXfer->mbIdx] = pMbXfer->framefd; - -/* Enable Message Buffer Interrupt. */ - uint32_t uint32_tmask = 1; - - FLEXCAN_EnableMbInterrupts(flex_can, uint32_tmask << pMbXfer->mbIdx); - - status = Status_Flexcan_Success; - } - else - { - status = Status_Flexcan_RxBusy; - } - - return (status); -} - /** * @brief Receives a message from Rx FIFO using IRQ. * @@ -2476,59 +1512,6 @@ void FLEXCAN_TransferAbortSend(FLEXCAN_TypeDef *flex_can, flexcan_handle_t *hand handle->mbState[mbIdx] = (uint8_t)Enum_Flexcan_StateIdle; } -/*! - * @brief Aborts the interrupt driven message send process. - * - * This function aborts the interrupt driven message send process. - * - * @param flex_can FlexCAN peripheral base address. - * @param handle FlexCAN handle pointer. - * @param mbIdx The FlexCAN FD Message Buffer index. - */ -void FLEXCAN_TransferFDAbortSend(FLEXCAN_TypeDef *flex_can, flexcan_handle_t *handle, uint8_t mbIdx) -{ - volatile uint32_t *mbAddr; - uint32_t offset; - uint16_t timestamp; - -/* Disable Message Buffer Interrupt. */ - uint32_t uint32_tmask = 1; - - FLEXCAN_DisableMbInterrupts(flex_can, uint32_tmask << mbIdx); - - /* Update the TX frame 's time stamp by flex_can->MB[offset for CANFD].CS. */ - mbAddr = &(flex_can->MB[0].CS); - offset = FLEXCAN_GetFDMailboxOffset(flex_can, mbIdx); - timestamp = (uint16_t)((mbAddr[offset] & FLEXCAN_CS_TIME_STAMP_Msk) >> FLEXCAN_CS_TIME_STAMP_Pos); - handle->timestamp[mbIdx] = timestamp; - - /* Clean Message Buffer. */ - FLEXCAN_FDTxMbConfig(flex_can, mbIdx, ENABLE); - - handle->mbState[mbIdx] = (uint8_t)Enum_Flexcan_StateIdle; -} - -/** - * @brief Aborts the interrupt driven message receive process. - * - * This function aborts the interrupt driven message receive process. - * - * @param flex_can FlexCAN peripheral base address. - * @param handle FlexCAN handle pointer. - * @param mbIdx The FlexCAN FD Message Buffer index. - */ -void FLEXCAN_TransferFDAbortReceive(FLEXCAN_TypeDef *flex_can, flexcan_handle_t *handle, uint8_t mbIdx) -{ -/* Disable Message Buffer Interrupt. */ - uint32_t uint32_tmask = 1; - - FLEXCAN_DisableMbInterrupts(flex_can, uint32_tmask << mbIdx); - - /* Un-register handle. */ - handle->mbFDFrameBuf[mbIdx] = NULL; - handle->mbState[mbIdx] = (uint8_t)Enum_Flexcan_StateIdle; -} - /** * @brief Aborts the interrupt driven message receive process. * @@ -2696,77 +1679,31 @@ static uint32_t FLEXCAN_SubHandlerForDataTransfered(FLEXCAN_TypeDef *flex_can, f /* Solve Rx Data Frame. */ case (uint8_t)Enum_Flexcan_StateRxData: - if (0U != (flex_can->MCR & FLEXCAN_MCR_FDEN_Msk)) - { - status = FLEXCAN_ReadFDRxMb(flex_can, (uint8_t)result, handle->mbFDFrameBuf[result]); - - if (Status_Flexcan_Success == status) - { - /* Align the current index of RX MB timestamp to the timestamp array by handle. */ - handle->timestamp[result] = handle->mbFDFrameBuf[result]->timestamp; - status = Status_Flexcan_RxIdle; - } - } - else - { - status = FLEXCAN_ReadRxMb(flex_can, (uint8_t)result, handle->mbFrameBuf[result]); - - if (Status_Flexcan_Success == status) - { - /* Align the current index of RX MB timestamp to the timestamp array by handle. */ - handle->timestamp[result] = handle->mbFrameBuf[result]->timestamp; - status = Status_Flexcan_RxIdle; - } - } - - if (0U != (flex_can->MCR & FLEXCAN_MCR_FDEN_Msk)) - { - FLEXCAN_TransferFDAbortReceive(flex_can, handle, (uint8_t)result); - } - else - { - FLEXCAN_TransferAbortReceive(flex_can, handle, (uint8_t)result); + status = FLEXCAN_ReadRxMb(flex_can, (u8)result, handle->mbFrameBuf[result]); + if (Status_Flexcan_Success == status) { + // Align the current index of RX MB timestamp to the timestamp array by handle. + handle->timestamp[result] = handle->mbFrameBuf[result]->timestamp; + status = Status_Flexcan_RxIdle; } - + FLEXCAN_TransferAbortReceive(flex_can, handle, (u8)result); break; /* Sove Rx Remote Frame. User need to Read the frame in Mail box in time by Read from MB API. */ case (uint8_t)Enum_Flexcan_StateRxRemote: status = Status_Flexcan_RxRemote; - - if (0U != (flex_can->MCR & FLEXCAN_MCR_FDEN_Msk)) - { - FLEXCAN_TransferFDAbortReceive(flex_can, handle, (uint8_t)result); - } - else - { - FLEXCAN_TransferAbortReceive(flex_can, handle, (uint8_t)result); - } - + FLEXCAN_TransferAbortReceive(flex_can, handle, (u8)result); break; /* Solve Tx Data Frame. */ case (uint8_t)Enum_Flexcan_StateTxData: status = Status_Flexcan_TxIdle; - - if (0U != (flex_can->MCR & FLEXCAN_MCR_FDEN_Msk)) - { - FLEXCAN_TransferFDAbortSend(flex_can, handle, (uint8_t)result); - } - else - { - FLEXCAN_TransferAbortSend(flex_can, handle, (uint8_t)result); - } - + FLEXCAN_TransferAbortSend(flex_can, handle, (u8)result); break; /* Solve Tx Remote Frame. */ case (uint8_t)Enum_Flexcan_StateTxRemote: - handle->mbState[result] = (uint8_t)Enum_Flexcan_StateRxRemote; - status = Status_Flexcan_TxSwitchToRx; - { - FLEXCAN_TransferAbortSend(flex_can, handle, (uint8_t)result); - } + handle->mbState[result] = (u8)Enum_Flexcan_StateRxRemote; + status = Status_Flexcan_TxSwitchToRx; break; default: @@ -2837,12 +1774,6 @@ void FLEXCAN_SetBaudRate(FLEXCAN_TypeDef *flex_can, flexcan_timing_config_t timi FLEXCAN_SetTimingConfig(flex_can, (const flexcan_timing_config_t *)(uint32_t)&timingConfig); } -void FLEXCAN_SetFDBaudRate(FLEXCAN_TypeDef *flex_can, flexcan_timing_config_t timingConfig) -{ - /* Update actual timing characteristic. */ - FLEXCAN_SetFDTimingConfig(flex_can, (const flexcan_timing_config_t *)(uint32_t)&timingConfig); -} - /** * @} */ diff --git a/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_gpio.c b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_gpio.c index 28593964190..6f78b763e82 100644 --- a/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_gpio.c +++ b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_gpio.c @@ -326,6 +326,22 @@ void GPIO_PinAFConfig(GPIO_TypeDef *gpio, uint8_t pin, uint8_t alternate_functio *ptr = (*ptr & ~(0x0F << shift)) | (alternate_function << shift); } +/** + * @brief Configure the pull-up or pull-down of the GPIO port in open-drain output mode. + * @param gpio: to select the GPIO peripheral. + * @param pin: This parameter can be one of GPIO_Pin_x where x can be (0..15). + * @param od_mode: Specifies the pull-up and pull-down modes for the port. + * This parameter can be one of the following values: + * @arg GPIO_OD_NoPull + * @arg GPIO_OD_PullDown + * @arg GPIO_OD_PullUp + * @retval None. + */ +void GPIO_PinODConfig(GPIO_TypeDef *gpio, uint16_t pin, uint32_t od_mode) +{ + MODIFY_REG(gpio->DCR, GPIO_DCR_PX0_Msk << (pin * 2), od_mode << (pin * 2)); +} + /** * @} */ diff --git a/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_i2c.c b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_i2c.c index 13523270886..0a7a4936207 100644 --- a/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_i2c.c +++ b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_i2c.c @@ -439,8 +439,6 @@ void I2C_ClearFlag(I2C_TypeDef *i2c, uint32_t flag) { temp = i2c->GC; } - - temp += 1; } /** diff --git a/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_rcc.c b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_rcc.c index 58d3c2d630a..0ad53fa30bf 100644 --- a/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_rcc.c +++ b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_rcc.c @@ -654,7 +654,6 @@ void RCC_AHBPeriphClockCmd(uint32_t ahb_periph, FunctionalState state) * @arg RCC_APB2Periph_TIM1 * @arg RCC_APB2Periph_TIM8 * @arg RCC_APB2Periph_UART1 - * @arg RCC_APB2Periph_UART6 * @arg RCC_APB2Periph_ADC1 * @arg RCC_APB2Periph_ADC2 * @arg RCC_APB2Periph_SPI1 @@ -699,7 +698,6 @@ void RCC_APB2PeriphClockCmd(uint32_t apb2_periph, FunctionalState state) * @arg RCC_APB1Periph_BKP * @arg RCC_APB1Periph_PWRDBG * @arg RCC_APB1Periph_DAC - * @arg RCC_APB1Periph_UART7 * @param state: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None. @@ -749,7 +747,6 @@ void RCC_AHBPeriphResetCmd(uint32_t ahb_periph, FunctionalState state) * @arg RCC_APB2Periph_TIM1 * @arg RCC_APB2Periph_TIM8 * @arg RCC_APB2Periph_UART1 - * @arg RCC_APB2Periph_UART6 * @arg RCC_APB2Periph_ADC1 * @arg RCC_APB2Periph_ADC2 * @arg RCC_APB2Periph_SPI1 @@ -794,7 +791,6 @@ void RCC_APB2PeriphResetCmd(uint32_t apb2_periph, FunctionalState state) * @arg RCC_APB1Periph_BKP * @arg RCC_APB1Periph_PWRDBG * @arg RCC_APB1Periph_DAC - * @arg RCC_APB1Periph_UART7 * @param state: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None. diff --git a/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_spi.c b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_spi.c index 6623e056cf3..a2cb2d64774 100644 --- a/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_spi.c +++ b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_spi.c @@ -630,7 +630,7 @@ void I2S_Init(SPI_TypeDef *spi, I2S_InitTypeDef *I2S_InitStruct) */ void I2S_CommunicationModeConfig(SPI_TypeDef *spi, uint32_t com_mode) { - MODIFY_REG(spi->CCTL, SPI_I2SCFGR_HDSEL_Msk, com_mode); + MODIFY_REG(spi->I2SCFGR, SPI_I2SCFGR_HDSEL_Msk, com_mode); } /** @@ -647,7 +647,7 @@ void I2S_CommunicationModeConfig(SPI_TypeDef *spi, uint32_t com_mode) */ void I2S_MCKOutputConfig(SPI_TypeDef *spi, uint32_t output_sel) { - MODIFY_REG(spi->CCTL, SPI_I2SCFGR_MCKSEL_Msk, output_sel); + MODIFY_REG(spi->I2SCFGR, SPI_I2SCFGR_MCKSEL_Msk, output_sel); } /** diff --git a/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_syscfg.c b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_syscfg.c index 0d991bd9531..9d0ce612b43 100644 --- a/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_syscfg.c +++ b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_syscfg.c @@ -208,15 +208,7 @@ FlagStatus SYSCFG_GetPVDOFlagStatus(uint32_t flag) * @arg #define SYSCFG_UART4_RX_RMP_DMA2_CH3 * @arg #define SYSCFG_UART4_RX_RMP_DMA2_CH7 * @arg #define SYSCFG_UART4_TX_RMP_DMA2_CH5 - * @arg #define SYSCFG_UART4_TX_RMP_DMA2_CH8 - * @arg #define SYSCFG_UART6_RX_RMP_DMA1_CH1 - * @arg #define SYSCFG_UART6_RX_RMP_DMA2_CH6 - * @arg #define SYSCFG_UART6_TX_RMP_DMA2_CH4 - * @arg #define SYSCFG_UART6_TX_RMP_DMA1_CH8 - * @arg #define SYSCFG_UART7_RX_RMP_DMA2_CH1 - * @arg #define SYSCFG_UART7_RX_RMP_DMA2_CH7 - * @arg #define SYSCFG_UART7_TX_RMP_DMA2_CH2 - * @arg #define SYSCFG_UART7_TX_RMP_DMA2_CH8 + * @arg #define SYSCFG_UART4_TX_RMP_DMA2_CH8 * @arg #define SYSCFG_DAC_CH1_RMP_DMA2_CH3 * @arg #define SYSCFG_DAC_CH1_RMP_DMA2_CH7 * @arg #define SYSCFG_DAC_CH2_RMP_DMA2_CH4 diff --git a/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_uart.c b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_uart.c index 696a0a2be39..d25e88dfbf3 100644 --- a/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_uart.c +++ b/bsp/mm32f526x/Libraries/MM32F526x/HAL_Lib/Src/hal_uart.c @@ -80,18 +80,6 @@ void UART_DeInit(UART_TypeDef *uart) RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); } - - if (uart == UART6) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_UART6, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_UART6, DISABLE); - } - - if (uart == UART7) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, DISABLE); - } } /** @@ -123,7 +111,7 @@ void UART_Init(UART_TypeDef *uart, UART_InitTypeDef *init_struct) /* UART BRR Configuration */ /* Configure the UART Baud Rate */ - if ((uart == UART1) || (uart == UART6)) + if (uart == UART1) { apbclock = RCC_ClocksStatus.PCLK2_Frequency; } diff --git a/bsp/mm32f526x/Libraries/MM32F526x/Include/reg_flash.h b/bsp/mm32f526x/Libraries/MM32F526x/Include/reg_flash.h index dfdd2448714..164d3d1a053 100644 --- a/bsp/mm32f526x/Libraries/MM32F526x/Include/reg_flash.h +++ b/bsp/mm32f526x/Libraries/MM32F526x/Include/reg_flash.h @@ -33,13 +33,10 @@ /* Files includes ----------------------------------------------------------------------------------------------------*/ #include "core_starmc1.h" -#define FLASH_BASE (0x08000000U) /*!< FLASH base address in the alias region*/ -#define SRAM_BASE (0x30000000U) /*!< SRAM base address in the alias region*/ -//#define CACHE_BASE (APB2PERIPH_BASE + 0x6000) ///< Base Address: 0x40016000 /** * @brief FLASH Base Address Definition */ -#define FLASH_REG_BASE 0x40022000 /*! #include +#include "hal_rcc.h" +#include "hal_gpio.h" -/* defined the LED pin: PB15 */ -#define LED_PIN 31 +#define LED1_PIN 31 +#define LED2_PIN 30 int main(void) { /* set LED1 pin mode to output */ - rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + rt_pin_mode(LED1_PIN, PIN_MODE_OUTPUT); + + /* set LED2 pin mode to output */ + rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT); while (1) { - rt_pin_write(LED_PIN, PIN_HIGH); + rt_pin_write(LED1_PIN, PIN_HIGH); + rt_pin_write(LED2_PIN, PIN_HIGH); rt_thread_mdelay(500); - rt_pin_write(LED_PIN, PIN_LOW); + rt_pin_write(LED1_PIN, PIN_LOW); + rt_pin_write(LED2_PIN, PIN_LOW); rt_thread_mdelay(500); } diff --git a/bsp/mm32f526x/drivers/Kconfig b/bsp/mm32f526x/drivers/Kconfig index 4cc82bc179d..c86a5a08eb7 100644 --- a/bsp/mm32f526x/drivers/Kconfig +++ b/bsp/mm32f526x/drivers/Kconfig @@ -37,36 +37,6 @@ menu "Hardware Drivers Config" default n endif - menuconfig BSP_USING_I2C1 - bool "Enable I2C1 BUS (software simulation)" - default n - select RT_USING_I2C - select RT_USING_I2C_BITOPS - select RT_USING_PIN - if BSP_USING_I2C1 - config BSP_I2C1_SCL_PIN - int "i2c1 scl pin number" - default 40 - config BSP_I2C1_SDA_PIN - int "I2C1 sda pin number" - default 39 - endif - - menuconfig BSP_USING_I2C2 - bool "Enable I2C2 BUS (software simulation)" - default n - select RT_USING_I2C - select RT_USING_I2C_BITOPS - select RT_USING_PIN - if BSP_USING_I2C2 - config BSP_I2C2_SCL_PIN - int "i2c2 scl pin number" - default 10 - config BSP_I2C2_SDA_PIN - int "I2C2 sda pin number" - default 12 - endif - menu "Flash Drivers" config BSP_USING_OCFLASH bool "Enable On Chip Flash" diff --git a/bsp/mm32f526x/drivers/SConscript b/bsp/mm32f526x/drivers/SConscript index cade92d9ebd..4ac25cef4f6 100644 --- a/bsp/mm32f526x/drivers/SConscript +++ b/bsp/mm32f526x/drivers/SConscript @@ -24,10 +24,6 @@ if GetDepend(['BSP_USING_GPIO']): if GetDepend(['BSP_USING_ADC']): src += ['drv_adc.c'] -# add soft i2c driver code -if GetDepend(['RT_USING_I2C']) or GetDepend(['RT_USING_I2C_BITOPS']): - src += ['drv_soft_i2c.c'] - # add flash driver code if GetDepend(['BSP_USING_OCFLASH']): src += ['drv_flash.c'] diff --git a/bsp/mm32f526x/drivers/board.c b/bsp/mm32f526x/drivers/board.c index d1858f455d4..0a61a4966cd 100644 --- a/bsp/mm32f526x/drivers/board.c +++ b/bsp/mm32f526x/drivers/board.c @@ -11,11 +11,41 @@ #include extern uint32_t SystemCoreClock; extern void SystemInit(void); + +/** + * this function will delay for some us. + * + * @param us the delay time of us + */ +void rt_hw_us_delay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) { + tnow = SysTick->VAL; + if (tnow != told) { + if (tnow < told) { + tcnt += told - tnow; + } else { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) { + break; + } + } + } +} + static void bsp_clock_config(void) { - SystemInit(); - SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); - SysTick->CTRL |= 0x00000004UL; + SystemInit(); + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + SysTick->CTRL |= 0x00000004UL; } void SysTick_Handler(void) @@ -32,13 +62,26 @@ void SysTick_Handler(void) void rt_hw_board_init() { bsp_clock_config(); + #if defined(RT_USING_HEAP) rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); #endif -#ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); + +#ifdef RT_USING_PIN + extern int rt_hw_pin_init(void); + rt_hw_pin_init(); #endif + +#ifdef RT_USING_SERIAL + extern int rt_hw_uart_init(void); + rt_hw_uart_init(); +#endif + #if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) rt_console_set_device(RT_CONSOLE_DEVICE_NAME); #endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif } diff --git a/bsp/mm32f526x/drivers/board.h b/bsp/mm32f526x/drivers/board.h index 6a439812c24..b6fdd94362f 100644 --- a/bsp/mm32f526x/drivers/board.h +++ b/bsp/mm32f526x/drivers/board.h @@ -11,11 +11,15 @@ #ifndef __BOARD_H__ #define __BOARD_H__ #include -#include "hal_device.h" +#include +#include #include "mm32_device.h" +#include #define SRAM_SIZE 0x1C000 +#define SRAM_BASE (0x30000000) + #define SRAM_END (SRAM_BASE + SRAM_SIZE) #ifdef __CC_ARM extern int Image$$RW_IRAM1$$ZI$$Limit; @@ -24,10 +28,14 @@ #pragma section = "HEAP" #define HEAP_BEGIN (__segment_end("HEAP")) #else - extern int __bss_end; - #define HEAP_BEGIN ((void *)&__bss_end) + extern int __bss_end__; + #define HEAP_BEGIN ((void *)&__bss_end__) #endif #define HEAP_END SRAM_END #define HEAP_SIZE (HEAP_END - (rt_uint32_t)HEAP_BEGIN) extern void rt_hw_board_init(void); + +#define CLOCK_SYS_FREQ 120000000u +#define CLOCK_SYSTICK_FREQ (CLOCK_SYS_FREQ/8u) + #endif diff --git a/bsp/mm32f526x/drivers/drv_adc.c b/bsp/mm32f526x/drivers/drv_adc.c index 15d86d03b2e..8a141d864ee 100644 --- a/bsp/mm32f526x/drivers/drv_adc.c +++ b/bsp/mm32f526x/drivers/drv_adc.c @@ -7,8 +7,8 @@ * Date Author Notes * 2023-03-17 letian first version */ -#include #include +#include "board.h" #include "drv_adc.h" #include #include @@ -17,9 +17,9 @@ #if defined(BSP_USING_ADC) -#define ADC_CONFIG_GPIORCC RCC_AHBENR_GPIOA +#define ADC_CONFIG_GPIORCC RCC_AHBPeriph_GPIOA #define ADC_CONFIG_GPIOX GPIOA -#define ADC_CONFIG_IOX GPIO_Pin_5 | GPIO_Pin_4 +#define ADC_CONFIG_IOX GPIO_Pin_0 | GPIO_Pin_1 struct mm32_adc { @@ -42,62 +42,82 @@ struct mm32_adc mm32_adc2_config = { }; #endif /* BSP_USING_ADC2 */ -static void ADCxChannelEnable(ADC_TypeDef* ADCn, ADCCHANNEL_TypeDef channel) +static void ADCxChannelEnable(ADC_TypeDef* ADCn, rt_uint32_t channel) { - ADCn->CHSR &= ~(1 << channel); - ADCn->CHSR |= (1 << channel); + ADCn->ADCHS &= ~(1 << channel); + ADCn->ADCHS |= (1 << channel); } -static rt_err_t mm32_adc_init(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) +static rt_err_t mm32_adc_init(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled) { ADC_InitTypeDef ADC_InitStruct; ADC_TypeDef *adc_x; RT_ASSERT(device != RT_NULL); adc_x = device->parent.user_data; - #if defined(BSP_USING_ADC1) - RCC_APB2PeriphClockCmd(RCC_APB2ENR_ADC1, ENABLE); //Enable ADC1 clock - #endif /* BSP_USING_ADC1 */ + if (enabled) { + #if defined(BSP_USING_ADC1) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE); //Enable ADC1 clock + #endif /* BSP_USING_ADC1 */ - #if defined(BSP_USING_ADC2) - RCC_APB2PeriphClockCmd(RCC_APB2ENR_ADC2, ENABLE); //Enable ADC2 clock - #endif /* BSP_USING_ADC2 */ + #if defined(BSP_USING_ADC2) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC2, ENABLE); //Enable ADC2 clock + #endif /* BSP_USING_ADC2 */ + + ADC_CalibrationConfig(adc_x, 0x1FE); + + ADC_StructInit(&ADC_InitStruct); + ADC_InitStruct.ADC_Resolution = ADC_Resolution_12b; + ADC_InitStruct.ADC_Prescaler = ADC_Prescaler_16; //ADC prescale factor + ADC_InitStruct.ADC_Mode = ADC_Mode_Scan; //Set ADC mode to continuous conversion mode + ADC_InitStruct.ADC_DataAlign = ADC_DataAlign_Right; //AD data right-justified + ADC_Init(adc_x, &ADC_InitStruct); + + ADC_SampleTimeConfig(adc_x, channel, ADC_SampleTime_240_5); + ADC_ChannelCmd(adc_x, channel, ENABLE); - ADC_StructInit(&ADC_InitStruct); - ADC_InitStruct.ADC_Resolution = ADC_Resolution_12b; - ADC_InitStruct.ADC_PRESCARE = ADC_PCLK2_PRESCARE_16; //ADC prescale factor - ADC_InitStruct.ADC_Mode = ADC_Mode_Continue; //Set ADC mode to continuous conversion mode - ADC_InitStruct.ADC_DataAlign = ADC_DataAlign_Right; //AD data right-justified - ADC_InitStruct.ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; - ADC_Init(adc_x, &ADC_InitStruct); + ADC_DifferentialConversionConfig(adc_x, ADC_Differential_Conversion_4_5); - ADC_RegularChannelConfig(adc_x, channel, 0, ADC_Samctl_239_5); - ADC_Cmd(adc_x, ENABLE); - ADCxChannelEnable(adc_x, channel); + //config gpio + GPIO_InitTypeDef GPIO_InitStruct; + GPIO_StructInit(&GPIO_InitStruct); - //config gpio - GPIO_InitTypeDef GPIO_InitStruct; - GPIO_StructInit(&GPIO_InitStruct); + RCC_AHBPeriphClockCmd(ADC_CONFIG_GPIORCC, ENABLE); + GPIO_InitStruct.GPIO_Pin = ADC_CONFIG_IOX; + GPIO_InitStruct.GPIO_Speed = GPIO_Speed_High; + GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AIN; + GPIO_Init(ADC_CONFIG_GPIOX, &GPIO_InitStruct); - RCC_AHBPeriphClockCmd(ADC_CONFIG_GPIORCC, ENABLE); - GPIO_InitStruct.GPIO_Pin = ADC_CONFIG_IOX; - GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AIN; - GPIO_Init(ADC_CONFIG_GPIOX, &GPIO_InitStruct); + ADC_Cmd(adc_x, ENABLE); + } else { + #if defined(BSP_USING_ADC1) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, DISABLE); //disable ADC1 clock + #endif /* BSP_USING_ADC1 */ + + #if defined(BSP_USING_ADC2) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC2, DISABLE); //disable ADC2 clock + #endif /* BSP_USING_ADC2 */ + + ADC_DeInit(adc_x); + ADC_Cmd(adc_x, DISABLE); + } return RT_EOK; } -static rt_err_t mm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) +static rt_err_t mm32_get_adc_value(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value) { ADC_TypeDef *adc_x; RT_ASSERT(device != RT_NULL); adc_x = device->parent.user_data; ADC_SoftwareStartConvCmd(adc_x, ENABLE); - while(ADC_GetFlagStatus(adc_x, ADC_IT_EOC) == 0); - ADC_ClearFlag(adc_x, ADC_IT_EOC); - *value = ADC_GetConversionValue(adc_x); + while(ADC_GetFlagStatus(adc_x, ADC_IT_EOS) == 0) + rt_thread_mdelay(1); + + ADC_ClearFlag(adc_x, ADC_IT_EOS); + + *value = ADC_GetChannelConvertedValue(adc_x, channel); return RT_EOK; } @@ -107,7 +127,7 @@ static rt_uint8_t mm32_adc_get_resolution(struct rt_adc_device *device) RT_ASSERT(device != RT_NULL); - switch( ((adc_x->CFGR)&(0x00000380)) ) + switch( ((adc_x->ADCFG)&(0x00000380)) ) { case ADC_Resolution_12b: return 12; @@ -120,7 +140,7 @@ static rt_uint8_t mm32_adc_get_resolution(struct rt_adc_device *device) case ADC_Resolution_8b: return 8; default: - return 0; + return 12; } } diff --git a/bsp/mm32f526x/drivers/drv_gpio.c b/bsp/mm32f526x/drivers/drv_gpio.c index 015f73d0718..2df521a5a33 100644 --- a/bsp/mm32f526x/drivers/drv_gpio.c +++ b/bsp/mm32f526x/drivers/drv_gpio.c @@ -10,6 +10,7 @@ #include #include +#include "drv_gpio.h" #include #include #include @@ -17,76 +18,21 @@ #include #include -#define MM32_PIN(index, rcc, gpio, gpio_index) \ - { \ - 0, RCC_##rcc##Periph_GPIO##gpio, GPIO##gpio, GPIO_Pin_##gpio_index, GPIO_PortSourceGPIO##gpio, GPIO_PinSource##gpio_index \ - } -#define MM32_PIN_DEFAULT \ - { \ - -1, 0, 0, 0, 0, 0 \ - } -/* MM32 GPIO driver */ -struct pin_index -{ - int index; - uint32_t rcc; - GPIO_TypeDef *gpio; - uint32_t pin; - uint8_t port_source; - uint8_t pin_source; -}; -static const struct pin_index mm32_pin_map[] = -{ - MM32_PIN_DEFAULT, - MM32_PIN_DEFAULT, - MM32_PIN(2, AHB, C, 13), - MM32_PIN(3, AHB, C, 14), - MM32_PIN(4, AHB, C, 15), - MM32_PIN_DEFAULT, - MM32_PIN_DEFAULT, - MM32_PIN_DEFAULT, - MM32_PIN_DEFAULT, - MM32_PIN_DEFAULT, - MM32_PIN(10, AHB, A, 0), - MM32_PIN(11, AHB, A, 1), - MM32_PIN(12, AHB, A, 2), - MM32_PIN(13, AHB, A, 3), - MM32_PIN(14, AHB, A, 4), - MM32_PIN(15, AHB, A, 5), - MM32_PIN(16, AHB, A, 6), - MM32_PIN(17, AHB, A, 7), - MM32_PIN(18, AHB, B, 0), - MM32_PIN(19, AHB, B, 1), - MM32_PIN(20, AHB, B, 2), - MM32_PIN(21, AHB, B, 10), - MM32_PIN(22, AHB, B, 11), - MM32_PIN_DEFAULT, - MM32_PIN_DEFAULT, - MM32_PIN(25, AHB, B, 12), - MM32_PIN(26, AHB, B, 13), - MM32_PIN(27, AHB, B, 14), - MM32_PIN(28, AHB, B, 15), - MM32_PIN(29, AHB, A, 8), - MM32_PIN(30, AHB, A, 9), - MM32_PIN(31, AHB, A, 10), - MM32_PIN(32, AHB, A, 11), - MM32_PIN(33, AHB, A, 12), - MM32_PIN(34, AHB, A, 13), - MM32_PIN_DEFAULT, - MM32_PIN_DEFAULT, - MM32_PIN(37, AHB, A, 14), - MM32_PIN(38, AHB, A, 15), - MM32_PIN(39, AHB, B, 3), - MM32_PIN(40, AHB, B, 4), - MM32_PIN(41, AHB, B, 5), - MM32_PIN(42, AHB, B, 6), - MM32_PIN(43, AHB, B, 7), - MM32_PIN_DEFAULT, - MM32_PIN(45, AHB, B, 8), - MM32_PIN(46, AHB, B, 9), - MM32_PIN_DEFAULT, - MM32_PIN_DEFAULT, -}; +#define PIN_NUM(port, no) (((((port) & 0xFu) << 4) | ((no) & 0xFu))) +#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu)) +#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu)) +#define RCC_PIN_PORT(pin) ((uint32_t)(0x01u << (PIN_PORT(pin)))) + +#define PIN_ATPORTSOURCE(pin) ((uint8_t)(((pin) & 0xF0u) >> 4)) +#define PIN_ATPINSOURCE(pin) ((uint8_t)((pin) & 0xFu)) + +#define PIN_ATPORT(pin) ((GPIO_TypeDef *)(GPIOA_BASE + (0x400u * PIN_PORT(pin)))) +#define PIN_ATPIN(pin) ((uint16_t)(1u << PIN_NO(pin))) + +/* mm32f5265 pin port */ +#define __MM32_PORT_MAX 6u + +#define PIN_ATPORT_MAX __MM32_PORT_MAX struct pin_irq_map { @@ -132,146 +78,152 @@ struct rt_pin_irq_hdr mm32_pin_irq_hdr_tab[] = {-1, 0, RT_NULL, RT_NULL}, {-1, 0, RT_NULL, RT_NULL}, }; + #define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) -const struct pin_index *get_pin(uint8_t pin) + +static rt_base_t mm32_pin_get(const char *name) { - const struct pin_index *index; + rt_base_t pin = 0; + int hw_port_num, hw_pin_num = 0; + int i, name_len; - if (pin < ITEM_NUM(mm32_pin_map)) - { - index = &mm32_pin_map[pin]; - if (index->gpio == 0) - index = RT_NULL; + name_len = rt_strlen(name); + + if ((name_len < 4) || (name_len >= 6)) { + return -RT_EINVAL; } - else - { - index = RT_NULL; + + if ((name[0] != 'P') || (name[2] != '.')) { + return -RT_EINVAL; } - return index; -}; + if ((name[1] >= 'A') && (name[1] <= 'Z')) { + hw_port_num = (int)(name[1] - 'A'); + } else { + return -RT_EINVAL; + } + + for (i = 3; i < name_len; i++) { + hw_pin_num *= 10; + hw_pin_num += name[i] - '0'; + } + + pin = PIN_NUM(hw_port_num, hw_pin_num); + + return pin; +} void mm32_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value) { - const struct pin_index *index; + GPIO_TypeDef *gpio_port; - index = get_pin(pin); - if (index == RT_NULL) - { + uint16_t gpio_pin; + if (PIN_PORT(pin) < PIN_ATPORT_MAX) { + gpio_port = PIN_ATPORT(pin); + gpio_pin = PIN_ATPIN(pin); + } else { return; } - if (value == PIN_LOW) - { - GPIO_ResetBits(index->gpio, index->pin); - } - else - { - GPIO_SetBits(index->gpio, index->pin); - } + GPIO_WriteBit(gpio_port, gpio_pin, (PIN_LOW == value) ? Bit_RESET : Bit_SET); } rt_ssize_t mm32_pin_read(rt_device_t dev, rt_base_t pin) { - rt_ssize_t value; - const struct pin_index *index; + GPIO_TypeDef *gpio_port; + uint16_t gpio_pin; + int value; value = PIN_LOW; - index = get_pin(pin); - if (index == RT_NULL) - { + + if (PIN_PORT(pin) < PIN_ATPORT_MAX) { + gpio_port = PIN_ATPORT(pin); + gpio_pin = PIN_ATPIN(pin); + value = GPIO_ReadInputDataBit(gpio_port, gpio_pin); + } else { return -RT_EINVAL; } - if (GPIO_ReadInputDataBit(index->gpio, index->pin) == Bit_RESET) - { - value = PIN_LOW; - } - else - { - value = PIN_HIGH; - } + return value; } void mm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode) { - const struct pin_index *index; + GPIO_TypeDef *gpio_port; + uint16_t gpio_pin; GPIO_InitTypeDef GPIO_InitStructure; - index = get_pin(pin); - if (index == RT_NULL) - { + if (PIN_PORT(pin) < PIN_ATPORT_MAX) { + gpio_port = PIN_ATPORT(pin); + gpio_pin = PIN_ATPIN(pin); + } else { return; } + /* GPIO Periph clock enable */ - RCC_AHBPeriphClockCmd(index->rcc, ENABLE); + RCC_AHBPeriphClockCmd(RCC_PIN_PORT(pin), ENABLE); + /* Configure GPIO_InitStructure */ - GPIO_InitStructure.GPIO_Pin = index->pin; + GPIO_InitStructure.GPIO_Pin = gpio_pin; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_High; - if (mode == PIN_MODE_OUTPUT) - { + + if (mode == PIN_MODE_OUTPUT) { /* output setting */ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - } - else if (mode == PIN_MODE_OUTPUT_OD) - { + } else if (mode == PIN_MODE_OUTPUT_OD) { /* output setting: od. */ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD; - } - else if (mode == PIN_MODE_INPUT) - { + } else if (mode == PIN_MODE_INPUT) { /* input setting: not pull. */ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_FLOATING; - } - else if (mode == PIN_MODE_INPUT_PULLUP) - { + } else if (mode == PIN_MODE_INPUT_PULLUP) { /* input setting: pull up. */ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; - } - else - { + } else { /* input setting:default. */ GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; } - GPIO_Init(index->gpio, &GPIO_InitStructure); + + GPIO_Init(gpio_port, &GPIO_InitStructure); } + rt_inline rt_int32_t bit2bitno(rt_uint32_t bit) { int i; - for (i = 0; i < 32; i++) - { - if ((0x01 << i) == bit) - { + for (i = 0; i < 32; i++) { + if ((0x01 << i) == bit) { return i; } } + return -1; } + rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit) { rt_int32_t mapindex = bit2bitno(pinbit); - if (mapindex < 0 || mapindex >= ITEM_NUM(mm32_pin_irq_map)) - { + if (mapindex < 0 || mapindex >= ITEM_NUM(mm32_pin_irq_map)) { return RT_NULL; } return &mm32_pin_irq_map[mapindex]; }; + rt_err_t mm32_pin_attach_irq(struct rt_device *device, rt_base_t pin, rt_uint8_t mode, void (*hdr)(void *args), void *args) { - const struct pin_index *index; + uint16_t gpio_pin; rt_base_t level; rt_int32_t irqindex = -1; - index = get_pin(pin); - if (index == RT_NULL) - { - return -RT_ENOSYS; + if (PIN_PORT(pin) < PIN_ATPORT_MAX) { + gpio_pin = PIN_ATPIN(pin); + } else { + return -RT_EINVAL; } - irqindex = bit2bitno(index->pin); - if (irqindex < 0 || irqindex >= ITEM_NUM(mm32_pin_irq_map)) - { + + irqindex = bit2bitno(gpio_pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(mm32_pin_irq_map)) { return -RT_ENOSYS; } @@ -284,11 +236,12 @@ rt_err_t mm32_pin_attach_irq(struct rt_device *device, rt_base_t pin, rt_hw_interrupt_enable(level); return RT_EOK; } - if (mm32_pin_irq_hdr_tab[irqindex].pin != -1) - { + + if (mm32_pin_irq_hdr_tab[irqindex].pin != -1) { rt_hw_interrupt_enable(level); return -RT_EBUSY; } + mm32_pin_irq_hdr_tab[irqindex].pin = pin; mm32_pin_irq_hdr_tab[irqindex].hdr = hdr; mm32_pin_irq_hdr_tab[irqindex].mode = mode; @@ -299,27 +252,27 @@ rt_err_t mm32_pin_attach_irq(struct rt_device *device, rt_base_t pin, } rt_err_t mm32_pin_detach_irq(struct rt_device *device, rt_base_t pin) { - const struct pin_index *index; - rt_base_t level; + uint16_t gpio_pin; + rt_base_t level; rt_int32_t irqindex = -1; - index = get_pin(pin); - if (index == RT_NULL) - { - return -RT_ENOSYS; + if (PIN_PORT(pin) < PIN_ATPORT_MAX) { + gpio_pin = PIN_ATPIN(pin); + } else { + return -RT_EINVAL; } - irqindex = bit2bitno(index->pin); - if (irqindex < 0 || irqindex >= ITEM_NUM(mm32_pin_irq_map)) - { + + irqindex = bit2bitno(gpio_pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(mm32_pin_irq_map)) { return -RT_ENOSYS; } level = rt_hw_interrupt_disable(); - if (mm32_pin_irq_hdr_tab[irqindex].pin == -1) - { + if (mm32_pin_irq_hdr_tab[irqindex].pin == -1) { rt_hw_interrupt_enable(level); return RT_EOK; } + mm32_pin_irq_hdr_tab[irqindex].pin = -1; mm32_pin_irq_hdr_tab[irqindex].hdr = RT_NULL; mm32_pin_irq_hdr_tab[irqindex].mode = 0; @@ -328,10 +281,12 @@ rt_err_t mm32_pin_detach_irq(struct rt_device *device, rt_base_t pin) return RT_EOK; } + rt_err_t mm32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled) { - const struct pin_index *index; + GPIO_TypeDef *gpio_port; + uint16_t gpio_pin; const struct pin_irq_map *irqmap; rt_base_t level; rt_int32_t irqindex = -1; @@ -339,32 +294,34 @@ rt_err_t mm32_pin_irq_enable(struct rt_device *device, rt_base_t pin, NVIC_InitTypeDef NVIC_InitStructure; EXTI_InitTypeDef EXTI_InitStructure; - index = get_pin(pin); - if (index == RT_NULL) - { - return -RT_ENOSYS; + if (PIN_PORT(pin) < PIN_ATPORT_MAX) { + gpio_port = PIN_ATPORT(pin); + gpio_pin = PIN_ATPIN(pin); + } else { + return -RT_EINVAL; } + if (enabled == PIN_IRQ_ENABLE) { - irqindex = bit2bitno(index->pin); - if (irqindex < 0 || irqindex >= ITEM_NUM(mm32_pin_irq_map)) - { + irqindex = bit2bitno(gpio_pin); + if (irqindex < 0 || irqindex >= ITEM_NUM(mm32_pin_irq_map)) { return -RT_ENOSYS; } level = rt_hw_interrupt_disable(); - if (mm32_pin_irq_hdr_tab[irqindex].pin == -1) - { + if (mm32_pin_irq_hdr_tab[irqindex].pin == -1) { rt_hw_interrupt_enable(level); return -RT_ENOSYS; } irqmap = &mm32_pin_irq_map[irqindex]; + /* GPIO Periph clock enable */ - RCC_APB2PeriphClockCmd(index->rcc, ENABLE); + RCC_AHBPeriphClockCmd(RCC_PIN_PORT(pin), ENABLE); + /* Configure GPIO_InitStructure */ - GPIO_InitStructure.GPIO_Pin = index->pin; + GPIO_InitStructure.GPIO_Pin = gpio_pin; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_High; - GPIO_Init(index->gpio, &GPIO_InitStructure); + GPIO_Init(gpio_port, &GPIO_InitStructure); NVIC_InitStructure.NVIC_IRQChannel = irqmap->irqno; NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; @@ -374,8 +331,7 @@ rt_err_t mm32_pin_irq_enable(struct rt_device *device, rt_base_t pin, EXTI_InitStructure.EXTI_Line = irqmap->irqbit; EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; - switch (mm32_pin_irq_hdr_tab[irqindex].mode) - { + switch (mm32_pin_irq_hdr_tab[irqindex].mode) { case PIN_IRQ_MODE_RISING: EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; break; @@ -389,12 +345,9 @@ rt_err_t mm32_pin_irq_enable(struct rt_device *device, rt_base_t pin, EXTI_InitStructure.EXTI_LineCmd = ENABLE; EXTI_Init(&EXTI_InitStructure); rt_hw_interrupt_enable(level); - } - else if (enabled == PIN_IRQ_DISABLE) - { - irqmap = get_pin_irq_map(index->pin); - if (irqmap == RT_NULL) - { + } else if (enabled == PIN_IRQ_DISABLE) { + irqmap = get_pin_irq_map(gpio_pin); + if (irqmap == RT_NULL) { return -RT_ENOSYS; } EXTI_InitStructure.EXTI_Line = irqmap->irqbit; @@ -402,9 +355,7 @@ rt_err_t mm32_pin_irq_enable(struct rt_device *device, rt_base_t pin, EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; EXTI_InitStructure.EXTI_LineCmd = DISABLE; EXTI_Init(&EXTI_InitStructure); - } - else - { + } else { return -RT_ENOSYS; } @@ -418,7 +369,7 @@ const static struct rt_pin_ops _mm32_pin_ops = mm32_pin_attach_irq, mm32_pin_detach_irq, mm32_pin_irq_enable, - RT_NULL, + mm32_pin_get, }; int rt_hw_pin_init(void) @@ -428,7 +379,6 @@ int rt_hw_pin_init(void) result = rt_device_pin_register("pin", &_mm32_pin_ops, RT_NULL); return result; } -INIT_BOARD_EXPORT(rt_hw_pin_init); rt_inline void pin_irq_hdr(int irqno) { diff --git a/bsp/mm32f526x/drivers/drv_soft_i2c.c b/bsp/mm32f526x/drivers/drv_soft_i2c.c deleted file mode 100644 index 17b55efcc3a..00000000000 --- a/bsp/mm32f526x/drivers/drv_soft_i2c.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * Copyright (c) 2024, Chasel - * - * Change Logs: - * Date Author Notes - * 2025-01-06 Chasel first commit - */ - -#include "drv_soft_i2c.h" - -#if defined(BSP_USING_I2C1) || defined(BSP_USING_I2C2) - - -static const struct mm32_soft_i2c_config soft_i2c_config[] = -{ -#ifdef BSP_USING_I2C1 - I2C1_BUS_CONFIG, -#endif -#ifdef BSP_USING_I2C2 - I2C2_BUS_CONFIG, -#endif -}; - -static struct mm32_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])]; - -/** - * This function initializes the i2c pin. - * - * @param mm32 i2c dirver class. - */ -static void mm32_i2c_gpio_init(struct mm32_i2c *i2c) -{ - struct mm32_soft_i2c_config* cfg = (struct mm32_soft_i2c_config*)i2c->ops.data; - - rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD); - rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD); - - rt_pin_write(cfg->scl, PIN_HIGH); - rt_pin_write(cfg->sda, PIN_HIGH); -} - -static void mm32_i2c_pin_init(void) -{ - rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct mm32_i2c); - - for(rt_size_t i = 0; i < obj_num; i++) - { - mm32_i2c_gpio_init(&i2c_obj[i]); - } -} - -/** - * This function sets the sda pin. - * - * @param mm32 config class. - * @param The sda pin state. - */ -static void mm32_set_sda(void *data, rt_int32_t state) -{ - struct mm32_soft_i2c_config* cfg = (struct mm32_soft_i2c_config*)data; - if (state) - { - rt_pin_write(cfg->sda, PIN_HIGH); - } - else - { - rt_pin_write(cfg->sda, PIN_LOW); - } -} - -/** - * This function sets the scl pin. - * - * @param mm32 config class. - * @param The scl pin state. - */ -static void mm32_set_scl(void *data, rt_int32_t state) -{ - struct mm32_soft_i2c_config* cfg = (struct mm32_soft_i2c_config*)data; - if (state) - { - rt_pin_write(cfg->scl, PIN_HIGH); - } - else - { - rt_pin_write(cfg->scl, PIN_LOW); - } -} - -/** - * This function gets the sda pin state. - * - * @param The sda pin state. - */ -static rt_int32_t mm32_get_sda(void *data) -{ - struct mm32_soft_i2c_config* cfg = (struct mm32_soft_i2c_config*)data; - return rt_pin_read(cfg->sda); -} - -/** - * This function gets the scl pin state. - * - * @param The scl pin state. - */ -static rt_int32_t mm32_get_scl(void *data) -{ - struct mm32_soft_i2c_config* cfg = (struct mm32_soft_i2c_config*)data; - return rt_pin_read(cfg->scl); -} - -static const struct rt_i2c_bit_ops mm32_bit_ops_default = -{ - .data = RT_NULL, - .pin_init = mm32_i2c_pin_init, - .set_sda = mm32_set_sda, - .set_scl = mm32_set_scl, - .get_sda = mm32_get_sda, - .get_scl = mm32_get_scl, - .udelay = rt_hw_us_delay, - .delay_us = 1, - .timeout = 100, - .i2c_pin_init_flag = RT_FALSE -}; - -/** - * if i2c is locked, this function will unlock it - * - * @param mm32 config class - * - * @return RT_EOK indicates successful unlock. - */ -static rt_err_t mm32_i2c_bus_unlock(const struct mm32_soft_i2c_config *cfg) -{ - rt_int32_t i = 0; - - if (PIN_LOW == rt_pin_read(cfg->sda)) - { - while (i++ < 9) - { - rt_pin_write(cfg->scl, PIN_HIGH); - rt_hw_us_delay(100); - rt_pin_write(cfg->scl, PIN_LOW); - rt_hw_us_delay(100); - } - } - if (PIN_LOW == rt_pin_read(cfg->sda)) - { - return -RT_ERROR; - } - - return RT_EOK; -} - -/* I2C initialization function */ -int rt_hw_i2c_init(void) -{ - rt_err_t result; - - for (rt_size_t i = 0; i < sizeof(i2c_obj) / sizeof(struct mm32_i2c); i++) - { - i2c_obj[i].ops = mm32_bit_ops_default; - i2c_obj[i].ops.data = (void*)&soft_i2c_config[i]; - i2c_obj[i].i2c_bus.priv = &i2c_obj[i].ops; - result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c_bus, soft_i2c_config[i].bus_name); - RT_ASSERT(result == RT_EOK); - mm32_i2c_bus_unlock(&soft_i2c_config[i]); - } - - return RT_EOK; -} -INIT_BOARD_EXPORT(rt_hw_i2c_init); - -#endif /* defined(BSP_USING_I2C1) || defined(BSP_USING_I2C2) */ diff --git a/bsp/mm32f526x/drivers/drv_soft_i2c.h b/bsp/mm32f526x/drivers/drv_soft_i2c.h deleted file mode 100644 index 1bd5ed31191..00000000000 --- a/bsp/mm32f526x/drivers/drv_soft_i2c.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2025, Chasel - * - * Change Logs: - * Date Author Notes - * 2025-01-06 Chasel first version - */ - -#ifndef __DRV_I2C__ -#define __DRV_I2C__ - -#include -#include -#include - -/* mm32 config class */ -struct mm32_soft_i2c_config -{ - rt_uint8_t scl; - rt_uint8_t sda; - const char *bus_name; -}; -/* mm32 i2c dirver class */ -struct mm32_i2c -{ - struct rt_i2c_bit_ops ops; - struct rt_i2c_bus_device i2c_bus; -}; - -#ifdef BSP_USING_I2C1 -#define I2C1_BUS_CONFIG \ - { \ - .scl = BSP_I2C1_SCL_PIN, \ - .sda = BSP_I2C1_SDA_PIN, \ - .bus_name = "i2c1", \ - } -#endif - -#ifdef BSP_USING_I2C2 -#define I2C2_BUS_CONFIG \ - { \ - .scl = BSP_I2C2_SCL_PIN, \ - .sda = BSP_I2C2_SDA_PIN, \ - .bus_name = "i2c2", \ - } -#endif - -int rt_hw_i2c_init(void); - -#endif diff --git a/bsp/mm32f526x/drivers/drv_uart.c b/bsp/mm32f526x/drivers/drv_uart.c index 447b30c7acc..88ec547d77f 100644 --- a/bsp/mm32f526x/drivers/drv_uart.c +++ b/bsp/mm32f526x/drivers/drv_uart.c @@ -7,7 +7,7 @@ * Date Author Notes * 2021-08-05 mazhiyuan first version */ -#include +#include #include #include "drv_uart.h" #include @@ -40,6 +40,7 @@ static rt_err_t mm32_uart_configure(struct rt_serial_device *serial, struct seri UART_InitStructure.HWFlowControl = UART_HWFlowControl_None; UART_InitStructure.Mode = UART_Mode_Rx | UART_Mode_Tx; UART_Init(uart->uart, &UART_InitStructure); + /* Enable UART */ UART_Cmd(uart->uart, ENABLE); @@ -186,7 +187,6 @@ static void UART1PINconfigStepA(void) static void UART1PINconfigStepB(void) { - GPIO_InitTypeDef GPIO_InitStructure; /* Configure USART Rx/tx PIN */ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; @@ -300,4 +300,3 @@ int rt_hw_uart_init(void) return 0; } -INIT_BOARD_EXPORT(rt_hw_uart_init); diff --git a/bsp/mm32f526x/drivers/linker_scripts/link.lds b/bsp/mm32f526x/drivers/linker_scripts/link.lds index 688df61446d..d32c5247671 100644 --- a/bsp/mm32f526x/drivers/linker_scripts/link.lds +++ b/bsp/mm32f526x/drivers/linker_scripts/link.lds @@ -29,7 +29,7 @@ __RAM_SIZE = 0x0001C000; -----------------------------------------------------------------------------*/ __STACK_SIZE = 0x00001000; -__HEAP_SIZE = 0x00001000; +/*__HEAP_SIZE = 0x00001000;*/ /* *-------------------- <<< end of configuration section >>> ------------------- @@ -84,29 +84,44 @@ SECTIONS { .text : { + . = ALIGN(4); KEEP(*(.vectors)) - *(.text*) + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; - KEEP(*(.init)) - KEEP(*(.fini)) + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) + . = ALIGN(4); - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); - *(.rodata*) + . = ALIGN(4); - KEEP(*(.eh_frame*)) + _etext = .; } > FLASH /* @@ -130,77 +145,32 @@ SECTIONS .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - - LONG (__etext) - LONG (__data_start__) - LONG ((__data_end__ - __data_start__) / 4) - /* Add each additional data section here */ -/* - LONG (__etext2) - LONG (__data2_start__) - LONG ((__data2_end__ - __data2_start__) / 4) -*/ - __copy_table_end__ = .; - } > FLASH - - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - /* Add each additional bss section here */ -/* - LONG (__bss2_start__) - LONG ((__bss2_end__ - __bss2_start__) / 4) -*/ - __zero_table_end__ = .; + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; } > FLASH + __exidx_end = .; - /** - * Location counter can end up 2byte aligned with narrow Thumb code but - * __etext is assumed by startup code to be the LMA of a section in RAM - * which must be 4byte aligned - */ - __etext = ALIGN (4); + __etext = ALIGN (4); .data : AT (__etext) { - __data_start__ = .; - *(vtable) - *(.data) - *(.data.*) - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); - KEEP(*(.jcr*)) - . = ALIGN(4); - /* All data end */ - __data_end__ = .; + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; } > RAM @@ -226,16 +196,56 @@ SECTIONS } > RAM2 */ +/* + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + */ + + + /* ARMv8-M stack sealing: + to use ARMv8-M stack sealing uncomment '.stackseal' section + */ +/* + .stackseal : + { + . = ALIGN(8); + __StackSeal = .; + . = . + 8; + . = ALIGN(8); + } > RAM +*/ + + .stack : + { + . = ALIGN(8); + _sstack = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > RAM + + __bss_start__ = .; .bss : { . = ALIGN(4); - __bss_start__ = .; + _sbss = .; + *(.bss) *(.bss.*) *(COMMON) . = ALIGN(4); - __bss_end__ = .; - } > RAM AT > RAM + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end__ = .; /* * Secondary bss section, optional @@ -255,40 +265,4 @@ SECTIONS __bss2_end__ = .; } > RAM2 AT > RAM2 */ - - .heap (COPY) : - { - . = ALIGN(8); - __end__ = .; - PROVIDE(end = .); - . = . + __HEAP_SIZE; - . = ALIGN(8); - __HeapLimit = .; - } > RAM - - .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackLimit = .; - . = . + __STACK_SIZE; - . = ALIGN(8); - __StackTop = .; - } > RAM - PROVIDE(__stack = __StackTop); - - /* ARMv8-M stack sealing: - to use ARMv8-M stack sealing uncomment '.stackseal' section - */ -/* - .stackseal (ORIGIN(RAM) + LENGTH(RAM) - __STACKSEAL_SIZE) (COPY) : - { - . = ALIGN(8); - __StackSeal = .; - . = . + 8; - . = ALIGN(8); - } > RAM -*/ - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") } diff --git a/bsp/mm32f526x/rtconfig.h b/bsp/mm32f526x/rtconfig.h index 9e13052c582..698d497dea8 100644 --- a/bsp/mm32f526x/rtconfig.h +++ b/bsp/mm32f526x/rtconfig.h @@ -66,13 +66,16 @@ #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 100 +#define RT_TICK_PER_SECOND 1000 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 /* kservice options */ @@ -95,8 +98,6 @@ #define RT_USING_MEMPOOL #define RT_USING_SMALL_MEM -#define RT_USING_MEMHEAP -#define RT_MEMHEAP_FAST_MODE #define RT_USING_SMALL_MEM_AS_HEAP #define RT_USING_HEAP /* end of Memory Management */ @@ -112,14 +113,14 @@ #define RT_USING_COMPONENTS_INIT #define RT_USING_USER_MAIN -#define RT_MAIN_THREAD_STACK_SIZE 1024 +#define RT_MAIN_THREAD_STACK_SIZE 2048 #define RT_MAIN_THREAD_PRIORITY 10 #define RT_USING_MSH #define RT_USING_FINSH #define FINSH_USING_MSH #define FINSH_THREAD_NAME "tshell" #define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 1024 +#define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_USING_HISTORY #define FINSH_HISTORY_LINES 5 #define FINSH_USING_SYMTAB @@ -139,9 +140,9 @@ #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SERIAL #define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA #define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_I2C -#define RT_USING_I2C_BITOPS +#define RT_USING_ADC #define RT_USING_PIN /* end of Device Drivers */ @@ -297,8 +298,6 @@ /* touch drivers */ /* end of touch drivers */ -#define PKG_USING_AT24CXX -#define PKG_USING_AT24CXX_LATEST_VERSION /* end of peripheral libraries and drivers */ /* AI packages */ @@ -383,9 +382,8 @@ #define BSP_USING_UART3 /* end of UART Drivers */ -#define BSP_USING_I2C1 -#define BSP_I2C1_SCL_PIN 40 -#define BSP_I2C1_SDA_PIN 39 +#define BSP_USING_ADC +#define BSP_USING_ADC1 /* Flash Drivers */ diff --git a/bsp/mm32f526x/rtconfig.py b/bsp/mm32f526x/rtconfig.py index a8462c3056a..c292fce8de8 100644 --- a/bsp/mm32f526x/rtconfig.py +++ b/bsp/mm32f526x/rtconfig.py @@ -31,21 +31,22 @@ #BUILD = 'release' if PLATFORM == 'gcc': + # toolchains PREFIX = 'arm-none-eabi-' CC = PREFIX + 'gcc' - CXX = PREFIX + 'g++' AS = PREFIX + 'gcc' AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' LINK = PREFIX + 'gcc' TARGET_EXT = 'elf' SIZE = PREFIX + 'size' OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' - DEVICE = ' -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mthumb -ffunction-sections -fdata-sections -Wall' - CFLAGS = DEVICE + ' -std=c99' + DEVICE = ' -mcpu=cortex-m33 -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds' CPATH = '' LPATH = '' @@ -56,9 +57,12 @@ else: CFLAGS += ' -O2' + CXXFLAGS = CFLAGS + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' POST_ACTION += OBJCPY + ' -O ihex $TARGET rtthread.hex\n' POST_ACTION += SIZE + ' $TARGET\n' + elif PLATFORM == 'armcc': # toolchains CC = 'armcc'