Example Program doesn't appear to work

[lucasbanting]

The example program appears to have been update to vivado 2020.1.
Vivado 2020.1 has a bug: https://support.xilinx.com/s/article/75502?language=en_US

When I try to generate the block design for the sample project, I get the error:
[BD 41-237] Bus Interface property FREQ_HZ does not match between /xadc_wiz_0/s_axi_lite(100000000) and /axi_interconnect_0/xbar/M02_AXI(125000000)

Which appears to be related to the aforementioned Vivado bug. Does anyone have a currently working configuration they are using that works with the sample project?

[RHSResearchLLC]

I haven't yet updated the project to Vivado 2021. If you open in Vivado 2021, it should auto-update.

[lucasbanting]

For what it is worth I am running on an unsupported OS, but after pulling the last git commit 3 days ago I can now synthesize the project successfully. I am using vivado 2021.2, not 2021.1.

The only message I found when upgrading the IP's was:

2. Customization warnings

---

An attempt to modify the value of disabled parameter 'pf1_msix_cap_table_size' from '000' to '01F' has been ignored for IP 'project_bd_xdma_1_0'

An attempt to modify the value of disabled parameter 'pf1_msix_cap_table_offset' from '00000000' to '00009000' has been ignored for IP 'project_bd_xdma_1_0'

An attempt to modify the value of disabled parameter 'pf1_msix_cap_pba_offset' from '00000000' to '00009FE0' has been ignored for IP 'project_bd_xdma_1_0'

Should these be values be re-customized to remove the warning?