From 57fe870f2d1150cb191785283c2c29c1872018cf Mon Sep 17 00:00:00 2001
From: Luciano Bello <luciano.bello@ibm.com>
Date: Sun, 26 Apr 2020 14:31:15 -0400
Subject: [PATCH 01/13] drafting

---
 qiskit/visualization/circuit_visualization.py |  6 +++--
 qiskit/visualization/text.py                  | 10 ++++---
 .../visualization/test_circuit_text_drawer.py | 26 +++++++++++++++++++
 3 files changed, 36 insertions(+), 6 deletions(-)

diff --git a/qiskit/visualization/circuit_visualization.py b/qiskit/visualization/circuit_visualization.py
index 1407388e4372..5db8bb2f247f 100644
--- a/qiskit/visualization/circuit_visualization.py
+++ b/qiskit/visualization/circuit_visualization.py
@@ -406,7 +406,8 @@ def qx_color_scheme():
 
 def _text_circuit_drawer(circuit, filename=None, line_length=None, reverse_bits=False,
                          plot_barriers=True, justify=None, vertical_compression='high',
-                         idle_wires=True, with_layout=True, fold=None, initial_state=True):
+                         idle_wires=True, with_layout=True, fold=None, initial_state=True,
+                         cregbundle=False):
     """Draws a circuit using ascii art.
 
     Args:
@@ -442,7 +443,8 @@ def _text_circuit_drawer(circuit, filename=None, line_length=None, reverse_bits=
     if line_length:
         warn('The parameter "line_length" is being replaced by "fold"', DeprecationWarning, 3)
         fold = line_length
-    text_drawing = _text.TextDrawing(qregs, cregs, ops, layout=layout, initial_state=initial_state)
+    text_drawing = _text.TextDrawing(qregs, cregs, ops, layout=layout, initial_state=initial_state,
+                                     cregbundle=cregbundle)
     text_drawing.plotbarriers = plot_barriers
     text_drawing.line_length = fold
     text_drawing.vertical_compression = vertical_compression
diff --git a/qiskit/visualization/text.py b/qiskit/visualization/text.py
index 0f839046a63b..0ea4e00dd191 100644
--- a/qiskit/visualization/text.py
+++ b/qiskit/visualization/text.py
@@ -166,11 +166,11 @@ class MeasureTo(DrawElement):
         bot:
     """
 
-    def __init__(self):
+    def __init__(self, label=''):
         super().__init__()
         self.top_connect = " ║ "
         self.mid_content = "═╩═"
-        self.bot_connect = "   "
+        self.bot_connect = label
         self.mid_bck = "═"
 
 
@@ -495,13 +495,15 @@ class TextDrawing():
     """ The text drawing"""
 
     def __init__(self, qregs, cregs, instructions, plotbarriers=True,
-                 line_length=None, vertical_compression='high', layout=None, initial_state=True):
+                 line_length=None, vertical_compression='high', layout=None, initial_state=True,
+                 cregbundle=False):
         self.qregs = qregs
         self.cregs = cregs
         self.instructions = instructions
         self.layout = layout
         self.initial_state = initial_state
 
+        self.cregbundle = cregbundle
         self.plotbarriers = plotbarriers
         self.line_length = line_length
         if vertical_compression not in ['high', 'medium', 'low']:
@@ -984,7 +986,7 @@ def build_layers(self):
         if not wire_names:
             return []
 
-        layers = [InputWire.fillup_layer(wire_names)]
+        layers = [InputWire.fillup_layer(wire_names, cregbundle=self.cregbundle)]
 
         for instruction_layer in self.instructions:
             layer = Layer(self.qregs, self.cregs)
diff --git a/test/python/visualization/test_circuit_text_drawer.py b/test/python/visualization/test_circuit_text_drawer.py
index 33d62b98b720..a3f5a323922b 100644
--- a/test/python/visualization/test_circuit_text_drawer.py
+++ b/test/python/visualization/test_circuit_text_drawer.py
@@ -60,6 +60,14 @@ def test_measure_to(self):
                     "   "]
         self.assertEqualElement(expected, element)
 
+    def test_measure_to_label(self):
+        """ MeasureTo element with cregbundle """
+        element = elements.MeasureTo('1')
+        expected = [" ║ ",
+                    "═╩═",
+                    " 1 "]
+        self.assertEqualElement(expected, element)
+
     def test_measure_from(self):
         """ MeasureFrom element. """
         element = elements.MeasureFrom()
@@ -124,6 +132,24 @@ def test_text_no_pager(self):
 class TestTextDrawerGatesInCircuit(QiskitTestCase):
     """ Gate by gate checks in different settings."""
 
+    def test_text_measure_cregbundle(self):
+        """ The measure operator, using 3-bit-length registers with cregbundle=True. """
+        expected = '\n'.join(['        ┌─┐      ',
+                              'q_0: |0>┤M├──────',
+                              '        └╥┘┌─┐   ',
+                              'q_1: |0>─╫─┤M├───',
+                              '         ║ └╥┘┌─┐',
+                              'q_2: |0>─╫──╫─┤M├',
+                              '         ║  ║ └╥┘',
+                              ' c: 0 3/═╩══╩══╩═',
+                              '         1  2  3 '])
+
+        qr = QuantumRegister(3, 'q')
+        cr = ClassicalRegister(3, 'c')
+        circuit = QuantumCircuit(qr, cr)
+        circuit.measure(qr, cr)
+        self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=True)), expected)
+
     def test_text_measure_1(self):
         """ The measure operator, using 3-bit-length registers. """
         expected = '\n'.join(['        ┌─┐      ',

From 56a0a331ea5fbc8f1d4c50d200468e7be00348c5 Mon Sep 17 00:00:00 2001
From: Luciano Bello <luciano.bello@ibm.com>
Date: Sun, 26 Apr 2020 14:57:50 -0400
Subject: [PATCH 02/13] size

---
 qiskit/visualization/text.py                     | 16 +++++++++++++---
 .../visualization/test_circuit_text_drawer.py    |  2 +-
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/qiskit/visualization/text.py b/qiskit/visualization/text.py
index 0ea4e00dd191..21a76abfedfb 100644
--- a/qiskit/visualization/text.py
+++ b/qiskit/visualization/text.py
@@ -638,9 +638,19 @@ def wire_names(self, with_initial_state=False):
                                                  index=self.layout[bit.index].index,
                                                  physical=bit.index))
         clbit_labels = []
+        previous_creg = None
         for bit in self.cregs:
-            label = '{name}_{index}: ' + initial_clbit_value
-            clbit_labels.append(label.format(name=bit.register.name, index=bit.index))
+            if self.cregbundle:
+                if previous_creg == bit.register:
+                    continue
+                previous_creg = bit.register
+                label = '{name}: {initial_value} {size}/'
+                clbit_labels.append(label.format(name=bit.register.name,
+                                                 initial_value=initial_clbit_value,
+                                                 size=bit.register.size))
+            else:
+                label = '{name}_{index}: ' + initial_clbit_value
+                clbit_labels.append(label.format(name=bit.register.name, index=bit.index))
         return qubit_labels + clbit_labels
 
     def should_compress(self, top_line, bot_line):
@@ -986,7 +996,7 @@ def build_layers(self):
         if not wire_names:
             return []
 
-        layers = [InputWire.fillup_layer(wire_names, cregbundle=self.cregbundle)]
+        layers = [InputWire.fillup_layer(wire_names)]
 
         for instruction_layer in self.instructions:
             layer = Layer(self.qregs, self.cregs)
diff --git a/test/python/visualization/test_circuit_text_drawer.py b/test/python/visualization/test_circuit_text_drawer.py
index a3f5a323922b..0c3811fb8185 100644
--- a/test/python/visualization/test_circuit_text_drawer.py
+++ b/test/python/visualization/test_circuit_text_drawer.py
@@ -143,7 +143,7 @@ def test_text_measure_cregbundle(self):
                               '         ║  ║ └╥┘',
                               ' c: 0 3/═╩══╩══╩═',
                               '         1  2  3 '])
-
+        expected = ''
         qr = QuantumRegister(3, 'q')
         cr = ClassicalRegister(3, 'c')
         circuit = QuantumCircuit(qr, cr)

From d0b13a04f1fccecad48748d8ffcc56204edc6065 Mon Sep 17 00:00:00 2001
From: Luciano Bello <luciano.bello@ibm.com>
Date: Sun, 26 Apr 2020 15:29:53 -0400
Subject: [PATCH 03/13] layer is cregbundle aware

---
 qiskit/visualization/text.py | 25 ++++++++++++++++++++-----
 1 file changed, 20 insertions(+), 5 deletions(-)

diff --git a/qiskit/visualization/text.py b/qiskit/visualization/text.py
index 21a76abfedfb..4a7ff8be482d 100644
--- a/qiskit/visualization/text.py
+++ b/qiskit/visualization/text.py
@@ -897,7 +897,10 @@ def add_connected_gate(instruction, gates, layer, current_cons):
         elif instruction.name == 'measure':
             gate = MeasureFrom()
             layer.set_qubit(instruction.qargs[0], gate)
-            layer.set_clbit(instruction.cargs[0], MeasureTo())
+            if self.cregbundle:
+                layer.set_clbit(instruction.cargs[0], MeasureTo(str(instruction.cargs[0].index)))
+            else:
+                layer.set_clbit(instruction.cargs[0], MeasureTo())
 
         elif instruction.name in ['barrier', 'snapshot', 'save', 'load', 'noise']:
             # barrier
@@ -999,7 +1002,7 @@ def build_layers(self):
         layers = [InputWire.fillup_layer(wire_names)]
 
         for instruction_layer in self.instructions:
-            layer = Layer(self.qregs, self.cregs)
+            layer = Layer(self.qregs, self.cregs, self.cregbundle)
 
             for instruction in instruction_layer:
                 layer, current_connections, connection_label = \
@@ -1015,12 +1018,21 @@ def build_layers(self):
 class Layer:
     """ A layer is the "column" of the circuit. """
 
-    def __init__(self, qregs, cregs):
+    def __init__(self, qregs, cregs, cregbundle=False):
         self.qregs = qregs
-        self.cregs = cregs
+        if cregbundle:
+            self.cregs = []
+            previous_creg = None
+            for bit in cregs:
+                if previous_creg == bit.register:
+                    continue
+                self.cregs.append(bit.register)
+        else:
+            self.cregs = cregs
         self.qubit_layer = [None] * len(qregs)
         self.connections = []
         self.clbit_layer = [None] * len(cregs)
+        self.cregbundle = cregbundle
 
     @property
     def full_layer(self):
@@ -1047,7 +1059,10 @@ def set_clbit(self, clbit, element):
             clbit (cbit): Element of self.cregs.
             element (DrawElement): Element to set in the clbit
         """
-        self.clbit_layer[self.cregs.index(clbit)] = element
+        if self.cregbundle:
+            self.clbit_layer[self.cregs.index(clbit.register)] = element
+        else:
+            self.clbit_layer[self.cregs.index(clbit)] = element
 
     def _set_multibox(self, label, qubits=None, clbits=None, top_connect=None,
                       bot_connect=None, conditional=False, controlled_edge=None):

From 4ff139c3c9d3159b9fb7ef6e452e7d6b3e73b540 Mon Sep 17 00:00:00 2001
From: Luciano Bello <luciano.bello@ibm.com>
Date: Sun, 26 Apr 2020 15:31:48 -0400
Subject: [PATCH 04/13] test

---
 .../visualization/test_circuit_text_drawer.py | 20 +++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/test/python/visualization/test_circuit_text_drawer.py b/test/python/visualization/test_circuit_text_drawer.py
index 0c3811fb8185..e63431e4b4b4 100644
--- a/test/python/visualization/test_circuit_text_drawer.py
+++ b/test/python/visualization/test_circuit_text_drawer.py
@@ -134,16 +134,16 @@ class TestTextDrawerGatesInCircuit(QiskitTestCase):
 
     def test_text_measure_cregbundle(self):
         """ The measure operator, using 3-bit-length registers with cregbundle=True. """
-        expected = '\n'.join(['        ┌─┐      ',
-                              'q_0: |0>┤M├──────',
-                              '        └╥┘┌─┐   ',
-                              'q_1: |0>─╫─┤M├───',
-                              '         ║ └╥┘┌─┐',
-                              'q_2: |0>─╫──╫─┤M├',
-                              '         ║  ║ └╥┘',
-                              ' c: 0 3/═╩══╩══╩═',
-                              '         1  2  3 '])
-        expected = ''
+        expected = '\n'.join(["        ┌─┐      "
+                              "q_0: |0>┤M├──────"
+                              "        └╥┘┌─┐   "
+                              "q_1: |0>─╫─┤M├───"
+                              "         ║ └╥┘┌─┐"
+                              "q_2: |0>─╫──╫─┤M├"
+                              "         ║  ║ └╥┘"
+                              "c: 0  3/═╩══╩══╩═"
+                              "         0  1  2 "])
+
         qr = QuantumRegister(3, 'q')
         cr = ClassicalRegister(3, 'c')
         circuit = QuantumCircuit(qr, cr)

From ca561ded609b72396d30746571d3aa2709d1a2c3 Mon Sep 17 00:00:00 2001
From: Luciano Bello <luciano.bello@ibm.com>
Date: Mon, 27 Apr 2020 12:49:43 -0400
Subject: [PATCH 05/13] expose it in .draw()

---
 qiskit/circuit/quantumcircuit.py                 |  7 +++++--
 qiskit/visualization/circuit_visualization.py    |  8 ++++++--
 qiskit/visualization/text.py                     |  3 ++-
 .../visualization/test_circuit_text_drawer.py    | 16 ++++++++--------
 4 files changed, 21 insertions(+), 13 deletions(-)

diff --git a/qiskit/circuit/quantumcircuit.py b/qiskit/circuit/quantumcircuit.py
index d94c9e580f4b..2e860e016fac 100644
--- a/qiskit/circuit/quantumcircuit.py
+++ b/qiskit/circuit/quantumcircuit.py
@@ -749,7 +749,7 @@ def qasm(self, formatted=False, filename=None):
     def draw(self, output=None, scale=0.7, filename=None, style=None,
              interactive=False, line_length=None, plot_barriers=True,
              reverse_bits=False, justify=None, vertical_compression='medium', idle_wires=True,
-             with_layout=True, fold=None, ax=None, initial_state=False):
+             with_layout=True, fold=None, ax=None, initial_state=False, cregbundle=True):
         """Draw the quantum circuit.
 
         **text**: ASCII art TextDrawing that can be printed in the console.
@@ -822,6 +822,8 @@ def draw(self, output=None, scale=0.7, filename=None, style=None,
             initial_state (bool): Optional. Adds ``|0>`` in the beginning of the wire.
                 Only used by the ``text``, ``latex`` and ``latex_source`` outputs.
                 Default: ``False``.
+            cregbundle (bool): Optional. If set True bundle classical registers. Only used by
+                the ``text`` output. Default: ``True``.
 
         Returns:
             :class:`PIL.Image` or :class:`matplotlib.figure` or :class:`str` or
@@ -964,7 +966,8 @@ def draw(self, output=None, scale=0.7, filename=None, style=None,
                               with_layout=with_layout,
                               fold=fold,
                               ax=ax,
-                              initial_state=initial_state)
+                              initial_state=initial_state,
+                              cregbundle=cregbundle)
 
     def size(self):
         """Returns total number of gate operations in circuit.
diff --git a/qiskit/visualization/circuit_visualization.py b/qiskit/visualization/circuit_visualization.py
index 5db8bb2f247f..fad7177c1abd 100644
--- a/qiskit/visualization/circuit_visualization.py
+++ b/qiskit/visualization/circuit_visualization.py
@@ -65,7 +65,8 @@ def circuit_drawer(circuit,
                    with_layout=True,
                    fold=None,
                    ax=None,
-                   initial_state=False):
+                   initial_state=False,
+                   cregbundle=True):
     """Draw a quantum circuit to different formats (set by output parameter):
 
     **text**: ASCII art TextDrawing that can be printed in the console.
@@ -137,6 +138,8 @@ def circuit_drawer(circuit,
         initial_state (bool): Optional. Adds ``|0>`` in the beginning of the wire.
             Only used by the ``text``, ``latex`` and ``latex_source`` outputs.
             Default: ``False``.
+        cregbundle (bool): Optional. If set True bundle classical registers. Only used by
+            the ``text`` output. Default: ``True``.
     Returns:
         :class:`PIL.Image` or :class:`matplotlib.figure` or :class:`str` or
         :class:`TextDrawing`:
@@ -286,7 +289,8 @@ def circuit_drawer(circuit,
                                     idle_wires=idle_wires,
                                     with_layout=with_layout,
                                     fold=fold,
-                                    initial_state=initial_state)
+                                    initial_state=initial_state,
+                                    cregbundle=cregbundle)
     elif output == 'latex':
         image = _latex_circuit_drawer(circuit, scale=scale,
                                       filename=filename, style=style,
diff --git a/qiskit/visualization/text.py b/qiskit/visualization/text.py
index 90b92a123267..1ba32e970e4f 100644
--- a/qiskit/visualization/text.py
+++ b/qiskit/visualization/text.py
@@ -649,7 +649,8 @@ def wire_names(self, with_initial_state=False):
                 if previous_creg == bit.register:
                     continue
                 previous_creg = bit.register
-                label = '{name}: {initial_value} {size}/'
+                label = '{name}: {initial_value}{size}/'
+                print('-'+initial_clbit_value+'-')
                 clbit_labels.append(label.format(name=bit.register.name,
                                                  initial_value=initial_clbit_value,
                                                  size=bit.register.size))
diff --git a/test/python/visualization/test_circuit_text_drawer.py b/test/python/visualization/test_circuit_text_drawer.py
index 6789f0e11011..50a7fea1302b 100644
--- a/test/python/visualization/test_circuit_text_drawer.py
+++ b/test/python/visualization/test_circuit_text_drawer.py
@@ -134,14 +134,14 @@ class TestTextDrawerGatesInCircuit(QiskitTestCase):
 
     def test_text_measure_cregbundle(self):
         """ The measure operator, using 3-bit-length registers with cregbundle=True. """
-        expected = '\n'.join(["        ┌─┐      "
-                              "q_0: |0>┤M├──────"
-                              "        └╥┘┌─┐   "
-                              "q_1: |0>─╫─┤M├───"
-                              "         ║ └╥┘┌─┐"
-                              "q_2: |0>─╫──╫─┤M├"
-                              "         ║  ║ └╥┘"
-                              "c: 0  3/═╩══╩══╩═"
+        expected = '\n'.join(["        ┌─┐      ",
+                              "q_0: |0>┤M├──────",
+                              "        └╥┘┌─┐   ",
+                              "q_1: |0>─╫─┤M├───",
+                              "         ║ └╥┘┌─┐",
+                              "q_2: |0>─╫──╫─┤M├",
+                              "         ║  ║ └╥┘",
+                              "c: 0  3/═╩══╩══╩═",
                               "         0  1  2 "])
 
         qr = QuantumRegister(3, 'q')

From ec7ea812a8d2c47267a788b34dfd841d9eb6c802 Mon Sep 17 00:00:00 2001
From: Luciano Bello <luciano.bello@ibm.com>
Date: Mon, 27 Apr 2020 12:52:49 -0400
Subject: [PATCH 06/13] print

---
 qiskit/visualization/text.py | 1 -
 1 file changed, 1 deletion(-)

diff --git a/qiskit/visualization/text.py b/qiskit/visualization/text.py
index 1ba32e970e4f..b943762faab3 100644
--- a/qiskit/visualization/text.py
+++ b/qiskit/visualization/text.py
@@ -650,7 +650,6 @@ def wire_names(self, with_initial_state=False):
                     continue
                 previous_creg = bit.register
                 label = '{name}: {initial_value}{size}/'
-                print('-'+initial_clbit_value+'-')
                 clbit_labels.append(label.format(name=bit.register.name,
                                                  initial_value=initial_clbit_value,
                                                  size=bit.register.size))

From 193238f7aa78b0b0f2d612ef80a40bb3f34ca2dd Mon Sep 17 00:00:00 2001
From: Luciano Bello <luciano.bello@ibm.com>
Date: Mon, 27 Apr 2020 12:55:41 -0400
Subject: [PATCH 07/13] scale docstring

---
 qiskit/visualization/circuit_visualization.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/qiskit/visualization/circuit_visualization.py b/qiskit/visualization/circuit_visualization.py
index fad7177c1abd..71140f8157a3 100644
--- a/qiskit/visualization/circuit_visualization.py
+++ b/qiskit/visualization/circuit_visualization.py
@@ -79,7 +79,8 @@ def circuit_drawer(circuit,
 
     Args:
         circuit (QuantumCircuit): the quantum circuit to draw
-        scale (float): scale of image to draw (shrink if < 1)
+        scale (float): scale of image to draw (shrink if < 1). Only used by the ``mpl``,
+            ``latex``, and ``latex_source`` outputs.
         filename (str): file path to save image to
         style (dict or str): dictionary of style or file name of style file.
             This option is only used by the ``mpl`` output type. If a str is

From 950c17796a96c48788ccbf4ca85d4af46c0c6367 Mon Sep 17 00:00:00 2001
From: Luciano Bello <luciano.bello@ibm.com>
Date: Mon, 27 Apr 2020 13:04:51 -0400
Subject: [PATCH 08/13] lint

---
 qiskit/visualization/circuit_visualization.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/qiskit/visualization/circuit_visualization.py b/qiskit/visualization/circuit_visualization.py
index 71140f8157a3..aeb90f6d83a3 100644
--- a/qiskit/visualization/circuit_visualization.py
+++ b/qiskit/visualization/circuit_visualization.py
@@ -434,6 +434,8 @@ def _text_circuit_drawer(circuit, filename=None, line_length=None, reverse_bits=
                     `shutil.get_terminal_size()`. If you don't want pagination
                    at all, set `fold=-1`.
         initial_state (bool): Optional. Adds |0> in the beginning of the line. Default: `True`.
+        cregbundle (bool): Optional. If set True bundle classical registers. Only used by
+            the ``text`` output. Default: ``False``.
     Returns:
         TextDrawing: An instances that, when printed, draws the circuit in ascii art.
     """

From daaab296e1474ade052e0532f41faaeaf7a203a7 Mon Sep 17 00:00:00 2001
From: Luciano Bello <luciano.bello@ibm.com>
Date: Mon, 27 Apr 2020 14:09:13 -0400
Subject: [PATCH 09/13] test adjustment

---
 .../python/visualization/test_circuit_text_drawer.py | 12 +++++++-----
 .../test_circuit_visualization_output.py             |  3 ++-
 2 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/test/python/visualization/test_circuit_text_drawer.py b/test/python/visualization/test_circuit_text_drawer.py
index 50a7fea1302b..a1243e593c5c 100644
--- a/test/python/visualization/test_circuit_text_drawer.py
+++ b/test/python/visualization/test_circuit_text_drawer.py
@@ -141,7 +141,7 @@ def test_text_measure_cregbundle(self):
                               "         ║ └╥┘┌─┐",
                               "q_2: |0>─╫──╫─┤M├",
                               "         ║  ║ └╥┘",
-                              "c: 0  3/═╩══╩══╩═",
+                              " c: 0 3/═╩══╩══╩═",
                               "         0  1  2 "])
 
         qr = QuantumRegister(3, 'q')
@@ -2633,7 +2633,7 @@ def test_after_transpile(self):
                         [13, 12]]
         qc_result = transpile(qc, basis_gates=['u1', 'u2', 'u3', 'cx', 'id'],
                               coupling_map=coupling_map, optimization_level=0, seed_transpiler=0)
-        self.assertEqual(qc_result.draw(output='text').single_string(), expected)
+        self.assertEqual(qc_result.draw(output='text', cregbundle=False).single_string(), expected)
 
 
 class TestTextInitialValue(QiskitTestCase):
@@ -2657,7 +2657,8 @@ def test_draw_initial_value_default(self):
                               "c_1: ════╩═",
                               "           "])
 
-        self.assertEqual(self.circuit.draw(output='text').single_string(), expected)
+        self.assertEqual(self.circuit.draw(output='text', cregbundle=False).single_string(),
+                         expected)
 
     def test_draw_initial_value_true(self):
         """ Text drawer .draw(initial_state=True). """
@@ -2670,8 +2671,9 @@ def test_draw_initial_value_true(self):
                               "            ║ ",
                               " c_1: 0 ════╩═",
                               "              "])
-        self.assertEqual(self.circuit.draw(output='text', initial_state=True).single_string(),
-                         expected)
+        self.assertEqual(self.circuit.draw(output='text',
+                                           initial_state=True,
+                                           cregbundle=False).single_string(), expected)
 
     def test_initial_value_false(self):
         """ Text drawer with initial_state parameter False. """
diff --git a/test/python/visualization/test_circuit_visualization_output.py b/test/python/visualization/test_circuit_visualization_output.py
index 4476b2856e79..6e4938fa5288 100644
--- a/test/python/visualization/test_circuit_visualization_output.py
+++ b/test/python/visualization/test_circuit_visualization_output.py
@@ -100,7 +100,8 @@ def test_matplotlib_drawer(self):
     def test_text_drawer(self):
         filename = self._get_resource_path('current_textplot.txt')
         qc = self.sample_circuit()
-        output = circuit_drawer(qc, filename=filename, output="text", fold=-1, initial_state=True)
+        output = circuit_drawer(qc, filename=filename, output="text", fold=-1, initial_state=True,
+                                cregbundle=False)
         self.assertFilesAreEqual(filename, self.text_reference)
         os.remove(filename)
         try:

From 0c18f2e1b644ccfc4d80f0979854e27783ae22ae Mon Sep 17 00:00:00 2001
From: Luciano Bello <luciano.bello@ibm.com>
Date: Mon, 27 Apr 2020 16:33:00 -0400
Subject: [PATCH 10/13] multiple cregs

---
 qiskit/visualization/text.py                  |  2 ++
 .../visualization/test_circuit_text_drawer.py | 20 +++++++++++++++++++
 2 files changed, 22 insertions(+)

diff --git a/qiskit/visualization/text.py b/qiskit/visualization/text.py
index f9b7470c4a86..63af44b39522 100644
--- a/qiskit/visualization/text.py
+++ b/qiskit/visualization/text.py
@@ -810,6 +810,8 @@ def merge_lines(top, bot, icod="top"):
                 ret += "┬"
             elif topc in "┘└" and botc in "─" and icod == 'top':
                 ret += "┴"
+            elif botc == " " and icod == 'top':
+                ret += topc
             else:
                 ret += botc
         return ret
diff --git a/test/python/visualization/test_circuit_text_drawer.py b/test/python/visualization/test_circuit_text_drawer.py
index a1243e593c5c..73afa088f57b 100644
--- a/test/python/visualization/test_circuit_text_drawer.py
+++ b/test/python/visualization/test_circuit_text_drawer.py
@@ -150,6 +150,26 @@ def test_text_measure_cregbundle(self):
         circuit.measure(qr, cr)
         self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=True)), expected)
 
+    def test_text_measure_cregbundle_2(self):
+        """ The measure operator, using 2 classical registers with cregbundle=True. """
+        expected = '\n'.join(["        ┌─┐   ",
+                              "q_0: |0>┤M├───",
+                              "        └╥┘┌─┐",
+                              "q_1: |0>─╫─┤M├",
+                              "         ║ └╥┘",
+                              "cA: 0 1/═╩══╬═",
+                              "         0  ║ ",
+                              "cB: 0 1/════╩═",
+                              "            0 "])
+
+        qr = QuantumRegister(2, 'q')
+        crA = ClassicalRegister(1, 'cA')
+        crB = ClassicalRegister(1, 'cB')
+        circuit = QuantumCircuit(qr, crA, crB)
+        circuit.measure(qr[0], crA[0])
+        circuit.measure(qr[1], crB[0])
+        self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=True)), expected)
+
     def test_text_measure_1(self):
         """ The measure operator, using 3-bit-length registers. """
         expected = '\n'.join(['        ┌─┐      ',

From 6672f845a9fcf55ca4fbd8812e63bfde3efb2a68 Mon Sep 17 00:00:00 2001
From: Luciano Bello <luciano.bello@ibm.com>
Date: Mon, 27 Apr 2020 17:28:30 -0400
Subject: [PATCH 11/13] lint

---
 test/python/visualization/test_circuit_text_drawer.py | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/test/python/visualization/test_circuit_text_drawer.py b/test/python/visualization/test_circuit_text_drawer.py
index 73afa088f57b..9cf090284925 100644
--- a/test/python/visualization/test_circuit_text_drawer.py
+++ b/test/python/visualization/test_circuit_text_drawer.py
@@ -163,11 +163,11 @@ def test_text_measure_cregbundle_2(self):
                               "            0 "])
 
         qr = QuantumRegister(2, 'q')
-        crA = ClassicalRegister(1, 'cA')
-        crB = ClassicalRegister(1, 'cB')
-        circuit = QuantumCircuit(qr, crA, crB)
-        circuit.measure(qr[0], crA[0])
-        circuit.measure(qr[1], crB[0])
+        cr_A = ClassicalRegister(1, 'cA')
+        cr_B = ClassicalRegister(1, 'cB')
+        circuit = QuantumCircuit(qr, cr_A, cr_B)
+        circuit.measure(qr[0], cr_A[0])
+        circuit.measure(qr[1], cr_B[0])
         self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=True)), expected)
 
     def test_text_measure_1(self):

From fa34491e8fd37fd47c728722a7510a915920dd48 Mon Sep 17 00:00:00 2001
From: Luciano Bello <luciano.bello@ibm.com>
Date: Mon, 27 Apr 2020 18:04:21 -0400
Subject: [PATCH 12/13] conditional

---
 qiskit/visualization/text.py                  |  8 +++-
 .../visualization/test_circuit_text_drawer.py | 43 +++++++++++++++++++
 2 files changed, 49 insertions(+), 2 deletions(-)

diff --git a/qiskit/visualization/text.py b/qiskit/visualization/text.py
index 63af44b39522..f10bf5954297 100644
--- a/qiskit/visualization/text.py
+++ b/qiskit/visualization/text.py
@@ -1043,6 +1043,7 @@ def __init__(self, qregs, cregs, cregbundle=False):
             for bit in cregs:
                 if previous_creg == bit.register:
                     continue
+                previous_creg = bit.register
                 self.cregs.append(bit.register)
         else:
             self.cregs = cregs
@@ -1183,8 +1184,11 @@ def set_cl_multibox(self, creg, label, top_connect='┴'):
             label (string): The label for the multi clbit box.
             top_connect (char): The char to connect the box on the top.
         """
-        clbit = [bit for bit in self.cregs if bit.register == creg]
-        self._set_multibox(label, clbits=clbit, top_connect=top_connect)
+        if self.cregbundle:
+            self.set_clbit(creg[0], BoxOnClWire(label=label, top_connect=top_connect))
+        else:
+            clbit = [bit for bit in self.cregs if bit.register == creg]
+            self._set_multibox(label, clbits=clbit, top_connect=top_connect)
 
     def set_qu_multibox(self, bits, label, top_connect=None, bot_connect=None,
                         conditional=False, controlled_edge=None):
diff --git a/test/python/visualization/test_circuit_text_drawer.py b/test/python/visualization/test_circuit_text_drawer.py
index 9cf090284925..77add22c792e 100644
--- a/test/python/visualization/test_circuit_text_drawer.py
+++ b/test/python/visualization/test_circuit_text_drawer.py
@@ -1188,6 +1188,28 @@ def test_text_measure_with_spaces(self):
 class TestTextConditional(QiskitTestCase):
     """Gates with conditionals"""
 
+    def test_text_conditional_1_cregbundle(self):
+        """ Conditional drawing with 1-bit-length regs and cregbundle."""
+        qasm_string = """
+        OPENQASM 2.0;
+        include "qelib1.inc";
+        qreg q[1];
+        creg c0[1];
+        creg c1[1];
+        if(c0==1) x q[0];
+        if(c1==1) x q[0];
+        """
+        expected = '\n'.join(["         ┌───┐  ┌───┐ ",
+                              "q_0: |0>─┤ X ├──┤ X ├─",
+                              "        ┌┴─┴─┴┐ └─┬─┘ ",
+                              "c0: 0 1/╡ = 1 ╞═══╪═══",
+                              "        └─────┘┌──┴──┐",
+                              "c1: 0 1/═══════╡ = 1 ╞",
+                              "               └─────┘"])
+
+        circuit = QuantumCircuit.from_qasm_str(qasm_string)
+        self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=True)), expected)
+
     def test_text_conditional_1(self):
         """ Conditional drawing with 1-bit-length regs."""
         qasm_string = """
@@ -1210,6 +1232,27 @@ def test_text_conditional_1(self):
         circuit = QuantumCircuit.from_qasm_str(qasm_string)
         self.assertEqual(str(_text_circuit_drawer(circuit)), expected)
 
+    def test_text_conditional_2_cregbundle(self):
+        """ Conditional drawing with 2-bit-length regs with cregbundle"""
+        qasm_string = """
+        OPENQASM 2.0;
+        include "qelib1.inc";
+        qreg q[1];
+        creg c0[2];
+        creg c1[2];
+        if(c0==2) x q[0];
+        if(c1==2) x q[0];
+        """
+        expected = '\n'.join(["         ┌───┐  ┌───┐ ",
+                              "q_0: |0>─┤ X ├──┤ X ├─",
+                              "        ┌┴─┴─┴┐ └─┬─┘ ",
+                              "c0: 0 2/╡ = 2 ╞═══╪═══",
+                              "        └─────┘┌──┴──┐",
+                              "c1: 0 2/═══════╡ = 2 ╞",
+                              "               └─────┘"])
+        circuit = QuantumCircuit.from_qasm_str(qasm_string)
+        self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=True)), expected)
+
     def test_text_conditional_2(self):
         """ Conditional drawing with 2-bit-length regs."""
         qasm_string = """

From 19bee26bf3f64b9320c58304237969d911c8f479 Mon Sep 17 00:00:00 2001
From: Luciano Bello <luciano.bello@ibm.com>
Date: Mon, 27 Apr 2020 18:07:20 -0400
Subject: [PATCH 13/13] lint

---
 test/python/visualization/test_circuit_text_drawer.py | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/test/python/visualization/test_circuit_text_drawer.py b/test/python/visualization/test_circuit_text_drawer.py
index 77add22c792e..df0e046f2d26 100644
--- a/test/python/visualization/test_circuit_text_drawer.py
+++ b/test/python/visualization/test_circuit_text_drawer.py
@@ -163,11 +163,11 @@ def test_text_measure_cregbundle_2(self):
                               "            0 "])
 
         qr = QuantumRegister(2, 'q')
-        cr_A = ClassicalRegister(1, 'cA')
-        cr_B = ClassicalRegister(1, 'cB')
-        circuit = QuantumCircuit(qr, cr_A, cr_B)
-        circuit.measure(qr[0], cr_A[0])
-        circuit.measure(qr[1], cr_B[0])
+        cr_a = ClassicalRegister(1, 'cA')
+        cr_b = ClassicalRegister(1, 'cB')
+        circuit = QuantumCircuit(qr, cr_a, cr_b)
+        circuit.measure(qr[0], cr_a[0])
+        circuit.measure(qr[1], cr_b[0])
         self.assertEqual(str(_text_circuit_drawer(circuit, cregbundle=True)), expected)
 
     def test_text_measure_1(self):