From 27c58426b566012f155867d88830108fc887bac7 Mon Sep 17 00:00:00 2001 From: "mergify[bot]" <37929162+mergify[bot]@users.noreply.github.com> Date: Mon, 8 Jul 2024 11:43:35 +0000 Subject: [PATCH] Remove DenseLayout from default pipeline (#12731) (#12732) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Jake Lishman (cherry picked from commit 865081e4afbb08225f7f12a3b55a0322e4574f97) Co-authored-by: Elena Peña Tapia <57907331+ElePT@users.noreply.github.com> --- qiskit/transpiler/__init__.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/qiskit/transpiler/__init__.py b/qiskit/transpiler/__init__.py index 12d9b9056b80..d4aad32cf7e4 100644 --- a/qiskit/transpiler/__init__.py +++ b/qiskit/transpiler/__init__.py @@ -650,8 +650,6 @@ .. image:: /source_images/mapping.png - - By default, qiskit will do this mapping for you. The choice of mapping depends on the properties of the circuit, the particular device you are targeting, and the optimization level that is chosen. The choice of initial layout is extremely important for minimizing the @@ -684,10 +682,12 @@ :class:`~.SabreLayout` is used to select a layout if a perfect layout isn't found for optimization levels 1, 2, and 3. - :class:`~.TrivialLayout`: Always used for the layout at optimization level 0. + +There are other passes than can be used for the heuristic stage, but are not included in the default +pipeline, such as: + - :class:`~.DenseLayout`: Finds the sub-graph of the device with greatest connectivity - that has the same number of qubits as the circuit. Used for - optimization level 1 if there are control flow operations (such as - :class:`~.IfElseOp`) present in the circuit. + that has the same number of qubits as the circuit. Let's see what layouts are automatically picked at various optimization levels. The circuits returned by :func:`qiskit.compiler.transpile` are annotated with this initial layout information,