diff --git a/test/python/circuit/test_compose.py b/test/python/circuit/test_compose.py
index d5b984c22fb5..f8b72a87018d 100644
--- a/test/python/circuit/test_compose.py
+++ b/test/python/circuit/test_compose.py
@@ -21,6 +21,7 @@
 from qiskit.circuit import (
     QuantumRegister,
     ClassicalRegister,
+    Clbit,
     QuantumCircuit,
     Parameter,
     Gate,
@@ -592,6 +593,64 @@ def test_wrapping_unitary_circuit(self):
             qc = qc_init.compose(qc_nonunitary, wrap=True)
             self.assertIsInstance(qc.data[1][0], Instruction)
 
+    def test_single_bit_condition(self):
+        """Test that compose can correctly handle circuits that contain conditions on single
+        bits.  This is a regression test of the bug that broke qiskit-experiments in gh-7653."""
+        base = QuantumCircuit(1, 1)
+        base.x(0).c_if(0, True)
+        test = QuantumCircuit(1, 1).compose(base)
+        self.assertIsNot(base.clbits[0], test.clbits[0])
+        self.assertEqual(base, test)
+        self.assertIs(test.data[0][0].condition[0], test.clbits[0])
+
+    def test_condition_mapping_ifelseop(self):
+        """Test that the condition in an `IfElseOp` is correctly mapped to a new set of bits and
+        registers."""
+        base_loose = Clbit()
+        base_creg = ClassicalRegister(2)
+        base_qreg = QuantumRegister(1)
+        base = QuantumCircuit(base_qreg, [base_loose], base_creg)
+        with base.if_test((base_loose, True)):
+            base.x(0)
+        with base.if_test((base_creg, 3)):
+            base.x(0)
+
+        test_loose = Clbit()
+        test_creg = ClassicalRegister(2)
+        test_qreg = QuantumRegister(1)
+        test = QuantumCircuit(test_qreg, [test_loose], test_creg).compose(base)
+
+        bit_instruction, *_ = test.data[0]
+        reg_instruction, *_ = test.data[1]
+        self.assertIs(bit_instruction.condition[0], test_loose)
+        self.assertEqual(bit_instruction.condition, (test_loose, True))
+        self.assertIs(reg_instruction.condition[0], test_creg)
+        self.assertEqual(reg_instruction.condition, (test_creg, 3))
+
+    def test_condition_mapping_whileloopop(self):
+        """Test that the condition in a `WhileLoopOp` is correctly mapped to a new set of bits and
+        registers."""
+        base_loose = Clbit()
+        base_creg = ClassicalRegister(2)
+        base_qreg = QuantumRegister(1)
+        base = QuantumCircuit(base_qreg, [base_loose], base_creg)
+        with base.while_loop((base_loose, True)):
+            base.x(0)
+        with base.while_loop((base_creg, 3)):
+            base.x(0)
+
+        test_loose = Clbit()
+        test_creg = ClassicalRegister(2)
+        test_qreg = QuantumRegister(1)
+        test = QuantumCircuit(test_qreg, [test_loose], test_creg).compose(base)
+
+        bit_instruction, *_ = test.data[0]
+        reg_instruction, *_ = test.data[1]
+        self.assertIs(bit_instruction.condition[0], test_loose)
+        self.assertEqual(bit_instruction.condition, (test_loose, True))
+        self.assertIs(reg_instruction.condition[0], test_creg)
+        self.assertEqual(reg_instruction.condition, (test_creg, 3))
+
 
 if __name__ == "__main__":
     unittest.main()