diff --git a/CONFIG.example b/CONFIG.example index 013b54a84..42098e3d5 100644 --- a/CONFIG.example +++ b/CONFIG.example @@ -12,8 +12,9 @@ # Definitions needed for FPGA build export VIVADO = /dls_sw/FPGA/Xilinx/Vivado/$(VIVADO_VER)/settings64.sh -export ISE = /dls_sw/FPGA/Xilinx/14.7/ISE_DS/settings64.sh -export LM_LICENSE_FILE = 2100@diamcslicserv01.dc.diamond.ac.uk + +# Specifiy licence server, if required +# export LM_LICENCE_FILE = # Location of rootfs builder. This needs to be at least version 1.13 and can be # downloaded from https://github.com/araneidae/rootfs diff --git a/Makefile b/Makefile index 30cf6cc64..9f4a36116 100644 --- a/Makefile +++ b/Makefile @@ -220,7 +220,7 @@ hdl_timing: $(TIMING_BUILD_DIRS) # FPGA build # The following phony targets are passed straight to the FPGA sub-make programme -FPGA_TARGETS = fpga-all fpga-bits carrier_fpga slow_fpga carrier_ip ps_core \ +FPGA_TARGETS = fpga-all fpga-bit carrier_fpga carrier_ip ps_core \ fsbl devicetree boot u-boot dts xsct sw_clean u-boot-src ip_clean ps_clean $(FPGA_TARGETS): $(TOP)/common/fpga.make $(AUTOGEN_BUILD_DIR) | update_VER @@ -278,7 +278,7 @@ ZPKG_LIST = targets/$(TARGET)/etc/panda-fpga.list ZPKG_VERSION = $(APP_NAME)-$(GIT_VERSION) ZPKG_FILE = $(BUILD_DIR)/panda-fpga@$(ZPKG_VERSION).zpg -ZPKG_DEPENDS += fpga-bits +ZPKG_DEPENDS += fpga-bit ZPKG_DEPENDS += $(APP_BUILD_DIR)/ipmi.ini ZPKG_DEPENDS += $(APP_BUILD_DIR)/extensions ZPKG_DEPENDS += $(DOCS_HTML_DIR) diff --git a/common/fpga.make b/common/fpga.make index 0cc7c23d3..cafc28522 100644 --- a/common/fpga.make +++ b/common/fpga.make @@ -69,9 +69,7 @@ U_BOOT_BUILD = $(BOOT_BUILD)/u-boot U_BOOT_ELF = $(U_BOOT_BUILD)/u-boot.elf IMAGE_DIR=$(TGT_BUILD_DIR)/boot - -BITS_PREREQ += carrier_fpga - + # ------------------------------------------------------------------------------ # Helper code lifted from rootfs and other miscellaneous functions @@ -81,15 +79,15 @@ EXTRACT_FILE = $(ROOTFS_TOP)/scripts/extract-tar $(SRC_ROOT) $1 $2 $(TAR_FILES) ##################################################################### # BUILD TARGETS includes HW and SW -fpga-all: fpga-bits boot -fpga-bits: $(BITS_PREREQ) +fpga-all: fpga-bit boot +fpga-bit: carrier_fpga carrier_ip: $(IP_DIR)/IP_BUILD_SUCCESS ps_core: $(PS_CORE) devicetree : $(DEVTREE_DTB) fsbl : $(FSBL) boot : $(IMAGE_DIR)/boot.bin $(DEVTREE_DTB) u-boot: $(U_BOOT_ELF) -.PHONY: fpga-all fpga-bits carrier_ip ps_core boot devicetree fsbl u-boot +.PHONY: fpga-all fpga-bit carrier_ip ps_core boot devicetree fsbl u-boot ##################################################################### # Compiler variables needed for u-boot build and other complitation diff --git a/modules/system/hdl/system_registers.vhd b/modules/system/hdl/system_registers.vhd index 5fcedfae6..92794f188 100644 --- a/modules/system/hdl/system_registers.vhd +++ b/modules/system/hdl/system_registers.vhd @@ -39,6 +39,32 @@ end system_registers; architecture rtl of system_registers is +-- Input Encoder Address List +constant INPROT_ADDR_LIST : page_array(ENC_NUM-1 downto 0) := ( + TO_SVECTOR(INENC4_PROTOCOL, PAGE_AW), + TO_SVECTOR(INENC3_PROTOCOL, PAGE_AW), + TO_SVECTOR(INENC2_PROTOCOL, PAGE_AW), + TO_SVECTOR(INENC1_PROTOCOL, PAGE_AW) + ); + +-- Output Encoder Address List +constant OUTPROT_ADDR_LIST : page_array(ENC_NUM-1 downto 0) := ( + TO_SVECTOR(OUTENC4_PROTOCOL, PAGE_AW), + TO_SVECTOR(OUTENC3_PROTOCOL, PAGE_AW), + TO_SVECTOR(OUTENC2_PROTOCOL, PAGE_AW), + TO_SVECTOR(OUTENC1_PROTOCOL, PAGE_AW) + ); + +-- TTLIN TERM Address List +constant TTLTERM_ADDR_LIST : page_array(TTLIN_NUM-1 downto 0) := ( + TO_SVECTOR(TTLIN6_TERM, PAGE_AW), + TO_SVECTOR(TTLIN5_TERM, PAGE_AW), + TO_SVECTOR(TTLIN4_TERM, PAGE_AW), + TO_SVECTOR(TTLIN3_TERM, PAGE_AW), + TO_SVECTOR(TTLIN2_TERM, PAGE_AW), + TO_SVECTOR(TTLIN1_TERM, PAGE_AW) + ); + begin --------------------------------------------------------------------------- diff --git a/targets/PandABox/SlowFPGA/SlowFPGA.make b/targets/PandABox/SlowFPGA/SlowFPGA.make deleted file mode 100644 index d8791d94e..000000000 --- a/targets/PandABox/SlowFPGA/SlowFPGA.make +++ /dev/null @@ -1,56 +0,0 @@ -ifndef TOP -$(error Do not call this make file directly) -endif - -VPATH = $(SRC_DIR) - -# Top-level design name -SYSTEM = slow_top - -LIST_FILE = $(SYSTEM).lst - -SCR_FILE = $(SRC_DIR)/syn/xilinx/$(SYSTEM).scr -UCF_FILE = $(SRC_DIR)/syn/constr/$(SYSTEM).ucf - -POSTSYN_NETLIST = $(SYSTEM).ngc -NGD_FILE = $(SYSTEM).ngd -MAPPED_NCD_FILE = $(SYSTEM)_map.ncd -ROUTED_NCD_FILE = $(SYSTEM).ncd -PCF_FILE = $(SYSTEM).pcf -TWX_FILE = $(SYSTEM).twx -BIT_FILE = $(SYSTEM).bit -BIN_FILE = $(SYSTEM).bin - -# Print the names of unlocked (unconstrainted) IOs -export XIL_PAR_DESIGN_CHECK_VERBOSE=1 - -bin: $(BIN_FILE) -.PHONY: bin - -# We have to take a bit of care when building the list file: it turns out that -# xst can't cope with long file names. -refresh_list_file: $(SRC_DIR)/syn/xilinx/slow_top.files - ln -sfn $(SRC_DIR)/.. target_dir - ln -sfn $(TOP)/common/hdl/ common_hdl - ln -sfn $(AUTOGEN)/hdl autogen_hdl - cp $< $(LIST_FILE) -.PHONY: refresh_list_file - -MAP_FLAGS = -detail -w -ol high -pr b -PAR_FLAGS = -w -ol high -TRCE_FLAGS = -e 3 -l 3 - -slow_bit: refresh_list_file - xst -ifn $(SCR_FILE) - ngdbuild -uc $(UCF_FILE) $(POSTSYN_NETLIST) - map $(MAP_FLAGS) $(NGD_FILE) -o $(MAPPED_NCD_FILE) $(PCF_FILE) - par $(PAR_FLAGS) $(MAPPED_NCD_FILE) $(ROUTED_NCD_FILE) $(PCF_FILE) - trce $(TRCE_FLAGS) $(ROUTED_NCD_FILE) $(PCF_FILE) -xml $(TWX_FILE) - bitgen -w $(ROUTED_NCD_FILE) -.PHONY: slow_bit - -$(BIT_FILE) : slow_bit - -$(BIN_FILE): $(BIT_FILE) - promgen -w -p bin -u 0 $< - diff --git a/targets/PandABox/SlowFPGA/sim/bench/i2c_slave_model.vhd b/targets/PandABox/SlowFPGA/sim/bench/i2c_slave_model.vhd deleted file mode 100644 index 4270ab5bf..000000000 --- a/targets/PandABox/SlowFPGA/sim/bench/i2c_slave_model.vhd +++ /dev/null @@ -1,320 +0,0 @@ ---------------------------------------------------------------------/ ----- ---- ----- WISHBONE rev.B2 compliant synthesizable I2C Slave model ---- ----- ---- ----- ---- ----- Authors: Richard Herveille (richard@asics.ws) www.asics.ws ---- ----- John Sheahan (jrsheahan@optushome.com.au) ---- ----- ---- ----- Downloaded from: http:--www.opencores.org/projects/i2c/ ---- ----- ---- ---------------------------------------------------------------------/ ----- ---- ----- Copyright (C) 2001,2002 Richard Herveille ---- ----- richard@asics.ws ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer.---- ----- ---- ----- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ---- ----- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ---- ----- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ---- ----- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ---- ----- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ---- ----- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ---- ----- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ---- ----- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ---- ----- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ---- ----- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ---- ----- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ---- ----- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ---- ----- POSSIBILITY OF SUCH DAMAGE. ---- ----- ---- ---------------------------------------------------------------------/ - --- CVS Log --- --- $Id: i2c_slave_model.v,v 1.6 2005/02/28 11:33:48 rherveille Exp $ --- --- $Date: 2005/02/28 11:33:48 $ --- $Revision: 1.6 $ --- $Author: rherveille $ --- $Locker: $ --- $State: Exp $ --- --- Change History: --- $Log: i2c_slave_model.v,v $ --- Revision 1.6 2005/02/28 11:33:48 rherveille --- Fixed Tsu:sta timing check. --- Added Thd:sta timing check. --- --- Revision 1.5 2003/12/05 11:05:19 rherveille --- Fixed slave address MSB='1' bug --- --- Revision 1.4 2003/09/11 08:25:37 rherveille --- Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. --- --- Revision 1.3 2002/10/30 18:11:06 rherveille --- Added timing tests to i2c_model. --- Updated testbench. --- --- Revision 1.2 2002/03/17 10:26:38 rherveille --- Fixed some race conditions in the i2c-slave model. --- Added debug information. --- Added headers. --- - -library ieee; -use ieee.std_logic_1164.all ; -use ieee.std_logic_arith.all ; -use ieee.std_logic_unsigned.all ; -use ieee.std_logic_misc.all ; - -entity i2c_slave_model is -generic ( - I2C_ADR : std_logic_vector(6 downto 0) := "1001000" -); -port ( - scl : in std_logic; - sda : inout std_logic -); -end i2c_slave_model; - - -architecture syn of i2c_slave_model is - -constant debug :std_logic := '1'; - -type std_2d is array(natural range <>) of std_logic_vector(7 downto 0); -type i2s_slave_sm_type is (idle, slave_ack, get_mem_adr, gma_ack, data, data_ack); - -signal state : i2s_slave_sm_type:=idle; - -signal mem : std_2d(7 downto 0) := ( - X"00", X"01", X"02", X"03", X"04", X"05", X"06", X"07" - ); -signal mem_adr : std_logic_vector(7 downto 0); -signal mem_do : std_logic_vector(7 downto 0); - -signal sr : std_logic_vector(7 downto 0); -signal bit_cnt : std_logic_vector(2 downto 0); -signal sta : std_logic; -signal d_sta : std_logic; -signal sto : std_logic; -signal d_sto : std_logic; - -signal i2c_reset : std_logic; -signal sda_o : std_logic := '1'; - -signal sda_dly : std_logic; -signal ld : std_logic; -signal acc_done : std_logic; -signal my_adr : std_logic; -signal rw : std_logic; - -begin - -shift_reg: process(scl) -begin - -if( scl'event and (scl = '1' or scl = 'H')) then - if (sda = '1' or sda = 'H') then - sr <= sr(6 downto 0) & '1' after 1 ns; - else - sr <= sr(6 downto 0) & '0' after 1 ns; - end if; - - if (ld = '1') then - bit_cnt <= (others =>'1') after 1 ns; - else - bit_cnt <= bit_cnt - 1 after 1 ns; - end if; - - -end if; -end process; - -detct_proc: process(sda, scl) -begin - -if( sda'event and sda = '0' ) then - if(scl = '1' or scl = 'H') then - sta <= '1' after 1 ns; - d_sta <= '0' after 1 ns; - sto <= '0' after 1 ns; - if(debug = '1') then - report("DEBUG i2c_slave; start condition detected "); - end if; - else - sta <= '0' after 1 ns; - end if; - -elsif( sda'event and (sda = '1' or sda = 'H')) then - if(scl = '1' or scl = 'H') then - sta <= '0' after 1 ns; - sto <= '1' after 1 ns; - if(debug = '1') then - report("DEBUG i2c_slave; stop condition detected"); - end if; - else - sto <= '0' after 1 ns; - end if; - -elsif ( scl'event and (scl = '1' or scl = 'H')) then - d_sta <= sta after 1 ns; - -end if; -end process; - -sm_proc: process(scl, sto) -variable rw_var :std_logic; -begin - -if( (scl'event and scl = '0') or (sto'event and sto = '0')) then - if (sto = '1' or( sta = '1' and d_sta= '0')) then - state <= idle after 1 ns; - sda_o <= '1' after 1 ns; - ld <= '1' after 1 ns; - else - sda_o <= '1' after 1 ns; - ld <= '0' after 1 ns; - - case state is - when idle => - if(acc_done = '1' and my_adr= '1') then - state <= slave_ack after 1 ns; - rw <= sr(0) after 1 ns; - rw_var := sr(0); - sda_o <= '0' after 1 ns; - - if (debug = '1' and sr(0) = '1') then - report("DEBUG i2c_slave; command byte received (read)" ); - elsif (debug = '1' and sr(0) = '0') then - report("DEBUG i2c_slave; command byte received (write)" ); - end if; - - if (rw_var = '1') then - mem_do <= mem(conv_integer(mem_adr)) after 1 ns; - if (debug = '1') then - report ("DEBUG i2c_slave; data block read from address "); - end if; - end if; - end if; - - - when slave_ack => - if (rw = '1') then - state <= data after 1 ns; - sda_o <= mem_do(7) after 1 ns; - else - state <= get_mem_adr after 1 ns; - ld <= '1' after 1 ns; - end if; - - - - when get_mem_adr => - if (acc_done = '1') then - state <= gma_ack after 1 ns; - mem_adr <= sr after 1 ns; - if (sr <= conv_std_logic_vector(15,7)) then - sda_o <= '0' after 1 ns; - else - sda_o <= '1' after 1 ns; - end if; - - if (debug = '1') then - report ("DEBUG i2c_slave; address received. "); - end if; - end if; - - - when gma_ack => - state <= data after 1 ns; - ld <= '1' after 1 ns; - - - when data => - if(rw = '1') then - sda_o <= mem_do(7) after 1 ns; - end if; - - if(acc_done = '1') then - state <= data_ack after 1 ns; - mem_adr <= mem_adr + 1 after 2 ns; - if (rw= '1'and mem_adr <= conv_std_logic_vector(15,7)) then - sda_o <= '1' after 3 ns; - else - sda_o <= '0' after 1 ns; - end if; - - if(rw= '1') then - mem_do <= mem(conv_integer(mem_adr)) after 3 ns; - if (debug = '1') then - report ("DEBUG i2c_slave; data block read"); - end if; - end if; - - if (rw= '0') then - mem(conv_integer(mem_adr)) <= sr after 1 ns; - if (debug = '1') then - report ("DEBUG i2c_slave; data block write "); - end if; - end if; - end if; - - - - - when data_ack => - ld <= '1' after 1 ns; - - if (rw= '1') then - if (sda = '1' or sda = 'H') then - state <= idle after 1 ns; - sda_o <= '1' after 1 ns; - else - state <= data after 1 ns; - sda_o <= mem_do(7) after 1 ns; - end if; - else - state <= data after 1 ns; - sda_o <= '1' after 1 ns; - end if; - - end case; - - - end if; -elsif( scl'event and (scl = '1' or scl = 'H')) then - if (acc_done = '0' and rw = '1') then - mem_do <= mem_do(6 downto 0) & '1'; - end if; - -end if; - - -end process; - -my_adr <= '1' when sr(7 downto 1) = i2c_adr else '0'; --detect if it is our address - -acc_done <= not or_reduce(bit_cnt); --generate access done signal - --- generate delayed version of sda --- this model assumes a hold time for sda after the falling edge of scl. --- According to the Phillips i2c spec, there s/b a 0 ns hold time for sda --- with regards to scl. If the data changes coincident with the clock, the --- acknowledge is missed --- Fix by Michael Sosnoski -sda_dly <= '1' after 1 ns when sda = '1' or sda = 'H' else '0' after 1 ns; - ---generate i2c_reset signal -i2c_reset <= sta or sto; - --- generate tri-states -sda <= '0' when sda_o = '0' else 'Z'; - -end syn; - diff --git a/targets/PandABox/SlowFPGA/sim/bench/temp_sensors_tb.vhd b/targets/PandABox/SlowFPGA/sim/bench/temp_sensors_tb.vhd deleted file mode 100644 index 2c2cc2ca8..000000000 --- a/targets/PandABox/SlowFPGA/sim/bench/temp_sensors_tb.vhd +++ /dev/null @@ -1,59 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; - -entity temp_sensors_tb is -end entity temp_sensors_tb; - -architecture rtl of temp_sensors_tb is - -signal clk_i : std_logic := '0'; -signal reset_i : std_logic := '1'; -signal TEMP_PSU : std_logic_vector(31 downto 0); -signal TEMP_SFP : std_logic_vector(31 downto 0); -signal TEMP_ENC_L : std_logic_vector(31 downto 0); -signal TEMP_PICO : std_logic_vector(31 downto 0); -signal TEMP_ENC_R : std_logic_vector(31 downto 0); -signal sda : std_logic; -signal scl : std_logic; - -begin - -clk_i <= not clk_i after 10 ns; -reset_i <= '0' after 1000 ns; - -uut : entity work.temp_sensors -port map ( - clk_i => clk_i, - reset_i => reset_i, - sda => sda, - scl => scl, - TEMP_PSU => TEMP_PSU, - TEMP_SFP => TEMP_SFP, - TEMP_ENC_L => TEMP_ENC_L, - TEMP_PICO => TEMP_PICO, - TEMP_ENC_R => TEMP_ENC_R -); - -i2c_slave_model_inst0 : entity work.i2c_slave_model -generic map ( - I2C_ADR => "1001000" -) -port map ( - scl => scl, - sda => sda -); - ---i2c_slave_model_inst1 : entity work.i2c_slave_model ---generic map ( --- I2C_ADR => "1001001" ---) ---port map ( --- scl => scl, --- sda => sda ---); - -scl <= 'H'; -sda <= 'H'; - -end rtl; - diff --git a/targets/PandABox/SlowFPGA/src/hdl/clkgen.vhd b/targets/PandABox/SlowFPGA/src/hdl/clkgen.vhd deleted file mode 100755 index 16eb15730..000000000 --- a/targets/PandABox/SlowFPGA/src/hdl/clkgen.vhd +++ /dev/null @@ -1,117 +0,0 @@ ------------------------------------------------------------------------------- --- "Output Output Phase Duty Pk-to-Pk Phase" --- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" ------------------------------------------------------------------------------- --- CLK_OUT1____50.000______0.000______50.0______600.000____150.000 --- ------------------------------------------------------------------------------- --- "Input Clock Freq (MHz) Input Jitter (UI)" ------------------------------------------------------------------------------- --- __primary_____________125____________0.010 - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; -use ieee.std_logic_arith.all; -use ieee.numeric_std.all; - -library unisim; -use unisim.vcomponents.all; - -entity clkgen is -port - (-- Clock in ports - CLK_IN1 : in std_logic; - -- Clock out ports - CLK_OUT1 : out std_logic; - -- Status and control signals - RESET : in std_logic; - LOCKED : out std_logic - ); -end clkgen; - -architecture xilinx of clkgen is - -- Input clock buffering / unused connectors - signal clkin1 : std_logic; - -- Output clock buffering - signal clkfb : std_logic; - signal clk0 : std_logic; - signal clkfx : std_logic; - signal clkfbout : std_logic; - signal locked_internal : std_logic; - signal status_internal : std_logic_vector(7 downto 0); -begin - - - -- Input buffering - -------------------------------------- - clkin1_buf : IBUFG - port map - (O => clkin1, - I => CLK_IN1); - - - -- Clocking primitive - -------------------------------------- - - -- Instantiation of the DCM primitive - -- * Unused inputs are tied off - -- * Unused outputs are labeled unused - dcm_sp_inst: DCM_SP - generic map - (CLKDV_DIVIDE => 2.500, - CLKFX_DIVIDE => 5, - CLKFX_MULTIPLY => 2, - CLKIN_DIVIDE_BY_2 => FALSE, - CLKIN_PERIOD => 8.0, - CLKOUT_PHASE_SHIFT => "NONE", - CLK_FEEDBACK => "1X", - DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", - PHASE_SHIFT => 0, - STARTUP_WAIT => FALSE) - port map - -- Input clock - (CLKIN => clkin1, - CLKFB => clkfb, - -- Output clocks - CLK0 => clk0, - CLK90 => open, - CLK180 => open, - CLK270 => open, - CLK2X => open, - CLK2X180 => open, - CLKFX => clkfx, - CLKFX180 => open, - CLKDV => open, - -- Ports for dynamic phase shift - PSCLK => '0', - PSEN => '0', - PSINCDEC => '0', - PSDONE => open, - -- Other control and status signals - LOCKED => locked_internal, - STATUS => status_internal, - RST => RESET, - -- Unused pin, tie low - DSSEN => '0'); - - LOCKED <= locked_internal; - - - - -- Output buffering - ------------------------------------- - clkf_buf : BUFG - port map - (O => clkfb, - I => clk0); - - - clkout1_buf : BUFG - port map - (O => CLK_OUT1, - I => clkfx); - - - -end xilinx; diff --git a/targets/PandABox/SlowFPGA/src/hdl/dcard_ctrl.vhd b/targets/PandABox/SlowFPGA/src/hdl/dcard_ctrl.vhd deleted file mode 100644 index 4a1ade805..000000000 --- a/targets/PandABox/SlowFPGA/src/hdl/dcard_ctrl.vhd +++ /dev/null @@ -1,143 +0,0 @@ --------------------------------------------------------------------------------- --- PandA Motion Project - 2016 --- Diamond Light Source, Oxford, UK --- SOLEIL Synchrotron, GIF-sur-YVETTE, France --- --- Author : Dr. Isa Uzun (isa.uzun@diamond.ac.uk) --------------------------------------------------------------------------------- --- --- Description : Daughter Card control logic for on-board buffers based on : --- PROTOCOL, --- DCARD MODE, and --- OUTENC_CONN connection from user. --- --------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.top_defines.all; -use work.addr_defines.all; - -entity dcard_ctrl is -port ( - -- 50MHz system clock - clk_i : in std_logic; - reset_i : in std_logic; - -- Encoder Daughter Card Control Interface - dcard_ctrl1_io : inout std_logic_vector(15 downto 0); - dcard_ctrl2_io : inout std_logic_vector(15 downto 0); - dcard_ctrl3_io : inout std_logic_vector(15 downto 0); - dcard_ctrl4_io : inout std_logic_vector(15 downto 0); - -- Front Panel Shift Register Interface - OUTENC_CONN : in std_logic_vector(3 downto 0); - INENC_PROTOCOL : in std3_array(3 downto 0); - OUTENC_PROTOCOL : in std3_array(3 downto 0); - DCARD_MODE : out std4_array(3 downto 0) -); -end dcard_ctrl; - -architecture rtl of dcard_ctrl is - -function INENC_CONV (PROTOCOL : std_logic_vector) return std_logic_vector is -begin - case (PROTOCOL(2 downto 0)) is - when "000" => -- INC - return X"03"; - when "001" => -- SSI - return X"0C"; - when "010" => -- BiSS-C - return X"0C"; - when "011" => -- EnDat - return X"14"; - when others => - return X"00"; - end case; -end INENC_CONV; - -function OUTENC_CONV (PROTOCOL : std_logic_vector) return std_logic_vector is -begin - case (PROTOCOL(2 downto 0)) is - when "000" => -- INC - return X"07"; - when "001" => -- SSI - return X"28"; - when "010" => -- BiSS-C - return X"28"; - when "011" => -- EnDat - return X"10"; - when "100" => -- Pass - return X"07"; - when "101" => -- Data passthrough (same as SSI) - return X"28"; - when others => - return X"00"; - end case; -end OUTENC_CONV; - -function CONV_PADS(INENC, OUTENC : std_logic_vector) return std_logic_vector is - variable enc_ctrl_pad : std_logic_vector(11 downto 0); -begin - - enc_ctrl_pad(1 downto 0) := INENC(1 downto 0); - enc_ctrl_pad(3 downto 2) := OUTENC(1 downto 0); - enc_ctrl_pad(4) := INENC(2); - enc_ctrl_pad(5) := OUTENC(2); - enc_ctrl_pad(7 downto 6) := INENC(4 downto 3); - enc_ctrl_pad(9 downto 8) := OUTENC(4 downto 3); - enc_ctrl_pad(10) := INENC(5); - enc_ctrl_pad(11) := OUTENC(5); - - return enc_ctrl_pad; -end CONV_PADS; - -signal DCARD_MODE_i : std4_array(3 downto 0) - := (others => (others => '0')); -signal inenc_ctrl : std8_array(3 downto 0); -signal outenc_ctrl : std8_array(3 downto 0); - -begin - --- DCARD configuration from on-board 0-Ohm settings. --- These pins have weak pull-ups on the chip to detect --- un-installed daughter cards -DCARD_MODE_i(0) <= dcard_ctrl1_io(15 downto 12); -DCARD_MODE_i(1) <= dcard_ctrl2_io(15 downto 12); -DCARD_MODE_i(2) <= dcard_ctrl3_io(15 downto 12); -DCARD_MODE_i(3) <= dcard_ctrl4_io(15 downto 12); - --- Assign CTRL values for Input Encoder ICs on the Daughter Card -INENC_CTRL_GEN : FOR I IN 0 TO 3 GENERATE - inenc_ctrl(I) <= INENC_CONV(INENC_PROTOCOL(I)); -END GENERATE; - --- Output Encoder Buffer Control depends on Daughter Card Mode, Protocol, and --- OUTENC_CONN setting. --- -process(INENC_PROTOCOL, OUTENC_PROTOCOL, DCARD_MODE_i, OUTENC_CONN) -begin - FOR I IN 0 TO 3 LOOP - -- Disable all OUTENC buffers. ??? - if (OUTENC_CONN(I) = '0') then - outenc_ctrl(I) <= OUTENC_CONV(OUTENC_PROTOCOL(I)); - -- Daugther Card in LOOPBACK mode. - elsif (DCARD_MODE_i(I)(3 downto 1) = DCARD_MONITOR) then - outenc_ctrl(I) <= OUTENC_CONV(INENC_PROTOCOL(I)); - -- Daughter Card in NORMAL mode. - else - outenc_ctrl(I) <= OUTENC_CONV(OUTENC_PROTOCOL(I)); - end if; - END LOOP; -end process; - --- Interleave Input and Output Controls to the Daughter Card Pins. -dcard_ctrl1_io(11 downto 0) <= CONV_PADS(inenc_ctrl(0), outenc_ctrl(0)); -dcard_ctrl2_io(11 downto 0) <= CONV_PADS(inenc_ctrl(1), outenc_ctrl(1)); -dcard_ctrl3_io(11 downto 0) <= CONV_PADS(inenc_ctrl(2), outenc_ctrl(2)); -dcard_ctrl4_io(11 downto 0) <= CONV_PADS(inenc_ctrl(3), outenc_ctrl(3)); - -DCARD_MODE <= DCARD_MODE_i; - -end rtl; diff --git a/targets/PandABox/SlowFPGA/src/hdl/enc_ctrl.vhd b/targets/PandABox/SlowFPGA/src/hdl/enc_ctrl.vhd deleted file mode 100644 index 12102a0bf..000000000 --- a/targets/PandABox/SlowFPGA/src/hdl/enc_ctrl.vhd +++ /dev/null @@ -1,95 +0,0 @@ --------------------------------------------------------------------------------- --- PandA Motion Project - 2016 --- Diamond Light Source, Oxford, UK --- SOLEIL Synchrotron, GIF-sur-YVETTE, France --- --- Author : Dr. Isa Uzun (isa.uzun@diamond.ac.uk) --------------------------------------------------------------------------------- --- --- Description : Encoder Daugther Card receive interface. --- --- --------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.top_defines.all; -use work.slow_defines.all; -use work.addr_defines.all; - -entity enc_ctrl is -generic ( - AW : natural := 10; - DW : natural := 32 -); -port ( - -- 50MHz system clock - clk_i : in std_logic; - reset_i : in std_logic; - -- Serial Receive Interface - rx_addr_i : in std_logic_vector(AW-1 downto 0); - rx_valid_i : in std_logic; - rx_data_i : in std_logic_vector(DW-1 downto 0); - -- Encoder Daughter Card Control interface - INENC_PROTOCOL : out std3_array(3 downto 0); - OUTENC_PROTOCOL : out std3_array(3 downto 0) -); -end enc_ctrl; - -architecture rtl of enc_ctrl is - -signal rx_addr : natural range 0 to (2**AW - 1); - -begin - -rx_addr <= to_integer(unsigned(rx_addr_i)); - --- --- Read Register Interface --- -process(clk_i) begin - if rising_edge(clk_i) then - if (reset_i = '1') then - INENC_PROTOCOL <= (others => (others => '0')); - OUTENC_PROTOCOL <= (others => (others => '0')); - else - if (rx_valid_i = '1' and rx_addr = INENC1_PROTOCOL) then - INENC_PROTOCOL(0) <= rx_data_i(2 downto 0); - end if; - - if (rx_valid_i = '1' and rx_addr = INENC2_PROTOCOL) then - INENC_PROTOCOL(1) <= rx_data_i(2 downto 0); - end if; - - if (rx_valid_i = '1' and rx_addr = INENC3_PROTOCOL) then - INENC_PROTOCOL(2) <= rx_data_i(2 downto 0); - end if; - - if (rx_valid_i = '1' and rx_addr = INENC4_PROTOCOL) then - INENC_PROTOCOL(3) <= rx_data_i(2 downto 0); - end if; - - if (rx_valid_i = '1' and rx_addr = OUTENC1_PROTOCOL) then - OUTENC_PROTOCOL(0) <= rx_data_i(2 downto 0); - end if; - - if (rx_valid_i = '1' and rx_addr = OUTENC2_PROTOCOL) then - OUTENC_PROTOCOL(1) <= rx_data_i(2 downto 0); - end if; - - if (rx_valid_i = '1' and rx_addr = OUTENC3_PROTOCOL) then - OUTENC_PROTOCOL(2) <= rx_data_i(2 downto 0); - end if; - - if (rx_valid_i = '1' and rx_addr = OUTENC4_PROTOCOL) then - OUTENC_PROTOCOL(3) <= rx_data_i(2 downto 0); - end if; - - end if; - end if; -end process; - -end rtl; diff --git a/targets/PandABox/SlowFPGA/src/hdl/fpanel_if.vhd b/targets/PandABox/SlowFPGA/src/hdl/fpanel_if.vhd deleted file mode 100644 index 7c61b9e35..000000000 --- a/targets/PandABox/SlowFPGA/src/hdl/fpanel_if.vhd +++ /dev/null @@ -1,151 +0,0 @@ --------------------------------------------------------------------------------- --- PandA Motion Project - 2016 --- Diamond Light Source, Oxford, UK --- SOLEIL Synchrotron, GIF-sur-YVETTE, France --- --- Author : Dr. Isa Uzun (isa.uzun@diamond.ac.uk) --------------------------------------------------------------------------------- --- --- Description : Shifts data onto the front panel shift registers (SN74HC595PW) --- --------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.support.all; -use work.slow_defines.all; - -library unisim; -use unisim.vcomponents.all; - -entity fpanel_if is -port ( - -- 50MHz system clock. - clk_i : in std_logic; - reset_i : in std_logic; - -- Front-Panel Control Values. - ttl_leds_i : in std_logic_vector(15 downto 0); - ttlin_term_i : in std_logic_vector(5 downto 0); - status_leds_i : in std_logic_vector(3 downto 0); - -- Shift Register Interface. - shift_reg_sdata_o : out std_logic; - shift_reg_sclk_o : out std_logic; - shift_reg_latch_o : out std_logic; - shift_reg_oe_n_o : out std_logic -); -end fpanel_if; - -architecture rtl of fpanel_if is - -type shift_fsm_t is (IDLE, SYNC, SHIFTING, LATCH); -signal shift_fsm : shift_fsm_t; - --- Number of bits to shifth -signal shift_clock : std_logic; -signal shift_reg_sclk : std_logic; -signal shift_reg_latch : std_logic; - -signal data : std_logic_vector(31 downto 0); -signal data_prev : std_logic_vector(31 downto 0); -signal data_slr : std_logic_vector(31 downto 0); - -signal shift_index : integer range 0 to 31; - -begin - --- --- Shift register clock rate is 2x1usec. --- -shift_clk: entity work.prescaler -port map ( - clk_i => clk_i, - reset_i => reset_i, - PERIOD => TO_SVECTOR(50, 32), - pulse_o => shift_clock -); - --- --- Latch and shift data on DATA change. Make sure that there is not --- already an ongoing shifting. --- -process(clk_i) begin - if rising_edge(clk_i) then - if (reset_i = '1') then - shift_reg_oe_n_o <= '1'; - shift_reg_sclk <= '0'; - shift_reg_latch <= '0'; - shift_index <= 0; - data <= (others => '0'); - data_prev <= (others => '0'); - data_slr <= (others => '0'); - else - -- Register input data with gaps according to schematics; - data <= BITREV(ttl_leds_i) & BITREV(ttlin_term_i) & - "00" & BITREV(status_leds_i) & "0000"; - - case shift_fsm is - -- Wait for change on data; - when IDLE => - shift_reg_sclk <= '0'; - shift_reg_latch <= '0'; - - if (data /= data_prev) then - data_prev <= data; - data_slr <= data; - shift_fsm <= SYNC; - end if; - - -- Sync data stream to shift clock before starting - when SYNC => - if (shift_clock = '1') then - shift_fsm <= SHIFTING; - end if; - - -- Shift data and keep track of bits; - when SHIFTING => - -- Toggle clock at 1usec - if (shift_clock = '1') then - shift_reg_sclk <= not shift_reg_sclk; - end if; - - -- Shift new bit on falling edge of sclk to have enough - -- setup time; - if (shift_reg_sclk = '1' and shift_clock = '1') then - data_slr <= '0' & data_slr(31 downto 1); - -- Last bit shifted, now latch. - if (shift_index = 31) then - shift_reg_latch <= '1'; - shift_fsm <= LATCH; - shift_index <= 0; - -- Continue shifting; - else - shift_index <= shift_index + 1; - end if; - end if; - - -- 1usec latch pulse; - when LATCH => - if (shift_clock = '1') then - shift_reg_latch <= '0'; - shift_fsm <= IDLE; - end if; - - -- Enable shift register output permanently after the - --first write; - shift_reg_oe_n_o <= '0'; - - - when others => - end case; - end if; - end if; -end process; - -shift_reg_sclk_o <= shift_reg_sclk; -shift_reg_sdata_o <= data_slr(0); -shift_reg_latch_o <= shift_reg_latch; - -end rtl; diff --git a/targets/PandABox/SlowFPGA/src/hdl/i2c_master.vhd b/targets/PandABox/SlowFPGA/src/hdl/i2c_master.vhd deleted file mode 100644 index e588564ff..000000000 --- a/targets/PandABox/SlowFPGA/src/hdl/i2c_master.vhd +++ /dev/null @@ -1,254 +0,0 @@ --------------------------------------------------------------------------------- --- --- FileName: i2c_master.vhd --- Dependencies: none --- Design Software: Quartus II 64-bit Version 13.1 Build 162 SJ Full Version --- --- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY --- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT --- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A --- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY --- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL --- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF --- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS --- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), --- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. --- --- Version History --- Version 1.0 11/01/2012 Scott Larson --- Initial Public Release --- Version 2.0 06/20/2014 Scott Larson --- Added ability to interface with different slaves in the same transaction --- Corrected ack_error bug where ack_error went 'Z' instead of '1' on error --- Corrected timing of when ack_error signal clears --- Version 2.1 10/21/2014 Scott Larson --- Replaced gated clock with clock enable --- Adjusted timing of SCL during start and stop conditions --- Version 2.2 02/05/2015 Scott Larson --- Corrected small SDA glitch introduced in version 2.1 --- --------------------------------------------------------------------------------- - -LIBRARY ieee; -USE ieee.std_logic_1164.all; -USE ieee.std_logic_unsigned.all; - -ENTITY i2c_master IS - GENERIC( - input_clk : INTEGER := 50_000_000; -- Input clock [Hz] - bus_clk : INTEGER := 400_000 -- I2C clock [Hz] -); --speed the i2c bus (scl) will run at in Hz - PORT( - clk : IN STD_LOGIC; - reset : IN STD_LOGIC; - ena : IN STD_LOGIC; --latch in command - addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave - rw : IN STD_LOGIC; --'0' is write, '1' is read - data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave - busy : OUT STD_LOGIC; --transaction in progress - data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave - ack_error : BUFFER STD_LOGIC; --acknowledge from slave - sda : in std_logic; - scl : in std_logic; - sda_t : out std_logic; - scl_t : out std_logic -); -END i2c_master; - -ARCHITECTURE logic OF i2c_master IS -CONSTANT divider : INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl -TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states -SIGNAL state : machine; --state machine -SIGNAL data_clk : STD_LOGIC; --data clock for sda -SIGNAL data_clk_prev : STD_LOGIC; --data clock during previous system clock -SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl -SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output -SIGNAL sda_int : STD_LOGIC := '1'; --internal sda -SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output -SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write -SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave -SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave -SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction -SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl -BEGIN - - --generate the timing for the bus clock (scl_clk) and the data clock (data_clk) - PROCESS(clk, reset) - VARIABLE count : INTEGER RANGE 0 TO divider*4; --timing for clock generation - BEGIN - IF(reset = '1') THEN --reset asserted - stretch <= '0'; - count := 0; - ELSIF(clk'EVENT AND clk = '1') THEN - data_clk_prev <= data_clk; --store previous value of data clock - IF(count = divider*4-1) THEN --end of timing cycle - count := 0; --reset timer - ELSIF(stretch = '0') THEN --clock stretching from slave not detected - count := count + 1; --continue clock generation timing - END IF; - CASE count IS - WHEN 0 TO divider-1 => --first 1/4 cycle of clocking - scl_clk <= '0'; - data_clk <= '0'; - WHEN divider TO divider*2-1 => --second 1/4 cycle of clocking - scl_clk <= '0'; - data_clk <= '1'; - WHEN divider*2 TO divider*3-1 => --third 1/4 cycle of clocking - scl_clk <= '1'; --release scl - IF(scl = '0') THEN --detect if slave is stretching clock - stretch <= '1'; - ELSE - stretch <= '0'; - END IF; - data_clk <= '1'; - WHEN OTHERS => --last 1/4 cycle of clocking - scl_clk <= '1'; - data_clk <= '0'; - END CASE; - END IF; - END PROCESS; - - --state machine and writing to sda during scl low (data_clk rising edge) - PROCESS(clk, reset) - BEGIN - IF(reset = '1') THEN --reset asserted - state <= ready; --return to initial state - busy <= '1'; --indicate not available - scl_ena <= '0'; --sets scl high impedance - sda_int <= '1'; --sets sda high impedance - ack_error <= '0'; --clear acknowledge error flag - bit_cnt <= 7; --restarts data bit counter - data_rd <= "00000000"; --clear data read port - ELSIF(clk'EVENT AND clk = '1') THEN - IF(data_clk = '1' AND data_clk_prev = '0') THEN --data clock rising edge - CASE state IS - WHEN ready => --idle state - IF(ena = '1') THEN --transaction requested - busy <= '1'; --flag busy - addr_rw <= addr & rw; --collect requested slave address and command - data_tx <= data_wr; --collect requested data to write - state <= start; --go to start bit - ELSE --remain idle - busy <= '0'; --unflag busy - state <= ready; --remain idle - END IF; - WHEN start => --start bit of transaction - busy <= '1'; --resume busy if continuous mode - sda_int <= addr_rw(bit_cnt); --set first address bit to bus - state <= command; --go to command - WHEN command => --address and command byte of transaction - IF(bit_cnt = 0) THEN --command transmit finished - sda_int <= '1'; --release sda for slave acknowledge - bit_cnt <= 7; --reset bit counter for "byte" states - state <= slv_ack1; --go to slave acknowledge (command) - ELSE --next clock cycle of command state - bit_cnt <= bit_cnt - 1; --keep track of transaction bits - sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus - state <= command; --continue with command - END IF; - WHEN slv_ack1 => --slave acknowledge bit (command) - IF(addr_rw(0) = '0') THEN --write command - sda_int <= data_tx(bit_cnt); --write first bit of data - state <= wr; --go to write byte - ELSE --read command - sda_int <= '1'; --release sda from incoming data - state <= rd; --go to read byte - END IF; - WHEN wr => --write byte of transaction - busy <= '1'; --resume busy if continuous mode - IF(bit_cnt = 0) THEN --write byte transmit finished - sda_int <= '1'; --release sda for slave acknowledge - bit_cnt <= 7; --reset bit counter for "byte" states - state <= slv_ack2; --go to slave acknowledge (write) - ELSE --next clock cycle of write state - bit_cnt <= bit_cnt - 1; --keep track of transaction bits - sda_int <= data_tx(bit_cnt-1); --write next bit to bus - state <= wr; --continue writing - END IF; - WHEN rd => --read byte of transaction - busy <= '1'; --resume busy if continuous mode - IF(bit_cnt = 0) THEN --read byte receive finished - IF(ena = '1' AND addr_rw = addr & rw) THEN --continuing with another read at same address - sda_int <= '0'; --acknowledge the byte has been received - ELSE --stopping or continuing with a write - sda_int <= '1'; --send a no-acknowledge (before stop or repeated start) - END IF; - bit_cnt <= 7; --reset bit counter for "byte" states - data_rd <= data_rx; --output received data - state <= mstr_ack; --go to master acknowledge - ELSE --next clock cycle of read state - bit_cnt <= bit_cnt - 1; --keep track of transaction bits - state <= rd; --continue reading - END IF; - WHEN slv_ack2 => --slave acknowledge bit (write) - IF(ena = '1') THEN --continue transaction - busy <= '0'; --continue is accepted - addr_rw <= addr & rw; --collect requested slave address and command - data_tx <= data_wr; --collect requested data to write - IF(addr_rw = addr & rw) THEN --continue transaction with another write - sda_int <= data_wr(bit_cnt); --write first bit of data - state <= wr; --go to write byte - ELSE --continue transaction with a read or new slave - state <= start; --go to repeated start - END IF; - ELSE --complete transaction - state <= stop; --go to stop bit - END IF; - WHEN mstr_ack => --master acknowledge bit after a read - IF(ena = '1') THEN --continue transaction - busy <= '0'; --continue is accepted and data received is available on bus - addr_rw <= addr & rw; --collect requested slave address and command - data_tx <= data_wr; --collect requested data to write - IF(addr_rw = addr & rw) THEN --continue transaction with another read - sda_int <= '1'; --release sda from incoming data - state <= rd; --go to read byte - ELSE --continue transaction with a write or new slave - state <= start; --repeated start - END IF; - ELSE --complete transaction - state <= stop; --go to stop bit - END IF; - WHEN stop => --stop bit of transaction - busy <= '0'; --unflag busy - state <= ready; --go to idle state - END CASE; - ELSIF(data_clk = '0' AND data_clk_prev = '1') THEN --data clock falling edge - CASE state IS - WHEN start => - IF(scl_ena = '0') THEN --starting new transaction - scl_ena <= '1'; --enable scl output - ack_error <= '0'; --reset acknowledge error output - END IF; - WHEN slv_ack1 => --receiving slave acknowledge (command) - IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge - ack_error <= '1'; --set error output if no-acknowledge - END IF; - WHEN rd => --receiving slave data - data_rx(bit_cnt) <= sda; --receive current slave data bit - WHEN slv_ack2 => --receiving slave acknowledge (write) - IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge - ack_error <= '1'; --set error output if no-acknowledge - END IF; - WHEN stop => - scl_ena <= '0'; --disable scl - WHEN OTHERS => - NULL; - END CASE; - END IF; - END IF; - END PROCESS; - - --set sda output - WITH state SELECT - sda_ena_n <= data_clk_prev WHEN start, --generate start condition - NOT data_clk_prev WHEN stop, --generate stop condition - sda_int WHEN OTHERS; --set to internal sda signal - ---set scl and sda outputs ---scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z'; ---sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z'; - -scl_t <= '0' when (scl_ena = '1' and scl_clk = '0') else '1'; -sda_t <= '0' when (sda_ena_n = '0') else '1'; - -END logic; diff --git a/targets/PandABox/SlowFPGA/src/hdl/leds_ctrl.vhd b/targets/PandABox/SlowFPGA/src/hdl/leds_ctrl.vhd deleted file mode 100644 index 669fab60a..000000000 --- a/targets/PandABox/SlowFPGA/src/hdl/leds_ctrl.vhd +++ /dev/null @@ -1,72 +0,0 @@ --------------------------------------------------------------------------------- --- PandA Motion Project - 2016 --- Diamond Light Source, Oxford, UK --- SOLEIL Synchrotron, GIF-sur-YVETTE, France --- --- Author : Dr. Isa Uzun (isa.uzun@diamond.ac.uk) --------------------------------------------------------------------------------- --- --- Description : Encoder Daugther Card receive front_panel led and custom. --- bus updates from Zynq FPGA. --- --------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.support.all; -use work.slow_defines.all; - -entity leds_ctrl is -generic ( - AW : natural := 10; - DW : natural := 32 -); -port ( - -- 50MHz system clock - clk_i : in std_logic; - reset_i : in std_logic; - -- Serial Receive Interface - rx_addr_i : in std_logic_vector(AW-1 downto 0); - rx_valid_i : in std_logic; - rx_data_i : in std_logic_vector(DW-1 downto 0); - -- Encoder Daughter Card Control interface - ttl_leds_o : out std_logic_vector(15 downto 0); - status_leds_o : out std_logic_vector(3 downto 0); - enc_leds_o : out std_logic_vector(3 downto 0); - outenc_conn_o : out std_logic_vector(3 downto 0) -); -end leds_ctrl; - -architecture rtl of leds_ctrl is - -signal rx_addr : natural range 0 to (2**AW - 1); - -begin - -rx_addr <= to_integer(unsigned(rx_addr_i)); - --- --- Receive Register Interface --- -process(clk_i) begin - if rising_edge(clk_i) then - if (reset_i = '1') then - ttl_leds_o <= (others => '0'); - status_leds_o <= (others => '0'); - outenc_conn_o <= (others => '0'); - enc_leds_o <= (others => '0'); - else - if (rx_valid_i = '1' and rx_addr = TTL_LEDS) then - ttl_leds_o <= rx_data_i(15 downto 0); - outenc_conn_o <= rx_data_i(19 downto 16); - status_leds_o <= rx_data_i(23 downto 20); - enc_leds_o <= rx_data_i(27 downto 24); - end if; - end if; - end if; -end process; - -end rtl; diff --git a/targets/PandABox/SlowFPGA/src/hdl/prescaler.vhd b/targets/PandABox/SlowFPGA/src/hdl/prescaler.vhd deleted file mode 100644 index a4f6fd025..000000000 --- a/targets/PandABox/SlowFPGA/src/hdl/prescaler.vhd +++ /dev/null @@ -1,46 +0,0 @@ --------------------------------------------------------------------------------- --- File: prescaler.vhd --- Desc: A simple 32-bit prescaler. --- --------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -entity prescaler is -port ( - clk_i : in std_logic; - reset_i : in std_logic; - PERIOD : in std_logic_vector(31 downto 0); - pulse_o : out std_logic -); -end prescaler; - -architecture rtl of prescaler is - -signal clk_cnt : unsigned(31 downto 0) := (others => '0'); - -begin - --- --- Generate QENC clk defined by the prescaler --- -qenc_clk_gen : process(clk_i) -begin - if rising_edge(clk_i) then - if (reset_i = '1') then - pulse_o <= '0'; - clk_cnt <= (others => '0'); - else - if (clk_cnt = unsigned(PERIOD)-1) then - pulse_o <= '1'; - clk_cnt <= (others => '0'); - else - pulse_o <= '0'; - clk_cnt <= clk_cnt + 1; - end if; - end if; - end if; -end process; - -end rtl; diff --git a/targets/PandABox/SlowFPGA/src/hdl/slow_top.vhd b/targets/PandABox/SlowFPGA/src/hdl/slow_top.vhd deleted file mode 100644 index b1ebb4eb2..000000000 --- a/targets/PandABox/SlowFPGA/src/hdl/slow_top.vhd +++ /dev/null @@ -1,216 +0,0 @@ --------------------------------------------------------------------------------- --- PandA Motion Project - 2016 --- Diamond Light Source, Oxford, UK --- SOLEIL Synchrotron, GIF-sur-YVETTE, France --- --- Author : Dr. Isa Uzun (isa.uzun@diamond.ac.uk) --------------------------------------------------------------------------------- --- --- Description : Serial Interface core is used to handle communication between --- Zynq and Slow Control FPGA. --- --------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.support.all; -use work.top_defines.all; -use work.slow_defines.all; -use work.addr_defines.all; - -library unisim; -use unisim.vcomponents.all; - -entity slow_top is -generic ( - STATUS_PERIOD : natural := 10_000_000;-- 10ms - SYS_PERIOD : natural := 20 -- 20ns -); -port ( - -- 50MHz system clock - clk50_i : in std_logic; - clk125_i : in std_logic; - -- Zynq Tx/Rx Serial Interface - spi_sclk_i : in std_logic; - spi_dat_i : in std_logic; - spi_sclk_o : out std_logic; - spi_dat_o : out std_logic; - -- Encoder Daughter Card Control Interface - dcard_ctrl1_io : inout std_logic_vector(15 downto 0); - dcard_ctrl2_io : inout std_logic_vector(15 downto 0); - dcard_ctrl3_io : inout std_logic_vector(15 downto 0); - dcard_ctrl4_io : inout std_logic_vector(15 downto 0); - -- Misc control - SEL_GTXCLK1 : out std_logic; -- 0: Si570, 1: FMC - ENC_LED : out std_logic_vector(3 downto 0); - -- Front Panel Shift Register Interface - shift_reg_sdata_o : out std_logic; - shift_reg_sclk_o : out std_logic; - shift_reg_latch_o : out std_logic; - shift_reg_oe_n_o : out std_logic; - -- I2C SFP Interface - i2c_sfp_sda : inout std_logic; - i2c_sfp_scl : inout std_logic; - -- I2C Si570 XO Interface - i2c_clock_sda : inout std_logic; - i2c_clock_scl : inout std_logic; - -- I2C Temperature Sensor Interface - i2c_temp_sda : inout std_logic; - i2c_temp_scl : inout std_logic; - -- I2C Voltage Sensor Interface - i2c_vmon_sda : inout std_logic; - i2c_vmon_scl : inout std_logic -); -end slow_top; - -architecture rtl of slow_top is - -signal DATA : STD_LOGIC_VECTOR(31 DOWNTO 0); -signal TRIG0 : STD_LOGIC_VECTOR(7 DOWNTO 0); -signal CONTROL0 : STD_LOGIC_VECTOR(35 DOWNTO 0); - -signal OUTENC_CONN : std_logic_vector(3 downto 0); -signal INENC_PROTOCOL : std3_array(3 downto 0); -signal OUTENC_PROTOCOL : std3_array(3 downto 0); -signal DCARD_MODE : std4_array(3 downto 0); -signal TEMP_MON : std32_array(4 downto 0); -signal VOLT_MON : std32_array(7 downto 0); -signal init_reset_n : std_logic; -signal init_reset : std_logic; -signal reset_n : std_logic; -signal reset : std_logic; -signal ttlin_term : std_logic_vector(5 downto 0); -signal ttl_leds : std_logic_vector(15 downto 0); -signal status_leds : std_logic_vector(3 downto 0); -signal enc_leds : std_logic_vector(3 downto 0); -signal clk50_pad : std_logic; -signal clk50_pll : std_logic; -signal sysclk : std_logic; -signal spi_sclk : std_logic; -signal spi_dat : std_logic; - -begin - -spi_sclk_o <= spi_sclk; -spi_dat_o <= spi_dat; - ---SEL_GTXCLK1 <= '1'; -- FMC as clock source -SEL_GTXCLK1 <= '0'; -- Si570 as clock source - --- Encoder LEDs (D5-D8) -ENC_LED <= enc_leds; - --------------------------------------------------------------------------- --- Clock PLL and Startup Reset --------------------------------------------------------------------------- -clk50_buf : BUFG -port map ( - O => clk50_pad, - I => clk50_i -); - -clkgen_inst : entity work.clkgen -port map ( - CLK_IN1 => clk125_i, - CLK_OUT1 => clk50_pll, - RESET => '0', - LOCKED => reset_n - ); - -reset <= not reset_n; - -sysclk <= clk50_pad; -- clk50_pll; - --- --- Data Send/Receive Engine to Zynq --- -zynq_interface_inst : entity work.zynq_interface -generic map ( - STATUS_PERIOD => STATUS_PERIOD, - SYS_PERIOD => SYS_PERIOD -) -port map ( - clk_i => sysclk, - reset_i => reset, - - spi_sclk_i => spi_sclk_i, - spi_dat_i => spi_dat_i, - spi_sclk_o => spi_sclk, - spi_dat_o => spi_dat, - - ttlin_term_o => ttlin_term, - ttl_leds_o => ttl_leds, - status_leds_o => status_leds, - enc_leds_o => enc_leds, - outenc_conn_o => OUTENC_CONN, - - INENC_PROTOCOL => INENC_PROTOCOL, - OUTENC_PROTOCOL => OUTENC_PROTOCOL, - DCARD_MODE => DCARD_MODE, - TEMP_MON => TEMP_MON, - VOLT_MON => VOLT_MON -); - --- --- Daughter Card Control Interface --- -dcard_ctrl_inst : entity work.dcard_ctrl -port map ( - clk_i => sysclk, - reset_i => reset, - -- Encoder Daughter Card Control Interface - dcard_ctrl1_io => dcard_ctrl1_io, - dcard_ctrl2_io => dcard_ctrl2_io, - dcard_ctrl3_io => dcard_ctrl3_io, - dcard_ctrl4_io => dcard_ctrl4_io, - -- Front Panel Shift Register Interface - OUTENC_CONN => OUTENC_CONN, - INENC_PROTOCOL => INENC_PROTOCOL, - OUTENC_PROTOCOL => OUTENC_PROTOCOL, - DCARD_MODE => DCARD_MODE -); - --- --- Front Panel Shift Register Interface --- -fpanel_if_inst : entity work.fpanel_if -port map ( - clk_i => sysclk, - reset_i => reset, - ttlin_term_i => ttlin_term, - ttl_leds_i => ttl_leds, - status_leds_i => status_leds, - shift_reg_sdata_o => shift_reg_sdata_o, - shift_reg_sclk_o => shift_reg_sclk_o, - shift_reg_latch_o => shift_reg_latch_o, - shift_reg_oe_n_o => shift_reg_oe_n_o -); - --------------------------------------------------------------------------- --- Temp sensor interface --------------------------------------------------------------------------- -temp_sensors_inst : entity work.temp_sensors -port map ( - clk_i => sysclk, - reset_i => reset, - sda => i2c_temp_sda, - scl => i2c_temp_scl, - TEMP_MON => TEMP_MON -); - --------------------------------------------------------------------------- --- Voltage measurement interface --------------------------------------------------------------------------- -voltage_sensors_inst : entity work.voltage_sensors -port map ( - clk_i => sysclk, - reset_i => reset, - sda => i2c_vmon_sda, - scl => i2c_vmon_scl, - VOLT_MON => VOLT_MON -); - -end rtl; diff --git a/targets/PandABox/SlowFPGA/src/hdl/temp_sensors.vhd b/targets/PandABox/SlowFPGA/src/hdl/temp_sensors.vhd deleted file mode 100644 index 855bdc93c..000000000 --- a/targets/PandABox/SlowFPGA/src/hdl/temp_sensors.vhd +++ /dev/null @@ -1,224 +0,0 @@ --------------------------------------------------------------------------------- --- PandA Motion Project - 2016 --- Diamond Light Source, Oxford, UK --- SOLEIL Synchrotron, GIF-sur-YVETTE, France --- --- Author : Dr. Isa Uzun (isa.uzun@diamond.ac.uk) --------------------------------------------------------------------------------- --- --- Description : Read I2C temperature sensors in loop. --- --------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library unisim; -use unisim.vcomponents.all; - -library work; -use work.top_defines.all; -use work.support.all; -use work.addr_defines.all; - -entity temp_sensors is -port ( - -- 50MHz system clock - clk_i : in std_logic; - reset_i : in std_logic; - -- I2C Interface - sda : inout std_logic; - scl : inout std_logic; - -- Status registers - TEMP_MON : out std32_array(4 downto 0) -); -end temp_sensors; - -architecture rtl of temp_sensors is - -type i2c_fsm_t is (INIT, READ_DATA, NEXT_SLAVE); - --- Array of Slave addresses -constant SLAVE_ARRAY : std8_array(4 downto 0) := ( - "01001100", - "01001011", - "01001010", - "01001001", - "01001000"); - -signal i2c_fsm : i2c_fsm_t; -signal busy_prev : std_logic; -signal i2c_ena : std_logic; -signal i2c_addr : std_logic_vector(6 downto 0); -signal i2c_rw : std_logic; -signal i2c_data_wr : std_logic_vector(7 downto 0); -signal i2c_busy : std_logic; -signal i2c_data_rd : std_logic_vector(7 downto 0); -signal i2c_ack_error : std_logic; -signal i2c_rise : std_logic; -signal data_rd : std_logic_vector(15 downto 0); -signal i2c_start : std_logic; -signal sda_din : std_logic; -signal scl_din : std_logic; -signal sda_t : std_logic; -signal scl_t : std_logic; - -component icon -port ( - CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0) -); -end component; - -component ila -port ( - CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0); - CLK : IN STD_LOGIC; - DATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0); - TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0) -); -end component; - -signal CONTROL0 : STD_LOGIC_VECTOR(35 DOWNTO 0); -signal DATA : STD_LOGIC_VECTOR(63 DOWNTO 0); -signal TRIG0 : STD_LOGIC_VECTOR(7 DOWNTO 0); - -signal slave_index : natural range 0 to 4; - -begin - --------------------------------------------------------------------- --- 3-state I2C I/O Buffers --------------------------------------------------------------------- -iobuf_scl : iobuf -port map ( - I => '0', - O => scl_din, - IO => scl, - T => scl_t -); - -iobuf_sda : iobuf -port map ( - I => '0', - O => sda_din, - IO => sda, - T => sda_t -); - - --- Generate Internal from system clock -start_presc : entity work.prescaler -port map ( - clk_i => clk_i, - reset_i => reset_i, - PERIOD => TO_SVECTOR(50_000_000,32), -- 1sec - pulse_o => i2c_start -); - -i2c_master_inst : entity work.i2c_master -generic map ( - input_clk => 50_000_000, - bus_clk => 10_000 -) -port map ( - clk => clk_i, - reset => reset_i, - ena => i2c_ena, - addr => i2c_addr, - rw => i2c_rw, - data_wr => i2c_data_wr, - busy => i2c_busy, - data_rd => i2c_data_rd, - ack_error => i2c_ack_error, - sda => sda_din, - scl => scl_din, - sda_t => sda_t, - scl_t => scl_t -); - --------------------------------------------------------------------- --- Main read state machine loops through all SLAVES --------------------------------------------------------------------- -i2c_rise <= i2c_busy and not busy_prev; - -process(clk_i) - variable busy_cnt : natural range 0 to 3; -begin - if rising_edge(clk_i) then - if (reset_i = '1') then - i2c_fsm <= INIT; - slave_index <= 0; - busy_cnt := 0; - busy_prev <= '1'; - i2c_rw <= '1'; - i2c_ena <= '0'; - i2c_addr <= (others => '0'); - i2c_data_wr <= X"00"; - data_rd <= (others => '0'); - TEMP_MON <= (others => (others => '0')); - else - busy_prev <= i2c_busy; - - case (i2c_fsm) is - -- Wait for 1 sec to start - when INIT => - if (i2c_busy = '0' and i2c_start = '1') then - i2c_fsm <= READ_DATA; - end if; - - -- Pointer register defaults to temperature reg. So, - -- directly Read i2 bytes from the current slave - when READ_DATA => - if (i2c_rise = '1') then - busy_cnt := busy_cnt + 1; - end if; - - case busy_cnt is - -- Initiate the transaction by writing to - -- pointer register. - -- '0' is write, '1' is read - when 0 => - i2c_ena <= '1'; - i2c_addr <= SLAVE_ARRAY(slave_index)(6 downto 0); - i2c_rw <= '1'; -- read - when 1 => - if (i2c_busy = '0') then - data_rd(15 downto 8) <= i2c_data_rd; - end if; - when 2 => - i2c_ena <= '0'; - if (i2c_busy = '0') then - data_rd(7 downto 0) <= i2c_data_rd; - busy_cnt := 0; - i2c_fsm <= NEXT_SLAVE; - end if; - - when others => NULL; - end case; - - -- Latch read data and move to next slave - when NEXT_SLAVE => - if (i2c_start = '1') then - if (slave_index = 4) then - slave_index <= 0; - else - slave_index <= slave_index + 1; - end if; - - i2c_fsm <= READ_DATA; - end if; - - -- Latch and sign convert sensor data. It has 0.5C - -- resolution - TEMP_MON(slave_index) <= - std_logic_vector(resize(signed(data_rd(15 downto 8)), 32)); - - when others => NULL; - - end case; - end if; - end if; -end process; - -end rtl; diff --git a/targets/PandABox/SlowFPGA/src/hdl/ttl_ctrl.vhd b/targets/PandABox/SlowFPGA/src/hdl/ttl_ctrl.vhd deleted file mode 100644 index a51589314..000000000 --- a/targets/PandABox/SlowFPGA/src/hdl/ttl_ctrl.vhd +++ /dev/null @@ -1,83 +0,0 @@ --------------------------------------------------------------------------------- --- PandA Motion Project - 2016 --- Diamond Light Source, Oxford, UK --- SOLEIL Synchrotron, GIF-sur-YVETTE, France --- --- Author : Dr. Isa Uzun (isa.uzun@diamond.ac.uk) --------------------------------------------------------------------------------- --- --- Description : Encoder Daugther Card receive interface. --- --- --------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.support.all; -use work.slow_defines.all; - -entity ttl_ctrl is -generic ( - AW : natural := 10; - DW : natural := 32 -); -port ( - -- 50MHz system clock - clk_i : in std_logic; - reset_i : in std_logic; - -- Serial Receive Interface - rx_addr_i : in std_logic_vector(AW-1 downto 0); - rx_valid_i : in std_logic; - rx_data_i : in std_logic_vector(DW-1 downto 0); - -- Encoder Daughter Card Control interface - ttlin_term_o : out std_logic_vector(5 downto 0) -); -end ttl_ctrl; - -architecture rtl of ttl_ctrl is - -signal rx_addr : natural range 0 to (2**AW - 1); - -begin - -rx_addr <= to_integer(unsigned(rx_addr_i)); - --- --- Read Register Interface --- -process(clk_i) begin - if rising_edge(clk_i) then - if (reset_i = '1') then - ttlin_term_o <= (others => '0'); - else - if (rx_valid_i = '1' and rx_addr = TTLIN1_TERM) then - ttlin_term_o(0) <= rx_data_i(0); - end if; - - if (rx_valid_i = '1' and rx_addr = TTLIN2_TERM) then - ttlin_term_o(1) <= rx_data_i(0); - end if; - - if (rx_valid_i = '1' and rx_addr = TTLIN3_TERM) then - ttlin_term_o(2) <= rx_data_i(0); - end if; - - if (rx_valid_i = '1' and rx_addr = TTLIN4_TERM) then - ttlin_term_o(3) <= rx_data_i(0); - end if; - - if (rx_valid_i = '1' and rx_addr = TTLIN5_TERM) then - ttlin_term_o(4) <= rx_data_i(0); - end if; - - if (rx_valid_i = '1' and rx_addr = TTLIN6_TERM) then - ttlin_term_o(5) <= rx_data_i(0); - end if; - end if; - end if; -end process; - -end rtl; diff --git a/targets/PandABox/SlowFPGA/src/hdl/voltage_sensors.vhd b/targets/PandABox/SlowFPGA/src/hdl/voltage_sensors.vhd deleted file mode 100644 index 923feb6bd..000000000 --- a/targets/PandABox/SlowFPGA/src/hdl/voltage_sensors.vhd +++ /dev/null @@ -1,312 +0,0 @@ --------------------------------------------------------------------------------- --- PandA Motion Project - 2016 --- Diamond Light Source, Oxford, UK --- SOLEIL Synchrotron, GIF-sur-YVETTE, France --- --- Author : Dr. Isa Uzun (isa.uzun@diamond.ac.uk) --------------------------------------------------------------------------------- --- --- Description : Read I2C temperature sensors in loop. --- --------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library unisim; -use unisim.vcomponents.all; - -library work; -use work.top_defines.all; -use work.support.all; - -entity voltage_sensors is -port ( - -- 50MHz system clock - clk_i : in std_logic; - reset_i : in std_logic; - -- I2C Interface - sda : inout std_logic; - scl : inout std_logic; - -- Status registers - VOLT_MON : out std32_array(7 downto 0) -); -end voltage_sensors; - -architecture rtl of voltage_sensors is - -component icon -port ( - CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0) -); -end component; - -component ila -port ( - CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0); - CLK : IN STD_LOGIC; - DATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0); - TRIG0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0) -); -end component; - -signal DATA : STD_LOGIC_VECTOR(63 DOWNTO 0); -signal TRIG0 : STD_LOGIC_VECTOR(7 DOWNTO 0); -signal CONTROL0 : STD_LOGIC_VECTOR(35 DOWNTO 0); - -type i2c_fsm_t is (INIT, SET_ENABLE, SET_CONTROL, READ_DATA, NEXT_CHANNEL); - --- Array of Slave addresses -constant SLAVE_ADDR : std_logic_vector(6 downto 0) := "1001100"; --- Enable register addr -constant ENABLE_ADDR : unsigned(7 downto 0) := X"01"; --- Control register addr -constant CONTROL_ADDR : unsigned(7 downto 0) := X"08"; --- V_N registers start address -constant READ_ADDR : unsigned(7 downto 0) := X"0A"; - -signal i2c_fsm : i2c_fsm_t; -signal busy_prev : std_logic; -signal i2c_ena : std_logic; -signal i2c_addr : std_logic_vector(6 downto 0); -signal i2c_rw : std_logic; -signal i2c_data_wr : unsigned(7 downto 0); -signal i2c_busy : std_logic; -signal i2c_data_rd : std_logic_vector(7 downto 0); -signal i2c_ack_error : std_logic; -signal i2c_rise : std_logic; -signal data_rd : std_logic_vector(15 downto 0); -signal i2c_start : std_logic; -signal sda_din : std_logic; -signal scl_din : std_logic; -signal sda_t : std_logic; -signal scl_t : std_logic; -signal channel_index : natural range 0 to 7; - -begin - --------------------------------------------------------------------- --- 3-state I2C I/O Buffers --------------------------------------------------------------------- -iobuf_scl : iobuf -port map ( - I => '0', - O => scl_din, - IO => scl, - T => scl_t -); - -iobuf_sda : iobuf -port map ( - I => '0', - O => sda_din, - IO => sda, - T => sda_t -); - --- Generate Internal from system clock -start_presc : entity work.prescaler -port map ( - clk_i => clk_i, - reset_i => reset_i, - PERIOD => TO_SVECTOR(50_000_000,32), -- 1sec - pulse_o => i2c_start -); - -i2c_master_inst : entity work.i2c_master -generic map ( - input_clk => 50_000_000, - bus_clk => 10_000 -) -port map ( - clk => clk_i, - reset => reset_i, - ena => i2c_ena, - addr => i2c_addr, - rw => i2c_rw, - data_wr => std_logic_vector(i2c_data_wr), - busy => i2c_busy, - data_rd => i2c_data_rd, - ack_error => i2c_ack_error, - sda => sda_din, - scl => scl_din, - sda_t => sda_t, - scl_t => scl_t -); - --------------------------------------------------------------------- --- Main read state machine loops through all SLAVES --------------------------------------------------------------------- -i2c_rise <= i2c_busy and not busy_prev; - -process(clk_i) - variable busy_cnt : natural range 0 to 3; -begin - if rising_edge(clk_i) then - if (reset_i = '1') then - i2c_fsm <= INIT; - channel_index <= 0; - busy_cnt := 0; - busy_prev <= '1'; - i2c_rw <= '1'; - i2c_ena <= '0'; - i2c_addr <= (others => '0'); - i2c_data_wr <= X"00"; - data_rd <= (others => '0'); - VOLT_MON <= (others => (others => '0')); - else - busy_prev <= i2c_busy; - - case (i2c_fsm) is - -- Wait for 1 sec to start - when INIT => - if (i2c_busy = '0' and i2c_start = '1') then - i2c_fsm <= SET_ENABLE; - end if; - - -- Enable all channels - when SET_ENABLE => - if (i2c_rise = '1') then - busy_cnt := busy_cnt + 1; - end if; - - case busy_cnt is - -- Write command to send the register address - when 0 => - i2c_ena <= '1'; - i2c_addr <= SLAVE_ADDR; - i2c_rw <= '0'; -- write - i2c_data_wr <= ENABLE_ADDR; - - -- Read command to read 2 consecutive bytes - when 1 => - i2c_data_wr <= X"FF"; -- Enable all data - when 2 => - i2c_ena <= '0'; - if (i2c_busy = '0' and i2c_start = '1') then - busy_cnt := 0; - i2c_fsm <= SET_CONTROL; - end if; - - when others => NULL; - end case; - - -- Set repeated conversion - when SET_CONTROL => - if (i2c_rise = '1') then - busy_cnt := busy_cnt + 1; - end if; - - case busy_cnt is - -- Write command to send the register address - when 0 => - i2c_ena <= '1'; - i2c_addr <= SLAVE_ADDR; - i2c_rw <= '0'; -- write - i2c_data_wr <= CONTROL_ADDR; - - -- Read command to read 2 consecutive bytes - when 1 => - i2c_data_wr <= X"10"; -- Repeated capture - when 2 => - i2c_ena <= '0'; - if (i2c_busy = '0' and i2c_start = '1') then - busy_cnt := 0; - -- Latch register start address - i2c_data_wr <= READ_ADDR; - -- Move to read data loop - i2c_fsm <= READ_DATA; - end if; - - when others => NULL; - end case; - - -- Pointer register defaults to temperature reg. So, - -- directly Read i2 bytes from the current slave - when READ_DATA => - if (i2c_rise = '1') then - busy_cnt := busy_cnt + 1; - end if; - - case busy_cnt is - -- Write command to send the register address - when 0 => - i2c_ena <= '1'; - i2c_addr <= SLAVE_ADDR; - i2c_rw <= '0'; -- write - - -- Read command to read 2 consecutive bytes - when 1 => - i2c_rw <= '1'; -- read - - when 2 => - if (i2c_busy = '0') then - data_rd(15 downto 8) <= i2c_data_rd; - end if; - - when 3 => - i2c_ena <= '0'; - if (i2c_busy = '0') then - data_rd(7 downto 0) <= i2c_data_rd; - busy_cnt := 0; - i2c_fsm <= NEXT_CHANNEL; - end if; - - when others => NULL; - end case; - - -- Latch read data and move to next slave - when NEXT_CHANNEL => - if (i2c_start = '1') then - -- Wrap up register address after the last - -- channel. - if (channel_index = 7) then - i2c_data_wr <= READ_ADDR; - channel_index <= 0; - else - i2c_data_wr <= i2c_data_wr + 2; - channel_index <= channel_index+ 1; - end if; - - i2c_fsm <= READ_DATA; - end if; - - -- Bits[14:0] is used for Volt - VOLT_MON(channel_index) <= - std_logic_vector(resize(signed(data_rd(14 downto 0)), 32)); - - when others => NULL; - - end case; - end if; - end if; -end process; - ---icon_inst : icon ---port map ( --- CONTROL0 => CONTROL0 ---); --- ---ila_inst : ila ---port map ( --- CONTROL => CONTROL0, --- CLK => clk_i, --- DATA => DATA, --- TRIG0 => TRIG0 ---); --- ---TRIG0(0) <= scl_din; ---TRIG0(1) <= sda_din; ---TRIG0(2) <= i2c_start; ---TRIG0(7 downto 3) <= (others => '0'); --- ---DATA(0) <= scl_din; ---DATA(1) <= sda_din; ---DATA(2) <= i2c_start; ---DATA(3) <= i2c_ena; ---DATA(4) <= i2c_busy; ---DATA(20 downto 5) <= data_rd; ---DATA(63 downto 21) <= (others => '0'); - -end rtl; diff --git a/targets/PandABox/SlowFPGA/src/hdl/zynq_interface.vhd b/targets/PandABox/SlowFPGA/src/hdl/zynq_interface.vhd deleted file mode 100644 index 3cb87efd8..000000000 --- a/targets/PandABox/SlowFPGA/src/hdl/zynq_interface.vhd +++ /dev/null @@ -1,206 +0,0 @@ --------------------------------------------------------------------------------- --- PandA Motion Project - 2016 --- Diamond Light Source, Oxford, UK --- SOLEIL Synchrotron, GIF-sur-YVETTE, France --- --- Author : Dr. Isa Uzun (isa.uzun@diamond.ac.uk) --------------------------------------------------------------------------------- --- --- Description : Serial Interface core is used to handle communication between --- Zynq and Slow Control FPGA. --- --------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.support.all; -use work.top_defines.all; -use work.slow_defines.all; -use work.version.all; -use work.addr_defines.all; - -entity zynq_interface is -generic ( - STATUS_PERIOD : natural := 10_000_000;-- 10ms - SYS_PERIOD : natural := 20 -- 20ns/50MHz -); -port ( - -- 50MHz system clock - clk_i : in std_logic; - reset_i : in std_logic; - -- Encoder Daughter Card Control and Status Registers - INENC_PROTOCOL : buffer std3_array(3 downto 0); - OUTENC_PROTOCOL : buffer std3_array(3 downto 0); - DCARD_MODE : in std4_array(3 downto 0); - TEMP_MON : in std32_array(4 downto 0); - VOLT_MON : in std32_array(7 downto 0); - -- Front-Panel Control - ttlin_term_o : out std_logic_vector(5 downto 0); - ttl_leds_o : out std_logic_vector(15 downto 0); - status_leds_o : out std_logic_vector(3 downto 0); - enc_leds_o : out std_logic_vector(3 downto 0); - outenc_conn_o : out std_logic_vector(3 downto 0); - -- Serial Physical interface - spi_sclk_i : in std_logic; - spi_dat_i : in std_logic; - spi_sclk_o : out std_logic; - spi_dat_o : out std_logic -); -end zynq_interface; - -architecture rtl of zynq_interface is - --- Pack dcard outenc and inenc readback values with mode pin value -function dcard_pack ( - outenc : std_logic_vector; - inenc : std_logic_vector; - mode : std_logic_vector -) return std_logic_vector is -begin - -- Align at 8-bit boundries - return X"00" & "00000" & outenc & "00000" & inenc & X"0" & mode; -end dcard_pack; - --- There are 32 status registers allocated for slow controller -signal STATUS_LIST : std32_array(31 downto 0) := - (others => (others => '0')); -signal register_index : natural range 0 to 31; - -signal wr_req : std_logic; -signal wr_dat : std_logic_vector(31 downto 0); -signal wr_adr : std_logic_vector(9 downto 0); -signal rd_adr : std_logic_vector(9 downto 0); -signal rd_dat : std_logic_vector(31 downto 0); -signal rd_val : std_logic; -signal busy : std_logic; -signal wr_start : std_logic; - -begin - --------------------------------------------------------------------------- --- Serial Interface TX/RX Engine IP --------------------------------------------------------------------------- -serial_engine_inst : entity work.serial_engine -generic map ( - SYS_PERIOD => SYS_PERIOD -) -port map ( - clk_i => clk_i, - reset_i => reset_i, - - wr_rst_i => '0', - wr_req_i => wr_req, - wr_dat_i => wr_dat, - wr_adr_i => wr_adr, - rd_adr_o => rd_adr, - rd_dat_o => rd_dat, - rd_val_o => rd_val, - busy_o => busy, - - spi_sclk_i => spi_sclk_i, - spi_dat_i => spi_dat_i, - spi_sclk_o => spi_sclk_o, - spi_dat_o => spi_dat_o -); - --- --- Receive Configuration Registers from Zynq --- -enc_ctrl_inst : entity work.enc_ctrl -port map ( - clk_i => clk_i, - reset_i => reset_i, - rx_addr_i => rd_adr, - rx_valid_i => rd_val, - rx_data_i => rd_dat, - INENC_PROTOCOL => INENC_PROTOCOL, - OUTENC_PROTOCOL => OUTENC_PROTOCOL -); - -ttl_ctrl_inst : entity work.ttl_ctrl -port map ( - clk_i => clk_i, - reset_i => reset_i, - rx_addr_i => rd_adr, - rx_valid_i => rd_val, - rx_data_i => rd_dat, - ttlin_term_o => ttlin_term_o -); - -leds_ctrl_inst : entity work.leds_ctrl -port map ( - clk_i => clk_i, - reset_i => reset_i, - rx_addr_i => rd_adr, - rx_valid_i => rd_val, - rx_data_i => rd_dat, - ttl_leds_o => ttl_leds_o, - status_leds_o => status_leds_o, - enc_leds_o => enc_leds_o, - outenc_conn_o => outenc_conn_o -); - --- --- Transmit Interface : --- Transmit the status registers to Zynq in a rolling fashion at 10ms intervals --- -send_trigger : entity work.prescaler -port map ( - clk_i => clk_i, - reset_i => reset_i, - PERIOD => TO_SVECTOR(STATUS_PERIOD/SYS_PERIOD, 32), - pulse_o => wr_start -); - --- Assemble Status Register List -STATUS_LIST(SLOW_VERSION) <= FPGA_VERSION; -STATUS_LIST(DCARD1_MODE) <= dcard_pack(OUTENC_PROTOCOL(0), INENC_PROTOCOL(0), DCARD_MODE(0)); -STATUS_LIST(DCARD2_MODE) <= dcard_pack(OUTENC_PROTOCOL(1), INENC_PROTOCOL(1), DCARD_MODE(1)); -STATUS_LIST(DCARD3_MODE) <= dcard_pack(OUTENC_PROTOCOL(2), INENC_PROTOCOL(2), DCARD_MODE(2)); -STATUS_LIST(DCARD4_MODE) <= dcard_pack(OUTENC_PROTOCOL(3), INENC_PROTOCOL(3), DCARD_MODE(3)); -STATUS_LIST(TEMP_PSU) <= TEMP_MON(0); -STATUS_LIST(TEMP_SFP) <= TEMP_MON(1); -STATUS_LIST(TEMP_ENC_L) <= TEMP_MON(2); -STATUS_LIST(TEMP_PICO) <= TEMP_MON(3); -STATUS_LIST(TEMP_ENC_R) <= TEMP_MON(4); -STATUS_LIST(ALIM_12V0) <= VOLT_MON(0); -STATUS_LIST(PICO_5V0) <= VOLT_MON(1); -STATUS_LIST(IO_5V0) <= VOLT_MON(2); -STATUS_LIST(SFP_3V3) <= VOLT_MON(3); -STATUS_LIST(FMC_15VN) <= VOLT_MON(4); -STATUS_LIST(FMC_15VP) <= VOLT_MON(5); -STATUS_LIST(ENC_24V) <= VOLT_MON(6); -STATUS_LIST(FMC_12V) <= VOLT_MON(7); - -process(clk_i) begin - if rising_edge(clk_i) then - if (reset_i = '1') then - register_index <= 0; - wr_req <= '0'; - wr_adr <= (others => '0'); - wr_dat <= (others => '0'); - else - -- Cycle through registers contiuously. - if (busy = '0' and wr_start = '1') then - wr_req <= '1'; - wr_adr <= TO_SVECTOR(register_index, 10); - wr_dat <= STATUS_LIST(register_index); - -- Keep track of registers - if (register_index = 31) then - register_index <= 0; - else - register_index <= register_index + 1; - end if; - else - wr_req <= '0'; - wr_adr <= wr_adr; - wr_dat <= wr_dat; - end if; - end if; - end if; -end process; - -end rtl; diff --git a/targets/PandABox/SlowFPGA/syn/constr/slow_top.ucf b/targets/PandABox/SlowFPGA/syn/constr/slow_top.ucf deleted file mode 100644 index c2b4515c8..000000000 --- a/targets/PandABox/SlowFPGA/syn/constr/slow_top.ucf +++ /dev/null @@ -1,108 +0,0 @@ - -#Created by Constraints Editor (xc6slx9-tqg144-3) - 2012/01/10 -NET "clk50_i" TNM_NET = "clk50_i"; -TIMESPEC TS_clk50_i = PERIOD "clk50_i" 20 ns HIGH 50 %; - -NET "clk125_i" TNM_NET = "clk125_i"; -TIMESPEC TS_clk50_i = PERIOD "clk125_i" 8 ns HIGH 50 %; - -NET "clk50_i" LOC = P134; -NET "clk125_i" LOC = P92; - -NET "spi_sclk_i" LOC = P69; # SPI_FPGA_CLK -NET "spi_dat_i" LOC = P66; # SPI_FPGA_DI -NET "spi_sclk_o" LOC = P133; # SPI_FPGA_CS -NET "spi_dat_o" LOC = P64; # SPI_FPGA_DO - -NET "shift_reg_sdata_o" LOC = P7; -NET "shift_reg_sclk_o" LOC = P8; -NET "shift_reg_latch_o" LOC = P9; -NET "shift_reg_oe_n_o" LOC = P10; - -NET "dcard_ctrl1_io[0]" LOC = P14; -NET "dcard_ctrl1_io[1]" LOC = P15; -NET "dcard_ctrl1_io[2]" LOC = P16; -NET "dcard_ctrl1_io[3]" LOC = P17; -NET "dcard_ctrl1_io[4]" LOC = P21; -NET "dcard_ctrl1_io[5]" LOC = P22; -NET "dcard_ctrl1_io[6]" LOC = P23; -NET "dcard_ctrl1_io[7]" LOC = P24; -NET "dcard_ctrl1_io[8]" LOC = P26; -NET "dcard_ctrl1_io[9]" LOC = P27; -NET "dcard_ctrl1_io[10]" LOC = P29; -NET "dcard_ctrl1_io[11]" LOC = P30; -NET "dcard_ctrl1_io[12]" LOC = P32; -NET "dcard_ctrl1_io[13]" LOC = P33 | PULLUP; -NET "dcard_ctrl1_io[14]" LOC = P34 | PULLUP; -NET "dcard_ctrl1_io[15]" LOC = P35 | PULLUP; - -NET "dcard_ctrl2_io[0]" LOC = P38; -NET "dcard_ctrl2_io[1]" LOC = P40; -NET "dcard_ctrl2_io[2]" LOC = P41; -NET "dcard_ctrl2_io[3]" LOC = P43; -NET "dcard_ctrl2_io[4]" LOC = P44; -NET "dcard_ctrl2_io[5]" LOC = P45; -NET "dcard_ctrl2_io[6]" LOC = P46; -NET "dcard_ctrl2_io[7]" LOC = P47; -NET "dcard_ctrl2_io[8]" LOC = P48; -NET "dcard_ctrl2_io[9]" LOC = P50; -NET "dcard_ctrl2_io[10]" LOC = P51; -NET "dcard_ctrl2_io[11]" LOC = P55; -NET "dcard_ctrl2_io[12]" LOC = P56; -NET "dcard_ctrl2_io[13]" LOC = P57 | PULLUP; -NET "dcard_ctrl2_io[14]" LOC = P58 | PULLUP; -NET "dcard_ctrl2_io[15]" LOC = P59 | PULLUP; - -NET "dcard_ctrl3_io[0]" LOC = P74; -NET "dcard_ctrl3_io[1]" LOC = P75; -NET "dcard_ctrl3_io[2]" LOC = P78; -NET "dcard_ctrl3_io[3]" LOC = P79; -NET "dcard_ctrl3_io[4]" LOC = P80; -NET "dcard_ctrl3_io[5]" LOC = P81; -NET "dcard_ctrl3_io[6]" LOC = P82; -NET "dcard_ctrl3_io[7]" LOC = P83; -NET "dcard_ctrl3_io[8]" LOC = P97; -NET "dcard_ctrl3_io[9]" LOC = P98; -NET "dcard_ctrl3_io[10]" LOC = P99; -NET "dcard_ctrl3_io[11]" LOC = P100; -NET "dcard_ctrl3_io[12]" LOC = P101; -NET "dcard_ctrl3_io[13]" LOC = P102 | PULLUP; -NET "dcard_ctrl3_io[14]" LOC = P104 | PULLUP; -NET "dcard_ctrl3_io[15]" LOC = P105 | PULLUP; - -NET "dcard_ctrl4_io[0]" LOC = P111; -NET "dcard_ctrl4_io[1]" LOC = P112; -NET "dcard_ctrl4_io[2]" LOC = P114; -NET "dcard_ctrl4_io[3]" LOC = P115; -NET "dcard_ctrl4_io[4]" LOC = P116; -NET "dcard_ctrl4_io[5]" LOC = P117; -NET "dcard_ctrl4_io[6]" LOC = P118; -NET "dcard_ctrl4_io[7]" LOC = P119; -NET "dcard_ctrl4_io[8]" LOC = P120; -NET "dcard_ctrl4_io[9]" LOC = P121; -NET "dcard_ctrl4_io[10]" LOC = P123; -NET "dcard_ctrl4_io[11]" LOC = P124; -NET "dcard_ctrl4_io[12]" LOC = P126; -NET "dcard_ctrl4_io[13]" LOC = P127 | PULLUP; -NET "dcard_ctrl4_io[14]" LOC = P131 | PULLUP; -NET "dcard_ctrl4_io[15]" LOC = P132 | PULLUP; - -NET "i2c_sfp_sda" LOC = P87; -NET "i2c_sfp_scl" LOC = P88; - -NET "i2c_clock_sda" LOC = P141; -NET "i2c_clock_scl" LOC = P142; - -NET "i2c_temp_sda" LOC = P61; -NET "i2c_temp_scl" LOC = P62; - -NET "i2c_vmon_sda" LOC = P84; -NET "i2c_vmon_scl" LOC = P85; - -NET "SEL_GTXCLK1" LOC = P144; - -NET "ENC_LED[0]" LOC = P137; -NET "ENC_LED[1]" LOC = P138; -NET "ENC_LED[2]" LOC = P139; -NET "ENC_LED[3]" LOC = P140; - diff --git a/targets/PandABox/SlowFPGA/syn/xilinx/loadFPGA.cmd b/targets/PandABox/SlowFPGA/syn/xilinx/loadFPGA.cmd deleted file mode 100644 index 066e874da..000000000 --- a/targets/PandABox/SlowFPGA/syn/xilinx/loadFPGA.cmd +++ /dev/null @@ -1,9 +0,0 @@ -setMode -bs -setCable -port auto -identify -inferir -identifyMPM -assignFile -p 4 -file "../run/slow_top.bit" -setAttribute -position 4 -attr packageName -value "" -program -p 4 -defaultVersion 0 -quit - diff --git a/targets/PandABox/SlowFPGA/syn/xilinx/loadPROM.cmd b/targets/PandABox/SlowFPGA/syn/xilinx/loadPROM.cmd deleted file mode 100644 index 93719f347..000000000 --- a/targets/PandABox/SlowFPGA/syn/xilinx/loadPROM.cmd +++ /dev/null @@ -1,8 +0,0 @@ -setMode -bs -setCable -port auto -Identify -inferir -identifyMPM -assignFile -p 3 -file slow_top.mcs -Program -p 3 -e -v - -quit diff --git a/targets/PandABox/SlowFPGA/syn/xilinx/slow_top.files b/targets/PandABox/SlowFPGA/syn/xilinx/slow_top.files deleted file mode 100644 index bd06450fe..000000000 --- a/targets/PandABox/SlowFPGA/syn/xilinx/slow_top.files +++ /dev/null @@ -1,14 +0,0 @@ -vhdl work common_hdl/defines/*.vhd -vhdl work target_dir/hdl/slow_defines.vhd -vhdl work autogen_hdl/addr_defines.vhd -vhdl work autogen_hdl/version.vhd -vhdl work autogen_hdl/top_defines.vhd -vhdl work common_hdl/serial_engine_rx.vhd -vhdl work common_hdl/serial_engine_tx.vhd -vhdl work common_hdl/serial_engine.vhd -vhdl work common_hdl/serial_link_detect.vhd -vhdl work common_hdl/shifter_in.vhd -vhdl work common_hdl/ssi_clock_gen.vhd -vhdl work common_hdl/prescaler.vhd -vhdl work target_dir/SlowFPGA/src/hdl/*.vhd - diff --git a/targets/PandABox/SlowFPGA/syn/xilinx/slow_top.scr b/targets/PandABox/SlowFPGA/syn/xilinx/slow_top.scr deleted file mode 100644 index 8d2afa3fd..000000000 --- a/targets/PandABox/SlowFPGA/syn/xilinx/slow_top.scr +++ /dev/null @@ -1,9 +0,0 @@ -run --ifn slow_top.lst --ofn slow_top --ofmt NGC --p xc6slx9-3tqg144 --top slow_top --opt_mode area --opt_level 2 --keep_hierarchy Soft diff --git a/targets/PandABox/etc/panda-fpga.list b/targets/PandABox/etc/panda-fpga.list index 7642c980e..8d693a294 100644 --- a/targets/PandABox/etc/panda-fpga.list +++ b/targets/PandABox/etc/panda-fpga.list @@ -24,7 +24,6 @@ t bin etc/show_ipmi # Firmware b share/panda-fpga FPGA/panda_top.bin -b share/panda-fpga ../../targets/PandABox/SlowFPGA/slow_top.bin # Docs (built once for all zpkgs) t etc/www etc/panda-fpga.docs.html diff --git a/targets/PandABox/hdl/slow_defines.vhd b/targets/PandABox/hdl/slow_defines.vhd index 61632b4ea..4cecbf3e8 100644 --- a/targets/PandABox/hdl/slow_defines.vhd +++ b/targets/PandABox/hdl/slow_defines.vhd @@ -1,21 +1,13 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.top_defines.all; -use work.support.all; -use work.addr_defines.all; +-- NB: This file must be kept in sync between both the PandABlocks-FPGA +-- and PandABlocks-slowFPGA repository. Changing this file requires an +-- update to the major version number. package slow_defines is --- Number of Status Registers -constant REGS_NUM : natural := 4; - -- -- WRITE ONLY Registers -- -constant WRITE_RESET : natural := 0; +--constant WRITE_RESET : natural := 0; --unused constant INENC1_PROTOCOL : natural := 1; constant INENC2_PROTOCOL : natural := 2; constant INENC3_PROTOCOL : natural := 3; @@ -54,35 +46,10 @@ constant FMC_15VP : natural := 15; constant ENC_24V : natural := 16; constant FMC_12V : natural := 17; --- Input Encoder Address List -constant INPROT_ADDR_LIST : page_array(ENC_NUM-1 downto 0) := ( - TO_SVECTOR(INENC4_PROTOCOL, PAGE_AW), - TO_SVECTOR(INENC3_PROTOCOL, PAGE_AW), - TO_SVECTOR(INENC2_PROTOCOL, PAGE_AW), - TO_SVECTOR(INENC1_PROTOCOL, PAGE_AW) - ); - --- Output Encoder Address List -constant OUTPROT_ADDR_LIST : page_array(ENC_NUM-1 downto 0) := ( - TO_SVECTOR(OUTENC4_PROTOCOL, PAGE_AW), - TO_SVECTOR(OUTENC3_PROTOCOL, PAGE_AW), - TO_SVECTOR(OUTENC2_PROTOCOL, PAGE_AW), - TO_SVECTOR(OUTENC1_PROTOCOL, PAGE_AW) - ); - --- TTLIN TERM Address List -constant TTLTERM_ADDR_LIST : page_array(TTLIN_NUM-1 downto 0) := ( - TO_SVECTOR(TTLIN6_TERM, PAGE_AW), - TO_SVECTOR(TTLIN5_TERM, PAGE_AW), - TO_SVECTOR(TTLIN4_TERM, PAGE_AW), - TO_SVECTOR(TTLIN3_TERM, PAGE_AW), - TO_SVECTOR(TTLIN2_TERM, PAGE_AW), - TO_SVECTOR(TTLIN1_TERM, PAGE_AW) - ); - end slow_defines; package body slow_defines is end slow_defines; + diff --git a/targets/PandABox/target_incl.make b/targets/PandABox/target_incl.make deleted file mode 100644 index a4a1533b7..000000000 --- a/targets/PandABox/target_incl.make +++ /dev/null @@ -1,22 +0,0 @@ -SLOW_FPGA_BUILD_DIR = $(TGT_BUILD_DIR)/SlowFPGA -SLOW_BIN = $(TGT_BUILD_DIR)/SlowFPGA/slow_top.bin - -BITS_PREREQ += slow_fpga - -# Build SlowFPGA Firmware target - -# Slow FPFA requires VERSION_FILE to be present and correct, but does not check its timestamp, -# as every app contains its own built copy of VERSION_FILE. Instead it uses the $(VER) file, -# as we do not want to rebuild the Slow FPGA for each app if nothing else has changed. - -$(SLOW_BIN): $(TARGET_DIR)/SlowFPGA/SlowFPGA.make $(VER) | $(VERSION_FILE) - mkdir -p $(SLOW_FPGA_BUILD_DIR) - echo building SlowFPGA - source $(ISE) && \ - $(MAKE) -C $(SLOW_FPGA_BUILD_DIR) -f $< \ - TOP=$(TOP) SRC_DIR=$(TARGET_DIR)/SlowFPGA AUTOGEN=$(AUTOGEN) \ - bin - -slow_fpga : $(SLOW_BIN) -.PHONY: slow_fpga -