From 0050ceb1d7625d39d238f4560888a3177666aa9a Mon Sep 17 00:00:00 2001
From: Seth Foster <seth@opentrons.com>
Date: Fri, 6 Dec 2024 12:06:46 -0500
Subject: [PATCH] layers/meta-opentrons: maturin: add missing patch

---
 .../0001-Add-32-bit-RISC-V-support.patch      | 102 ++++++++++++++++++
 1 file changed, 102 insertions(+)
 create mode 100644 layers/meta-opentrons/recipes-devtools/python3-maturin/files/0001-Add-32-bit-RISC-V-support.patch

diff --git a/layers/meta-opentrons/recipes-devtools/python3-maturin/files/0001-Add-32-bit-RISC-V-support.patch b/layers/meta-opentrons/recipes-devtools/python3-maturin/files/0001-Add-32-bit-RISC-V-support.patch
new file mode 100644
index 00000000..a0ef0c9e
--- /dev/null
+++ b/layers/meta-opentrons/recipes-devtools/python3-maturin/files/0001-Add-32-bit-RISC-V-support.patch
@@ -0,0 +1,102 @@
+From a945706bd610c5400fc85a248d5e0c96ebd2e953 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Tue, 27 Feb 2024 10:38:49 -0800
+Subject: [PATCH] Add 32-bit RISC-V support
+
+Tested with qemuriscv32 and it builds fine with all tests passed on a
+qemu machine.
+
+Upstream-Status: Submitted [https://github.com/PyO3/maturin/pull/1969]
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+---
+ src/target.rs | 11 ++++++++++-
+ 1 file changed, 10 insertions(+), 1 deletion(-)
+
+diff --git a/src/target.rs b/src/target.rs
+index fbb93531..33fa9273 100644
+--- a/src/target.rs
++++ b/src/target.rs
+@@ -69,6 +69,7 @@ pub enum Arch {
+     X86_64,
+     S390X,
+     Wasm32,
++    Riscv32,
+     Riscv64,
+     Mips64el,
+     Mips64,
+@@ -91,6 +92,7 @@ impl fmt::Display for Arch {
+             Arch::X86_64 => write!(f, "x86_64"),
+             Arch::S390X => write!(f, "s390x"),
+             Arch::Wasm32 => write!(f, "wasm32"),
++            Arch::Riscv32 => write!(f, "riscv32"),
+             Arch::Riscv64 => write!(f, "riscv64"),
+             Arch::Mips64el => write!(f, "mips64el"),
+             Arch::Mips64 => write!(f, "mips64"),
+@@ -115,7 +117,7 @@ impl Arch {
+             Arch::Powerpc | Arch::Powerpc64Le | Arch::Powerpc64 => "powerpc",
+             Arch::X86 => "i386",
+             Arch::X86_64 => "amd64",
+-            Arch::Riscv64 => "riscv",
++            Arch::Riscv32 | Arch::Riscv64 => "riscv",
+             Arch::Mips64el | Arch::Mips64 | Arch::Mipsel | Arch::Mips => "mips",
+             // sparc64 is unsupported since FreeBSD 13.0
+             Arch::Sparc64 => "sparc64",
+@@ -139,6 +141,7 @@ fn get_supported_architectures(os: &Os) -> Vec<Arch> {
+             Arch::S390X,
+             Arch::X86,
+             Arch::X86_64,
++            Arch::Riscv32,
+             Arch::Riscv64,
+             Arch::Mips64el,
+             Arch::Mips64,
+@@ -158,6 +161,7 @@ fn get_supported_architectures(os: &Os) -> Vec<Arch> {
+             Arch::Powerpc64Le,
+             Arch::X86,
+             Arch::X86_64,
++            Arch::Riscv32,
+             Arch::Riscv64,
+             Arch::Mips64el,
+             Arch::Mipsel,
+@@ -171,6 +175,7 @@ fn get_supported_architectures(os: &Os) -> Vec<Arch> {
+             Arch::Powerpc,
+             Arch::Powerpc64,
+             Arch::Powerpc64Le,
++            Arch::Riscv32,
+             Arch::Riscv64,
+             Arch::Sparc64,
+         ],
+@@ -255,6 +260,7 @@ impl Target {
+             Architecture::Powerpc64le => Arch::Powerpc64Le,
+             Architecture::S390x => Arch::S390X,
+             Architecture::Wasm32 => Arch::Wasm32,
++            Architecture::Riscv32(_) => Arch::Riscv32,
+             Architecture::Riscv64(_) => Arch::Riscv64,
+             Architecture::Mips64(mips64_arch) => match mips64_arch {
+                 Mips64Architecture::Mips64el => Arch::Mips64el,
+@@ -343,6 +349,7 @@ impl Target {
+             Arch::X86_64 => "x86_64",
+             Arch::S390X => "s390x",
+             Arch::Wasm32 => "wasm32",
++            Arch::Riscv32 => "riscv32",
+             Arch::Riscv64 => "riscv64",
+             // It's kinda surprising that Python doesn't include the `el` suffix
+             Arch::Mips64el | Arch::Mips64 => "mips64",
+@@ -388,6 +395,7 @@ impl Target {
+             }
+             Arch::Armv6L
+             | Arch::Wasm32
++            | Arch::Riscv32
+             | Arch::Riscv64
+             | Arch::Mips64el
+             | Arch::Mips64
+@@ -418,6 +426,7 @@ impl Target {
+             | Arch::Wasm32
+             | Arch::Mipsel
+             | Arch::Mips
++            | Arch::Riscv32
+             | Arch::Powerpc => 32,
+         }
+     }
+-- 
+2.44.0
+