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SolaraCell.kicad_pcb
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SolaraCell.kicad_pcb
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(kicad_pcb (version 20221018) (generator pcbnew)
(general
(thickness 1.6)
)
(paper "A4")
(layers
(0 "F.Cu" signal)
(31 "B.Cu" signal)
(32 "B.Adhes" user "B.Adhesive")
(33 "F.Adhes" user "F.Adhesive")
(34 "B.Paste" user)
(35 "F.Paste" user)
(36 "B.SilkS" user "B.Silkscreen")
(37 "F.SilkS" user "F.Silkscreen")
(38 "B.Mask" user)
(39 "F.Mask" user)
(40 "Dwgs.User" user "User.Drawings")
(41 "Cmts.User" user "User.Comments")
(42 "Eco1.User" user "User.Eco1")
(43 "Eco2.User" user "User.Eco2")
(44 "Edge.Cuts" user)
(45 "Margin" user)
(46 "B.CrtYd" user "B.Courtyard")
(47 "F.CrtYd" user "F.Courtyard")
(48 "B.Fab" user)
(49 "F.Fab" user)
(50 "User.1" user)
(51 "User.2" user)
(52 "User.3" user)
(53 "User.4" user)
(54 "User.5" user)
(55 "User.6" user)
(56 "User.7" user)
(57 "User.8" user)
(58 "User.9" user)
)
(setup
(pad_to_mask_clearance 0)
(pcbplotparams
(layerselection 0x00010fc_ffffffff)
(plot_on_all_layers_selection 0x0000000_00000000)
(disableapertmacros false)
(usegerberextensions false)
(usegerberattributes true)
(usegerberadvancedattributes true)
(creategerberjobfile true)
(dashed_line_dash_ratio 12.000000)
(dashed_line_gap_ratio 3.000000)
(svgprecision 4)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(dxfpolygonmode true)
(dxfimperialunits true)
(dxfusepcbnewfont true)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(sketchpadsonfab false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 0)
(scaleselection 1)
(outputdirectory "gerbs/")
)
)
(net 0 "")
(net 1 "VBUS")
(net 2 "GND")
(net 3 "VLIPO")
(net 4 "/SOLAR+")
(net 5 "Net-(D2-K)")
(net 6 "Net-(D2-A)")
(net 7 "Net-(D3-K)")
(net 8 "Net-(D3-A)")
(net 9 "/THERM")
(net 10 "BQ_OUT")
(net 11 "/CE")
(net 12 "Net-(JP1-B)")
(net 13 "Net-(U1-ITERM)")
(net 14 "Net-(U1-ILIM)")
(net 15 "Net-(U1-ISET)")
(footprint "KiCad Footprints:PCBWay_CastellatedHole" (layer "F.Cu")
(tstamp 06439062-2886-4a9f-b08e-bddb5f61e296)
(at 139.7 68.58 -90)
(attr through_hole)
(fp_text reference "REF**" (at 0 -1.778 -90 unlocked) (layer "F.SilkS") hide
(effects (font (size 1 1) (thickness 0.1)))
(tstamp 8ca0b784-83fc-42d1-b3eb-90a01074e465)
)
(fp_text value "PCBWay_CastellatedHole" (at 0 3.048 -90 unlocked) (layer "F.Fab") hide
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 8abd75aa-3328-413a-a895-bb9a74de3243)
)
(fp_text user "${REFERENCE}" (at 0 4.572 -90 unlocked) (layer "F.Fab") hide
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 676d1d95-fcfe-44c3-ac6c-e344c94c6265)
)
(pad "1" thru_hole rect (at 0 0 270) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (tstamp c2984cb8-ee07-491c-a81a-f170a5b376cd))
(pad "1" thru_hole roundrect (at 0 1.27 270) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (roundrect_rratio 0.25)
(chamfer_ratio 0) (chamfer top_left top_right) (tstamp f08c380e-4e7a-4745-a64e-e7175e483484))
)
(footprint "KiCad Footprints:PCBWay_CastellatedHole" (layer "F.Cu")
(tstamp 22dd8dbb-b05c-4a72-9c94-88d96003c240)
(at 139.7 76.2 -90)
(attr through_hole)
(fp_text reference "REF**" (at 0 -1.778 -90 unlocked) (layer "F.SilkS") hide
(effects (font (size 1 1) (thickness 0.1)))
(tstamp b1d14052-4904-4dee-bf1e-c87a9f2ae287)
)
(fp_text value "PCBWay_CastellatedHole" (at 0 3.048 -90 unlocked) (layer "F.Fab") hide
(effects (font (size 1 1) (thickness 0.15)))
(tstamp f12bf990-e558-482c-ab7a-58085b83e948)
)
(fp_text user "${REFERENCE}" (at 0 4.572 -90 unlocked) (layer "F.Fab") hide
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 85f12ed0-03eb-4cad-82da-8eae2e20a13a)
)
(pad "1" thru_hole rect (at 0 0 270) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (tstamp 4ecc0f3f-ef51-4bf2-a248-f9c8d3f66649))
(pad "1" thru_hole roundrect (at 0 1.27 270) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (roundrect_rratio 0.25)
(chamfer_ratio 0) (chamfer top_left top_right) (tstamp 311213d5-5ad1-4cc9-b669-fb787c3c3a8e))
)
(footprint "KiCad Footprints:PCBWay_CastellatedHole" (layer "F.Cu")
(tstamp 287063af-900d-4be8-a01f-eef9d9c01bcc)
(at 119.38 78.74 90)
(attr through_hole)
(fp_text reference "REF**" (at 0 -1.778 90 unlocked) (layer "F.SilkS") hide
(effects (font (size 1 1) (thickness 0.1)))
(tstamp 23cc859d-5e7e-46e4-aa9d-2085d2fc7c25)
)
(fp_text value "PCBWay_CastellatedHole" (at 0 3.048 90 unlocked) (layer "F.Fab") hide
(effects (font (size 1 1) (thickness 0.15)))
(tstamp f0a46661-e6d0-403a-a3ee-c76f3e8403ed)
)
(fp_text user "${REFERENCE}" (at 0 4.572 90 unlocked) (layer "F.Fab") hide
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 5634a22d-c9ed-4cd1-88c0-69cc1ad555f8)
)
(pad "1" thru_hole rect (at 0 0 90) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (tstamp 61d9a35b-5249-42f6-9b28-f643d9cff977))
(pad "1" thru_hole roundrect (at 0 1.27 90) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (roundrect_rratio 0.25)
(chamfer_ratio 0) (chamfer top_left top_right) (tstamp ae4251b5-0233-4142-8a69-e77b05e82f27))
)
(footprint "KiCad Footprints:PCBWay_CastellatedHole" (layer "F.Cu")
(tstamp 2d617c7a-cca3-4338-8e19-b0844d39e5bc)
(at 119.38 76.2 90)
(attr through_hole)
(fp_text reference "REF**" (at 0 -1.778 90 unlocked) (layer "F.SilkS") hide
(effects (font (size 1 1) (thickness 0.1)))
(tstamp 8ac2cde2-d64b-49e6-aa4f-28a8b00d1847)
)
(fp_text value "PCBWay_CastellatedHole" (at 0 3.048 90 unlocked) (layer "F.Fab") hide
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 0114c489-78f7-4d51-b960-e3d0d6075938)
)
(fp_text user "${REFERENCE}" (at 0 4.572 90 unlocked) (layer "F.Fab") hide
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 49486289-d014-4429-8efc-5f83798af90c)
)
(pad "1" thru_hole rect (at 0 0 90) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (tstamp 4cd8af7b-5159-4935-9d56-bada3ff9f23b))
(pad "1" thru_hole roundrect (at 0 1.27 90) (size 1.7 1.7) (drill 1) (layers "*.Cu" "*.Mask") (roundrect_rratio 0.25)
(chamfer_ratio 0) (chamfer top_left top_right) (tstamp b0f6ca5a-598f-496b-88be-17bb00114491))
)
(footprint "Capacitor_SMD:C_0805_2012Metric" (layer "F.Cu")
(tstamp 360fb305-3a13-4d1e-b15e-1c845826cc55)
(at 122.809065 68.383653 90)
(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf, https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags "capacitor")
(property "Sheetfile" "SolaraCell.kicad_sch")
(property "Sheetname" "")
(property "ki_description" "Unpolarized capacitor, small symbol")
(property "ki_keywords" "capacitor cap")
(path "/41a65a7f-fade-485b-90ad-a69b066e5e39")
(attr smd)
(fp_text reference "C2" (at 0 -1.68 90) (layer "F.SilkS") hide
(effects (font (size 1 1) (thickness 0.15)))
(tstamp 423676d8-3d89-49b6-93dd-43239102f7f0)
)
(fp_text value "10uF" (at 0 1.68 90) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp c57cf69e-7705-4a9d-a9e0-622e7e6f3e4a)
)
(fp_text user "${REFERENCE}" (at 0 0 90) (layer "F.Fab")
(effects (font (size 0.5 0.5) (thickness 0.08)))
(tstamp 535e9197-3d65-43ce-aaeb-487287a19456)
)
(fp_line (start -0.261252 -0.735) (end 0.261252 -0.735)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp a9170a0a-38bb-42df-8f3d-75d8eb7d5669))
(fp_line (start -0.261252 0.735) (end 0.261252 0.735)
(stroke (width 0.12) (type solid)) (layer "F.SilkS") (tstamp 4538fc86-03de-4a82-ae7e-2ae78bfc6985))
(fp_line (start -1.7 -0.98) (end 1.7 -0.98)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 049b4429-da34-45a8-ba3e-11f511824c1d))
(fp_line (start -1.7 0.98) (end -1.7 -0.98)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 5a9e368d-bc61-4743-a330-f6ac58370c40))
(fp_line (start 1.7 -0.98) (end 1.7 0.98)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 962c51aa-7103-476a-862f-f54821444eb4))
(fp_line (start 1.7 0.98) (end -1.7 0.98)
(stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 8dec5743-ec62-45d9-85e7-e613482d53dc))
(fp_line (start -1 -0.625) (end 1 -0.625)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 5085957d-fa41-4b3c-86f7-b2c0af172ecb))
(fp_line (start -1 0.625) (end -1 -0.625)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp ad822511-3188-4a52-b2b9-0f490e9d79a2))
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(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp f1961327-a9c3-407d-85cc-06c44cf47983))
(fp_line (start 1 0.625) (end -1 0.625)
(stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 1c3736a7-715c-48c9-beff-919d469c0c31))
(pad "1" smd roundrect (at -0.95 0 90) (size 1 1.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 3 "VLIPO") (pintype "passive") (tstamp 363b4516-bfdd-440c-b154-79f7a22a911a))
(pad "2" smd roundrect (at 0.95 0 90) (size 1 1.45) (layers "F.Cu" "F.Paste" "F.Mask") (roundrect_rratio 0.25)
(net 2 "GND") (pintype "passive") (tstamp c26245ee-598c-4aa0-8ac6-480883e4321b))
(model "${KICAD6_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0805_2012Metric.wrl"
(offset (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(footprint "KiCad Footprints:PCBWay_CastellatedHole" (layer "F.Cu")
(tstamp 37d4c97e-dd4a-4e4f-bbad-a92ad600052b)
(at 139.7 78.74 -90)
(property "Sheetfile" "SolaraCell.kicad_sch")
(property "Sheetname" "")
(property "ki_description" "Generic connector, single row, 01x01, script generated (kicad-library-utils/schlib/autogen/connector/)")
(property "ki_keywords" "connector")
(path "/bbd55e50-1044-41dd-bede-668856045957")
(attr through_hole)
(fp_text reference "J6" (at 0 -1.778 -90 unlocked) (layer "F.SilkS") hide
(effects (font (size 1 1) (thickness 0.1)))
(tstamp cc23593f-75df-411c-a518-44a8d5eb9372)
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(fp_text value "GND" (at 0 3.048 -90 unlocked) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
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