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MCLZ8.ino
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MCLZ8.ino
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//
//
// File Name : MCLZ8.c
// Used on :
// Author : Ted Fried, MicroCore Labs
// Creation : 4/20/2022
//
// Description:
// ============
//
// Zilog Z80 emulator running on a Teensy 4.1.
//
//------------------------------------------------------------------------
//
// Modification History:
// =====================
//
// Revision 1 4/20/2022
// Initial revision
//
//
//------------------------------------------------------------------------
//
// Copyright (c) 2022 Ted Fried
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all
// copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
//
//------------------------------------------------------------------------
#include <stdint.h>
// Need for Command-line Code
#include <stdio.h>
// Teensy 4.1 pin assignments
//
#define PIN_RESET 23 // In-Buffer 1/8
#define PIN_CLK 21 // In-Buffer 2/8
#define PIN_NMI 19 // In-Buffer 3/8
#define PIN_INTR 20 // In-Buffer 4/8
#define PIN_WAIT 22 // In-Buffer 5/8
#define PIN_M1 12 // Out-direct
#define PIN_HALT 24 // Out-direct
#define PIN_RD 25 // Out-direct
#define PIN_WR 26 // Out-direct
#define PIN_MREQ 27 // Out-direct
#define PIN_IOREQ 28 // Out-direct
#define PIN_RFSH 29 // Out-direct
#define PIN_ADDR15 30 // Out-direct
#define PIN_ADDR14 31 // Out-direct
#define PIN_ADDR13 32 // Out-direct
#define PIN_ADDR12 33 // Out-direct
#define PIN_ADDR11 34 // Out-direct
#define PIN_ADDR10 35 // Out-direct
#define PIN_ADDR9 36 // Out-direct
#define PIN_ADDR8 37 // Out-direct
#define PIN_AD7_OUT 10 // Out-Buffer
#define PIN_AD6_OUT 9 // Out-Buffer
#define PIN_AD5_OUT 8 // Out-Buffer
#define PIN_AD4_OUT 7 // Out-Buffer
#define PIN_AD3_OUT 6 // Out-Buffer
#define PIN_AD2_OUT 5 // Out-Buffer
#define PIN_AD1_OUT 4 // Out-Buffer
#define PIN_AD0_OUT 3 // Out-Buffer
#define PIN_DATA_OE_n 2 // Out-Buffer
#define PIN_ADDR_LATCH_n 11 // Out-direct
#define PIN_AD7_IN 39 // In-Buffer
#define PIN_AD6_IN 40 // In-Buffer
#define PIN_AD5_IN 41 // In-Buffer
#define PIN_AD4_IN 14 // In-Buffer
#define PIN_AD3_IN 15 // In-Buffer
#define PIN_AD2_IN 16 // In-Buffer
#define PIN_AD1_IN 17 // In-Buffer
#define PIN_AD0_IN 18 // In-Buffer
// --------------------------------------------------------------------------------------------------
// --------------------------------------------------------------------------------------------------
#define OPCODE_READ_M1 0x07
#define MEM_WRITE_BYTE 0x02
#define MEM_READ_BYTE 0x03
#define IO_WRITE_BYTE 0x04
#define IO_READ_BYTE 0x05
#define INTERRUPT_ACK 0x09
#define flag_s ( (register_f & 0x80)==0 ? 0 : 1 )
#define flag_z ( (register_f & 0x40)==0 ? 0 : 1 )
#define flag_h ( (register_f & 0x10)==0 ? 0 : 1 )
#define flag_p ( (register_f & 0x04)==0 ? 0 : 1 )
#define flag_n ( (register_f & 0x02)==0 ? 0 : 1 )
#define flag_c ( (register_f & 0x01)==0 ? 0 : 1 )
#define REGISTER_BC ( (register_b<<8) | register_c )
#define REGISTER_DE ( (register_d<<8) | register_e )
#define REGISTER_HL ( (register_h<<8) | register_l )
#define REGISTER_AF ( (register_a<<8) | register_f )
#define REGISTER_IX ( (register_ixh<<8) | register_ixl )
#define REGISTER_IY ( (register_iyh<<8) | register_iyl )
#define REG_BC 1
#define REG_DE 2
#define REG_HL 3
#define REG_AF 4
#define REG_IX 5
#define REG_IY 6
// --------------------------------------------------------------------------------------------------
// --------------------------------------------------------------------------------------------------
uint8_t clock_counter=0;
uint8_t pause_interrupts=0;
uint8_t temp8=0;
uint8_t opcode_byte=0;
uint8_t opcode_second_byte=0;
uint8_t debounce_refresh=0;
uint8_t last_instruction_set_a_prefix=0;
uint8_t and_opcode=0;
uint8_t prefix_dd=0;
uint8_t prefix_fd=0;
uint8_t prefix_cb=0;
uint8_t inc_dec=0;
uint8_t with_carry=0;
uint8_t CB_opcode=0;
uint8_t cp_opcode=0;
uint8_t halt_in_progress=0;
uint8_t assert_iack_type0=0;
uint8_t cb_prefix_offset=0;
uint8_t register_a = 0;
uint8_t register_b = 0;
uint8_t register_c = 0;
uint8_t register_d = 0;
uint8_t register_e = 0;
uint8_t register_f = 0;
uint8_t register_h = 0;
uint8_t register_l = 0;
uint8_t register_a2 = 0;
uint8_t register_b2 = 0;
uint8_t register_c2 = 0;
uint8_t register_d2 = 0;
uint8_t register_e2 = 0;
uint8_t register_f2 = 0;
uint8_t register_h2 = 0;
uint8_t register_l2 = 0;
uint8_t register_iff1 = 0;
uint8_t register_iff2 = 0;
uint8_t register_im = 0;
uint8_t register_i = 0;
uint8_t register_r = 0;
uint8_t register_ixh = 0;
uint8_t register_ixl = 0;
uint8_t register_iyh = 0;
uint8_t register_iyl = 0;
uint8_t special = 0;
uint8_t nmi_latched=0;
uint8_t mode=0;
int incomingByte;
uint16_t register_sp = 0;
uint16_t register_pc = 0;
uint16_t temp16=0;
uint32_t direct_nmi=0;
uint32_t direct_nmi_d=0;
uint32_t direct_wait=0;
uint32_t direct_intr=0;
uint32_t direct_reset=0;
uint32_t GPIO6_raw_data=0;
// Internal RAM for acceleration
uint8_t internal_RAM[65536];
// Arrays which hold the Z80 clock cycles for each opcode
uint8_t Opcode_Timing_Main[256] = {0x0,0x6,0x3,0x2,0x0,0x0,0x3,0x0,0x0,0x7,0x3,0x2,0x0,0x0,0x3,0x0,0x4,0x6,0x3,0x2,0x0,0x0,0x3,0x0,0x8,0x7,0x3,0x2,0x0,0x0,0x3,0x0,0x3,0x6,0xc,0x2,0x0,0x0,0x3,0x0,0x3,0x7,0xc,0x2,0x0,0x0,0x3,0x0,0x3,0x6,0x9,0x2,0x7,0x7,0x6,0x0,0x3,0x7,0x9,0x2,0x0,0x0,0x3,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x3,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x3,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x3,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x3,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x3,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x3,0x0,0x3,0x3,0x3,0x3,0x3,0x3,0x0,0x3,0x0,0x0,0x0,0x0,0x0,0x0,0x3,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x3,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x3,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x3,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x3,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x3,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x3,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x3,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x3,0x0,0x1,0x6,0x6,0x6,0x6,0x7,0x3,0x7,0x1,0x6,0x6,0x0,0x6,0xd,0x3,0x7,0x1,0x6,0x6,0x7,0x6,0x7,0x3,0x7,0x1,0x0,0x6,0x7,0x6,0x0,0x3,0x7,0x1,0x6,0x6,0xf,0x6,0x7,0x3,0x7,0x1,0x0,0x6,0x0,0x6,0x0,0x3,0x7,0x1,0x6,0x6,0x0,0x6,0x7,0x3,0x7,0x1,0x2,0x6,0x0,0x6,0x0,0x3,0x7 };
uint8_t Opcode_Timing_ED[256] = {0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x8,0x8,0xb,0x10,0x4,0xa,0x4,0x5,0x8,0x8,0xb,0x10,0x4,0xa,0x4,0x5,0x8,0x8,0xb,0x10,0x4,0xa,0x4,0x5,0x8,0x8,0xb,0x10,0x4,0xa,0x4,0x5,0x8,0x8,0xb,0x10,0x4,0xa,0x4,0xe,0x8,0x8,0xb,0x10,0x4,0xa,0x4,0xe,0x8,0x8,0xb,0x10,0x4,0xa,0x4,0x4,0x8,0x8,0xb,0x10,0x4,0xa,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0xc,0xc,0xc,0xc,0x4,0x4,0x4,0x4,0xc,0xc,0xc,0xc,0x4,0x4,0x4,0x4,0xc,0xc,0xc,0xc,0x4,0x4,0x4,0x4,0xc,0xc,0xc,0xc,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0x4 };
uint8_t Opcode_Timing_DDFD[256] = {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0xb,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0xb,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0xa,0x10,0x6,0x4,0x4,0x7,0x0,0x0,0xb,0x10,0x6,0x4,0x4,0x7,0x0,0x0,0x0,0x0,0x0,0x13,0x13,0xf,0x0,0x0,0xb,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x4,0x4,0xf,0x0,0x0,0x0,0x0,0x0,0x4,0x4,0xf,0x0,0x0,0x0,0x0,0x0,0x4,0x4,0xf,0x0,0x0,0x0,0x0,0x0,0x4,0x4,0xf,0x0,0x4,0x4,0x4,0x4,0x4,0x4,0xf,0x4,0x4,0x4,0x4,0x4,0x4,0x4,0xf,0x4,0xf,0xf,0xf,0xf,0xf,0xf,0x0,0xf,0x0,0x0,0x0,0x0,0x4,0x4,0xf,0x0,0x0,0x0,0x0,0x0,0x4,0x4,0xf,0x0,0x0,0x0,0x0,0x0,0x4,0x4,0xf,0x0,0x0,0x0,0x0,0x0,0x4,0x4,0xf,0x0,0x0,0x0,0x0,0x0,0x4,0x4,0xf,0x0,0x0,0x0,0x0,0x0,0x4,0x4,0xf,0x0,0x0,0x0,0x0,0x0,0x4,0x4,0xf,0x0,0x0,0x0,0x0,0x0,0x4,0x4,0xf,0x0,0x0,0x0,0x0,0x0,0x4,0x4,0xf,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0xa,0x0,0x13,0x0,0xb,0x0,0x0,0x0,0x4,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x6,0x0,0x0,0x0,0x0,0x0,0x0 };
// Pre-calculated 8-bit parity
uint8_t Parity_Array[256] = {4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4 };
// Teensy 4.1 GPIO register mapping for address and data busses
uint32_t gpio7_low_array[0x100] = {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x400,0x400,0x400,0x400,0x400,0x400,0x400,0x400,0x20000,0x20000,0x20000,0x20000,0x20000,0x20000,0x20000,0x20000,0x20400,0x20400,0x20400,0x20400,0x20400,0x20400,0x20400,0x20400,0x10000,0x10000,0x10000,0x10000,0x10000,0x10000,0x10000,0x10000,0x10400,0x10400,0x10400,0x10400,0x10400,0x10400,0x10400,0x10400,0x30000,0x30000,0x30000,0x30000,0x30000,0x30000,0x30000,0x30000,0x30400,0x30400,0x30400,0x30400,0x30400,0x30400,0x30400,0x30400,0x800,0x800,0x800,0x800,0x800,0x800,0x800,0x800,0xc00,0xc00,0xc00,0xc00,0xc00,0xc00,0xc00,0xc00,0x20800,0x20800,0x20800,0x20800,0x20800,0x20800,0x20800,0x20800,0x20c00,0x20c00,0x20c00,0x20c00,0x20c00,0x20c00,0x20c00,0x20c00,0x10800,0x10800,0x10800,0x10800,0x10800,0x10800,0x10800,0x10800,0x10c00,0x10c00,0x10c00,0x10c00,0x10c00,0x10c00,0x10c00,0x10c00,0x30800,0x30800,0x30800,0x30800,0x30800,0x30800,0x30800,0x30800,0x30c00,0x30c00,0x30c00,0x30c00,0x30c00,0x30c00,0x30c00,0x30c00,0x1,0x1,0x1,0x1,0x1,0x1,0x1,0x1,0x401,0x401,0x401,0x401,0x401,0x401,0x401,0x401,0x20001,0x20001,0x20001,0x20001,0x20001,0x20001,0x20001,0x20001,0x20401,0x20401,0x20401,0x20401,0x20401,0x20401,0x20401,0x20401,0x10001,0x10001,0x10001,0x10001,0x10001,0x10001,0x10001,0x10001,0x10401,0x10401,0x10401,0x10401,0x10401,0x10401,0x10401,0x10401,0x30001,0x30001,0x30001,0x30001,0x30001,0x30001,0x30001,0x30001,0x30401,0x30401,0x30401,0x30401,0x30401,0x30401,0x30401,0x30401,0x801,0x801,0x801,0x801,0x801,0x801,0x801,0x801,0xc01,0xc01,0xc01,0xc01,0xc01,0xc01,0xc01,0xc01,0x20801,0x20801,0x20801,0x20801,0x20801,0x20801,0x20801,0x20801,0x20c01,0x20c01,0x20c01,0x20c01,0x20c01,0x20c01,0x20c01,0x20c01,0x10801,0x10801,0x10801,0x10801,0x10801,0x10801,0x10801,0x10801,0x10c01,0x10c01,0x10c01,0x10c01,0x10c01,0x10c01,0x10c01,0x10c01,0x30801,0x30801,0x30801,0x30801,0x30801,0x30801,0x30801,0x30801,0x30c01,0x30c01,0x30c01,0x30c01,0x30c01,0x30c01,0x30c01,0x30c01 };
uint32_t gpio9_low_array[0x100] = {0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160,0x0,0x20,0x40,0x60,0x100,0x120,0x140,0x160 };
uint32_t gpio7_high_array[0x100] = {0x0,0x80000,0x40000,0xc0000,0x10000000,0x10080000,0x10040000,0x100c0000,0x20000000,0x20080000,0x20040000,0x200c0000,0x30000000,0x30080000,0x30040000,0x300c0000,0x0,0x80000,0x40000,0xc0000,0x10000000,0x10080000,0x10040000,0x100c0000,0x20000000,0x20080000,0x20040000,0x200c0000,0x30000000,0x30080000,0x30040000,0x300c0000,0x1000,0x81000,0x41000,0xc1000,0x10001000,0x10081000,0x10041000,0x100c1000,0x20001000,0x20081000,0x20041000,0x200c1000,0x30001000,0x30081000,0x30041000,0x300c1000,0x1000,0x81000,0x41000,0xc1000,0x10001000,0x10081000,0x10041000,0x100c1000,0x20001000,0x20081000,0x20041000,0x200c1000,0x30001000,0x30081000,0x30041000,0x300c1000,0x0,0x80000,0x40000,0xc0000,0x10000000,0x10080000,0x10040000,0x100c0000,0x20000000,0x20080000,0x20040000,0x200c0000,0x30000000,0x30080000,0x30040000,0x300c0000,0x0,0x80000,0x40000,0xc0000,0x10000000,0x10080000,0x10040000,0x100c0000,0x20000000,0x20080000,0x20040000,0x200c0000,0x30000000,0x30080000,0x30040000,0x300c0000,0x1000,0x81000,0x41000,0xc1000,0x10001000,0x10081000,0x10041000,0x100c1000,0x20001000,0x20081000,0x20041000,0x200c1000,0x30001000,0x30081000,0x30041000,0x300c1000,0x1000,0x81000,0x41000,0xc1000,0x10001000,0x10081000,0x10041000,0x100c1000,0x20001000,0x20081000,0x20041000,0x200c1000,0x30001000,0x30081000,0x30041000,0x300c1000,0x0,0x80000,0x40000,0xc0000,0x10000000,0x10080000,0x10040000,0x100c0000,0x20000000,0x20080000,0x20040000,0x200c0000,0x30000000,0x30080000,0x30040000,0x300c0000,0x0,0x80000,0x40000,0xc0000,0x10000000,0x10080000,0x10040000,0x100c0000,0x20000000,0x20080000,0x20040000,0x200c0000,0x30000000,0x30080000,0x30040000,0x300c0000,0x1000,0x81000,0x41000,0xc1000,0x10001000,0x10081000,0x10041000,0x100c1000,0x20001000,0x20081000,0x20041000,0x200c1000,0x30001000,0x30081000,0x30041000,0x300c1000,0x1000,0x81000,0x41000,0xc1000,0x10001000,0x10081000,0x10041000,0x100c1000,0x20001000,0x20081000,0x20041000,0x200c1000,0x30001000,0x30081000,0x30041000,0x300c1000,0x0,0x80000,0x40000,0xc0000,0x10000000,0x10080000,0x10040000,0x100c0000,0x20000000,0x20080000,0x20040000,0x200c0000,0x30000000,0x30080000,0x30040000,0x300c0000,0x0,0x80000,0x40000,0xc0000,0x10000000,0x10080000,0x10040000,0x100c0000,0x20000000,0x20080000,0x20040000,0x200c0000,0x30000000,0x30080000,0x30040000,0x300c0000,0x1000,0x81000,0x41000,0xc1000,0x10001000,0x10081000,0x10041000,0x100c1000,0x20001000,0x20081000,0x20041000,0x200c1000,0x30001000,0x30081000,0x30041000,0x300c1000,0x1000,0x81000,0x41000,0xc1000,0x10001000,0x10081000,0x10041000,0x100c1000,0x20001000,0x20081000,0x20041000,0x200c1000,0x30001000,0x30081000,0x30041000,0x300c1000 };
uint32_t gpio8_high_array[0x100] = {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x400000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0x800000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000,0xc00000 };
uint32_t gpio9_high_array[0x100] = {0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80,0x80 };
uint8_t read_data_array[0x10000] = { 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};
// --------------------------------------------------------------------------------------------------
// --------------------------------------------------------------------------------------------------
//
// Begin Z80 Bus Interface Unit
//
// --------------------------------------------------------------------------------------------------
// --------------------------------------------------------------------------------------------------
// Setup Teensy 4.1 IO's
//
void setup() {
pinMode(PIN_RESET, INPUT);
pinMode(PIN_CLK, INPUT);
pinMode(PIN_NMI, INPUT);
pinMode(PIN_INTR, INPUT);
pinMode(PIN_WAIT, INPUT);
pinMode(PIN_M1, OUTPUT);
pinMode(PIN_HALT, OUTPUT);
pinMode(PIN_RD, OUTPUT);
pinMode(PIN_WR, OUTPUT);
pinMode(PIN_MREQ, OUTPUT);
pinMode(PIN_IOREQ, OUTPUT);
pinMode(PIN_RFSH, OUTPUT);
pinMode(PIN_ADDR15, OUTPUT);
pinMode(PIN_ADDR14, OUTPUT);
pinMode(PIN_ADDR13, OUTPUT);
pinMode(PIN_ADDR12, OUTPUT);
pinMode(PIN_ADDR11, OUTPUT);
pinMode(PIN_ADDR10, OUTPUT);
pinMode(PIN_ADDR9, OUTPUT);
pinMode(PIN_ADDR8, OUTPUT);
pinMode(PIN_AD7_OUT, OUTPUT);
pinMode(PIN_AD6_OUT, OUTPUT);
pinMode(PIN_AD5_OUT, OUTPUT);
pinMode(PIN_AD4_OUT, OUTPUT);
pinMode(PIN_AD3_OUT, OUTPUT);
pinMode(PIN_AD2_OUT, OUTPUT);
pinMode(PIN_AD1_OUT, OUTPUT);
pinMode(PIN_AD0_OUT, OUTPUT);
pinMode(PIN_DATA_OE_n, OUTPUT);
pinMode(PIN_ADDR_LATCH_n, OUTPUT);
pinMode(PIN_AD7_IN, INPUT);
pinMode(PIN_AD6_IN, INPUT);
pinMode(PIN_AD5_IN, INPUT);
pinMode(PIN_AD4_IN, INPUT);
pinMode(PIN_AD3_IN, INPUT);
pinMode(PIN_AD2_IN, INPUT);
pinMode(PIN_AD1_IN, INPUT);
pinMode(PIN_AD0_IN, INPUT);
digitalWriteFast(PIN_M1,0x1);
digitalWriteFast(PIN_HALT,0x1);
digitalWriteFast(PIN_RD,0x1);
digitalWriteFast(PIN_WR,0x1);
digitalWriteFast(PIN_MREQ,0x1);
digitalWriteFast(PIN_IOREQ,0x1);
digitalWriteFast(PIN_RFSH,0x1);
digitalWriteFast(PIN_ADDR_LATCH_n,0x1);
Serial.begin(9600);
}
// ----------------------------------------------------------
// Address range check
// Return: 0x0 - All external memory accesses
// 0x1 - Reads and writes are cycle accurate using internal memory with writes passing through to motherboard
// 0x2 - Reads accelerated using internal memory and writes are cycle accurate and pass through to motherboard
// 0x3 - All read and write accesses use accelerated internal memory
// ----------------------------------------------------------
inline uint8_t internal_address_check(uint16_t local_address) {
if ( (local_address >= 0x0000) && (local_address <= 0x37DF) ) return mode; // TRS-80 Model III - ROM A, B, C
if ( (local_address >= 0x3C00) && (local_address <= 0x3FFF) ) return 0x0; // TRS-80 Model III - 1KB Video RAM
if ( (local_address >= 0x4000) && (local_address <= 0xFFFF) ) return mode; // TRS-80 Model III - 48KB DRAM
return 0x0;
}
// -------------------------------------------------
// Wait for the CLK rising edge
// -------------------------------------------------
inline void wait_for_CLK_rising_edge() {
while ( (GPIO6_DR&0x08000000) != 0) {} // First ensure clock is at a low level
do { GPIO6_raw_data = GPIO6_DR; } while ( (GPIO6_raw_data&0x08000000) == 0); // Then poll for the first instance where clock is not low
if (debounce_refresh==1) { digitalWriteFast(PIN_RFSH,0x1); debounce_refresh=0;}
direct_nmi = (GPIO6_raw_data&0x00010000);
direct_intr = (GPIO6_raw_data&0x04000000);
if (direct_nmi_d!=0 && direct_nmi==0) nmi_latched=1; // Latch NMI on both CLK edges
direct_nmi_d = direct_nmi;
return;}
// -------------------------------------------------
// Wait for the CLK falling edge
// -------------------------------------------------
inline void wait_for_CLK_falling_edge() {
if (clock_counter>0) clock_counter--; // Count down clock_counter here at end of each instruction
while ( (GPIO6_DR&0x08000000) == 0) {} // First ensure clock is at a high level
do { } while ( (GPIO6_DR&0x08000000) != 0); // Then poll for the first instance where clock is not high
GPIO6_raw_data = GPIO6_DR; // Store slightly-delayed version of GPIO6 in a global register
direct_wait = (GPIO6_raw_data&0x01000000);
direct_reset = (GPIO6_raw_data&0x02000000);
direct_nmi = (GPIO6_raw_data&0x00010000);
if (direct_nmi_d!=0 && direct_nmi==0) nmi_latched=1; // Latch NMI on both CLK edges
direct_nmi_d = direct_nmi;
return;
}
// -------------------------------------------------
// Initiate a Z80 Bus Cycle
// -------------------------------------------------
inline uint8_t BIU_Bus_Cycle(uint8_t biu_operation, uint16_t local_address , uint8_t local_data) {
register uint8_t read_cycle=0;
register uint8_t read_data=0;
register uint32_t read_data_raw=0;
register uint32_t writeback_data7=0;
register uint32_t writeback_data8=0;
register uint32_t writeback_data9=0;
register uint32_t gpio7_out=0;
register uint32_t gpio8_out=0;
register uint32_t gpio9_out=0;
register uint8_t local_address_high=0;
register uint8_t local_address_low=0;
register uint8_t m1_cycle=0;
uint8_t local_mode=0;
// For non-IO cycles, check address for the acceleration mode
//
if ((biu_operation!=IO_WRITE_BYTE) && (biu_operation!=IO_READ_BYTE) ) local_mode = internal_address_check(local_address); else local_mode=0;
read_cycle = (biu_operation & 0x1);
if ( (biu_operation==OPCODE_READ_M1) || ( biu_operation==INTERRUPT_ACK) ) m1_cycle=0; else m1_cycle=2;
if (local_mode>1 && ((biu_operation==OPCODE_READ_M1)||(biu_operation==MEM_READ_BYTE)) ) return internal_RAM[local_address]; // Mode 2, 3 Reads
if (local_mode>2 && local_address>=0x4000 && biu_operation==MEM_WRITE_BYTE ) {internal_RAM[local_address] = local_data; return 0xEE; } // Mode 3 Writes
noInterrupts(); // Disable Teensy interupts so the Z80 bus cycle can complete without interruption
digitalWriteFast(PIN_ADDR_LATCH_n,0x1); // Allow address to propagate through '373 latch
// Pre-calculate before the clock edge to gain speed
//
local_address_high = (local_address)>>8;
local_address_low = (0x00FF&local_address);
gpio7_out = gpio7_high_array[local_address_high] | gpio7_low_array[local_address_low];
gpio8_out = gpio8_high_array[local_address_high] ;
gpio9_out = gpio9_high_array[local_address_high] | gpio9_low_array[local_address_low];
writeback_data7 = (0xCFF0E3FC & GPIO7_DR) | m1_cycle;
writeback_data9 = (0xFFFFFE1F & GPIO9_DR);
writeback_data8 = (0xFF3FFFFF & GPIO8_DR);
// Address phase is common for all bus cycle types - Lower byte of address is multiplexed with data so needs to be externally latched
// -----------------------------------------------------------------------------------------------------------------------------------------
wait_for_CLK_rising_edge(); GPIO7_DR = writeback_data7 | gpio7_out; // T1 Rising
GPIO8_DR = writeback_data8 | gpio8_out;
GPIO9_DR = writeback_data9 | gpio9_out | 0x80000010; // disable PIN_RFSH and PIN_DATA_OE_n
// Opcode fetch - M1 type - 4 cycles
// -----------------------------------------------------------------------------
if (biu_operation == OPCODE_READ_M1) {
wait_for_CLK_falling_edge(); digitalWriteFast(PIN_MREQ,0x0); // T1 Falling
digitalWriteFast(PIN_RD,0x0);
//digitalWriteFast(PIN_ADDR_LATCH_n,0x0);
wait_for_CLK_falling_edge(); while (direct_wait==0) { wait_for_CLK_falling_edge(); } // T2 Falling
// Pre-calculate before the next clock edge to gain speed
//
local_address_high = register_i;
local_address_low = register_r;
gpio7_out = gpio7_high_array[local_address_high] | gpio7_low_array[local_address_low];
gpio8_out = gpio8_high_array[local_address_high] ;
gpio9_out = gpio9_high_array[local_address_high] | gpio9_low_array[local_address_low];
writeback_data7 = (0xCFF0E3FC & GPIO7_DR) | 0x2; // drive M1 high again
writeback_data8 = (0xFF3FFFFF & GPIO8_DR);
writeback_data9 = (0xFFFFFE1F & GPIO9_DR);
wait_for_CLK_rising_edge(); read_data_raw = GPIO6_raw_data; // T3 Rising -- Read data sampled on this edge
// Drive Refresh address
//
GPIO9_DR = writeback_data9 | gpio9_out;
GPIO8_DR = writeback_data8 | gpio8_out;
GPIO7_DR = writeback_data7 | gpio7_out;
digitalWriteFast(PIN_MREQ,0x1);
digitalWriteFast(PIN_RFSH,0x0);
digitalWriteFast(PIN_RD,0x1);
digitalWriteFast(PIN_M1,0x1);
wait_for_CLK_falling_edge(); digitalWriteFast(PIN_MREQ,0x0); // T3 Falling
read_data = read_data_array[ (read_data_raw>>16) ]; // Read the Z80 bus data, re-arranging bits through read_data_array
wait_for_CLK_falling_edge(); digitalWriteFast(PIN_MREQ,0x1); // T4 Falling
debounce_refresh=1;
interrupts();
if (local_mode>0) read_data = internal_RAM[local_address]; // Mode 1 Reads
return read_data;
}
// Memory Read/Write - 3 cycles
// -----------------------------------------------------------------------------
else if ( (biu_operation==MEM_READ_BYTE) || (biu_operation==MEM_WRITE_BYTE) ) {
wait_for_CLK_falling_edge(); digitalWriteFast(PIN_ADDR_LATCH_n,0x0); // T1 Falling
digitalWriteFast(PIN_MREQ,0x0);
digitalWriteFast(PIN_RD,!read_cycle);
digitalWriteFast(PIN_AD7_OUT, (local_data & 0x80) );
digitalWriteFast(PIN_AD6_OUT, (local_data & 0x40) );
digitalWriteFast(PIN_AD5_OUT, (local_data & 0x20) );
digitalWriteFast(PIN_AD4_OUT, (local_data & 0x10) );
digitalWriteFast(PIN_AD3_OUT, (local_data & 0x08) );
digitalWriteFast(PIN_AD2_OUT, (local_data & 0x04) );
digitalWriteFast(PIN_AD1_OUT, (local_data & 0x02) );
digitalWriteFast(PIN_AD0_OUT, (local_data & 0x01) );
digitalWriteFast(PIN_DATA_OE_n, read_cycle);
wait_for_CLK_falling_edge(); digitalWriteFast(PIN_WR,read_cycle); // T2 Falling
while (direct_wait==0) { wait_for_CLK_falling_edge(); }
wait_for_CLK_falling_edge(); digitalWriteFast(PIN_MREQ,0x1); // T3 Falling -- Read data sampled on this edge
digitalWriteFast(PIN_RD,0x1);
digitalWriteFast(PIN_WR,0x1);
read_data = read_data_array[ (GPIO6_raw_data>>16) ]; // Read the Z80 bus data, re-arranging bits through read_data_array
interrupts();
if ( (local_address>=0x4000) && read_cycle==0) internal_RAM[local_address] = local_data; // Mode 1 Writes -- Always write to internal RAM
if (local_mode>0) read_data = internal_RAM[local_address]; // Mode 1 Reads
return read_data;
}
// IO Read/Write - 3 cycles with one additional wait state
// -----------------------------------------------------------------------------
else if ( (biu_operation==IO_READ_BYTE) || (biu_operation==IO_WRITE_BYTE) ) {
wait_for_CLK_falling_edge(); digitalWriteFast(PIN_ADDR_LATCH_n,0x0); // T1 Falling
digitalWriteFast(PIN_AD7_OUT, (local_data & 0x80) );
digitalWriteFast(PIN_AD6_OUT, (local_data & 0x40) );
digitalWriteFast(PIN_AD5_OUT, (local_data & 0x20) );
digitalWriteFast(PIN_AD4_OUT, (local_data & 0x10) );
digitalWriteFast(PIN_AD3_OUT, (local_data & 0x08) );
digitalWriteFast(PIN_AD2_OUT, (local_data & 0x04) );
digitalWriteFast(PIN_AD1_OUT, (local_data & 0x02) );
digitalWriteFast(PIN_AD0_OUT, (local_data & 0x01) );
digitalWriteFast(PIN_DATA_OE_n, read_cycle);
wait_for_CLK_rising_edge(); digitalWriteFast(PIN_IOREQ,0x0); // T2 Rising
digitalWriteFast(PIN_RD,!read_cycle);
digitalWriteFast(PIN_WR,read_cycle);
wait_for_CLK_rising_edge(); // Tw Rising
wait_for_CLK_rising_edge(); // T3 Rising
wait_for_CLK_falling_edge(); while (direct_wait==0) { wait_for_CLK_falling_edge(); } // T3 Falling -- Read data sampled on this edge
digitalWriteFast(PIN_IOREQ,0x1);
digitalWriteFast(PIN_RD,0x1);
digitalWriteFast(PIN_WR,0x1);
read_data = read_data_array[ (GPIO6_raw_data>>16) ]; // Read the Z80 bus data, re-arranging bits through read_data_array
interrupts();
return read_data;
}
// Interrupt Acknowledge - 4 cycle M1 type but with two additional wait states
// -----------------------------------------------------------------------------
else if (biu_operation==INTERRUPT_ACK) {
wait_for_CLK_rising_edge(); // T2 Rising
wait_for_CLK_rising_edge(); // Tw1 Rising
wait_for_CLK_falling_edge(); digitalWriteFast(PIN_IOREQ,0x0); // Tw1 Falling
wait_for_CLK_falling_edge(); while (direct_wait==0) { wait_for_CLK_falling_edge(); } // Tw2 Falling
// Pre-calculate before the next clock edge to gain speed
//
local_address_high = register_i;
local_address_low = register_r;
gpio7_out = gpio7_high_array[local_address_high] | gpio7_low_array[local_address_low];
gpio8_out = gpio8_high_array[local_address_high] | 0x00040000 ; // Also set IOREQ_n high
gpio9_out = gpio9_high_array[local_address_high] | gpio9_low_array[local_address_low];
writeback_data7 = (0xCFF0E3FC & GPIO7_DR) | 0x2; // drive M1 high again
writeback_data9 = (0xFFFFFE1F & GPIO9_DR); // Read in current GPIOx register value and clear the bits we intend to update
writeback_data8 = (0xFF3FFFFF & GPIO8_DR); // Read in current GPIOx register value and clear the bits we intend to update
wait_for_CLK_rising_edge(); read_data_raw = GPIO6_raw_data; // T3 Rising -- Read data sampled on this edge
// Drive Refresh address
//
GPIO9_DR = writeback_data9 | gpio9_out;
GPIO8_DR = writeback_data8 | gpio8_out;
GPIO7_DR = writeback_data7 | gpio7_out;
digitalWriteFast(PIN_M1,0x1);
digitalWriteFast(PIN_RFSH,0x0);
digitalWriteFast(PIN_IOREQ,0x1);
wait_for_CLK_falling_edge(); digitalWriteFast(PIN_MREQ,0x0); // T3 Falling
read_data = read_data_array[ (read_data_raw>>16) ]; // Read the Z80 bus data, re-arranging bits through read_data_array
wait_for_CLK_falling_edge(); digitalWriteFast(PIN_MREQ,0x1); // T4 Falling
debounce_refresh=1;
interrupts();
return read_data;
}
return 0xEE;
}
// --------------------------------------------------------------------------------------------------
// --------------------------------------------------------------------------------------------------
//
// End Z80 Bus Interface Unit
//
// --------------------------------------------------------------------------------------------------
// --------------------------------------------------------------------------------------------------
uint16_t Sign_Extend(uint8_t local_data) { if ((0x0080&local_data)!=0) return (0xFF00|local_data); else return (0x00FF&local_data); }
// ------------------------------------------------------
// Z80 Reset routine
// ------------------------------------------------------
//
void reset_sequence() {
while (direct_reset==0) { wait_for_CLK_falling_edge(); } // Stay here until RESET is de-aserted
clock_counter=0; // Debounce prefix, cycle counter, and nmi
last_instruction_set_a_prefix=0;
prefix_dd = 0;
prefix_fd = 0;
prefix_cb = 0;
pause_interrupts=0;
halt_in_progress=0;
nmi_latched=0;
direct_nmi_d=0;
register_iff1 = 0; // Reset registers
register_iff2 = 0;
register_i = 0;
register_r = 0;
register_im = 0;
register_pc = 0;
register_sp = 0xFFFF;
register_a = 0x00;
register_f = 0xFF;
wait_for_CLK_rising_edge();
return;
}
// ------------------------------------------------------
// Fetch an opcode byte - M1 cycle
// ------------------------------------------------------
uint8_t Fetch_opcode() {
uint8_t local_byte;
if (assert_iack_type0==1) local_byte = BIU_Bus_Cycle(INTERRUPT_ACK , 0x0000 , 0x00 );
else local_byte = BIU_Bus_Cycle(OPCODE_READ_M1 , register_pc , 0x00 );
assert_iack_type0=0;
register_pc++;
register_r = (register_r&0x80) | (0x7F&(register_r+1));
return local_byte;
}
// ------------------------------------------------------
// Read and Write data from BIU
// ------------------------------------------------------
uint8_t Read_byte(uint16_t local_address) {
uint8_t local_byte;
local_byte = BIU_Bus_Cycle(MEM_READ_BYTE , local_address , 0x00 );
return local_byte;
}
uint16_t Read_word(uint16_t local_address) {
uint8_t local_byte1;
uint8_t local_byte2;
local_byte1 = BIU_Bus_Cycle(MEM_READ_BYTE , local_address , 0x00 );
local_byte2 = BIU_Bus_Cycle(MEM_READ_BYTE , local_address+1 , 0x00 );
return (local_byte1 | (local_byte2<<8));
}
void Write_byte(uint16_t local_address , uint8_t local_data) {
BIU_Bus_Cycle(MEM_WRITE_BYTE , local_address , local_data );
return;
}
void Write_word(uint16_t local_address , uint16_t local_data) {
BIU_Bus_Cycle(MEM_WRITE_BYTE , local_address , local_data );
BIU_Bus_Cycle(MEM_WRITE_BYTE , local_address+1 , local_data>>8 );
return;
}
void Writeback_Reg16(uint8_t local_reg , uint16_t local_data) {
switch (local_reg) {
case REG_BC: register_b=(local_data>>8); register_c=(0xFF&local_data); break;
case REG_DE: register_d=(local_data>>8); register_e=(0xFF&local_data); break;
case REG_HL: register_h=(local_data>>8); register_l=(0xFF&local_data); break;
case REG_AF: register_a=(local_data>>8); register_f=(0xFF&local_data); break;
case REG_IX: register_ixh=(local_data>>8); register_ixl=(0xFF&local_data); break;
case REG_IY: register_iyh=(local_data>>8); register_iyl=(0xFF&local_data); break;
}
return;
}
// ------------------------------------------------------
// Prefix Opcodes
// ------------------------------------------------------
void opcode_0xDD () {
prefix_dd=1;
last_instruction_set_a_prefix=1;
clock_counter = clock_counter + Opcode_Timing_DDFD[opcode_byte];
return;
}
void opcode_0xFD () {
prefix_fd=1;
last_instruction_set_a_prefix=1;
clock_counter = clock_counter + Opcode_Timing_DDFD[opcode_byte];
return;
}
void opcode_0x00 () { return; } // NOP
// ------------------------------------------------------
// Stack
// ------------------------------------------------------
void Push(uint16_t local_data) {
register_sp--;
BIU_Bus_Cycle(MEM_WRITE_BYTE , register_sp , local_data>>8 ); // High Byte
register_sp--;
BIU_Bus_Cycle(MEM_WRITE_BYTE , register_sp , local_data ); // Low Byte
return;
}
uint16_t Pop() {
uint8_t local_data_low;
uint8_t local_data_high;
local_data_low = BIU_Bus_Cycle(MEM_READ_BYTE , register_sp , 0x00 ); // Low Byte
register_sp++;
local_data_high = BIU_Bus_Cycle(MEM_READ_BYTE , register_sp , 0x00 ); // High Byte
register_sp++;
return( (local_data_high<<8) | local_data_low);
}
void opcode_0xC5() { Push(REGISTER_BC); return; } // push bc
void opcode_0xD5() { Push(REGISTER_DE); return; } // push de
void opcode_0xE5() { if (prefix_dd==1) Push(REGISTER_IX); else if (prefix_fd==1) Push(REGISTER_IY); else Push(REGISTER_HL); return; } // push hl
void opcode_0xF5() { Push(REGISTER_AF); return; } // push af
void opcode_0xF1() { uint16_t local_data = Pop(); register_a =(local_data>>8); register_f =(local_data&0xFF); return; } // pop af
void opcode_0xC1() { uint16_t local_data = Pop(); register_b =(local_data>>8); register_c =(local_data&0xFF); return; } // pop bc
void opcode_0xD1() { uint16_t local_data = Pop(); register_d =(local_data>>8); register_e =(local_data&0xFF); return; } // pop de
void opcode_0xE1() { uint16_t local_data = Pop(); if (prefix_dd==1) { register_ixh=(local_data>>8); register_ixl=(local_data&0xFF);} // pop ix
else if (prefix_fd==1) { register_iyh=(local_data>>8); register_iyl=(local_data&0xFF);} // pop iy
else { register_h =(local_data>>8); register_l =(local_data&0xFF);} return; } // pop hl
// ------------------------------------------------------
// Flags/Complements
// ------------------------------------------------------
void opcode_0x3F() { temp8 = register_f & 0x01; // Store old C Flag
register_f = register_f & 0xC4; // Clear H, C, N, 5,3
if (temp8==1) register_f = register_f | 0x10; // Set H
if (temp8==0) register_f = register_f | 0x01; // Compliiment C Flag
register_f = register_f | (register_a&0x28);
return; } // ccf
void opcode_0x2F() { register_a = 0xFF ^ register_a; // Compliment register a
register_f = register_f | 0x12; // Set N and H Flags
register_f = register_f & 0xD7; // Clear Flags 5,3
register_f = register_f | (register_a&0x28);
return; } // cpl
void opcode_0x37() { register_f = register_f | 0x01; // Set C
register_f = register_f & 0xC5; // Clear Flags H, N, 5,3
register_f = register_f | (register_a&0x28);
return; } // scf
// ------------------------------------------------------
// Interrupt enables and modes
// ------------------------------------------------------
void opcode_0xED46() { register_im=0; return; } // IM0
void opcode_0xED56() { register_im=1; return; } // IM1
void opcode_0xED5E() { register_im=2; return; } // IM2
void opcode_0xFB() { register_iff1=1; register_iff2=1; last_instruction_set_a_prefix=0; return; } // ei
void opcode_0xF3() { register_iff1=0; register_iff2=0; return; } // di
// ------------------------------------------------------
// Exchanges
// ------------------------------------------------------
void opcode_0x08() { temp8=register_a; register_a=register_a2; register_a2=temp8; temp8=register_f; register_f=register_f2; register_f2=temp8; return; } // ex af,af'
void opcode_0xEB() { temp8=register_d; register_d=register_h; register_h=temp8; temp8=register_e; register_e=register_l; register_l=temp8; return; } // ex de hl
void opcode_0xD9() { temp8=register_b; register_b=register_b2; register_b2=temp8; temp8=register_c; register_c=register_c2; register_c2=temp8; // exx bc bc'
temp8=register_d; register_d=register_d2; register_d2=temp8; temp8=register_e; register_e=register_e2; register_e2=temp8; // de de'
temp8=register_h; register_h=register_h2; register_h2=temp8; temp8=register_l; register_l=register_l2; register_l2=temp8; return; } // hl hl'
void opcode_0xE3() { if (prefix_dd==1) { temp8=Read_byte(register_sp); Write_byte(register_sp ,register_ixl); register_ixl=temp8; // ex (sp),ix
temp8=Read_byte(register_sp+1); Write_byte(register_sp+1,register_ixh); register_ixh=temp8; } else
if (prefix_fd==1) { temp8=Read_byte(register_sp); Write_byte(register_sp ,register_iyl); register_iyl=temp8; // ex (sp),iy
temp8=Read_byte(register_sp+1); Write_byte(register_sp+1,register_iyh); register_iyh=temp8; } else
{ temp8=Read_byte(register_sp); Write_byte(register_sp ,register_l); register_l=temp8; // ex (sp),hl
temp8=Read_byte(register_sp+1); Write_byte(register_sp+1,register_h); register_h=temp8; } return; }
// ------------------------------------------------------
// Jumps, Calls, Returns
// ------------------------------------------------------
void Jump_Not_Taken8() {
Fetch_opcode();
return;
}
void Jump_Not_Taken16() {
Fetch_opcode();
Fetch_opcode();
return;
}
void Jump_Taken8() {
uint16_t local_displacement;
local_displacement = Sign_Extend(Fetch_opcode());
register_pc = (register_pc) + local_displacement;
return;
}
void Jump_Taken16() {
uint16_t local_displacement;
local_displacement = Fetch_opcode();
register_pc = (Fetch_opcode()<<8) | local_displacement;
return;
}
void opcode_0x18() { clock_counter=clock_counter+5; Jump_Taken8(); return; } // jr * - Disp8
void opcode_0x20() { if (flag_z == 0) {clock_counter=clock_counter+5; Jump_Taken8();} else Jump_Not_Taken8(); return; } // jr nz,* - Disp8
void opcode_0x28() { if (flag_z == 1) {clock_counter=clock_counter+5; Jump_Taken8();} else Jump_Not_Taken8(); return; } // jr z,* - Disp8
void opcode_0x30() { if (flag_c == 0) {clock_counter=clock_counter+5; Jump_Taken8();} else Jump_Not_Taken8(); return; } // jr nc,* - Disp8
void opcode_0x38() { if (flag_c == 1) {clock_counter=clock_counter+5; Jump_Taken8();} else Jump_Not_Taken8(); return; } // jr c,* - Disp8
void opcode_0x10() { register_b--; if (register_b != 0) {clock_counter=clock_counter+5; Jump_Taken8();} else Jump_Not_Taken8(); return; } // djnz * - Disp8
void opcode_0xC2() { if (flag_z == 0) Jump_Taken16(); else Jump_Not_Taken16(); return; } // jp nz,**
void opcode_0xCA() { if (flag_z == 1) Jump_Taken16(); else Jump_Not_Taken16(); return; } // jp z,**
void opcode_0xD2() { if (flag_c == 0) Jump_Taken16(); else Jump_Not_Taken16(); return; } // jp nc,**
void opcode_0xDA() { if (flag_c == 1) Jump_Taken16(); else Jump_Not_Taken16(); return; } // jp c,**
void opcode_0xE2() { if (flag_p == 0) Jump_Taken16(); else Jump_Not_Taken16(); return; } // jp po,**
void opcode_0xEA() { if (flag_p == 1) Jump_Taken16(); else Jump_Not_Taken16(); return; } // jp pe,**
void opcode_0xF2() { if (flag_s == 0) Jump_Taken16(); else Jump_Not_Taken16(); return; } // jp p,**
void opcode_0xFA() { if (flag_s == 1) Jump_Taken16(); else Jump_Not_Taken16(); return; } // jp m,**
void opcode_0xC3() { Jump_Taken16(); return; } // jp **
void opcode_0xE9() { if (prefix_dd==1) register_pc = (REGISTER_IX); else if (prefix_fd==1) register_pc = (REGISTER_IY); else register_pc = (REGISTER_HL); return; } // jp ix or iy, or (hl)
void opcode_0xC4() { if (flag_z == 0) { clock_counter=clock_counter+7; Push(register_pc+2); Jump_Taken16(); } else Jump_Not_Taken16(); return; } // call nz,**
void opcode_0xCC() { if (flag_z == 1) { clock_counter=clock_counter+7; Push(register_pc+2); Jump_Taken16(); } else Jump_Not_Taken16(); return; } // call z,**
void opcode_0xD4() { if (flag_c == 0) { clock_counter=clock_counter+7; Push(register_pc+2); Jump_Taken16(); } else Jump_Not_Taken16(); return; } // call nc,**
void opcode_0xDC() { if (flag_c == 1) { clock_counter=clock_counter+7; Push(register_pc+2); Jump_Taken16(); } else Jump_Not_Taken16(); return; } // call c,**
void opcode_0xE4() { if (flag_p == 0) { clock_counter=clock_counter+7; Push(register_pc+2); Jump_Taken16(); } else Jump_Not_Taken16(); return; } // call po,**
void opcode_0xEC() { if (flag_p == 1) { clock_counter=clock_counter+7; Push(register_pc+2); Jump_Taken16(); } else Jump_Not_Taken16(); return; } // call pe,**
void opcode_0xF4() { if (flag_s == 0) { clock_counter=clock_counter+7; Push(register_pc+2); Jump_Taken16(); } else Jump_Not_Taken16(); return; } // call p,**
void opcode_0xFC() { if (flag_s == 1) { clock_counter=clock_counter+7; Push(register_pc+2); Jump_Taken16(); } else Jump_Not_Taken16(); return; } // call m,**
void opcode_0xCD() { clock_counter=clock_counter+7; Push(register_pc+2); Jump_Taken16(); return; } // call **
void opcode_0xC9() { clock_counter=clock_counter+6; register_pc = Pop(); return; } // ret
void opcode_0xC0() { if (flag_z == 0) {clock_counter=clock_counter+6; register_pc = Pop(); } return; } // ret nz
void opcode_0xC8() { if (flag_z == 1) {clock_counter=clock_counter+6; register_pc = Pop(); } return; } // ret z
void opcode_0xD0() { if (flag_c == 0) {clock_counter=clock_counter+6; register_pc = Pop(); } return; } // ret nc
void opcode_0xD8() { if (flag_c == 1) {clock_counter=clock_counter+6; register_pc = Pop(); } return; } // ret c
void opcode_0xE0() { if (flag_p == 0) {clock_counter=clock_counter+6; register_pc = Pop(); } return; } // ret po
void opcode_0xE8() { if (flag_p == 1) {clock_counter=clock_counter+6; register_pc = Pop(); } return; } // ret pe
void opcode_0xF0() { if (flag_s == 0) {clock_counter=clock_counter+6; register_pc = Pop(); } return; } // ret p
void opcode_0xF8() { if (flag_s == 1) {clock_counter=clock_counter+6; register_pc = Pop(); } return; } // ret m
void opcode_0xED45() { register_iff1=register_iff2; register_pc = Pop(); return; } // retn
void opcode_0xED4D() { register_pc = Pop(); return; } // reti
void opcode_0xC7() { Push(register_pc); register_pc = 0x00; return; } // rst 00h
void opcode_0xD7() { Push(register_pc); register_pc = 0x10; return; } // rst 10h
void opcode_0xE7() { Push(register_pc); register_pc = 0x20; return; } // rst 20h
void opcode_0xF7() { Push(register_pc); register_pc = 0x30; return; } // rst 30h
void opcode_0xCF() { Push(register_pc); register_pc = 0x08; return; } // rst 08h
void opcode_0xDF() { Push(register_pc); register_pc = 0x18; return; } // rst 18h
void opcode_0xEF() { Push(register_pc); register_pc = 0x28; return; } // rst 28h
void opcode_0xFF() { Push(register_pc); register_pc = 0x38; return; } // rst 38h
// ------------------------------------------------------
// Loads
// ------------------------------------------------------
void opcode_0x01 () { register_c = Fetch_opcode(); register_b = Fetch_opcode(); return; }
void opcode_0x11 () { register_e = Fetch_opcode(); register_d = Fetch_opcode(); return; }
void opcode_0x0A () { register_a = Read_byte(REGISTER_BC); return; }
void opcode_0x0E () { register_c = Fetch_opcode(); return; }
void opcode_0x1E () { register_e = Fetch_opcode(); return; }
void opcode_0x1A () { register_a = Read_byte(REGISTER_DE); return; }
void opcode_0x21 () { if (prefix_dd==1) { register_ixl = Fetch_opcode(); register_ixh = Fetch_opcode(); } else
if (prefix_fd==1) { register_iyl = Fetch_opcode(); register_iyh = Fetch_opcode(); } else
{ register_l = Fetch_opcode(); register_h = Fetch_opcode(); } return; }
void opcode_0x22 () {
uint16_t local_address;
local_address = Fetch_opcode();
local_address = (Fetch_opcode()<<8) | local_address;
if (prefix_dd==1) { Write_byte(local_address , register_ixl); Write_byte( local_address+1 , register_ixh); } else
if (prefix_fd==1) { Write_byte(local_address , register_iyl); Write_byte( local_address+1 , register_iyh); } else
{ Write_byte(local_address , register_l); Write_byte( local_address+1 , register_h); }
return; }
void opcode_0x2A () {
uint16_t local_address;
local_address = Fetch_opcode();
local_address = (Fetch_opcode()<<8) | local_address;
if (prefix_dd==1) { register_ixl = Read_byte(local_address); register_ixh = Read_byte(local_address+1); } else
if (prefix_fd==1) { register_iyl = Read_byte(local_address); register_iyh = Read_byte(local_address+1); } else
{ register_l = Read_byte(local_address); register_h = Read_byte(local_address+1); }
return; }
void opcode_0x06 () { register_b = Fetch_opcode(); return; }
void opcode_0x16 () { register_d = Fetch_opcode(); return; }
void opcode_0x26 () { if (prefix_dd==1) { register_ixh = Fetch_opcode(); } else if (prefix_fd==1) { register_iyh = Fetch_opcode(); } else register_h = Fetch_opcode(); return; }
void opcode_0x2E () { if (prefix_dd==1) { register_ixl = Fetch_opcode(); } else if (prefix_fd==1) { register_iyl = Fetch_opcode(); } else register_l = Fetch_opcode(); return; }
void opcode_0x31 () {
uint16_t local_address;
local_address = Fetch_opcode();
local_address = (Fetch_opcode()<<8) | local_address;
register_sp = local_address; return; }
void opcode_0x32 () {
uint16_t local_address;
local_address = Fetch_opcode();
local_address = (Fetch_opcode()<<8) | local_address;
Write_byte(local_address , register_a);
return; }
void opcode_0x36 () { if (prefix_dd==1) Write_byte(REGISTER_IX + Sign_Extend(Fetch_opcode()) , Fetch_opcode() ); else
if (prefix_fd==1) Write_byte(REGISTER_IY + Sign_Extend(Fetch_opcode()) , Fetch_opcode() ); else
Write_byte(REGISTER_HL , Fetch_opcode() ); return; }
void opcode_0x3A () { register_a = Read_byte((Fetch_opcode()|(Fetch_opcode()<<8))); return; }
void opcode_0x3E () { register_a = Fetch_opcode(); return; }
void opcode_0x40 () { register_b = register_b; return; }
void opcode_0x41 () { register_b = register_c; return; }
void opcode_0x42 () { register_b = register_d; return; }
void opcode_0x43 () { register_b = register_e; return; }
void opcode_0x44 () { if (prefix_dd==1) register_b = register_ixh; else if (prefix_fd==1) register_b = register_iyh; else register_b = register_h; return; }
void opcode_0x45 () { if (prefix_dd==1) register_b = register_ixl; else if (prefix_fd==1) register_b = register_iyl; else register_b = register_l; return; }
void opcode_0x46 () { if (prefix_dd==1) register_b = Read_byte(REGISTER_IX + Sign_Extend(Fetch_opcode()) ); else
if (prefix_fd==1) register_b = Read_byte(REGISTER_IY + Sign_Extend(Fetch_opcode()) ); else
register_b = Read_byte(REGISTER_HL); return; }
void opcode_0x47 () { register_b = register_a; return; }
void opcode_0x48 () { register_c = register_b; return; }
void opcode_0x49 () { register_c = register_c; return; }
void opcode_0x4A () { register_c = register_d; return; }
void opcode_0x4B () { register_c = register_e; return; }
void opcode_0x4C () { if (prefix_dd==1) register_c = register_ixh; else if (prefix_fd==1) register_c = register_iyh; else register_c = register_h; return; }
void opcode_0x4D () { if (prefix_dd==1) register_c = register_ixl; else if (prefix_fd==1) register_c = register_iyl; else register_c = register_l; return; }
void opcode_0x4E () { if (prefix_dd==1) register_c = Read_byte(REGISTER_IX + Sign_Extend(Fetch_opcode()) ); else
if (prefix_fd==1) register_c = Read_byte(REGISTER_IY + Sign_Extend(Fetch_opcode()) ); else
register_c = Read_byte(REGISTER_HL); return; }
void opcode_0x4F () { register_c = register_a; return; }
// ----------------------------------------
void opcode_0x50 () { register_d = register_b; return; }
void opcode_0x51 () { register_d = register_c; return; }
void opcode_0x52 () { register_d = register_d; return; }
void opcode_0x53 () { register_d = register_e; return; }
void opcode_0x54 () { if (prefix_dd==1) register_d = register_ixh; else if (prefix_fd==1) register_d = register_iyh; else register_d = register_h; return; }
void opcode_0x55 () { if (prefix_dd==1) register_d = register_ixl; else if (prefix_fd==1) register_d = register_iyl; else register_d = register_l; return; }
void opcode_0x56 () { if (prefix_dd==1) register_d = Read_byte(REGISTER_IX + Sign_Extend(Fetch_opcode()) ); else
if (prefix_fd==1) register_d = Read_byte(REGISTER_IY + Sign_Extend(Fetch_opcode()) ); else
register_d = Read_byte(REGISTER_HL); return; }
void opcode_0x57 () { register_d = register_a; return; }
void opcode_0x58 () { register_e = register_b; return; }
void opcode_0x59 () { register_e = register_c; return; }
void opcode_0x5A () { register_e = register_d; return; }
void opcode_0x5B () { register_e = register_e; return; }
void opcode_0x5C () { if (prefix_dd==1) register_e = register_ixh; else if (prefix_fd==1) register_e = register_iyh; else register_e = register_h; return; }
void opcode_0x5D () { if (prefix_dd==1) register_e = register_ixl; else if (prefix_fd==1) register_e = register_iyl; else register_e = register_l; return; }
void opcode_0x5E () { if (prefix_dd==1) register_e = Read_byte(REGISTER_IX + Sign_Extend(Fetch_opcode()) ); else
if (prefix_fd==1) register_e = Read_byte(REGISTER_IY + Sign_Extend(Fetch_opcode()) ); else
register_e = Read_byte(REGISTER_HL); return; }
void opcode_0x5F () { register_e = register_a; return; }
// ----------------------------------------
void opcode_0x60 () { if (prefix_dd==1) register_ixh = register_b; else if (prefix_fd==1) register_iyh = register_b; else register_h = register_b; return; }
void opcode_0x61 () { if (prefix_dd==1) register_ixh = register_c; else if (prefix_fd==1) register_iyh = register_c; else register_h = register_c; return; }
void opcode_0x62 () { if (prefix_dd==1) register_ixh = register_d; else if (prefix_fd==1) register_iyh = register_d; else register_h = register_d; return; }
void opcode_0x63 () { if (prefix_dd==1) register_ixh = register_e; else if (prefix_fd==1) register_iyh = register_e; else register_h = register_e; return; }
void opcode_0x64 () { if (prefix_dd==1) register_ixh = register_ixh; else if (prefix_fd==1) register_iyh = register_iyh; else register_h = register_h; return; }
void opcode_0x65 () { if (prefix_dd==1) register_ixh = register_ixl; else if (prefix_fd==1) register_iyh = register_iyl; else register_h = register_l; return; }
void opcode_0x66 () { if (prefix_dd==1) register_h = Read_byte(REGISTER_IX + Sign_Extend(Fetch_opcode()) ); else
if (prefix_fd==1) register_h = Read_byte(REGISTER_IY + Sign_Extend(Fetch_opcode()) ); else
register_h = Read_byte(REGISTER_HL); return; }
void opcode_0x67 () { if (prefix_dd==1) register_ixh = register_a; else if (prefix_fd==1) register_iyh = register_a; else register_h = register_a; return; }
void opcode_0x68 () { if (prefix_dd==1) register_ixl = register_b; else if (prefix_fd==1) register_iyl = register_b; else register_l = register_b; return; }