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QuarkFsp2_0Pei.fdf
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QuarkFsp2_0Pei.fdf
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## @file
# FDF file of Firmware Service Package (FSP) for Intel Quark X1000 SoC.
#
# This package provides specific modules of FSP for Intel Quark X1000 SoC.
# Copyright (c) 2013 - 2016 Intel Corporation.
#
# This program and the accompanying materials are licensed and made available
# under the terms and conditions of the BSD License which accompanies this
# distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
##
################################################################################
#
# Defines Section - statements that will be processed to create a Makefile.
#
################################################################################
[Defines]
DEFINE FLASH_BASE = 0x80040000 #The base address of the FSP
DEFINE FLASH_BLOCK_SIZE = 0x00001000 #The block size
#============================================================================#
DEFINE FLASH_SIZE = 0x00031000 #The flash size in bytes of the FSP
DEFINE FLASH_NUM_BLOCKS = 0x31 #The number of blocks
#============================================================================#
SET gQuarkFspTokenSpaceGuid.PcdFlashFvFsptSize = 0x00001000 #
SET gQuarkFspTokenSpaceGuid.PcdFlashFvFspmSize = 0x0002f000 #
SET gQuarkFspTokenSpaceGuid.PcdFlashFvFspsSize = 0x00001000 #
#============================================================================#
################################################################################
#
# FD Section
# The [FD] Section is made up of the definition statements and a
# description of what goes into the Flash Device Image. Each FD section
# defines one flash "device" image. A flash device image may be one of
# the following: Removable media bootable image (like a boot floppy
# image,) an Option ROM image (that would be "flashed" into an add-in
# card,) a System "Flash" image (that would be burned into a system's
# flash) or an Update ("Capsule") image that will be used to update and
# existing system flash.
#
################################################################################
[FD.QUARK]
BaseAddress = $(FLASH_BASE) | gIntelFsp2PkgTokenSpaceGuid.PcdFspAreaBaseAddress
Size = $(FLASH_SIZE) | gIntelFsp2PkgTokenSpaceGuid.PcdFspAreaSize
ErasePolarity = 1
BlockSize = $(FLASH_BLOCK_SIZE)
NumBlocks = $(FLASH_NUM_BLOCKS)
SET gQuarkFspTokenSpaceGuid.PcdFlashFvFspBase = $(FLASH_BASE)
SET gIntelFsp2PkgTokenSpaceGuid.PcdFspBootFirmwareVolumeBase = $(FLASH_BASE) + $(gQuarkFspTokenSpaceGuid.PcdFlashFvFspsSize)
#FSP-S
#FSP-S FV offset|FSP-S FV size
0x00000000|gQuarkFspTokenSpaceGuid.PcdFlashFvFspsSize
gQuarkFspTokenSpaceGuid.PcdFlashFvFspsBase|gQuarkFspTokenSpaceGuid.PcdFlashFvFspsSize
FV = FSP-S
#FSP-M
#FSP-M FV offset = FSP-S size|FSP-M FV size
$(gQuarkFspTokenSpaceGuid.PcdFlashFvFspsSize)|gQuarkFspTokenSpaceGuid.PcdFlashFvFspmSize
gQuarkFspTokenSpaceGuid.PcdFlashFvFspmBase|gQuarkFspTokenSpaceGuid.PcdFlashFvFspmSize
FV = FSP-M
#FSP-T
#FSP-T FV offset = FSP-S size + FSP-M size|FSP-T FV size
$(gQuarkFspTokenSpaceGuid.PcdFlashFvFspsSize) + $(gQuarkFspTokenSpaceGuid.PcdFlashFvFspmSize)|gQuarkFspTokenSpaceGuid.PcdFlashFvFsptSize
gQuarkFspTokenSpaceGuid.PcdFlashFvFsptBase|gQuarkFspTokenSpaceGuid.PcdFlashFvFsptSize
FV = FSP-T
################################################################################
#
# FV Section
#
# [FV] section is used to define what components or modules are placed within a flash
# device file. This section also defines order the components and modules are positioned
# within the image. The [FV] section consists of define statements, set statements and
# module statements.
#
################################################################################
[FV.FSP-T]
BlockSize = 0x00001000
FvAlignment = 16 #FV alignment and FV attributes setting.
ERASE_POLARITY = 1
MEMORY_MAPPED = TRUE
STICKY_WRITE = TRUE
LOCK_CAP = TRUE
LOCK_STATUS = TRUE
WRITE_DISABLED_CAP = TRUE
WRITE_ENABLED_CAP = TRUE
WRITE_STATUS = TRUE
WRITE_LOCK_CAP = TRUE
WRITE_LOCK_STATUS = TRUE
READ_DISABLED_CAP = TRUE
READ_ENABLED_CAP = TRUE
READ_STATUS = TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
FvNameGuid = 799b7f5d-dc13-40b2-b19e-da80e5e155ac
#
# FSP header
#
INF RuleOverride = FSPHEADER $(FSP_PACKAGE)/Fsp2Header/FspHeader.inf
INF RuleOverride = RELOC $(FSP_PACKAGE)/Override/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
#
# Project specific configuration data files
#
FILE RAW = $(FSP_T_UPD_FFS_GUID) {
SECTION RAW = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/$(FSP_T_UPD_TOOL_GUID).bin
}
#============================================================================#
[FV.FSP-M]
BlockSize = 0x00001000
FvAlignment = 16 #FV alignment and FV attributes setting.
ERASE_POLARITY = 1
MEMORY_MAPPED = TRUE
STICKY_WRITE = TRUE
LOCK_CAP = TRUE
LOCK_STATUS = TRUE
WRITE_DISABLED_CAP = TRUE
WRITE_ENABLED_CAP = TRUE
WRITE_STATUS = TRUE
WRITE_LOCK_CAP = TRUE
WRITE_LOCK_STATUS = TRUE
READ_DISABLED_CAP = TRUE
READ_ENABLED_CAP = TRUE
READ_STATUS = TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
FvNameGuid = 87c50b02-8ba6-4bde-b680-dca1fc066e8a
# Adding APRIORI PEI below causes
#
# python IntelFsp2Pkg/Tools/SplitFspBin.py \
# split \
# -n "FSP.fd" \
# -f $WORKSPACE/$FSP_BIN_PKG_NAME/$BD_TARGET/QUARK.fd \
# -o $WORKSPACE/$FSP_BIN_PKG_NAME/$BD_TARGET
#
# to fail with:
#
# Traceback (most recent call last):
# File "IntelFsp2Pkg/Tools/SplitFspBin.py", line 679, in <module>
# sys.exit(main())
# File "IntelFsp2Pkg/Tools/SplitFspBin.py", line 668, in main
# SplitFspBin (args.FspBinary, args.OutputDir, args.NameTemplate)
# File "IntelFsp2Pkg/Tools/SplitFspBin.py", line 540, in SplitFspBin
# fd.ParseFd ()
# File "IntelFsp2Pkg/Tools/SplitFspBin.py", line 369, in ParseFd
# fv.ParseFv ()
# File "IntelFsp2Pkg/Tools/SplitFspBin.py", line 307, in ParseFv
# ffs = FirmwareFile (offset, self.FvData[offset:offset + int(ffshdr.Size)])
# File "IntelFsp2Pkg/Tools/SplitFspBin.py", line 268, in __init__
# self.FfsHdr = EFI_FFS_FILE_HEADER.from_buffer (filedata, 0)
# ValueError: Buffer size too small (0 instead of at least 24 bytes)
#
# Tell the PEI dispatcher that FSP does not require the PCD PEIM.
# Without the APRIORI, the dispatcher automatically adds a dependency
# on the PCD PEIM!
#
#APRIORI PEI {
# INF $(FSP_PACKAGE)/MemoryInitPeim/MemoryInitPeim.inf
#}
#
# FSP header - First file header in the firmware volume
#
INF RuleOverride = FSPHEADER $(FSP_PACKAGE)/Fsp2Header/FspHeader.inf
#
# Manually add the PEI APRIORI file - Contains file GUIDs, 16 bytes each
# MemoryInitPeim/MemoryInitPeim.inf
#
FILE FREEFORM = 1B45CC0A-156A-428A-AF62-49864DA0E6E6 {
SECTION RAW = $(FSP_PACKAGE)/MemoryInitPeim/MemoryInitPeimGuid.bin
}
#
# It is important to keep the proper order for these PEIMs
# for this implementation
#
INF RuleOverride = RELOC $(FSP_PACKAGE)/Override/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
INF MdeModulePkg/Core/Pei/PeiMain.inf
#
# Project specific PEIMs
#
INF $(FSP_PACKAGE)/MemoryInitPeim/MemoryInitPeim.inf
#
# Description file
#
FILE RAW = D9093578-08EB-44DF-B9D8-D0C1D3D55D96 {
SECTION RAW = $(FSP_PACKAGE)/FspDescription/FspDescription.txt
}
#
# Project specific configuration data files
#
FILE RAW = $(FSP_M_UPD_FFS_GUID) {
SECTION RAW = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/$(FSP_M_UPD_TOOL_GUID).bin
}
#============================================================================#
[FV.FSP-S]
BlockSize = 0x00001000
FvAlignment = 16 #FV alignment and FV attributes setting.
ERASE_POLARITY = 1
MEMORY_MAPPED = TRUE
STICKY_WRITE = TRUE
LOCK_CAP = TRUE
LOCK_STATUS = TRUE
WRITE_DISABLED_CAP = TRUE
WRITE_ENABLED_CAP = TRUE
WRITE_STATUS = TRUE
WRITE_LOCK_CAP = TRUE
WRITE_LOCK_STATUS = TRUE
READ_DISABLED_CAP = TRUE
READ_ENABLED_CAP = TRUE
READ_STATUS = TRUE
READ_LOCK_CAP = TRUE
READ_LOCK_STATUS = TRUE
FvNameGuid = 526facba-2f7c-4548-888f-f9e11aa44e73
#
# FSP header
#
INF RuleOverride = FSPHEADER $(FSP_PACKAGE)/Fsp2Header/FspHeader.inf
#
# It is important to keep the proper order for these PEIMs
# for this implementation
#
INF RuleOverride = RELOC $(FSP_PACKAGE)/Override/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf
#
# Project specific configuration data files
#
FILE RAW = $(FSP_S_UPD_FFS_GUID) {
SECTION RAW = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/$(FSP_S_UPD_TOOL_GUID).bin
}
################################################################################
#
# Rules are use with the [FV] section's module INF type to define how an FFS
# file is created for a given INF file. The following Rule are the default
# rules for the different module type. User can add the customized rules to
# define the content of the FFS file.
#
################################################################################
[Rule.Common.SEC]
FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
TE TE Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi
}
[Rule.Common.SEC.RELOC]
FILE SEC = $(NAMED_GUID) {
TE TE Align = 8 $(INF_OUTPUT)/$(MODULE_NAME).efi
}
[Rule.Common.PEI_CORE]
FILE PEI_CORE = $(NAMED_GUID) {
TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
[Rule.Common.PEIM.NORELOC]
FILE PEIM = $(NAMED_GUID) RELOCS_STRIPPED {
PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
[Rule.Common.PEIM]
FILE PEIM = $(NAMED_GUID) {
PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
[Rule.Common.PEIM.PE32]
FILE PEIM = $(NAMED_GUID) {
PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
COMPRESS {
PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
}
[Rule.Common.USER_DEFINED.FSPHEADER]
FILE RAW = $(NAMED_GUID) {
RAW BIN |.acpi
}