diff --git a/lib/SPIRV/SPIRVWriter.cpp b/lib/SPIRV/SPIRVWriter.cpp
index eb23f46b4a..0abaf6275d 100644
--- a/lib/SPIRV/SPIRVWriter.cpp
+++ b/lib/SPIRV/SPIRVWriter.cpp
@@ -1348,6 +1348,30 @@ bool LLVMToSPIRV::transDecoration(Value *V, SPIRVValue *BV) {
     }
   }
 
+  if (auto BVF = dyn_cast_or_null<FPMathOperator>(V)) {
+    auto Opcode = BVF->getOpcode();
+    if (Opcode == Instruction::FAdd || Opcode == Instruction::FSub ||
+        Opcode == Instruction::FMul || Opcode == Instruction::FDiv ||
+        Opcode == Instruction::FRem) {
+      FastMathFlags FMF = BVF->getFastMathFlags();
+      SPIRVWord M{0};
+      if (FMF.isFast())
+        M |= FPFastMathModeFastMask;
+      else {
+        if (FMF.noNaNs())
+          M |= FPFastMathModeNotNaNMask;
+        if (FMF.noInfs())
+          M |= FPFastMathModeNotInfMask;
+        if (FMF.noSignedZeros())
+          M |= FPFastMathModeNSZMask;
+        if (FMF.allowReciprocal())
+          M |= FPFastMathModeAllowRecipMask;
+      }
+      if (M != 0)
+        BV->setFPFastMathMode(M);
+    }
+  }
+
   return true;
 }
 
diff --git a/lib/SPIRV/libSPIRV/SPIRVValue.cpp b/lib/SPIRV/libSPIRV/SPIRVValue.cpp
index 2b52c309a0..7a8c68799f 100644
--- a/lib/SPIRV/libSPIRV/SPIRVValue.cpp
+++ b/lib/SPIRV/libSPIRV/SPIRVValue.cpp
@@ -111,4 +111,14 @@ void SPIRVValue::setNoUnsignedWrap(bool HasNoUnsignedWrap) {
   }
 }
 
+void SPIRVValue::setFPFastMathMode(SPIRVWord M) {
+  if (M == 0) {
+    eraseDecorate(DecorationFPFastMathMode);
+    return;
+  }
+  addDecorate(new SPIRVDecorate(DecorationFPFastMathMode, this, M));
+  SPIRVDBG(spvdbgs() << "Set fast math mode to " << M << " for obj " << Id
+                     << "\n")
+}
+
 } // namespace SPIRV
diff --git a/lib/SPIRV/libSPIRV/SPIRVValue.h b/lib/SPIRV/libSPIRV/SPIRVValue.h
index 557a124abf..0843f4dc0f 100644
--- a/lib/SPIRV/libSPIRV/SPIRVValue.h
+++ b/lib/SPIRV/libSPIRV/SPIRVValue.h
@@ -98,6 +98,7 @@ class SPIRVValue : public SPIRVEntry {
   void setVolatile(bool IsVolatile);
   void setNoSignedWrap(bool HasNoSignedWrap);
   void setNoUnsignedWrap(bool HasNoUnsignedWrap);
+  void setFPFastMathMode(SPIRVWord FPFastMathMode);
 
   void validate() const override {
     SPIRVEntry::validate();
diff --git a/test/FPFastMathModeNotNaNFast.spvasm b/test/FPFastMathModeNotNaNFast.spvasm
new file mode 100644
index 0000000000..a7956d51f2
--- /dev/null
+++ b/test/FPFastMathModeNotNaNFast.spvasm
@@ -0,0 +1,38 @@
+; REQUIRES: spirv-as
+; RUN: spirv-as --target-env spv1.0 -o %t.spv %s
+; RUN: spirv-val %t.spv
+; RUN: llvm-spirv -r -o - %t.spv | llvm-dis | FileCheck %s
+               OpCapability Addresses
+               OpCapability Kernel
+               OpMemoryModel Physical32 OpenCL
+               OpEntryPoint Kernel %1 "testFPFastMathModeNotNaNFast"
+               OpName %a "a"
+               OpName %b "b"
+               OpName %r1 "r1"
+               OpName %r2 "r2"
+               OpName %r3 "r3"
+               OpName %r4 "r4"
+               OpName %r5 "r5"
+               OpDecorate %dec FPFastMathMode NotNaN|Fast
+        %dec = OpDecorationGroup
+               OpGroupDecorate %dec %r1 %r2 %r3 %r4 %r5
+       %void = OpTypeVoid
+      %float = OpTypeFloat 32
+          %5 = OpTypeFunction %void %float %float
+          %1 = OpFunction %void None %5
+          %a = OpFunctionParameter %float
+          %b = OpFunctionParameter %float
+          %6 = OpLabel
+         %r1 = OpFAdd %float %a %b
+         %r2 = OpFSub %float %a %b
+         %r3 = OpFMul %float %a %b
+         %r4 = OpFDiv %float %a %b
+         %r5 = OpFRem %float %a %b
+               OpReturn
+               OpFunctionEnd
+
+; CHECK: %r1 = fadd fast float %a, %b
+; CHECK: %r2 = fsub fast float %a, %b
+; CHECK: %r3 = fmul fast float %a, %b
+; CHECK: %r4 = fdiv fast float %a, %b
+; CHECK: %r5 = frem fast float %a, %b
diff --git a/test/OpFAdd.spvasm b/test/OpFAdd.spvasm
deleted file mode 100644
index e4629057e1..0000000000
--- a/test/OpFAdd.spvasm
+++ /dev/null
@@ -1,55 +0,0 @@
-; REQUIRES: spirv-as
-; RUN: spirv-as --target-env spv1.0 -o %t.spv %s
-; RUN: spirv-val %t.spv
-; RUN: llvm-spirv -r -o - %t.spv | llvm-dis | FileCheck %s
-               OpCapability Addresses
-               OpCapability Kernel
-               OpMemoryModel Physical32 OpenCL
-               OpEntryPoint Kernel %1 "testFAdd"
-               OpName %a "a"
-               OpName %b "b"
-               OpName %r1 "r1"
-               OpName %r2 "r2"
-               OpName %r3 "r3"
-               OpName %r4 "r4"
-               OpName %r5 "r5"
-               OpName %r6 "r6"
-               OpName %r7 "r7"
-               OpName %r8 "r8"
-               OpName %r9 "r9"
-               OpDecorate %r2 FPFastMathMode None
-               OpDecorate %r3 FPFastMathMode NotNaN
-               OpDecorate %r4 FPFastMathMode NotInf
-               OpDecorate %r5 FPFastMathMode NSZ
-               OpDecorate %r6 FPFastMathMode AllowRecip
-               OpDecorate %r7 FPFastMathMode Fast
-               OpDecorate %r8 FPFastMathMode NotNaN|NotInf
-               OpDecorate %r9 FPFastMathMode NotNaN|Fast
-       %void = OpTypeVoid
-      %float = OpTypeFloat 32
-          %5 = OpTypeFunction %void %float %float
-          %1 = OpFunction %void None %5
-          %a = OpFunctionParameter %float
-          %b = OpFunctionParameter %float
-          %6 = OpLabel
-         %r1 = OpFAdd %float %a %b
-         %r2 = OpFAdd %float %a %b
-         %r3 = OpFAdd %float %a %b
-         %r4 = OpFAdd %float %a %b
-         %r5 = OpFAdd %float %a %b
-         %r6 = OpFAdd %float %a %b
-         %r7 = OpFAdd %float %a %b
-         %r8 = OpFAdd %float %a %b
-         %r9 = OpFAdd %float %a %b
-               OpReturn
-               OpFunctionEnd
-
-; CHECK: %r1 = fadd float %a, %b
-; CHECK: %r2 = fadd float %a, %b
-; CHECK: %r3 = fadd nnan float %a, %b
-; CHECK: %r4 = fadd ninf float %a, %b
-; CHECK: %r5 = fadd nsz float %a, %b
-; CHECK: %r6 = fadd arcp float %a, %b
-; CHECK: %r7 = fadd fast float %a, %b
-; CHECK: %r8 = fadd nnan ninf float %a, %b
-; CHECK: %r9 = fadd fast float %a, %b
diff --git a/test/OpFDiv.spvasm b/test/OpFDiv.spvasm
deleted file mode 100644
index 1386f3012f..0000000000
--- a/test/OpFDiv.spvasm
+++ /dev/null
@@ -1,55 +0,0 @@
-; REQUIRES: spirv-as
-; RUN: spirv-as --target-env spv1.0 -o %t.spv %s
-; RUN: spirv-val %t.spv
-; RUN: llvm-spirv -r -o - %t.spv | llvm-dis | FileCheck %s
-               OpCapability Addresses
-               OpCapability Kernel
-               OpMemoryModel Physical32 OpenCL
-               OpEntryPoint Kernel %1 "testFDiv"
-               OpName %a "a"
-               OpName %b "b"
-               OpName %r1 "r1"
-               OpName %r2 "r2"
-               OpName %r3 "r3"
-               OpName %r4 "r4"
-               OpName %r5 "r5"
-               OpName %r6 "r6"
-               OpName %r7 "r7"
-               OpName %r8 "r8"
-               OpName %r9 "r9"
-               OpDecorate %r2 FPFastMathMode None
-               OpDecorate %r3 FPFastMathMode NotNaN
-               OpDecorate %r4 FPFastMathMode NotInf
-               OpDecorate %r5 FPFastMathMode NSZ
-               OpDecorate %r6 FPFastMathMode AllowRecip
-               OpDecorate %r7 FPFastMathMode Fast
-               OpDecorate %r8 FPFastMathMode NotNaN|NotInf
-               OpDecorate %r9 FPFastMathMode NotNaN|Fast
-       %void = OpTypeVoid
-      %float = OpTypeFloat 32
-          %5 = OpTypeFunction %void %float %float
-          %1 = OpFunction %void None %5
-          %a = OpFunctionParameter %float
-          %b = OpFunctionParameter %float
-          %6 = OpLabel
-         %r1 = OpFDiv %float %a %b
-         %r2 = OpFDiv %float %a %b
-         %r3 = OpFDiv %float %a %b
-         %r4 = OpFDiv %float %a %b
-         %r5 = OpFDiv %float %a %b
-         %r6 = OpFDiv %float %a %b
-         %r7 = OpFDiv %float %a %b
-         %r8 = OpFDiv %float %a %b
-         %r9 = OpFDiv %float %a %b
-               OpReturn
-               OpFunctionEnd
-
-; CHECK: %r1 = fdiv float %a, %b
-; CHECK: %r2 = fdiv float %a, %b
-; CHECK: %r3 = fdiv nnan float %a, %b
-; CHECK: %r4 = fdiv ninf float %a, %b
-; CHECK: %r5 = fdiv nsz float %a, %b
-; CHECK: %r6 = fdiv arcp float %a, %b
-; CHECK: %r7 = fdiv fast float %a, %b
-; CHECK: %r8 = fdiv nnan ninf float %a, %b
-; CHECK: %r9 = fdiv fast float %a, %b
diff --git a/test/OpFMul.spvasm b/test/OpFMul.spvasm
deleted file mode 100644
index 036315e283..0000000000
--- a/test/OpFMul.spvasm
+++ /dev/null
@@ -1,55 +0,0 @@
-; REQUIRES: spirv-as
-; RUN: spirv-as --target-env spv1.0 -o %t.spv %s
-; RUN: spirv-val %t.spv
-; RUN: llvm-spirv -r -o - %t.spv | llvm-dis | FileCheck %s
-               OpCapability Addresses
-               OpCapability Kernel
-               OpMemoryModel Physical32 OpenCL
-               OpEntryPoint Kernel %1 "testFMul"
-               OpName %a "a"
-               OpName %b "b"
-               OpName %r1 "r1"
-               OpName %r2 "r2"
-               OpName %r3 "r3"
-               OpName %r4 "r4"
-               OpName %r5 "r5"
-               OpName %r6 "r6"
-               OpName %r7 "r7"
-               OpName %r8 "r8"
-               OpName %r9 "r9"
-               OpDecorate %r2 FPFastMathMode None
-               OpDecorate %r3 FPFastMathMode NotNaN
-               OpDecorate %r4 FPFastMathMode NotInf
-               OpDecorate %r5 FPFastMathMode NSZ
-               OpDecorate %r6 FPFastMathMode AllowRecip
-               OpDecorate %r7 FPFastMathMode Fast
-               OpDecorate %r8 FPFastMathMode NotNaN|NotInf
-               OpDecorate %r9 FPFastMathMode NotNaN|Fast
-       %void = OpTypeVoid
-      %float = OpTypeFloat 32
-          %5 = OpTypeFunction %void %float %float
-          %1 = OpFunction %void None %5
-          %a = OpFunctionParameter %float
-          %b = OpFunctionParameter %float
-          %6 = OpLabel
-         %r1 = OpFMul %float %a %b
-         %r2 = OpFMul %float %a %b
-         %r3 = OpFMul %float %a %b
-         %r4 = OpFMul %float %a %b
-         %r5 = OpFMul %float %a %b
-         %r6 = OpFMul %float %a %b
-         %r7 = OpFMul %float %a %b
-         %r8 = OpFMul %float %a %b
-         %r9 = OpFMul %float %a %b
-               OpReturn
-               OpFunctionEnd
-
-; CHECK: %r1 = fmul float %a, %b
-; CHECK: %r2 = fmul float %a, %b
-; CHECK: %r3 = fmul nnan float %a, %b
-; CHECK: %r4 = fmul ninf float %a, %b
-; CHECK: %r5 = fmul nsz float %a, %b
-; CHECK: %r6 = fmul arcp float %a, %b
-; CHECK: %r7 = fmul fast float %a, %b
-; CHECK: %r8 = fmul nnan ninf float %a, %b
-; CHECK: %r9 = fmul fast float %a, %b
diff --git a/test/OpFRem.spvasm b/test/OpFRem.spvasm
deleted file mode 100644
index 47b060c902..0000000000
--- a/test/OpFRem.spvasm
+++ /dev/null
@@ -1,55 +0,0 @@
-; REQUIRES: spirv-as
-; RUN: spirv-as --target-env spv1.0 -o %t.spv %s
-; RUN: spirv-val %t.spv
-; RUN: llvm-spirv -r -o - %t.spv | llvm-dis | FileCheck %s
-               OpCapability Addresses
-               OpCapability Kernel
-               OpMemoryModel Physical32 OpenCL
-               OpEntryPoint Kernel %1 "testFRem"
-               OpName %a "a"
-               OpName %b "b"
-               OpName %r1 "r1"
-               OpName %r2 "r2"
-               OpName %r3 "r3"
-               OpName %r4 "r4"
-               OpName %r5 "r5"
-               OpName %r6 "r6"
-               OpName %r7 "r7"
-               OpName %r8 "r8"
-               OpName %r9 "r9"
-               OpDecorate %r2 FPFastMathMode None
-               OpDecorate %r3 FPFastMathMode NotNaN
-               OpDecorate %r4 FPFastMathMode NotInf
-               OpDecorate %r5 FPFastMathMode NSZ
-               OpDecorate %r6 FPFastMathMode AllowRecip
-               OpDecorate %r7 FPFastMathMode Fast
-               OpDecorate %r8 FPFastMathMode NotNaN|NotInf
-               OpDecorate %r9 FPFastMathMode NotNaN|Fast
-       %void = OpTypeVoid
-      %float = OpTypeFloat 32
-          %5 = OpTypeFunction %void %float %float
-          %1 = OpFunction %void None %5
-          %a = OpFunctionParameter %float
-          %b = OpFunctionParameter %float
-          %6 = OpLabel
-         %r1 = OpFRem %float %a %b
-         %r2 = OpFRem %float %a %b
-         %r3 = OpFRem %float %a %b
-         %r4 = OpFRem %float %a %b
-         %r5 = OpFRem %float %a %b
-         %r6 = OpFRem %float %a %b
-         %r7 = OpFRem %float %a %b
-         %r8 = OpFRem %float %a %b
-         %r9 = OpFRem %float %a %b
-               OpReturn
-               OpFunctionEnd
-
-; CHECK: %r1 = frem float %a, %b
-; CHECK: %r2 = frem float %a, %b
-; CHECK: %r3 = frem nnan float %a, %b
-; CHECK: %r4 = frem ninf float %a, %b
-; CHECK: %r5 = frem nsz float %a, %b
-; CHECK: %r6 = frem arcp float %a, %b
-; CHECK: %r7 = frem fast float %a, %b
-; CHECK: %r8 = frem nnan ninf float %a, %b
-; CHECK: %r9 = frem fast float %a, %b
diff --git a/test/OpFSub.spvasm b/test/OpFSub.spvasm
deleted file mode 100644
index c978a69eb5..0000000000
--- a/test/OpFSub.spvasm
+++ /dev/null
@@ -1,55 +0,0 @@
-; REQUIRES: spirv-as
-; RUN: spirv-as --target-env spv1.0 -o %t.spv %s
-; RUN: spirv-val %t.spv
-; RUN: llvm-spirv -r -o - %t.spv | llvm-dis | FileCheck %s
-               OpCapability Addresses
-               OpCapability Kernel
-               OpMemoryModel Physical32 OpenCL
-               OpEntryPoint Kernel %1 "testFSub"
-               OpName %a "a"
-               OpName %b "b"
-               OpName %r1 "r1"
-               OpName %r2 "r2"
-               OpName %r3 "r3"
-               OpName %r4 "r4"
-               OpName %r5 "r5"
-               OpName %r6 "r6"
-               OpName %r7 "r7"
-               OpName %r8 "r8"
-               OpName %r9 "r9"
-               OpDecorate %r2 FPFastMathMode None
-               OpDecorate %r3 FPFastMathMode NotNaN
-               OpDecorate %r4 FPFastMathMode NotInf
-               OpDecorate %r5 FPFastMathMode NSZ
-               OpDecorate %r6 FPFastMathMode AllowRecip
-               OpDecorate %r7 FPFastMathMode Fast
-               OpDecorate %r8 FPFastMathMode NotNaN|NotInf
-               OpDecorate %r9 FPFastMathMode NotNaN|Fast
-       %void = OpTypeVoid
-      %float = OpTypeFloat 32
-          %5 = OpTypeFunction %void %float %float
-          %1 = OpFunction %void None %5
-          %a = OpFunctionParameter %float
-          %b = OpFunctionParameter %float
-          %6 = OpLabel
-         %r1 = OpFSub %float %a %b
-         %r2 = OpFSub %float %a %b
-         %r3 = OpFSub %float %a %b
-         %r4 = OpFSub %float %a %b
-         %r5 = OpFSub %float %a %b
-         %r6 = OpFSub %float %a %b
-         %r7 = OpFSub %float %a %b
-         %r8 = OpFSub %float %a %b
-         %r9 = OpFSub %float %a %b
-               OpReturn
-               OpFunctionEnd
-
-; CHECK: %r1 = fsub float %a, %b
-; CHECK: %r2 = fsub float %a, %b
-; CHECK: %r3 = fsub nnan float %a, %b
-; CHECK: %r4 = fsub ninf float %a, %b
-; CHECK: %r5 = fsub nsz float %a, %b
-; CHECK: %r6 = fsub arcp float %a, %b
-; CHECK: %r7 = fsub fast float %a, %b
-; CHECK: %r8 = fsub nnan ninf float %a, %b
-; CHECK: %r9 = fsub fast float %a, %b
diff --git a/test/transcoding/fadd.ll b/test/transcoding/fadd.ll
new file mode 100644
index 0000000000..f1bb0a7f8b
--- /dev/null
+++ b/test/transcoding/fadd.ll
@@ -0,0 +1,65 @@
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv -spirv-text %t.bc -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llvm-spirv %t.bc -o %t.spv
+; RUN: spirv-val %t.spv
+; RUN: llvm-spirv -r %t.spv -o - | llvm-dis -o - | FileCheck %s --check-prefix=CHECK-LLVM
+
+; CHECK-SPIRV: 3 Name [[#r1:]] "r1"
+; CHECK-SPIRV: 3 Name [[#r2:]] "r2"
+; CHECK-SPIRV: 3 Name [[#r3:]] "r3"
+; CHECK-SPIRV: 3 Name [[#r4:]] "r4"
+; CHECK-SPIRV: 3 Name [[#r5:]] "r5"
+; CHECK-SPIRV: 3 Name [[#r6:]] "r6"
+; CHECK-SPIRV: 3 Name [[#r7:]] "r7"
+; CHECK-SPIRV-NOT: 4 Decorate [[#r1]] FPFastMathMode
+; CHECK-SPIRV-DAG: 4 Decorate [[#r2]] FPFastMathMode 1
+; CHECK-SPIRV-DAG: 4 Decorate [[#r3]] FPFastMathMode 2
+; CHECK-SPIRV-DAG: 4 Decorate [[#r4]] FPFastMathMode 4
+; CHECK-SPIRV-DAG: 4 Decorate [[#r5]] FPFastMathMode 8
+; CHECK-SPIRV-DAG: 4 Decorate [[#r6]] FPFastMathMode 16
+; CHECK-SPIRV-DAG: 4 Decorate [[#r7]] FPFastMathMode 3
+; CHECK-SPIRV: 3 TypeFloat [[float:[0-9]+]] 32
+; CHECK-SPIRV: 5 FAdd [[float]] [[#r1]]
+; CHECK-SPIRV: 5 FAdd [[float]] [[#r2]]
+; CHECK-SPIRV: 5 FAdd [[float]] [[#r3]]
+; CHECK-SPIRV: 5 FAdd [[float]] [[#r4]]
+; CHECK-SPIRV: 5 FAdd [[float]] [[#r5]]
+; CHECK-SPIRV: 5 FAdd [[float]] [[#r6]]
+; CHECK-SPIRV: 5 FAdd [[float]] [[#r7]]
+
+; CHECK-LLVM: %r1 = fadd float %a, %b
+; CHECK-LLVM: %r2 = fadd nnan float %a, %b
+; CHECK-LLVM: %r3 = fadd ninf float %a, %b
+; CHECK-LLVM: %r4 = fadd nsz float %a, %b
+; CHECK-LLVM: %r5 = fadd arcp float %a, %b
+; CHECK-LLVM: %r6 = fadd fast float %a, %b
+; CHECK-LLVM: %r7 = fadd nnan ninf float %a, %b
+
+target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir-unknown-unknown"
+
+; Function Attrs: nounwind
+define spir_kernel void @testFAdd(float %a, float %b) local_unnamed_addr #0 !kernel_arg_addr_space !2 !kernel_arg_access_qual !3 !kernel_arg_type !4 !kernel_arg_base_type !4 !kernel_arg_type_qual !5 {
+entry:
+  %r1 = fadd float %a, %b
+  %r2 = fadd nnan float %a, %b
+  %r3 = fadd ninf float %a, %b
+  %r4 = fadd nsz float %a, %b
+  %r5 = fadd arcp float %a, %b
+  %r6 = fadd fast float %a, %b
+  %r7 = fadd nnan ninf float %a, %b
+  ret void
+}
+
+attributes #0 = { convergent nounwind writeonly "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!opencl.ocl.version = !{!1}
+!opencl.spir.version = !{!1}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 2, i32 0}
+!2 = !{i32 0, i32 0}
+!3 = !{!"none", !"none"}
+!4 = !{!"float", !"float"}
+!5 = !{!"", !""}
diff --git a/test/transcoding/fdiv.ll b/test/transcoding/fdiv.ll
new file mode 100644
index 0000000000..1830efe16c
--- /dev/null
+++ b/test/transcoding/fdiv.ll
@@ -0,0 +1,65 @@
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv -spirv-text %t.bc -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llvm-spirv %t.bc -o %t.spv
+; RUN: spirv-val %t.spv
+; RUN: llvm-spirv -r %t.spv -o - | llvm-dis -o - | FileCheck %s --check-prefix=CHECK-LLVM
+
+; CHECK-SPIRV: 3 Name [[#r1:]] "r1"
+; CHECK-SPIRV: 3 Name [[#r2:]] "r2"
+; CHECK-SPIRV: 3 Name [[#r3:]] "r3"
+; CHECK-SPIRV: 3 Name [[#r4:]] "r4"
+; CHECK-SPIRV: 3 Name [[#r5:]] "r5"
+; CHECK-SPIRV: 3 Name [[#r6:]] "r6"
+; CHECK-SPIRV: 3 Name [[#r7:]] "r7"
+; CHECK-SPIRV-NOT: 4 Decorate [[#r1]] FPFastMathMode
+; CHECK-SPIRV-DAG: 4 Decorate [[#r2]] FPFastMathMode 1
+; CHECK-SPIRV-DAG: 4 Decorate [[#r3]] FPFastMathMode 2
+; CHECK-SPIRV-DAG: 4 Decorate [[#r4]] FPFastMathMode 4
+; CHECK-SPIRV-DAG: 4 Decorate [[#r5]] FPFastMathMode 8
+; CHECK-SPIRV-DAG: 4 Decorate [[#r6]] FPFastMathMode 16
+; CHECK-SPIRV-DAG: 4 Decorate [[#r7]] FPFastMathMode 3
+; CHECK-SPIRV: 3 TypeFloat [[float:[0-9]+]] 32
+; CHECK-SPIRV: 5 FDiv [[float]] [[#r1]]
+; CHECK-SPIRV: 5 FDiv [[float]] [[#r2]]
+; CHECK-SPIRV: 5 FDiv [[float]] [[#r3]]
+; CHECK-SPIRV: 5 FDiv [[float]] [[#r4]]
+; CHECK-SPIRV: 5 FDiv [[float]] [[#r5]]
+; CHECK-SPIRV: 5 FDiv [[float]] [[#r6]]
+; CHECK-SPIRV: 5 FDiv [[float]] [[#r7]]
+
+; CHECK-LLVM: %r1 = fdiv float %a, %b
+; CHECK-LLVM: %r2 = fdiv nnan float %a, %b
+; CHECK-LLVM: %r3 = fdiv ninf float %a, %b
+; CHECK-LLVM: %r4 = fdiv nsz float %a, %b
+; CHECK-LLVM: %r5 = fdiv arcp float %a, %b
+; CHECK-LLVM: %r6 = fdiv fast float %a, %b
+; CHECK-LLVM: %r7 = fdiv nnan ninf float %a, %b
+
+target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir-unknown-unknown"
+
+; Function Attrs: nounwind
+define spir_kernel void @testFDiv(float %a, float %b) local_unnamed_addr #0 !kernel_arg_addr_space !2 !kernel_arg_access_qual !3 !kernel_arg_type !4 !kernel_arg_base_type !4 !kernel_arg_type_qual !5 {
+entry:
+  %r1 = fdiv float %a, %b
+  %r2 = fdiv nnan float %a, %b
+  %r3 = fdiv ninf float %a, %b
+  %r4 = fdiv nsz float %a, %b
+  %r5 = fdiv arcp float %a, %b
+  %r6 = fdiv fast float %a, %b
+  %r7 = fdiv nnan ninf float %a, %b
+  ret void
+}
+
+attributes #0 = { convergent nounwind writeonly "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!opencl.ocl.version = !{!1}
+!opencl.spir.version = !{!1}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 2, i32 0}
+!2 = !{i32 0, i32 0}
+!3 = !{!"none", !"none"}
+!4 = !{!"float", !"float"}
+!5 = !{!"", !""}
diff --git a/test/transcoding/fmul.ll b/test/transcoding/fmul.ll
new file mode 100644
index 0000000000..04203a3aac
--- /dev/null
+++ b/test/transcoding/fmul.ll
@@ -0,0 +1,65 @@
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv -spirv-text %t.bc -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llvm-spirv %t.bc -o %t.spv
+; RUN: spirv-val %t.spv
+; RUN: llvm-spirv -r %t.spv -o - | llvm-dis -o - | FileCheck %s --check-prefix=CHECK-LLVM
+
+; CHECK-SPIRV: 3 Name [[#r1:]] "r1"
+; CHECK-SPIRV: 3 Name [[#r2:]] "r2"
+; CHECK-SPIRV: 3 Name [[#r3:]] "r3"
+; CHECK-SPIRV: 3 Name [[#r4:]] "r4"
+; CHECK-SPIRV: 3 Name [[#r5:]] "r5"
+; CHECK-SPIRV: 3 Name [[#r6:]] "r6"
+; CHECK-SPIRV: 3 Name [[#r7:]] "r7"
+; CHECK-SPIRV-NOT: 4 Decorate [[#r1]] FPFastMathMode
+; CHECK-SPIRV-DAG: 4 Decorate [[#r2]] FPFastMathMode 1
+; CHECK-SPIRV-DAG: 4 Decorate [[#r3]] FPFastMathMode 2
+; CHECK-SPIRV-DAG: 4 Decorate [[#r4]] FPFastMathMode 4
+; CHECK-SPIRV-DAG: 4 Decorate [[#r5]] FPFastMathMode 8
+; CHECK-SPIRV-DAG: 4 Decorate [[#r6]] FPFastMathMode 16
+; CHECK-SPIRV-DAG: 4 Decorate [[#r7]] FPFastMathMode 3
+; CHECK-SPIRV: 3 TypeFloat [[float:[0-9]+]] 32
+; CHECK-SPIRV: 5 FMul [[float]] [[#r1]]
+; CHECK-SPIRV: 5 FMul [[float]] [[#r2]]
+; CHECK-SPIRV: 5 FMul [[float]] [[#r3]]
+; CHECK-SPIRV: 5 FMul [[float]] [[#r4]]
+; CHECK-SPIRV: 5 FMul [[float]] [[#r5]]
+; CHECK-SPIRV: 5 FMul [[float]] [[#r6]]
+; CHECK-SPIRV: 5 FMul [[float]] [[#r7]]
+
+; CHECK-LLVM: %r1 = fmul float %a, %b
+; CHECK-LLVM: %r2 = fmul nnan float %a, %b
+; CHECK-LLVM: %r3 = fmul ninf float %a, %b
+; CHECK-LLVM: %r4 = fmul nsz float %a, %b
+; CHECK-LLVM: %r5 = fmul arcp float %a, %b
+; CHECK-LLVM: %r6 = fmul fast float %a, %b
+; CHECK-LLVM: %r7 = fmul nnan ninf float %a, %b
+
+target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir-unknown-unknown"
+
+; Function Attrs: nounwind
+define spir_kernel void @testFMul(float %a, float %b) local_unnamed_addr #0 !kernel_arg_addr_space !2 !kernel_arg_access_qual !3 !kernel_arg_type !4 !kernel_arg_base_type !4 !kernel_arg_type_qual !5 {
+entry:
+  %r1 = fmul float %a, %b
+  %r2 = fmul nnan float %a, %b
+  %r3 = fmul ninf float %a, %b
+  %r4 = fmul nsz float %a, %b
+  %r5 = fmul arcp float %a, %b
+  %r6 = fmul fast float %a, %b
+  %r7 = fmul nnan ninf float %a, %b
+  ret void
+}
+
+attributes #0 = { convergent nounwind writeonly "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!opencl.ocl.version = !{!1}
+!opencl.spir.version = !{!1}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 2, i32 0}
+!2 = !{i32 0, i32 0}
+!3 = !{!"none", !"none"}
+!4 = !{!"float", !"float"}
+!5 = !{!"", !""}
diff --git a/test/transcoding/frem.ll b/test/transcoding/frem.ll
new file mode 100644
index 0000000000..100d8bc898
--- /dev/null
+++ b/test/transcoding/frem.ll
@@ -0,0 +1,65 @@
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv -spirv-text %t.bc -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llvm-spirv %t.bc -o %t.spv
+; RUN: spirv-val %t.spv
+; RUN: llvm-spirv -r %t.spv -o - | llvm-dis -o - | FileCheck %s --check-prefix=CHECK-LLVM
+
+; CHECK-SPIRV: 3 Name [[#r1:]] "r1"
+; CHECK-SPIRV: 3 Name [[#r2:]] "r2"
+; CHECK-SPIRV: 3 Name [[#r3:]] "r3"
+; CHECK-SPIRV: 3 Name [[#r4:]] "r4"
+; CHECK-SPIRV: 3 Name [[#r5:]] "r5"
+; CHECK-SPIRV: 3 Name [[#r6:]] "r6"
+; CHECK-SPIRV: 3 Name [[#r7:]] "r7"
+; CHECK-SPIRV-NOT: 4 Decorate [[#r1]] FPFastMathMode
+; CHECK-SPIRV-DAG: 4 Decorate [[#r2]] FPFastMathMode 1
+; CHECK-SPIRV-DAG: 4 Decorate [[#r3]] FPFastMathMode 2
+; CHECK-SPIRV-DAG: 4 Decorate [[#r4]] FPFastMathMode 4
+; CHECK-SPIRV-DAG: 4 Decorate [[#r5]] FPFastMathMode 8
+; CHECK-SPIRV-DAG: 4 Decorate [[#r6]] FPFastMathMode 16
+; CHECK-SPIRV-DAG: 4 Decorate [[#r7]] FPFastMathMode 3
+; CHECK-SPIRV: 3 TypeFloat [[float:[0-9]+]] 32
+; CHECK-SPIRV: 5 FRem [[float]] [[#r1]]
+; CHECK-SPIRV: 5 FRem [[float]] [[#r2]]
+; CHECK-SPIRV: 5 FRem [[float]] [[#r3]]
+; CHECK-SPIRV: 5 FRem [[float]] [[#r4]]
+; CHECK-SPIRV: 5 FRem [[float]] [[#r5]]
+; CHECK-SPIRV: 5 FRem [[float]] [[#r6]]
+; CHECK-SPIRV: 5 FRem [[float]] [[#r7]]
+
+; CHECK-LLVM: %r1 = frem float %a, %b
+; CHECK-LLVM: %r2 = frem nnan float %a, %b
+; CHECK-LLVM: %r3 = frem ninf float %a, %b
+; CHECK-LLVM: %r4 = frem nsz float %a, %b
+; CHECK-LLVM: %r5 = frem arcp float %a, %b
+; CHECK-LLVM: %r6 = frem fast float %a, %b
+; CHECK-LLVM: %r7 = frem nnan ninf float %a, %b
+
+target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir-unknown-unknown"
+
+; Function Attrs: nounwind
+define spir_kernel void @testFRem(float %a, float %b) local_unnamed_addr #0 !kernel_arg_addr_space !2 !kernel_arg_access_qual !3 !kernel_arg_type !4 !kernel_arg_base_type !4 !kernel_arg_type_qual !5 {
+entry:
+  %r1 = frem float %a, %b
+  %r2 = frem nnan float %a, %b
+  %r3 = frem ninf float %a, %b
+  %r4 = frem nsz float %a, %b
+  %r5 = frem arcp float %a, %b
+  %r6 = frem fast float %a, %b
+  %r7 = frem nnan ninf float %a, %b
+  ret void
+}
+
+attributes #0 = { convergent nounwind writeonly "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!opencl.ocl.version = !{!1}
+!opencl.spir.version = !{!1}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 2, i32 0}
+!2 = !{i32 0, i32 0}
+!3 = !{!"none", !"none"}
+!4 = !{!"float", !"float"}
+!5 = !{!"", !""}
diff --git a/test/transcoding/fsub.ll b/test/transcoding/fsub.ll
new file mode 100644
index 0000000000..8e500785d1
--- /dev/null
+++ b/test/transcoding/fsub.ll
@@ -0,0 +1,65 @@
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv -spirv-text %t.bc -o - | FileCheck %s --check-prefix=CHECK-SPIRV
+; RUN: llvm-spirv %t.bc -o %t.spv
+; RUN: spirv-val %t.spv
+; RUN: llvm-spirv -r %t.spv -o - | llvm-dis -o - | FileCheck %s --check-prefix=CHECK-LLVM
+
+; CHECK-SPIRV: 3 Name [[#r1:]] "r1"
+; CHECK-SPIRV: 3 Name [[#r2:]] "r2"
+; CHECK-SPIRV: 3 Name [[#r3:]] "r3"
+; CHECK-SPIRV: 3 Name [[#r4:]] "r4"
+; CHECK-SPIRV: 3 Name [[#r5:]] "r5"
+; CHECK-SPIRV: 3 Name [[#r6:]] "r6"
+; CHECK-SPIRV: 3 Name [[#r7:]] "r7"
+; CHECK-SPIRV-NOT: 4 Decorate [[#r1]] FPFastMathMode
+; CHECK-SPIRV-DAG: 4 Decorate [[#r2]] FPFastMathMode 1
+; CHECK-SPIRV-DAG: 4 Decorate [[#r3]] FPFastMathMode 2
+; CHECK-SPIRV-DAG: 4 Decorate [[#r4]] FPFastMathMode 4
+; CHECK-SPIRV-DAG: 4 Decorate [[#r5]] FPFastMathMode 8
+; CHECK-SPIRV-DAG: 4 Decorate [[#r6]] FPFastMathMode 16
+; CHECK-SPIRV-DAG: 4 Decorate [[#r7]] FPFastMathMode 3
+; CHECK-SPIRV: 3 TypeFloat [[float:[0-9]+]] 32
+; CHECK-SPIRV: 5 FSub [[float]] [[#r1]]
+; CHECK-SPIRV: 5 FSub [[float]] [[#r2]]
+; CHECK-SPIRV: 5 FSub [[float]] [[#r3]]
+; CHECK-SPIRV: 5 FSub [[float]] [[#r4]]
+; CHECK-SPIRV: 5 FSub [[float]] [[#r5]]
+; CHECK-SPIRV: 5 FSub [[float]] [[#r6]]
+; CHECK-SPIRV: 5 FSub [[float]] [[#r7]]
+
+; CHECK-LLVM: %r1 = fsub float %a, %b
+; CHECK-LLVM: %r2 = fsub nnan float %a, %b
+; CHECK-LLVM: %r3 = fsub ninf float %a, %b
+; CHECK-LLVM: %r4 = fsub nsz float %a, %b
+; CHECK-LLVM: %r5 = fsub arcp float %a, %b
+; CHECK-LLVM: %r6 = fsub fast float %a, %b
+; CHECK-LLVM: %r7 = fsub nnan ninf float %a, %b
+
+target datalayout = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir-unknown-unknown"
+
+; Function Attrs: nounwind
+define spir_kernel void @testFSub(float %a, float %b) local_unnamed_addr #0 !kernel_arg_addr_space !2 !kernel_arg_access_qual !3 !kernel_arg_type !4 !kernel_arg_base_type !4 !kernel_arg_type_qual !5 {
+entry:
+  %r1 = fsub float %a, %b
+  %r2 = fsub nnan float %a, %b
+  %r3 = fsub ninf float %a, %b
+  %r4 = fsub nsz float %a, %b
+  %r5 = fsub arcp float %a, %b
+  %r6 = fsub fast float %a, %b
+  %r7 = fsub nnan ninf float %a, %b
+  ret void
+}
+
+attributes #0 = { convergent nounwind writeonly "correctly-rounded-divide-sqrt-fp-math"="false" "denorms-are-zero"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.module.flags = !{!0}
+!opencl.ocl.version = !{!1}
+!opencl.spir.version = !{!1}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{i32 2, i32 0}
+!2 = !{i32 0, i32 0}
+!3 = !{!"none", !"none"}
+!4 = !{!"float", !"float"}
+!5 = !{!"", !""}