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asm_arm.inc
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#define DEC_5 4
#define DEC_6 5
#define DEC_8 7
#define DEC(N) uECC_CONCAT(DEC_, N)
#define REPEAT_1(stuff) stuff
#define REPEAT_2(stuff) REPEAT_1(stuff) stuff
#define REPEAT_3(stuff) REPEAT_2(stuff) stuff
#define REPEAT_4(stuff) REPEAT_3(stuff) stuff
#define REPEAT_5(stuff) REPEAT_4(stuff) stuff
#define REPEAT_6(stuff) REPEAT_5(stuff) stuff
#define REPEAT_7(stuff) REPEAT_6(stuff) stuff
#define REPEAT_8(stuff) REPEAT_7(stuff) stuff
#define REPEAT(N, stuff) uECC_CONCAT(REPEAT_, N)(stuff)
#define STR2(thing) #thing
#define STR(thing) STR2(thing)
#if (uECC_ASM == uECC_asm_fast)
static uint32_t vli_add(uint32_t *p_result, uint32_t *p_left, uint32_t *p_right)
{
uint32_t l_carry = 0;
uint32_t l_left;
uint32_t l_right;
__asm__ volatile (
".syntax unified \n\t"
"ldmia %[lptr]!, {%[left]} \n\t" /* Load left word. */
"ldmia %[rptr]!, {%[right]} \n\t" /* Load right word. */
"adds %[left], %[right] \n\t" /* Add first word. */
"stmia %[dptr]!, {%[left]} \n\t" /* Store result word. */
/* Now we just do the remaining words with the carry bit (using ADC) */
REPEAT(DEC(uECC_WORDS), "ldmia %[lptr]!, {%[left]} \n\t"
"ldmia %[rptr]!, {%[right]} \n\t"
"adcs %[left], %[right] \n\t"
"stmia %[dptr]!, {%[left]} \n\t")
"adcs %[carry], %[carry] \n\t" /* Store carry bit in l_carry. */
#if (uECC_PLATFORM != uECC_arm_thumb2)
".syntax divided \n\t"
#endif
#if (uECC_PLATFORM == uECC_arm_thumb)
: [dptr] "+l" (p_result), [lptr] "+l" (p_left), [rptr] "+l" (p_right),
[carry] "+l" (l_carry), [left] "=l" (l_left), [right] "=l" (l_right)
#else
: [dptr] "+r" (p_result), [lptr] "+r" (p_left), [rptr] "+r" (p_right),
[carry] "+r" (l_carry), [left] "=r" (l_left), [right] "=r" (l_right)
#endif
:
: "cc", "memory"
);
return l_carry;
}
#define asm_add 1
static uint32_t vli_sub(uint32_t *p_result, uint32_t *p_left, uint32_t *p_right)
{
uint32_t l_carry = 0;
uint32_t l_left;
uint32_t l_right;
__asm__ volatile (
".syntax unified \n\t"
"ldmia %[lptr]!, {%[left]} \n\t" /* Load left word. */
"ldmia %[rptr]!, {%[right]} \n\t" /* Load right word. */
"subs %[left], %[right] \n\t" /* Subtract. */
"stmia %[dptr]!, {%[left]} \n\t" /* Store result word. */
/* Now we just do the remaining words with the carry bit (using SBC) */
REPEAT(DEC(uECC_WORDS), "ldmia %[lptr]!, {%[left]} \n\t"
"ldmia %[rptr]!, {%[right]} \n\t"
"sbcs %[left], %[right] \n\t"
"stmia %[dptr]!, {%[left]} \n\t")
"adcs %[carry], %[carry] \n\t" /* Store carry bit in l_carry. */
#if (uECC_PLATFORM != uECC_arm_thumb2)
".syntax divided \n\t"
#endif
#if (uECC_PLATFORM == uECC_arm_thumb)
: [dptr] "+l" (p_result), [lptr] "+l" (p_left), [rptr] "+l" (p_right),
[carry] "+l" (l_carry), [left] "=l" (l_left), [right] "=l" (l_right)
#else
: [dptr] "+r" (p_result), [lptr] "+r" (p_left), [rptr] "+r" (p_right),
[carry] "+r" (l_carry), [left] "=r" (l_left), [right] "=r" (l_right)
#endif
:
: "cc", "memory"
);
return !l_carry; // note that on ARM, carry flag set means "no borrow" when subtracting (for some reason...)
}
#define asm_sub 1
#if (uECC_PLATFORM != uECC_arm_thumb)
#if (uECC_WORDS == 5)
static void vli_mult(uint32_t *p_result, uint32_t *p_left, uint32_t *p_right)
{
register uint32_t *r0 __asm__("r0") = p_result;
register uint32_t *r1 __asm__("r1") = p_left;
register uint32_t *r2 __asm__("r2") = p_right;
__asm__ volatile (
".syntax unified \n\t"
"add r0, 12 \n\t"
"add r2, 12 \n\t"
"ldmia r1!, {r3,r4} \n\t"
"ldmia r2!, {r6,r7} \n\t"
"umull r11, r12, r3, r6 \n\t"
"stmia r0!, {r11} \n\t"
"mov r10, #0 \n\t"
"umull r11, r9, r3, r7 \n\t"
"adds r12, r11 \n\t"
"adc r9, #0 \n\t"
"umull r11, r14, r4, r6 \n\t"
"adds r12, r11 \n\t"
"adcs r9, r14 \n\t"
"adc r10, #0 \n\t"
"stmia r0!, {r12} \n\t"
"umull r12, r14, r4, r7 \n\t"
"adds r9, r12 \n\t"
"adc r10, r14 \n\t"
"stmia r0!, {r9, r10} \n\t"
"sub r0, 28 \n\t"
"sub r2, 20 \n\t"
"ldmia r2!, {r6,r7,r8} \n\t"
"ldmia r1!, {r5} \n\t"
"umull r11, r12, r3, r6 \n\t"
"stmia r0!, {r11} \n\t"
"mov r10, #0 \n\t"
"umull r11, r9, r3, r7 \n\t"
"adds r12, r11 \n\t"
"adc r9, #0 \n\t"
"umull r11, r14, r4, r6 \n\t"
"adds r12, r11 \n\t"
"adcs r9, r14 \n\t"
"adc r10, #0 \n\t"
"stmia r0!, {r12} \n\t"
"mov r11, #0 \n\t"
"umull r12, r14, r3, r8 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"umull r12, r14, r4, r7 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"umull r12, r14, r5, r6 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"stmia r0!, {r9} \n\t"
"ldmia r1!, {r3} \n\t"
"mov r12, #0 \n\t"
"umull r14, r9, r4, r8 \n\t"
"adds r10, r14 \n\t"
"adcs r11, r9 \n\t"
"adc r12, #0 \n\t"
"umull r14, r9, r5, r7 \n\t"
"adds r10, r14 \n\t"
"adcs r11, r9 \n\t"
"adc r12, #0 \n\t"
"umull r14, r9, r3, r6 \n\t"
"adds r10, r14 \n\t"
"adcs r11, r9 \n\t"
"adc r12, #0 \n\t"
"ldr r14, [r0] \n\t"
"adds r10, r14 \n\t"
"adcs r11, #0 \n\t"
"adc r12, #0 \n\t"
"stmia r0!, {r10} \n\t"
"ldmia r1!, {r4} \n\t"
"mov r14, #0 \n\t"
"umull r9, r10, r5, r8 \n\t"
"adds r11, r9 \n\t"
"adcs r12, r10 \n\t"
"adc r14, #0 \n\t"
"umull r9, r10, r3, r7 \n\t"
"adds r11, r9 \n\t"
"adcs r12, r10 \n\t"
"adc r14, #0 \n\t"
"umull r9, r10, r4, r6 \n\t"
"adds r11, r9 \n\t"
"adcs r12, r10 \n\t"
"adc r14, #0 \n\t"
"ldr r9, [r0] \n\t"
"adds r11, r9 \n\t"
"adcs r12, #0 \n\t"
"adc r14, #0 \n\t"
"stmia r0!, {r11} \n\t"
"ldmia r2!, {r6} \n\t"
"mov r9, #0 \n\t"
"umull r10, r11, r5, r6 \n\t"
"adds r12, r10 \n\t"
"adcs r14, r11 \n\t"
"adc r9, #0 \n\t"
"umull r10, r11, r3, r8 \n\t"
"adds r12, r10 \n\t"
"adcs r14, r11 \n\t"
"adc r9, #0 \n\t"
"umull r10, r11, r4, r7 \n\t"
"adds r12, r10 \n\t"
"adcs r14, r11 \n\t"
"adc r9, #0 \n\t"
"ldr r10, [r0] \n\t"
"adds r12, r10 \n\t"
"adcs r14, #0 \n\t"
"adc r9, #0 \n\t"
"stmia r0!, {r12} \n\t"
"ldmia r2!, {r7} \n\t"
"mov r10, #0 \n\t"
"umull r11, r12, r5, r7 \n\t"
"adds r14, r11 \n\t"
"adcs r9, r12 \n\t"
"adc r10, #0 \n\t"
"umull r11, r12, r3, r6 \n\t"
"adds r14, r11 \n\t"
"adcs r9, r12 \n\t"
"adc r10, #0 \n\t"
"umull r11, r12, r4, r8 \n\t"
"adds r14, r11 \n\t"
"adcs r9, r12 \n\t"
"adc r10, #0 \n\t"
"ldr r11, [r0] \n\t"
"adds r14, r11 \n\t"
"adcs r9, #0 \n\t"
"adc r10, #0 \n\t"
"stmia r0!, {r14} \n\t"
"mov r11, #0 \n\t"
"umull r12, r14, r3, r7 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"umull r12, r14, r4, r6 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"stmia r0!, {r9} \n\t"
"umull r14, r9, r4, r7 \n\t"
"adds r10, r14 \n\t"
"adc r11, r9 \n\t"
"stmia r0!, {r10, r11} \n\t"
#if (uECC_PLATFORM != uECC_arm_thumb2)
".syntax divided \n\t"
#endif
: "+r" (r0), "+r" (r1), "+r" (r2)
:
: "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r14", "cc", "memory"
);
}
#define asm_mult 1
#endif /* (uECC_WORDS == 5) */
#if (uECC_WORDS == 6)
static void vli_mult(uint32_t *p_result, uint32_t *p_left, uint32_t *p_right)
{
register uint32_t *r0 __asm__("r0") = p_result;
register uint32_t *r1 __asm__("r1") = p_left;
register uint32_t *r2 __asm__("r2") = p_right;
__asm__ volatile (
".syntax unified \n\t"
"add r0, 12 \n\t"
"add r2, 12 \n\t"
"ldmia r1!, {r3,r4,r5} \n\t"
"ldmia r2!, {r6,r7,r8} \n\t"
"umull r11, r12, r3, r6 \n\t"
"stmia r0!, {r11} \n\t"
"mov r10, #0 \n\t"
"umull r11, r9, r3, r7 \n\t"
"adds r12, r11 \n\t"
"adc r9, #0 \n\t"
"umull r11, r14, r4, r6 \n\t"
"adds r12, r11 \n\t"
"adcs r9, r14 \n\t"
"adc r10, #0 \n\t"
"stmia r0!, {r12} \n\t"
"mov r11, #0 \n\t"
"umull r12, r14, r3, r8 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"umull r12, r14, r4, r7 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"umull r12, r14, r5, r6 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"stmia r0!, {r9} \n\t"
"mov r12, #0 \n\t"
"umull r14, r9, r4, r8 \n\t"
"adds r10, r14 \n\t"
"adcs r11, r9 \n\t"
"adc r12, #0 \n\t"
"umull r14, r9, r5, r7 \n\t"
"adds r10, r14 \n\t"
"adcs r11, r9 \n\t"
"adc r12, #0 \n\t"
"stmia r0!, {r10} \n\t"
"umull r9, r10, r5, r8 \n\t"
"adds r11, r9 \n\t"
"adc r12, r10 \n\t"
"stmia r0!, {r11, r12} \n\t"
"sub r0, 36 \n\t"
"sub r2, 24 \n\t"
"ldmia r2!, {r6,r7,r8} \n\t"
"umull r11, r12, r3, r6 \n\t"
"stmia r0!, {r11} \n\t"
"mov r10, #0 \n\t"
"umull r11, r9, r3, r7 \n\t"
"adds r12, r11 \n\t"
"adc r9, #0 \n\t"
"umull r11, r14, r4, r6 \n\t"
"adds r12, r11 \n\t"
"adcs r9, r14 \n\t"
"adc r10, #0 \n\t"
"stmia r0!, {r12} \n\t"
"mov r11, #0 \n\t"
"umull r12, r14, r3, r8 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"umull r12, r14, r4, r7 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"umull r12, r14, r5, r6 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"stmia r0!, {r9} \n\t"
"ldmia r1!, {r3} \n\t"
"mov r12, #0 \n\t"
"umull r14, r9, r4, r8 \n\t"
"adds r10, r14 \n\t"
"adcs r11, r9 \n\t"
"adc r12, #0 \n\t"
"umull r14, r9, r5, r7 \n\t"
"adds r10, r14 \n\t"
"adcs r11, r9 \n\t"
"adc r12, #0 \n\t"
"umull r14, r9, r3, r6 \n\t"
"adds r10, r14 \n\t"
"adcs r11, r9 \n\t"
"adc r12, #0 \n\t"
"ldr r14, [r0] \n\t"
"adds r10, r14 \n\t"
"adcs r11, #0 \n\t"
"adc r12, #0 \n\t"
"stmia r0!, {r10} \n\t"
"ldmia r1!, {r4} \n\t"
"mov r14, #0 \n\t"
"umull r9, r10, r5, r8 \n\t"
"adds r11, r9 \n\t"
"adcs r12, r10 \n\t"
"adc r14, #0 \n\t"
"umull r9, r10, r3, r7 \n\t"
"adds r11, r9 \n\t"
"adcs r12, r10 \n\t"
"adc r14, #0 \n\t"
"umull r9, r10, r4, r6 \n\t"
"adds r11, r9 \n\t"
"adcs r12, r10 \n\t"
"adc r14, #0 \n\t"
"ldr r9, [r0] \n\t"
"adds r11, r9 \n\t"
"adcs r12, #0 \n\t"
"adc r14, #0 \n\t"
"stmia r0!, {r11} \n\t"
"ldmia r1!, {r5} \n\t"
"mov r9, #0 \n\t"
"umull r10, r11, r3, r8 \n\t"
"adds r12, r10 \n\t"
"adcs r14, r11 \n\t"
"adc r9, #0 \n\t"
"umull r10, r11, r4, r7 \n\t"
"adds r12, r10 \n\t"
"adcs r14, r11 \n\t"
"adc r9, #0 \n\t"
"umull r10, r11, r5, r6 \n\t"
"adds r12, r10 \n\t"
"adcs r14, r11 \n\t"
"adc r9, #0 \n\t"
"ldr r10, [r0] \n\t"
"adds r12, r10 \n\t"
"adcs r14, #0 \n\t"
"adc r9, #0 \n\t"
"stmia r0!, {r12} \n\t"
"ldmia r2!, {r6} \n\t"
"mov r10, #0 \n\t"
"umull r11, r12, r3, r6 \n\t"
"adds r14, r11 \n\t"
"adcs r9, r12 \n\t"
"adc r10, #0 \n\t"
"umull r11, r12, r4, r8 \n\t"
"adds r14, r11 \n\t"
"adcs r9, r12 \n\t"
"adc r10, #0 \n\t"
"umull r11, r12, r5, r7 \n\t"
"adds r14, r11 \n\t"
"adcs r9, r12 \n\t"
"adc r10, #0 \n\t"
"ldr r11, [r0] \n\t"
"adds r14, r11 \n\t"
"adcs r9, #0 \n\t"
"adc r10, #0 \n\t"
"stmia r0!, {r14} \n\t"
"ldmia r2!, {r7} \n\t"
"mov r11, #0 \n\t"
"umull r12, r14, r3, r7 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"umull r12, r14, r4, r6 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"umull r12, r14, r5, r8 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"ldr r12, [r0] \n\t"
"adds r9, r12 \n\t"
"adcs r10, #0 \n\t"
"adc r11, #0 \n\t"
"stmia r0!, {r9} \n\t"
"ldmia r2!, {r8} \n\t"
"mov r12, #0 \n\t"
"umull r14, r9, r3, r8 \n\t"
"adds r10, r14 \n\t"
"adcs r11, r9 \n\t"
"adc r12, #0 \n\t"
"umull r14, r9, r4, r7 \n\t"
"adds r10, r14 \n\t"
"adcs r11, r9 \n\t"
"adc r12, #0 \n\t"
"umull r14, r9, r5, r6 \n\t"
"adds r10, r14 \n\t"
"adcs r11, r9 \n\t"
"adc r12, #0 \n\t"
"ldr r14, [r0] \n\t"
"adds r10, r14 \n\t"
"adcs r11, #0 \n\t"
"adc r12, #0 \n\t"
"stmia r0!, {r10} \n\t"
"mov r14, #0 \n\t"
"umull r9, r10, r4, r8 \n\t"
"adds r11, r9 \n\t"
"adcs r12, r10 \n\t"
"adc r14, #0 \n\t"
"umull r9, r10, r5, r7 \n\t"
"adds r11, r9 \n\t"
"adcs r12, r10 \n\t"
"adc r14, #0 \n\t"
"stmia r0!, {r11} \n\t"
"umull r10, r11, r5, r8 \n\t"
"adds r12, r10 \n\t"
"adc r14, r11 \n\t"
"stmia r0!, {r12, r14} \n\t"
#if (uECC_PLATFORM != uECC_arm_thumb2)
".syntax divided \n\t"
#endif
: "+r" (r0), "+r" (r1), "+r" (r2)
:
: "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r14", "cc", "memory"
);
}
#define asm_mult 1
#endif /* (uECC_WORDS == 6) */
#if (uECC_WORDS == 8)
static void vli_mult(uint32_t *p_result, uint32_t *p_left, uint32_t *p_right)
{
register uint32_t *r0 __asm__("r0") = p_result;
register uint32_t *r1 __asm__("r1") = p_left;
register uint32_t *r2 __asm__("r2") = p_right;
__asm__ volatile (
".syntax unified \n\t"
"add r0, 24 \n\t"
"add r2, 24 \n\t"
"ldmia r1!, {r3,r4} \n\t"
"ldmia r2!, {r6,r7} \n\t"
"umull r11, r12, r3, r6 \n\t"
"stmia r0!, {r11} \n\t"
"mov r10, #0 \n\t"
"umull r11, r9, r3, r7 \n\t"
"adds r12, r11 \n\t"
"adc r9, #0 \n\t"
"umull r11, r14, r4, r6 \n\t"
"adds r12, r11 \n\t"
"adcs r9, r14 \n\t"
"adc r10, #0 \n\t"
"stmia r0!, {r12} \n\t"
"umull r12, r14, r4, r7 \n\t"
"adds r9, r12 \n\t"
"adc r10, r14 \n\t"
"stmia r0!, {r9, r10} \n\t"
"sub r0, 28 \n\t"
"sub r2, 20 \n\t"
"ldmia r2!, {r6,r7,r8} \n\t"
"ldmia r1!, {r5} \n\t"
"umull r11, r12, r3, r6 \n\t"
"stmia r0!, {r11} \n\t"
"mov r10, #0 \n\t"
"umull r11, r9, r3, r7 \n\t"
"adds r12, r11 \n\t"
"adc r9, #0 \n\t"
"umull r11, r14, r4, r6 \n\t"
"adds r12, r11 \n\t"
"adcs r9, r14 \n\t"
"adc r10, #0 \n\t"
"stmia r0!, {r12} \n\t"
"mov r11, #0 \n\t"
"umull r12, r14, r3, r8 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"umull r12, r14, r4, r7 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"umull r12, r14, r5, r6 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"stmia r0!, {r9} \n\t"
"ldmia r1!, {r3} \n\t"
"mov r12, #0 \n\t"
"umull r14, r9, r4, r8 \n\t"
"adds r10, r14 \n\t"
"adcs r11, r9 \n\t"
"adc r12, #0 \n\t"
"umull r14, r9, r5, r7 \n\t"
"adds r10, r14 \n\t"
"adcs r11, r9 \n\t"
"adc r12, #0 \n\t"
"umull r14, r9, r3, r6 \n\t"
"adds r10, r14 \n\t"
"adcs r11, r9 \n\t"
"adc r12, #0 \n\t"
"ldr r14, [r0] \n\t"
"adds r10, r14 \n\t"
"adcs r11, #0 \n\t"
"adc r12, #0 \n\t"
"stmia r0!, {r10} \n\t"
"ldmia r1!, {r4} \n\t"
"mov r14, #0 \n\t"
"umull r9, r10, r5, r8 \n\t"
"adds r11, r9 \n\t"
"adcs r12, r10 \n\t"
"adc r14, #0 \n\t"
"umull r9, r10, r3, r7 \n\t"
"adds r11, r9 \n\t"
"adcs r12, r10 \n\t"
"adc r14, #0 \n\t"
"umull r9, r10, r4, r6 \n\t"
"adds r11, r9 \n\t"
"adcs r12, r10 \n\t"
"adc r14, #0 \n\t"
"ldr r9, [r0] \n\t"
"adds r11, r9 \n\t"
"adcs r12, #0 \n\t"
"adc r14, #0 \n\t"
"stmia r0!, {r11} \n\t"
"ldmia r2!, {r6} \n\t"
"mov r9, #0 \n\t"
"umull r10, r11, r5, r6 \n\t"
"adds r12, r10 \n\t"
"adcs r14, r11 \n\t"
"adc r9, #0 \n\t"
"umull r10, r11, r3, r8 \n\t"
"adds r12, r10 \n\t"
"adcs r14, r11 \n\t"
"adc r9, #0 \n\t"
"umull r10, r11, r4, r7 \n\t"
"adds r12, r10 \n\t"
"adcs r14, r11 \n\t"
"adc r9, #0 \n\t"
"ldr r10, [r0] \n\t"
"adds r12, r10 \n\t"
"adcs r14, #0 \n\t"
"adc r9, #0 \n\t"
"stmia r0!, {r12} \n\t"
"ldmia r2!, {r7} \n\t"
"mov r10, #0 \n\t"
"umull r11, r12, r5, r7 \n\t"
"adds r14, r11 \n\t"
"adcs r9, r12 \n\t"
"adc r10, #0 \n\t"
"umull r11, r12, r3, r6 \n\t"
"adds r14, r11 \n\t"
"adcs r9, r12 \n\t"
"adc r10, #0 \n\t"
"umull r11, r12, r4, r8 \n\t"
"adds r14, r11 \n\t"
"adcs r9, r12 \n\t"
"adc r10, #0 \n\t"
"ldr r11, [r0] \n\t"
"adds r14, r11 \n\t"
"adcs r9, #0 \n\t"
"adc r10, #0 \n\t"
"stmia r0!, {r14} \n\t"
"mov r11, #0 \n\t"
"umull r12, r14, r3, r7 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"umull r12, r14, r4, r6 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"stmia r0!, {r9} \n\t"
"umull r14, r9, r4, r7 \n\t"
"adds r10, r14 \n\t"
"adc r11, r9 \n\t"
"stmia r0!, {r10, r11} \n\t"
"sub r0, 52 \n\t"
"sub r1, 20 \n\t"
"sub r2, 32 \n\t"
"ldmia r1!, {r3,r4,r5} \n\t"
"ldmia r2!, {r6,r7,r8} \n\t"
"umull r11, r12, r3, r6 \n\t"
"stmia r0!, {r11} \n\t"
"mov r10, #0 \n\t"
"umull r11, r9, r3, r7 \n\t"
"adds r12, r11 \n\t"
"adc r9, #0 \n\t"
"umull r11, r14, r4, r6 \n\t"
"adds r12, r11 \n\t"
"adcs r9, r14 \n\t"
"adc r10, #0 \n\t"
"stmia r0!, {r12} \n\t"
"mov r11, #0 \n\t"
"umull r12, r14, r3, r8 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"umull r12, r14, r4, r7 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"umull r12, r14, r5, r6 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"stmia r0!, {r9} \n\t"
"ldmia r1!, {r3} \n\t"
"mov r12, #0 \n\t"
"umull r14, r9, r4, r8 \n\t"
"adds r10, r14 \n\t"
"adcs r11, r9 \n\t"
"adc r12, #0 \n\t"
"umull r14, r9, r5, r7 \n\t"
"adds r10, r14 \n\t"
"adcs r11, r9 \n\t"
"adc r12, #0 \n\t"
"umull r14, r9, r3, r6 \n\t"
"adds r10, r14 \n\t"
"adcs r11, r9 \n\t"
"adc r12, #0 \n\t"
"ldr r14, [r0] \n\t"
"adds r10, r14 \n\t"
"adcs r11, #0 \n\t"
"adc r12, #0 \n\t"
"stmia r0!, {r10} \n\t"
"ldmia r1!, {r4} \n\t"
"mov r14, #0 \n\t"
"umull r9, r10, r5, r8 \n\t"
"adds r11, r9 \n\t"
"adcs r12, r10 \n\t"
"adc r14, #0 \n\t"
"umull r9, r10, r3, r7 \n\t"
"adds r11, r9 \n\t"
"adcs r12, r10 \n\t"
"adc r14, #0 \n\t"
"umull r9, r10, r4, r6 \n\t"
"adds r11, r9 \n\t"
"adcs r12, r10 \n\t"
"adc r14, #0 \n\t"
"ldr r9, [r0] \n\t"
"adds r11, r9 \n\t"
"adcs r12, #0 \n\t"
"adc r14, #0 \n\t"
"stmia r0!, {r11} \n\t"
"ldmia r1!, {r5} \n\t"
"mov r9, #0 \n\t"
"umull r10, r11, r3, r8 \n\t"
"adds r12, r10 \n\t"
"adcs r14, r11 \n\t"
"adc r9, #0 \n\t"
"umull r10, r11, r4, r7 \n\t"
"adds r12, r10 \n\t"
"adcs r14, r11 \n\t"
"adc r9, #0 \n\t"
"umull r10, r11, r5, r6 \n\t"
"adds r12, r10 \n\t"
"adcs r14, r11 \n\t"
"adc r9, #0 \n\t"
"ldr r10, [r0] \n\t"
"adds r12, r10 \n\t"
"adcs r14, #0 \n\t"
"adc r9, #0 \n\t"
"stmia r0!, {r12} \n\t"
"ldmia r1!, {r3} \n\t"
"mov r10, #0 \n\t"
"umull r11, r12, r4, r8 \n\t"
"adds r14, r11 \n\t"
"adcs r9, r12 \n\t"
"adc r10, #0 \n\t"
"umull r11, r12, r5, r7 \n\t"
"adds r14, r11 \n\t"
"adcs r9, r12 \n\t"
"adc r10, #0 \n\t"
"umull r11, r12, r3, r6 \n\t"
"adds r14, r11 \n\t"
"adcs r9, r12 \n\t"
"adc r10, #0 \n\t"
"ldr r11, [r0] \n\t"
"adds r14, r11 \n\t"
"adcs r9, #0 \n\t"
"adc r10, #0 \n\t"
"stmia r0!, {r14} \n\t"
"ldmia r1!, {r4} \n\t"
"mov r11, #0 \n\t"
"umull r12, r14, r5, r8 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"umull r12, r14, r3, r7 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"umull r12, r14, r4, r6 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"ldr r12, [r0] \n\t"
"adds r9, r12 \n\t"
"adcs r10, #0 \n\t"
"adc r11, #0 \n\t"
"stmia r0!, {r9} \n\t"
"ldmia r2!, {r6} \n\t"
"mov r12, #0 \n\t"
"umull r14, r9, r5, r6 \n\t"
"adds r10, r14 \n\t"
"adcs r11, r9 \n\t"
"adc r12, #0 \n\t"
"umull r14, r9, r3, r8 \n\t"
"adds r10, r14 \n\t"
"adcs r11, r9 \n\t"
"adc r12, #0 \n\t"
"umull r14, r9, r4, r7 \n\t"
"adds r10, r14 \n\t"
"adcs r11, r9 \n\t"
"adc r12, #0 \n\t"
"ldr r14, [r0] \n\t"
"adds r10, r14 \n\t"
"adcs r11, #0 \n\t"
"adc r12, #0 \n\t"
"stmia r0!, {r10} \n\t"
"ldmia r2!, {r7} \n\t"
"mov r14, #0 \n\t"
"umull r9, r10, r5, r7 \n\t"
"adds r11, r9 \n\t"
"adcs r12, r10 \n\t"
"adc r14, #0 \n\t"
"umull r9, r10, r3, r6 \n\t"
"adds r11, r9 \n\t"
"adcs r12, r10 \n\t"
"adc r14, #0 \n\t"
"umull r9, r10, r4, r8 \n\t"
"adds r11, r9 \n\t"
"adcs r12, r10 \n\t"
"adc r14, #0 \n\t"
"ldr r9, [r0] \n\t"
"adds r11, r9 \n\t"
"adcs r12, #0 \n\t"
"adc r14, #0 \n\t"
"stmia r0!, {r11} \n\t"
"ldmia r2!, {r8} \n\t"
"mov r9, #0 \n\t"
"umull r10, r11, r5, r8 \n\t"
"adds r12, r10 \n\t"
"adcs r14, r11 \n\t"
"adc r9, #0 \n\t"
"umull r10, r11, r3, r7 \n\t"
"adds r12, r10 \n\t"
"adcs r14, r11 \n\t"
"adc r9, #0 \n\t"
"umull r10, r11, r4, r6 \n\t"
"adds r12, r10 \n\t"
"adcs r14, r11 \n\t"
"adc r9, #0 \n\t"
"ldr r10, [r0] \n\t"
"adds r12, r10 \n\t"
"adcs r14, #0 \n\t"
"adc r9, #0 \n\t"
"stmia r0!, {r12} \n\t"
"ldmia r2!, {r6} \n\t"
"mov r10, #0 \n\t"
"umull r11, r12, r5, r6 \n\t"
"adds r14, r11 \n\t"
"adcs r9, r12 \n\t"
"adc r10, #0 \n\t"
"umull r11, r12, r3, r8 \n\t"
"adds r14, r11 \n\t"
"adcs r9, r12 \n\t"
"adc r10, #0 \n\t"
"umull r11, r12, r4, r7 \n\t"
"adds r14, r11 \n\t"
"adcs r9, r12 \n\t"
"adc r10, #0 \n\t"
"ldr r11, [r0] \n\t"
"adds r14, r11 \n\t"
"adcs r9, #0 \n\t"
"adc r10, #0 \n\t"
"stmia r0!, {r14} \n\t"
"ldmia r2!, {r7} \n\t"
"mov r11, #0 \n\t"
"umull r12, r14, r5, r7 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"umull r12, r14, r3, r6 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"umull r12, r14, r4, r8 \n\t"
"adds r9, r12 \n\t"
"adcs r10, r14 \n\t"
"adc r11, #0 \n\t"
"ldr r12, [r0] \n\t"
"adds r9, r12 \n\t"
"adcs r10, #0 \n\t"
"adc r11, #0 \n\t"
"stmia r0!, {r9} \n\t"
"mov r12, #0 \n\t"
"umull r14, r9, r3, r7 \n\t"
"adds r10, r14 \n\t"
"adcs r11, r9 \n\t"
"adc r12, #0 \n\t"
"umull r14, r9, r4, r6 \n\t"
"adds r10, r14 \n\t"
"adcs r11, r9 \n\t"
"adc r12, #0 \n\t"
"stmia r0!, {r10} \n\t"
"umull r9, r10, r4, r7 \n\t"
"adds r11, r9 \n\t"
"adc r12, r10 \n\t"
"stmia r0!, {r11, r12} \n\t"
#if (uECC_PLATFORM != uECC_arm_thumb2)
".syntax divided \n\t"
#endif
: "+r" (r0), "+r" (r1), "+r" (r2)
:
: "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r14", "cc", "memory"
);
}
#define asm_mult 1
#endif /* (uECC_WORDS == 8) */
#if (uECC_WORDS == 5)
static void vli_square(uint32_t *p_result, uint32_t *p_left)
{
register uint32_t *r0 __asm__("r0") = p_result;
register uint32_t *r1 __asm__("r1") = p_left;
__asm__ volatile (
".syntax unified \n\t"
"ldmia r1!, {r2,r3,r4,r5,r6} \n\t"
"umull r11, r12, r2, r2 \n\t"
"stmia r0!, {r11} \n\t"
"mov r9, #0 \n\t"
"umull r10, r11, r2, r3 \n\t"
"adds r12, r10 \n\t"
"adcs r8, r11, #0 \n\t"
"adc r9, #0 \n\t"
"adds r12, r10 \n\t"
"adcs r8, r11 \n\t"
"adc r9, #0 \n\t"
"stmia r0!, {r12} \n\t"
"mov r10, #0 \n\t"
"umull r11, r12, r2, r4 \n\t"
"adds r11, r11 \n\t"
"adcs r12, r12 \n\t"
"adc r10, #0 \n\t"
"adds r8, r11 \n\t"
"adcs r9, r12 \n\t"
"adc r10, #0 \n\t"
"umull r11, r12, r3, r3 \n\t"
"adds r8, r11 \n\t"
"adcs r9, r12 \n\t"
"adc r10, #0 \n\t"
"stmia r0!, {r8} \n\t"
"mov r12, #0 \n\t"
"umull r8, r11, r2, r5 \n\t"
"umull r1, r14, r3, r4 \n\t"
"adds r8, r1 \n\t"
"adcs r11, r14 \n\t"
"adc r12, #0 \n\t"
"adds r8, r8 \n\t"
"adcs r11, r11 \n\t"
"adc r12, r12 \n\t"
"adds r8, r9 \n\t"
"adcs r11, r10 \n\t"
"adc r12, #0 \n\t"
"stmia r0!, {r8} \n\t"
"mov r10, #0 \n\t"
"umull r8, r9, r2, r6 \n\t"
"umull r1, r14, r3, r5 \n\t"
"adds r8, r1 \n\t"
"adcs r9, r14 \n\t"
"adc r10, #0 \n\t"
"adds r8, r8 \n\t"
"adcs r9, r9 \n\t"
"adc r10, r10 \n\t"
"umull r1, r14, r4, r4 \n\t"
"adds r8, r1 \n\t"
"adcs r9, r14 \n\t"
"adc r10, #0 \n\t"
"adds r8, r11 \n\t"
"adcs r9, r12 \n\t"
"adc r10, #0 \n\t"
"stmia r0!, {r8} \n\t"
"mov r12, #0 \n\t"
"umull r8, r11, r3, r6 \n\t"
"umull r1, r14, r4, r5 \n\t"
"adds r8, r1 \n\t"
"adcs r11, r14 \n\t"
"adc r12, #0 \n\t"