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Interfacing of P-Mesh directly with the L1-cache while the IO remains routed via Avalon #2

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2 of 8 tasks

kunalgulati29 opened this issue Sep 19, 2019 · 0 comments

kunalgulati29 commented Sep 19, 2019 •

edited

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Getting the reads and writes working: (In Progress)
Confirm if line and burst request of a single type comes on the bus from L1.
passing cache way with request
invalidations
replace existing dcache-icache bypass
atomic channel to L1.5 (NC bypasses L1 which will be invalidated)
transducing I/O (potentially just using existing transducer)
write-through dcache

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