Soutys8.adf

[Project]
Current Flow=Multivendor
VCS=0
version=4
Current Config=compile
[Configurations]
compile=Soutys8
[Library]
Soutys8=.\Soutys8\Soutys8.lib
Soutys8_post_synthesis=.\Soutys8_post_synthesis\Soutys8_post_synthesis.lib
Soutys8_timing=.\Soutys8_timing\Soutys8_timing.lib
[$LibMap$]
Soutys8=.
Active_lib=
[SYNTHESIS]
SYNTH_DONT_RUN_SYNTHESIS=0
OBSOLETE_ALIASES=1
SYNTH_VIEW_MODE=RTL
VIEW_MODE=RTL
SYNTH_TOPLEVEL=top
SYNTH_FAMILY=Xilinx2021x Spartan7
SYNTH_DEVICE=7s50csga324
SYNTH_SPEED=-1
SYNTH_RUN_MODE=0
SYNTH_AUTO_CLOSE=0
SYNTH_OVERWRITE_EXISTING_PRJ=1
SYNTH_SIMULATION_OUTPUT_FORMAT=1
SYNTH_SYNTHESIS_CHECKPOINT=synthesis\top_synth.dcp
SYNTH_SYNTHESIS_CONSTRAINT_FILE=
SYNTH_FLATTEN_HIERARCHY=Rebuilt
SYNTH_GATED_CLOCK_CONVERSION=Off
SYNTH_FSM_EXTRACTION=Auto
SYNTH_DISABLE_LUT_COMBINING=0
SYNTH_NUMBER_OF_GLOBAL_CLOCK_BUFFERS=12
SYNTH_DIRECTIVE=Default
SYNTH_ADD_SPECIAL_LIBRARY_SOURCES=0
SYNTH_ONE_FILE_MODE=0
SYNTH_RUN_VIVADO_WITH=0
SYNTH_SELECTED_TCL_FILE=
SYNTH_SELECTED_CHECKPOINT_FILE=
SYNTH_KEEP_EQUIVALENT_REGISTERS=0
SYNTH_RESOURCE_SHARING=Auto
SYNTH_CONTROL_SET_OPTIMIZATION_THRESHOLD=Auto
SYNTH_SHIFT_REGISTER_MINIMUM_SIZE=3
SYNTH_MAX_BRAM=-1
SYNTH_MAX_DSP=-1
SYNTH_CASCADE_DSP=Auto
SYNTH_MAX_URAM=-1
SYNTH_MAX_CASCADED_BRAM=-1
SYNTH_MAX_CASCADED_URAM=-1
SYNTH_RETIMING=0
SYNTH_DISABLE_SHIFT_REGISTER_EXTRACTION=0
SYNTH_ENABLE_VHDL_ASSERT_STATEMENT=0
SYNTH_DISABLE_TIMING_DRIVEN=0
SYNTH_INCREMENTAL=0
SYNTH_INCREMENTAL_CHECKPOINT=
SYNTH_ENABLE_SRL_STYLE=0
SYNTH_SRL_STYLE=Register
SYNTH_DEBUG_LOG=1
SYNTH_ENABLE_RQS=0
SYNTH_RQS=
SYNTH_TEMPERATURE=
SYNTH_STATIC_POWER=
SYNTH_INCREMENTAL_COMBO=Off
TOPLEVEL=top
FAMILY=Xilinx2021x Spartan7
DEVICE=7s50csga324
SPEED=-1
TEMPERATURE=
STATIC_POWER=
OLD_FAMILY=Xilinx2021x Spartan7
OUTPUT_NETLIST=synthesis\top.edn
LAST_RUN=1669051842
OUTPUT_SIMUL_NETLIST=synthesis\top.vhd
[IMPLEMENTATION]
IMPL_DONT_RUN_LOGIC_OPTIMIZATION=0
IMPL_DONT_RUN_POWER_OPTIMIZATION=1
IMPL_DONT_RUN_PLACE=0
IMPL_DONT_RUN_POST_PLACE_POWER_OPTIMIZATION=0
IMPL_DONT_RUN_PLACED_NETLIST_OPTIMIZATION=1
IMPL_DONT_RUN_ROUTE=0
IMPL_DONT_RUN_ROUTED_NETLIST_OPTIMIZATION=1
IMPL_DONT_RUN_BITSTREAM=0
FLOW_STEPS_RESET=0
UCF=
FAMILY=Xilinx2021x Spartan7
DEVICE=7s50csga324
SPEED=-1
TEMPERATURE=
STATIC_POWER=
NETLIST=synthesis\top.edn
CHECKPOINT_FILE=synthesis\top_synth.dcp
IMPL_SWEEP=1
IMPL_RETARGET=1
IMPL_CONSTANT_PROPAGATION=1
IMPL_LUT_REMAPPING=0
IMPL_DIRECTIVE=Default
IMPL_BRAM_POWER_OPTIMIZATION=0
IMPL_RESYNTHESIS=0
IMPL_PLACE_CHECKPOINT=implement\top_placed.dcp
IMPL_PLACE_DIRECTIVE=Default
IMPL_DISABLE_TIMING_DRIVEN_PLACEMENT=0
IMPL_OTHER_PLACE_COMMAND_LINE_OPTIONS=
IMPL_ROUTE_CHECKPOINT=implement\top_routed.dcp
IMPL_ROUTE_DIRECTIVE=Default
IMPL_DISABLE_TIMING_DRIVEN_ROUTING=0
IMPL_PRESERVE=0
IMPL_UNROUTE=0
IMPL_OTHER_ROUTE_COMMAND_LINE_OPTIONS=
IMPL_WRITE_BINARY_BITFILE=1
IMPL_WRITE_RAW_BITFILE=0
IMPL_WRITE_MASK_FILE=0
IMPL_FAMILY=Xilinx2021x Spartan7
IMPL_DEVICE=7s50csga324
IMPL_SPEED=-1
IMPL_RUN_MODE=0
IMPL_OVERWRITE_EXISTING_PRJ=1
IMPL_CONSTRAINT_FILE=src\constraints\Arty-S7-50-Master.xdc
IMPL_CONSTRAINT_FILE_MODE=Custom constraint file
IMPL_SELECTED_TCL_FILE=
IMPL_NETLIST_FILE=synthesis\top.edn
IMPL_AUTO_CLOSE=0
IMPL_ONE_FILE_MODE=0
IMPL_RUN_VIVADO_WITH=0
IMPL_SELECTED_CHECKPOINT_FILE=
IMPL_PLACED_NETLIST_DIRECTIVE=Default
IMPL_WRITE_LOGIC_LOCATION_FILE=0
IMPL_WRITE_BINARY_BIT_FILE_WITHOUT_HEADER=0
IMPL_REFERENCE_BIT_FILE=
IMPL_PLACED_NETLIST_FANOUT_OPTIMIZATION=0
IMPL_PLACED_NETLIST_CRITICAL_CELL_OPTIMIZATION=0
IMPL_PLACED_NETLIST_REWIRE=0
IMPL_PLACED_NETLIST_FIX_HOLD_TIME_VIOLATIONS=0
IMPL_PLACE_INCREMENTAL=0
IMPL_PLACE_INCREMENTAL_CHECKPOINT=
IMPL_ENABLE_DIRECTIVE=1
IMPL_PLACE_ENABLE_DIRECTIVE=1
IMPL_PLACED_NETLIST_ENABLE_DIRECTIVE=1
IMPL_PLACED_NETLIST_PLACEMENT_OPTIMIZATION=0
IMPL_PLACED_NETLIST_DSP_REGISTER_OPTIMIZATION=0
IMPL_PLACED_NETLIST_BRAM_REGISTER_OPTIMIZATION=0
IMPL_PLACED_NETLIST_ENABLE_FORCE_REPLICATION=0
IMPL_PLACED_NETLIST_FORCE_REPLICATION=
IMPL_ROUTE_ENABLE_DIRECTIVE=1
IMPL_SIMULATION_OUTPUT_FORMAT=1
IMPL_RESYNTHESIS_SEQUENTIAL=0
IMPL_UNPLACE=0
IMPL_PLACED_NETLIST_CRITICAL_PIN_OPTIMIZATION=0
IMPL_POST_PLACE_OPTIMIZATION=0
IMPL_PLACED_NETLIST_BRAM_ENABLE_OPTIMIZATION=0
IMPL_PLACED_NETLIST_SHIFT_REGISTER_OPTIMIZATION=0
IMPL_WRITE_READBACK_FILE=0
IMPL_NETLIST_CHECKPOINT=0
IMPL_NETLIST_CHECKPOINT_FILE=synthesis\top_synth.dcp
IMPL_FIX_TNS_PATHS=0
IMPL_PLACED_NETLIST_RETIMING_OPTIMIZATION=0
IMPL_ROUTED_NETLIST_ENABLE_DIRECTIVE=1
IMPL_ROUTED_NETLIST_DIRECTIVE=Default
IMPL_ROUTED_NETLIST_RETIMING_OPTIMIZATION=0
IMPL_ROUTED_NETLIST_CRITICAL_CELL_OPTIMIZATION=0
IMPL_ROUTED_NETLIST_REWIRE=0
IMPL_ROUTED_NETLIST_PLACEMENT_OPTIMIZATION=0
IMPL_ROUTED_NETLIST_ROUTING_OPTIMIZATION=0
IMPL_ROUTED_NETLIST_CLOCK_SKEW_OPTIMIZATION=0
IMPL_WRITE_BITSTREAM_ONLY_FOR_SPECIFIC_CELL=
IMPL_DONT_WRITE_PARTIAL_BIT_FILE=0
IMPL_GLOBAL_BUFFER_OPTIMIZATION=0
IMPL_MUXF_REMAPPING=0
IMPL_CONTROL_SET_MERGING=0
IMPL_ENABLE_HIERARCHY_FANOUT_LIMIT=0
IMPL_HIERARCHY_FANOUT_LIMIT=512
IMPL_PLACED_NETLIST_ENABLE_PATH_GROUPS=0
IMPL_PLACED_NETLIST_PATH_GROUPS=
IMPL_ROUTED_NETLIST_CURRENT_ROUTING_PLACEMENT_OPTIMIZATION=0
IMPL_SHIFT_REGISTER_OPTIMIZATION=0
IMPL_CARRY_SIGNALS_REMAPPING=0
IMPL_EQUIVALENT_DRIVERS_MERGING=0
IMPL_DEBUG_INFO=0
IMPL_DISABLE_PSIP=0
IMPL_DISABLE_GLOBAL_BUFFER_INSERTION=0
IMPL_PLACED_NETLIST_URAM_REGISTER_OPTIMIZATION=0
IMPL_ROUTED_NETLIST_SLR_CROSSING_OPTIMIZATION=0
IMPL_PLACED_NETLIST_INSERT_NEGATIVE_EDGE_TRIGGERED_FFS=0
IMPL_ROUTED_NETLIST_INSERT_NEGATIVE_EDGE_TRIGGERED_FFS=0
IMPL_DSP_REGISTER_OPTIMIZATION=0
IMPL_PLACED_NETLIST_AGGRESSIVE_HOLD_TIME_VIOLATIONS_FIX=0
IMPL_ENABLE_TURBO_MODE_ROUTING=0
IMPL_ROUTED_NETLIST_AGGRESSIVE_HOLD_TIME_VIOLATIONS_FIX=0
IMPL_AGGRESSIVE_LUT_REMAPPING=0
IMPL_PLACED_NETLIST_TNS_CLEANUP=0
IMPL_PLACED_NETLIST_SLR_CROSSING_OPTIMIZATION=0
IMPL_PLACED_NETLIST_SLL_REGISTER_HOLD_FIX=0
IMPL_ROUTED_NETLIST_TNS_CLEANUP=0
IMPL_ROUTED_NETLIST_SLL_REGISTER_HOLD_FIX=0
IMPL_PROPERTY_OPTIMIZATIONS_ONLY=0
IMPL_ENABLE_SRL_FFS_REMAPPING=0
IMPL_SRL_FFS_REMAPPING=Automatic
IMPL_TARGET_FF_UTIL=0
IMPL_TARGET_LUTRAM_UTIL=0
IMPL_MIN_DEPTH_FFS_TO_SRL=0
IMPL_MAX_DEPTH_SRL_TO_FFS=0
IMPL_ENABLE_RQS=0
IMPL_RQS=D:\Programy\ActiveHDL\My_Designs\Soutys8_GitHub\Soutys8\synthesis\top_synth.rqs
IMPL_ECO=0
IMPL_TEMPERATURE=
IMPL_STATIC_POWER=
IMPL_RESYNTHESIS_REMAPPING=0
IMPL_MULTICLOCK_BUFFER_OPTIMIZATION=0
IMPL_PLACE_ENABLE_AUTO_DIRECTIVE_INDEX=0
IMPL_PLACE_AUTO_DIRECTIVE_INDEX=1
OLD_FAMILY=Xilinx2021x Spartan7
LAST_RUN=1665417573
OUTPUT_NETLIST=implement\top.v
OUTPUT_SDF=implement\top.sdf
[Settings]
RUN_MODE_SYNTH=0
FLOW_TYPE=HDL
LANGUAGE=VHDL
REFRESH_FLOW=1
FLOWTOOLS=IMPL_WITH_SYNTH
ON_SERVERFARM_SYNTH=0
ON_SERVERFARM_IMPL=0
ON_SERVERFARM_SIM=0
fileopenfolder=D:\Programy\ActiveHDL\My_Designs\Soutys8_GitHub\Soutys8\src\testbench
VerilogDirsChanged=0
SYNTH_STATUS=warnings
IMPL_TOOL=MV_VIVADO_IMPL_2021_1
SYNTH_TOOL=MV_VIVADO_SYNTH_2021_1
CSYNTH_TOOL=
PHYSSYNTH_TOOL=
FAMILY=Xilinx2021x Spartan7
FUNC_LIB=Soutys8
POST_LIB=Soutys8_post_synthesis
PHYSSYNTH_STATUS=none
IMPL_STATUS=none
RUN_MODE_IMPL=0
TIM_LIB=Soutys8_timing
[Files]
/softprocessor_constants.vhd=-1
/ALU.vhd=-1
/Clock_prescaler.vhd=-1
/constant_values.vhd=-1
/Control_unit.vhd=-1
/Data_memory.bde=-1
/GPIO.vhd=-1
/Instruction_decoder.vhd=-1
/MMIO.bde=-1
/MUX2_8bit_read_data.vhd=-1
/MUX2_8bit_src1.vhd=-1
/MUX2_8bit_src2.vhd=-1
/MUX2_16bit_addr.vhd=-1
/MUX2_16bit_branch.vhd=-1
/MUX2_16bit_PC.vhd=-1
/MUX4_8bit.vhd=-1
/Program_counter.vhd=-1
/Program_memory.vhd=-1
/Register_file.vhd=-1
/Reset_LED.vhd=-1
/SRAM.vhd=-1
/UART_Rx.vhd=-1
/UART_Tx.vhd=-1
/top.bde=-1
/Adder_16bit.vhd=-1
testbench/ALU_tb.vhd=-1
testbench/ALU_tb_runtest.do=-1
testbench/top_tb.vhd=-1
testbench/top_tb_runtest.do=-1
testbench/SRAM_tb.vhd=-1
testbench/SRAM_tb_runtest.do=-1
testbench/GPIO_tb.vhd=-1
testbench/GPIO_tb_runtest.do=-1
testbench/Program_counter_tb.vhd=-1
testbench/Program_counter_tb_runtest.do=-1
testbench/Register_file_tb.vhd=-1
testbench/Register_file_tb_runtest.do=-1
testbench/UART_Rx_tb.vhd=-1
testbench/UART_Rx_tb_runtest.do=-1
constraints/Arty-S7-50-Master.xdc=-1
post-synthesis/..\..\synthesis\top.edn=-1
post-synthesis/..\..\synthesis\top.vhd=-1
timing/..\..\implement\top.v=-1
timing/..\..\implement\top.sdf=-1
timing/..\..\implement\glbl.v=-1
[Files.Data]
.\src\softprocessor_constants.vhd=VHDL Source Code
.\src\ALU.vhd=VHDL Source Code
.\src\Clock_prescaler.vhd=VHDL Source Code
.\src\constant_values.vhd=VHDL Source Code
.\src\Control_unit.vhd=VHDL Source Code
.\src\Data_memory.bde=Block Diagram
.\src\GPIO.vhd=VHDL Source Code
.\src\Instruction_decoder.vhd=VHDL Source Code
.\src\MMIO.bde=Block Diagram
.\src\MUX2_8bit_read_data.vhd=VHDL Source Code
.\src\MUX2_8bit_src1.vhd=VHDL Source Code
.\src\MUX2_8bit_src2.vhd=VHDL Source Code
.\src\MUX2_16bit_addr.vhd=VHDL Source Code
.\src\MUX2_16bit_branch.vhd=VHDL Source Code
.\src\MUX2_16bit_PC.vhd=VHDL Source Code
.\src\MUX4_8bit.vhd=VHDL Source Code
.\src\Program_counter.vhd=VHDL Source Code
.\src\Program_memory.vhd=VHDL Source Code
.\src\Register_file.vhd=VHDL Source Code
.\src\Reset_LED.vhd=VHDL Source Code
.\src\SRAM.vhd=VHDL Source Code
.\src\UART_Rx.vhd=VHDL Source Code
.\src\UART_Tx.vhd=VHDL Source Code
.\src\top.bde=Block Diagram
.\src\Adder_16bit.vhd=VHDL Source Code
.\src\testbench\ALU_tb.vhd=VHDL Source Code
.\src\testbench\ALU_tb_runtest.do=Macro
.\src\testbench\top_tb.vhd=VHDL Source Code
.\src\testbench\top_tb_runtest.do=Macro
.\src\testbench\SRAM_tb.vhd=VHDL Source Code
.\src\testbench\SRAM_tb_runtest.do=Macro
.\src\testbench\GPIO_tb.vhd=VHDL Source Code
.\src\testbench\GPIO_tb_runtest.do=Macro
.\src\testbench\Program_counter_tb.vhd=VHDL Source Code
.\src\testbench\Program_counter_tb_runtest.do=Macro
.\src\testbench\Register_file_tb.vhd=VHDL Source Code
.\src\testbench\Register_file_tb_runtest.do=Macro
.\src\testbench\UART_Rx_tb.vhd=VHDL Source Code
.\src\testbench\UART_Rx_tb_runtest.do=Macro
.\src\constraints\Arty-S7-50-Master.xdc=External File
.\synthesis\top.edn=EDIF Netlist
.\synthesis\top.vhd=VHDL Source Code
.\implement\top.v=VERILOG SOURCE CODE
.\implement\top.sdf=SDF FILE
.\implement\glbl.v=VERILOG SOURCE CODE
[file_out:/MMIO.bde]
/..\compile\MMIO.vhd=-1
[file_out:/Data_memory.bde]
/..\compile\Data_memory.vhd=-1
[file_out:/top.bde]
/..\compile\top.vhd=-1
[PHYS_SYNTHESIS]
IN_DESIGN=synthesis\top.edn
OUT_DESIGN=
IN_CONSTRAINT=
OUT_CONSTRAINT=
REPORT=
[SIM.POST]
TOPLEVEL=top
[sdf.c.testbench_for_top]
0=implement\top.sdf| /top_tb/UUT, Average, No
[SIM.TIME]
TOPLEVEL=top glbl
SDF_PATH=implement\top.sdf
[HierarchyViewer]
HierarchyInformation=top_tb|testbench_for_top|1
ShowHide=ShowTopLevel
Selected=
[sdf.ea.top_tb-tb_architecture]
0=implement\top.sdf| /top_tb/UUT, Average, No
[Groups]
testbench=1
constraints=1
post-synthesis=1
timing=1