-
Notifications
You must be signed in to change notification settings - Fork 1
/
hg.mac
3790 lines (3591 loc) · 142 KB
/
hg.mac
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
; Copyright 2001-2016 - Mersenne Research, Inc. All rights reserved
; Author: George Woltman
; Email: [email protected]
;
; These macros implement the building blocks for our home grown primarily radix-4
; FFT used in prime95 from 1996 to 2009. It differs from a traditional FFT
; in that the multiplication by sin/cos values are delayed to the last possible
; moment. Two pass FFTs use a modified Bailey's method, where Bailey's premultipliers
; in pass 2 are applied during the first four levels of the second pass. This
; saves quite a bit of memory.
;
; These macros are optimized for the Core 2 / Core i7 architecture and are
; similar to the x87 macros found in lucas.mac.
;************************************************************
; These macros implement the first 3 FFT and last 3 inverse
; FFT levels. They support 5, 6, 7, or 8 inputs.
; The s macros swizzle their inputs (used in one pass FFTs).
; The x macros do not swizzle their inputs (two pass FFTs).
;************************************************************
s2cl_eight_reals_first_fft MACRO srcreg,srcinc,d1
shuffle_load xmm0,xmm2,[srcreg][rbx],[srcreg+16][rbx] ;; R1,R3
shuffle_load xmm1,xmm3,[srcreg+d1][rbx],[srcreg+d1+16][rbx] ;; R2,R4
shuffle_load xmm4,xmm6,[srcreg+32][rbx],[srcreg+48][rbx] ;; R5,R7
shuffle_load xmm5,xmm7,[srcreg+d1+32][rbx],[srcreg+d1+48][rbx] ;; R6,R8
x8r_fft
xstore [srcreg], xmm7
xstore [srcreg+16], xmm6
xstore [srcreg+32], xmm4
xstore [srcreg+48], xmm5
xstore [srcreg+d1], xmm1
xstore [srcreg+d1+16], xmm3
xstore [srcreg+d1+32], xmm0
xstore [srcreg+d1+48], xmm2
bump srcreg, srcinc
ENDM
x2cl_eight_reals_first_fft MACRO srcreg,srcinc,d1
xload xmm0, [srcreg][rbx]
xload xmm1, [srcreg+d1][rbx]
xload xmm2, [srcreg+16][rbx]
xload xmm3, [srcreg+d1+16][rbx]
xload xmm4, [srcreg+32][rbx]
xload xmm5, [srcreg+d1+32][rbx]
xload xmm6, [srcreg+48][rbx]
xload xmm7, [srcreg+d1+48][rbx]
x8r_fft
xstore [srcreg], xmm7
xstore [srcreg+16], xmm6
xstore [srcreg+32], xmm4
xstore [srcreg+48], xmm5
xstore [srcreg+d1], xmm1
xstore [srcreg+d1+16], xmm3
xstore [srcreg+d1+32], xmm0
xstore [srcreg+d1+48], xmm2
bump srcreg, srcinc
ENDM
x2cl_eight_reals_fft MACRO srcreg,srcinc,d1
xload xmm0, [srcreg]
xload xmm1, [srcreg+d1]
xload xmm2, [srcreg+16]
xload xmm3, [srcreg+d1+16]
xload xmm4, [srcreg+32]
xload xmm5, [srcreg+d1+32]
xload xmm6, [srcreg+48]
xload xmm7, [srcreg+d1+48]
x8r_fft
xstore [srcreg], xmm7
xstore [srcreg+16], xmm6
xstore [srcreg+32], xmm4
xstore [srcreg+48], xmm5
xstore [srcreg+d1], xmm1
xstore [srcreg+d1+16], xmm3
xstore [srcreg+d1+32], xmm0
xstore [srcreg+d1+48], xmm2
bump srcreg, srcinc
ENDM
g2cl_eight_reals_first_fft MACRO srcreg,srcinc,d1,dstreg,dstinc,e1
xload xmm0, [srcreg][rbx]
xload xmm1, [srcreg+d1][rbx]
xload xmm2, [srcreg+16][rbx]
xload xmm3, [srcreg+d1+16][rbx]
xload xmm4, [srcreg+32][rbx]
xload xmm5, [srcreg+d1+32][rbx]
xload xmm6, [srcreg+48][rbx]
xload xmm7, [srcreg+d1+48][rbx]
bump srcreg, srcinc
x8r_fft
xstore [dstreg], xmm7
xstore [dstreg+16], xmm6
xstore [dstreg+32], xmm4
xstore [dstreg+48], xmm5
xstore [dstreg+e1], xmm1
xstore [dstreg+e1+16], xmm3
xstore [dstreg+e1+32], xmm0
xstore [dstreg+e1+48], xmm2
bump dstreg, dstinc
ENDM
x8r_fft MACRO
subpd xmm3, xmm7 ;; new R8 = R4 - R8
multwo xmm7
addpd xmm7, xmm3 ;; new R4 = R4 + R8
subpd xmm1, xmm5 ;; new R6 = R2 - R6
multwo xmm5
addpd xmm5, xmm1 ;; new R2 = R2 + R6
mulpd xmm3, XMM_SQRTHALF ;; R8 = R8 * square root
mulpd xmm1, XMM_SQRTHALF ;; R6 = R6 * square root
subpd xmm0, xmm4 ;; new R5 = R1 - R5
multwo xmm4
addpd xmm4, xmm0 ;; new R1 = R1 + R5
subpd xmm5, xmm7 ;; R2 = R2 - R4 (new & final R4)
multwo xmm7 ;; R4 = R4 * 2
subpd xmm2, xmm6 ;; new R7 = R3 - R7
multwo xmm6
addpd xmm6, xmm2 ;; new R3 = R3 + R7
subpd xmm1, xmm3 ;; R6 = R6 - R8 (Real part)
multwo xmm3 ;; R8 = R8 * 2
subpd xmm4, xmm6 ;; R1 = R1 - R3 (new & final R3)
multwo xmm6 ;; R3 = R3 * 2
addpd xmm7, xmm5 ;; R4 = R2 + R4 (new R2)
addpd xmm3, xmm1 ;; R8 = R6 + R8 (Imaginary part)
subpd xmm0, xmm1 ;; R5 = R5 - R6 (final R7)
multwo xmm1 ;; R6 = R6 * 2
addpd xmm6, xmm4 ;; R3 = R1 + R3 (new R1)
subpd xmm2, xmm3 ;; R7 = R7 - R8 (final R8)
multwo xmm3 ;; R8 = R8 * 2
subpd xmm6, xmm7 ;; R1 = R1 - R2 (final R2)
multwo xmm7 ;; R2 = R2 * 2
addpd xmm1, xmm0 ;; R6 = R5 + R6 (final R5)
addpd xmm3, xmm2 ;; R8 = R7 + R8 (final R6)
addpd xmm7, xmm6 ;; R2 = R1 + R2 (final R1)
ENDM
;; Macro to operate on 4 64-byte cache lines. It does the last
;; three inverse FFT levels of a one pass FFT.
x4cl_eight_reals_last_unfft MACRO srcreg,srcinc,d1,d2
xload xmm0, [srcreg] ;; R1
xload xmm1, [srcreg+32] ;; R2
xload xmm2, [srcreg+d1] ;; R3
xload xmm3, [srcreg+d1+32] ;; R4
xload xmm4, [srcreg+d2] ;; R5
xload xmm5, [srcreg+d2+32] ;; R6
xload xmm6, [srcreg+d2+d1] ;; R7
xload xmm7, [srcreg+d2+d1+32] ;; R8
x8r_unfft xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
xstore [srcreg], xmm6 ;; Save R1
xstore [srcreg+d2], xmm4 ;; Save R2
xstore [srcreg+32], xmm2 ;; Save R5
xstore [srcreg+d2+32], xmm3 ;; Save R6
xload xmm6, [srcreg+16] ;; R1
xload xmm4, [srcreg+48] ;; R2
xload xmm2, [srcreg+d2+16] ;; R5
xload xmm3, [srcreg+d2+48] ;; R6
xstore [srcreg+16], xmm7 ;; Save R3
xstore [srcreg+d2+16], xmm5 ;; Save R4
xstore [srcreg+48], xmm1 ;; Save R7
xstore [srcreg+d2+48], xmm0 ;; Save R8
xload xmm7, [srcreg+d1+16] ;; R3
xload xmm5, [srcreg+d1+48] ;; R4
xload xmm1, [srcreg+d2+d1+16] ;; R7
xload xmm0, [srcreg+d2+d1+48] ;; R8
x8r_unfft xmm6, xmm4, xmm7, xmm5, xmm2, xmm3, xmm1, xmm0
xstore [srcreg+d1], xmm1 ;; Save R1
xstore [srcreg+d2+d1], xmm2 ;; Save R2
xstore [srcreg+d1+16], xmm0 ;; Save R3
xstore [srcreg+d2+d1+16], xmm3 ;; Save R4
xstore [srcreg+d1+32], xmm7 ;; Save R5
xstore [srcreg+d2+d1+32], xmm5 ;; Save R6
xstore [srcreg+d1+48], xmm4 ;; Save R7
xstore [srcreg+d2+d1+48], xmm6 ;; Save R8
bump srcreg, srcinc
ENDM
x8r_unfft MACRO r1, r2, r3, r4, r5, r6, r7, r8
subpd r6, r8 ;; new R8 = R6 - R8 ;1-4
multwo r8
addpd r8, r6 ;; new R7 = R6 + R8 ;3-6
subpd r5, r7 ;; new R6 = R5 - R7 ;5-8
multwo r7
addpd r7, r5 ;; new R5 = R5 + R7 ;7-10
subpd r1, r2 ;; new R2 = R1 - R2 ;9-12
multwo r2
addpd r2, r1 ;; new R1 = R1 + R2 ;11-14
subpd r6, r5 ;; R8 = R8 - R6 ;13-16
multwo r5
addpd r5, r6 ;; R6 = R6 + R8 ;15-18
subpd r1, r4 ;; R2 = R2 - R4 (new R4) ;17-20
mulpd r6, XMM_SQRTHALF ;; R8 = R8 * square root of 1/2 ;18-23
multwo r4 ;; R4 = R4 * 2 ;20-25
mulpd r5, XMM_SQRTHALF ;; R6 = R6 * square root of 1/2 ;22-27
subpd r2, r3 ;; R1 = R1 - R3 (new R3) ;19-22
multwo r3 ;; R3 = R3 * 2 ;24-29
addpd r4, r1 ;; R4 = R2 + R4 (new R2) ;27-30
subpd r1, r6 ;; newR4 = newR4-newR8(final R8);
multwo r6 ;; R8 = R8 * 2 ;
addpd r3, r2 ;; R3 = R1 + R3 (new R1) ;
subpd r2, r8 ;; R3 = R3 - R7 (final R7) ;
multwo r8 ;; R7 = R7 * 2 ;
subpd r4, r5 ;; R2 = R2 - R6 (final R6) ;
multwo r5 ;; R6 = R6 * 2 ;
subpd r3, r7 ;; R1 = R1 - R5 (final R5) ;
multwo r7 ;; R5 = R5 * 2 ;
addpd r6, r1 ;; R8 = R4 + R8 (final R4) ;
addpd r8, r2 ;; R7 = R3 + R7 (final R3) ;
addpd r5, r4 ;; R6 = R2 + R6 (final R2) ;
addpd r7, r3 ;; R5 = R1 + R5 (final R1) ;
ENDM
xfive_reals_fft_preload MACRO
ENDM
s5cl_five_reals_first_fft MACRO srcreg,srcinc,d1
shuffle_load xmm0,xmm7,[srcreg][rbx],[srcreg+16][rbx] ;; R1,R1
xstore [srcreg+16],xmm7 ;; Save it
shuffle_load xmm1,xmm2,[srcreg+3*d1][rbx],[srcreg+3*d1+16][rbx] ;;R2,R3
shuffle_load xmm3,xmm4,[srcreg+d1+32][rbx],[srcreg+d1+48][rbx] ;; R4,R5
x5r_fft xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
xstore [srcreg], xmm0 ;; Save R1
shuffle_load xmm0,xmm2,[srcreg+d1][rbx],[srcreg+d1+16][rbx] ;; R1,R2
xstore [srcreg+d1], xmm7 ;; Save R2
xstore [srcreg+d1+16], xmm1 ;; Save R3
xstore [srcreg+d1+32], xmm5 ;; Save R4
xstore [srcreg+d1+48], xmm6 ;; Save R5
shuffle_load xmm1,xmm7,[srcreg+32][rbx],[srcreg+48][rbx] ;; R3,R3
xstore [srcreg+48],xmm7 ;; Save it
shuffle_load xmm3,xmm4,[srcreg+3*d1+32][rbx],[srcreg+3*d1+48][rbx];;R4,R5
x5r_fft xmm0, xmm2, xmm1, xmm3, xmm4, xmm5, xmm6, xmm7
xstore [srcreg+32], xmm0 ;; Save R1
xstore [srcreg+3*d1], xmm7 ;; Save R2
xstore [srcreg+3*d1+16], xmm2 ;; Save R3
xstore [srcreg+3*d1+32], xmm5 ;; Save R4
xstore [srcreg+3*d1+48], xmm6 ;; Save R5
xload xmm0, [srcreg+16] ;; R1
shuffle_load xmm1,xmm2,[srcreg+4*d1][rbx],[srcreg+4*d1+16][rbx];;R2,R3
shuffle_load xmm3,xmm4,[srcreg+2*d1+32][rbx],[srcreg+2*d1+48][rbx];;R4,R5
x5r_fft xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
xstore [srcreg+16], xmm0 ;; Save R1
shuffle_load xmm0,xmm2,[srcreg+2*d1][rbx],[srcreg+2*d1+16][rbx];;R1,R2
xstore [srcreg+2*d1], xmm7 ;; Save R2
xstore [srcreg+2*d1+16], xmm1 ;; Save R3
xstore [srcreg+2*d1+32], xmm5 ;; Save R4
xstore [srcreg+2*d1+48], xmm6 ;; Save R5
xload xmm1, [srcreg+48] ;; R3
shuffle_load xmm3,xmm4,[srcreg+4*d1+32][rbx],[srcreg+4*d1+48][rbx];;R4,R5
x5r_fft xmm0, xmm2, xmm1, xmm3, xmm4, xmm5, xmm6, xmm7
xstore [srcreg+48], xmm0 ;; Save R1
xstore [srcreg+4*d1], xmm7 ;; Save R2
xstore [srcreg+4*d1+16], xmm2 ;; Save R3
xstore [srcreg+4*d1+32], xmm5 ;; Save R4
xstore [srcreg+4*d1+48], xmm6 ;; Save R5
bump srcreg, srcinc
ENDM
x5cl_five_reals_first_fft MACRO srcreg,srcinc,d1
xload xmm0, [srcreg][rbx]
xload xmm1, [srcreg+3*d1][rbx]
xload xmm2, [srcreg+3*d1+16][rbx]
xload xmm3, [srcreg+d1+32][rbx]
xload xmm4, [srcreg+d1+48][rbx]
x5r_fft xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
xload xmm2, [srcreg+d1][rbx] ;; Load R1
xload xmm3, [srcreg+d1+16][rbx] ;; Load R2
xstore [srcreg], xmm0 ;; Save R1
xstore [srcreg+d1], xmm7 ;; Save R2
xstore [srcreg+d1+16], xmm1 ;; Save R3
xstore [srcreg+d1+32], xmm5 ;; Save R4
xstore [srcreg+d1+48], xmm6 ;; Save R5
xload xmm0, [srcreg+32][rbx] ;; Load R3
xload xmm1, [srcreg+3*d1+32][rbx] ;; Load R4
xload xmm4, [srcreg+3*d1+48][rbx] ;; Load R5
x5r_fft xmm2, xmm3, xmm0, xmm1, xmm4, xmm5, xmm6, xmm7
xstore [srcreg+32], xmm2 ;; Save R1
xstore [srcreg+3*d1], xmm7 ;; Save R2
xstore [srcreg+3*d1+16], xmm3 ;; Save R3
xstore [srcreg+3*d1+32], xmm5 ;; Save R4
xstore [srcreg+3*d1+48], xmm6 ;; Save R5
xload xmm0, [srcreg+16][rbx]
xload xmm1, [srcreg+4*d1][rbx]
xload xmm2, [srcreg+4*d1+16][rbx]
xload xmm3, [srcreg+2*d1+32][rbx]
xload xmm4, [srcreg+2*d1+48][rbx]
x5r_fft xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
xload xmm2, [srcreg+2*d1][rbx] ;; Load R1
xload xmm3, [srcreg+2*d1+16][rbx] ;; Load R2
xstore [srcreg+16], xmm0 ;; Save R1
xstore [srcreg+2*d1], xmm7 ;; Save R2
xstore [srcreg+2*d1+16], xmm1 ;; Save R3
xstore [srcreg+2*d1+32], xmm5 ;; Save R4
xstore [srcreg+2*d1+48], xmm6 ;; Save R5
xload xmm0, [srcreg+48][rbx] ;; Load R3
xload xmm1, [srcreg+4*d1+32][rbx] ;; Load R4
xload xmm4, [srcreg+4*d1+48][rbx] ;; Load R5
x5r_fft xmm2, xmm3, xmm0, xmm1, xmm4, xmm5, xmm6, xmm7
xstore [srcreg+48], xmm2 ;; Save R1
xstore [srcreg+4*d1], xmm7 ;; Save R2
xstore [srcreg+4*d1+16], xmm3 ;; Save R3
xstore [srcreg+4*d1+32], xmm5 ;; Save R4
xstore [srcreg+4*d1+48], xmm6 ;; Save R5
bump srcreg, srcinc
ENDM
x5cl_five_reals_fft MACRO srcreg,srcinc,d1
xload xmm0, [srcreg]
xload xmm1, [srcreg+3*d1]
xload xmm2, [srcreg+3*d1+16]
xload xmm3, [srcreg+d1+32]
xload xmm4, [srcreg+d1+48]
x5r_fft xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
xload xmm2, [srcreg+d1] ;; Load R1
xload xmm3, [srcreg+d1+16] ;; Load R2
xstore [srcreg], xmm0 ;; Save R1
xstore [srcreg+d1], xmm7 ;; Save R2
xstore [srcreg+d1+16], xmm1 ;; Save R3
xstore [srcreg+d1+32], xmm5 ;; Save R4
xstore [srcreg+d1+48], xmm6 ;; Save R5
xload xmm0, [srcreg+32] ;; Load R3
xload xmm1, [srcreg+3*d1+32] ;; Load R4
xload xmm4, [srcreg+3*d1+48] ;; Load R5
x5r_fft xmm2, xmm3, xmm0, xmm1, xmm4, xmm5, xmm6, xmm7
xstore [srcreg+32], xmm2 ;; Save R1
xstore [srcreg+3*d1], xmm7 ;; Save R2
xstore [srcreg+3*d1+16], xmm3 ;; Save R3
xstore [srcreg+3*d1+32], xmm5 ;; Save R4
xstore [srcreg+3*d1+48], xmm6 ;; Save R5
xload xmm0, [srcreg+16]
xload xmm1, [srcreg+4*d1]
xload xmm2, [srcreg+4*d1+16]
xload xmm3, [srcreg+2*d1+32]
xload xmm4, [srcreg+2*d1+48]
x5r_fft xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
xload xmm2, [srcreg+2*d1] ;; Load R1
xload xmm3, [srcreg+2*d1+16] ;; Load R2
xstore [srcreg+16], xmm0 ;; Save R1
xstore [srcreg+2*d1], xmm7 ;; Save R2
xstore [srcreg+2*d1+16], xmm1 ;; Save R3
xstore [srcreg+2*d1+32], xmm5 ;; Save R4
xstore [srcreg+2*d1+48], xmm6 ;; Save R5
xload xmm0, [srcreg+48] ;; Load R3
xload xmm1, [srcreg+4*d1+32] ;; Load R4
xload xmm4, [srcreg+4*d1+48] ;; Load R5
x5r_fft xmm2, xmm3, xmm0, xmm1, xmm4, xmm5, xmm6, xmm7
xstore [srcreg+48], xmm2 ;; Save R1
xstore [srcreg+4*d1], xmm7 ;; Save R2
xstore [srcreg+4*d1+16], xmm3 ;; Save R3
xstore [srcreg+4*d1+32], xmm5 ;; Save R4
xstore [srcreg+4*d1+48], xmm6 ;; Save R5
bump srcreg, srcinc
ENDM
g5cl_five_reals_first_fft MACRO srcreg,srcinc,d1,dstreg,dstinc,e1
xload xmm0, [srcreg][rbx]
xload xmm1, [srcreg+3*d1][rbx]
xload xmm2, [srcreg+3*d1+16][rbx]
xload xmm3, [srcreg+d1+32][rbx]
xload xmm4, [srcreg+d1+48][rbx]
x5r_fft xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
xload xmm2, [srcreg+d1][rbx] ;; Load R1
xload xmm3, [srcreg+d1+16][rbx] ;; Load R2
xstore [dstreg], xmm0 ;; Save R1
xstore [dstreg+e1], xmm7 ;; Save R2
xstore [dstreg+e1+16], xmm1 ;; Save R3
xstore [dstreg+e1+32], xmm5 ;; Save R4
xstore [dstreg+e1+48], xmm6 ;; Save R5
xload xmm0, [srcreg+32][rbx] ;; Load R3
xload xmm1, [srcreg+3*d1+32][rbx] ;; Load R4
xload xmm4, [srcreg+3*d1+48][rbx] ;; Load R5
x5r_fft xmm2, xmm3, xmm0, xmm1, xmm4, xmm5, xmm6, xmm7
xstore [dstreg+32], xmm2 ;; Save R1
xstore [dstreg+3*e1], xmm7 ;; Save R2
xstore [dstreg+3*e1+16], xmm3 ;; Save R3
xstore [dstreg+3*e1+32], xmm5 ;; Save R4
xstore [dstreg+3*e1+48], xmm6 ;; Save R5
xload xmm0, [srcreg+16][rbx]
xload xmm1, [srcreg+4*d1][rbx]
xload xmm2, [srcreg+4*d1+16][rbx]
xload xmm3, [srcreg+2*d1+32][rbx]
xload xmm4, [srcreg+2*d1+48][rbx]
x5r_fft xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
xload xmm2, [srcreg+2*d1][rbx] ;; Load R1
xload xmm3, [srcreg+2*d1+16][rbx] ;; Load R2
xstore [dstreg+16], xmm0 ;; Save R1
xstore [dstreg+2*e1], xmm7 ;; Save R2
xstore [dstreg+2*e1+16], xmm1 ;; Save R3
xstore [dstreg+2*e1+32], xmm5 ;; Save R4
xstore [dstreg+2*e1+48], xmm6 ;; Save R5
xload xmm0, [srcreg+48][rbx] ;; Load R3
xload xmm1, [srcreg+4*d1+32][rbx] ;; Load R4
xload xmm4, [srcreg+4*d1+48][rbx] ;; Load R5
bump srcreg, srcinc
x5r_fft xmm2, xmm3, xmm0, xmm1, xmm4, xmm5, xmm6, xmm7
xstore [dstreg+48], xmm2 ;; Save R1
xstore [dstreg+4*e1], xmm7 ;; Save R2
xstore [dstreg+4*e1+16], xmm3 ;; Save R3
xstore [dstreg+4*e1+32], xmm5 ;; Save R4
xstore [dstreg+4*e1+48], xmm6 ;; Save R5
bump dstreg, dstinc
ENDM
x5r_fft MACRO r1, r2, r3, r4, r5, t1, t2, t3
xcopy t1, r5 ;; 0-5 Copy R5
addpd r5, r2 ;; 1-4 T1 = R2 + R5
xcopy t2, r4 ;; 2-7 Copy R4
addpd r4, r3 ;; 3-5 T2 = R3 + R4
xcopy t3, r1 ;; 4-9 newR2 = R1
subpd r2, t1 ;; 6-9 T3 = R2 - R5
xcopy t1, r1 ;; 7-12 newR3 = R1
subpd r3, t2 ;; 8-11 T4 = R3 - R4
xload t2, XMM_P618 ;; 9-14 const (.588/.951)
addpd r1, r5 ;; 10-13 newR1 = R1 + T1
mulpd r5, XMM_P309 ;; 11-16 T1 = T1 * .309
mulpd r2, XMM_P951 ;; 13-18 T3 = T3 * .951 (new I2)
addpd r1, r4 ;; 14-17 newR1 = newR1 + T2
mulpd r3, XMM_P588 ;; 15-20 T4 = T4 * .588
addpd t3, r5 ;; 17-20 newR2 = newR2 + T1
mulpd r4, XMM_M809 ;; 18-23 T2 = T2 * -.809
mulpd r5, XMM_M262 ;; 20-25 T1 = T1 * (-.809/.309)
mulpd t2, r2 ;; 22-27 T3 = T3 * (.588/.951)
addpd r2, r3 ;; 23-26 newI2 = newI2 + T4
mulpd r3, XMM_M162 ;; 24-29 T4 = T4 * (-.951/.588)
addpd t3, r4 ;; 25-28 newR2 = newR2 + T2
mulpd r4, XMM_M382 ;; 26-31 T2 = T2 * (.309/-.809)
addpd t1, r5 ;; 27-30 newR3 = newR3 + T1
addpd t2, r3 ;; 30-33 T3 = T3 + T4 (final I3)
addpd t1, r4 ;; 32-35 newR3 = newR3 + T2
ENDM
xfive_reals_unfft_preload MACRO
ENDM
x5cl_five_reals_last_unfft MACRO srcreg,srcinc,d1
xload xmm0, [srcreg] ;; R1
xload xmm1, [srcreg+d1] ;; R2
xload xmm2, [srcreg+d1+32] ;; R3
xload xmm3, [srcreg+3*d1] ;; R4
xload xmm4, [srcreg+3*d1+32] ;; R5
x5r_unfft xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, [srcreg]
xload xmm1, [srcreg+d1+16] ;; R2
xload xmm2, [srcreg+d1+48] ;; R3
xstore [srcreg+d1+32], xmm3 ;; Save R4
xstore [srcreg+d1+48], xmm7 ;; Save R5
xload xmm3, [srcreg+3*d1+16] ;; R4
xload xmm4, [srcreg+3*d1+48] ;; R5
xstore [srcreg+3*d1], xmm5 ;; Save R2
xstore [srcreg+3*d1+16], xmm6 ;; Save R3
xload xmm0, [srcreg+32] ;; R1
x5r_unfft xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, [srcreg+d1]
xstore [srcreg+d1+16], xmm5 ;; Save R2
xstore [srcreg+32], xmm6 ;; Save R3
xstore [srcreg+3*d1+32], xmm3 ;; Save R4
xstore [srcreg+3*d1+48], xmm7 ;; Save R5
xload xmm0, [srcreg+16] ;; R1
xload xmm1, [srcreg+2*d1] ;; R2
xload xmm2, [srcreg+2*d1+32] ;; R3
xload xmm3, [srcreg+4*d1] ;; R4
xload xmm4, [srcreg+4*d1+32] ;; R5
x5r_unfft xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, [srcreg+16]
xload xmm1, [srcreg+2*d1+16] ;; R2
xload xmm2, [srcreg+2*d1+48] ;; R3
xstore [srcreg+2*d1+32], xmm3 ;; Save R4
xstore [srcreg+2*d1+48], xmm7 ;; Save R5
xload xmm3, [srcreg+4*d1+16] ;; R4
xload xmm4, [srcreg+4*d1+48] ;; R5
xstore [srcreg+4*d1], xmm5 ;; Save R2
xstore [srcreg+4*d1+16], xmm6 ;; Save R3
xload xmm0, [srcreg+48] ;; R1
x5r_unfft xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, [srcreg+2*d1]
xstore [srcreg+2*d1+16], xmm5 ;; Save R2
xstore [srcreg+48], xmm6 ;; Save R3
xstore [srcreg+4*d1+32], xmm3 ;; Save R4
xstore [srcreg+4*d1+48], xmm7 ;; Save R5
bump srcreg, srcinc
ENDM
x5r_unfft MACRO r1, r2, r3, r4, r5, t1, t2, t3, mem1
xload t1, XMM_P309 ;; Load .309
mulpd t1, r2 ;; 1-6 R2*.309
xload t2, XMM_M809 ;; Load -.809
mulpd t2, r2 ;; 3-8 R2*-.809
addpd r2, r4 ;; 4-7 R2+R3
xload t3, XMM_M809 ;; Load .309
mulpd t3, r4 ;; 5-10 R3*-.809
addpd r2, r1 ;; 6-9 R1+R2+R3 (final R1)
mulpd r4, XMM_P309 ;; 7-12 R3*.309
addpd t1, r1 ;; 8-11 R1 + R2*.309
xstore mem1, r2 ;; Save final R1
xload r2, XMM_P951 ;; Load 0.951
mulpd r2, r3 ;; 9-14 I2*.951
addpd t2, r1 ;; 10-13 R1 + R2*-.809
xload r1, XMM_P588 ;; Load 0.588
mulpd r1, r5 ;; 11-16 I3*.588
addpd t1, t3 ;; 12-15 R1 + R2*.309 - R3*.809
mulpd r3, XMM_P588 ;; 13-18 I2*.588
addpd t2, r4 ;; 14-17 R1 - R2*.809 + R3*.309
mulpd r5, XMM_P951 ;; 15-20 I3*-.951
xcopy t3, t1 ;; 16-21 R1 + R2*.309 - R3*.809
addpd r2, r1 ;; 17-20 I2*.951 + I3*.588
xcopy r4, t2 ;; 18-23 R1 - R2*.809 + R3*.309
subpd r3, r5 ;; 21-24 I2*.588 - I3*.951
addpd t1, r2 ;; 23-26 final R2
subpd t3, r2 ;; 25-28 final R5
addpd t2, r3 ;; 27-30 final R3
subpd r4, r3 ;; 29-31 final R4
ENDM
xsix_reals_fft_preload MACRO
ENDM
s3cl_six_reals_first_fft MACRO srcreg,srcinc,d1
low_load xmm0, [srcreg][rbx], [srcreg+16][rbx] ;; R1
low_load xmm3, [srcreg+32][rbx], [srcreg+48][rbx] ;; R4
high_load xmm2, [srcreg+d1][rbx], [srcreg+d1+16][rbx] ;; R3
high_load xmm5, [srcreg+d1+32][rbx], [srcreg+d1+48][rbx] ;; R6
low_load xmm1, [srcreg+2*d1][rbx], [srcreg+2*d1+16][rbx] ;; R2
low_load xmm4, [srcreg+2*d1+32][rbx], [srcreg+2*d1+48][rbx] ;; R5
x6r_fft xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
high_load xmm3, [srcreg][rbx], [srcreg+16][rbx] ;; R2
high_load xmm4, [srcreg+32][rbx], [srcreg+48][rbx] ;; R5
xstore [srcreg], xmm1 ;; Save R1
xstore [srcreg+32], xmm2 ;; Save R2
low_load xmm1, [srcreg+d1][rbx], [srcreg+d1+16][rbx] ;; R1
low_load xmm2, [srcreg+d1+32][rbx], [srcreg+d1+48][rbx] ;; R4
xstore [srcreg+d1], xmm5 ;; Save R3
xstore [srcreg+d1+16], xmm7 ;; Save R4
xstore [srcreg+d1+32], xmm0 ;; Save R5
xstore [srcreg+d1+48], xmm6 ;; Save R6
high_load xmm5, [srcreg+2*d1][rbx], [srcreg+2*d1+16][rbx] ;; R3
high_load xmm7, [srcreg+2*d1+32][rbx], [srcreg+2*d1+48][rbx] ;; R6
x6r_fft xmm1, xmm3, xmm5, xmm2, xmm4, xmm7, xmm0, xmm6
xstore [srcreg+16], xmm3 ;; Save R1
xstore [srcreg+48], xmm5 ;; Save R2
xstore [srcreg+2*d1], xmm7 ;; Save R3
xstore [srcreg+2*d1+16], xmm6 ;; Save R4
xstore [srcreg+2*d1+32], xmm1 ;; Save R5
xstore [srcreg+2*d1+48], xmm0 ;; Save R6
bump srcreg, srcinc
ENDM
x3cl_six_reals_first_fft MACRO srcreg,srcinc,d1
xload xmm0, [srcreg][rbx]
xload xmm3, [srcreg+32][rbx]
xload xmm2, [srcreg+d1+16][rbx]
xload xmm5, [srcreg+d1+48][rbx]
xload xmm1, [srcreg+2*d1][rbx]
xload xmm4, [srcreg+2*d1+32][rbx]
x6r_fft xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
xstore [srcreg], xmm1
xstore [srcreg+32], xmm2
xstore [srcreg+d1+16], xmm7
xstore [srcreg+d1+48], xmm6
xload xmm1, [srcreg+d1][rbx] ;; R1
xload xmm2, [srcreg+d1+32][rbx] ;; R4
xstore [srcreg+d1], xmm5
xstore [srcreg+d1+32], xmm0
xload xmm3, [srcreg+16][rbx] ;; R2
xload xmm4, [srcreg+48][rbx] ;; R5
xload xmm5, [srcreg+2*d1+16][rbx] ;; R3
xload xmm6, [srcreg+2*d1+48][rbx] ;; R6
x6r_fft xmm1, xmm3, xmm5, xmm2, xmm4, xmm6, xmm0, xmm7
xstore [srcreg+16], xmm3
xstore [srcreg+48], xmm5
xstore [srcreg+2*d1], xmm6
xstore [srcreg+2*d1+16], xmm7
xstore [srcreg+2*d1+32], xmm1
xstore [srcreg+2*d1+48], xmm0
bump srcreg, srcinc
ENDM
x3cl_six_reals_fft MACRO srcreg,srcinc,d1
xload xmm0, [srcreg]
xload xmm3, [srcreg+32]
xload xmm2, [srcreg+d1+16]
xload xmm5, [srcreg+d1+48]
xload xmm1, [srcreg+2*d1]
xload xmm4, [srcreg+2*d1+32]
x6r_fft xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
xstore [srcreg], xmm1
xstore [srcreg+32], xmm2
xstore [srcreg+d1+16], xmm7
xstore [srcreg+d1+48], xmm6
xload xmm1, [srcreg+d1] ;; R1
xload xmm2, [srcreg+d1+32] ;; R4
xstore [srcreg+d1], xmm5
xstore [srcreg+d1+32], xmm0
xload xmm3, [srcreg+16] ;; R2
xload xmm4, [srcreg+48] ;; R5
xload xmm5, [srcreg+2*d1+16] ;; R3
xload xmm6, [srcreg+2*d1+48] ;; R6
x6r_fft xmm1, xmm3, xmm5, xmm2, xmm4, xmm6, xmm0, xmm7
xstore [srcreg+16], xmm3
xstore [srcreg+48], xmm5
xstore [srcreg+2*d1], xmm6
xstore [srcreg+2*d1+16], xmm7
xstore [srcreg+2*d1+32], xmm1
xstore [srcreg+2*d1+48], xmm0
bump srcreg, srcinc
ENDM
g3cl_six_reals_first_fft MACRO srcreg,srcinc,d1,dstreg,dstinc,e1
xload xmm0, [srcreg][rbx]
xload xmm3, [srcreg+32][rbx]
xload xmm2, [srcreg+d1+16][rbx]
xload xmm5, [srcreg+d1+48][rbx]
xload xmm1, [srcreg+2*d1][rbx]
xload xmm4, [srcreg+2*d1+32][rbx]
x6r_fft xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
xstore [dstreg], xmm1
xstore [dstreg+32], xmm2
xstore [dstreg+e1+16], xmm7
xstore [dstreg+e1+48], xmm6
xload xmm1, [srcreg+d1][rbx] ;; R1
xload xmm2, [srcreg+d1+32][rbx] ;; R4
xstore [dstreg+e1], xmm5
xstore [dstreg+e1+32], xmm0
xload xmm3, [srcreg+16][rbx] ;; R2
xload xmm4, [srcreg+48][rbx] ;; R5
xload xmm5, [srcreg+2*d1+16][rbx] ;; R3
xload xmm6, [srcreg+2*d1+48][rbx] ;; R6
bump srcreg, srcinc
x6r_fft xmm1, xmm3, xmm5, xmm2, xmm4, xmm6, xmm0, xmm7
xstore [dstreg+16], xmm3
xstore [dstreg+48], xmm5
xstore [dstreg+2*e1], xmm6
xstore [dstreg+2*e1+16], xmm7
xstore [dstreg+2*e1+32], xmm1
xstore [dstreg+2*e1+48], xmm0
bump dstreg, dstinc
ENDM
; Simplifying the pseudo code from pfa.mac yields:
; new R1 = R1 + R3 + R5
; new R2 = R1 - 0.5 * (R3 + R5)
; new R3 = R2 + R4 + R6
; new I2 = 0.866 * (R3 - R5)
; new R4 = 0.5 * (R2 + R6) - R4
; new I4 = 0.866 * (R2 - R6)
; R1 + R3 (final R1)
; R1 - R3 (final R2)
; R2 + R4 (final R3)
; R2 - R4 (final R5)
; I2 + I4 (final R4)
; I2 - I4 (final R6)
x6r_fft MACRO r1, r2, r3, r4, r5, r6, t1, t2
xcopy t1, r3
addpd r3, r5 ;; T4 = R3 + R5
xcopy t2, r2
addpd r2, r6 ;; T2 = R2 + R6
subpd t1, r5 ;; T3 = R3 - R5
subpd t2, r6 ;; T1 = R2 - R6
xload r5, XMM_HALF
mulpd r5, r3 ;; 0.5 * (R3 + R5)
addpd r3, r1 ;; new R1 = R1 + R3 + R5
xload r6, XMM_HALF
mulpd r6, r2 ;; 0.5 * (R2 + R6)
addpd r2, r4 ;; new R3 = R2 + R4 + R6
mulpd t1, XMM_P866 ;; new I2 = 0.866 * (R3 - R5)
subpd r1, r5 ;; new R2 = R1 - 0.5 * (R3 + R5)
mulpd t2, XMM_P866 ;; new I4 = 0.866 * (R2 - R6)
subpd r6, r4 ;; new R4 = 0.5 * (R2 + R6) - R4
xcopy r5, r3
subpd r3, r2 ;; R1 = R1 - R3 (final R2)
addpd r2, r5 ;; R3 = R1 + R3 (final R1)
xcopy r4, t1
subpd t1, t2 ;; I2 = I2 - I4 (final R6)
addpd t2, r4 ;; I4 = I2 + I4 (final R4)
xcopy r5, r1
subpd r1, r6 ;; R2 = R2 - R4 (final R5)
addpd r6, r5 ;; R4 = R2 + R4 (final R3)
ENDM
xsix_reals_unfft_preload MACRO
ENDM
x3cl_six_reals_last_unfft MACRO srcreg,srcinc,d1
xload xmm0, [srcreg] ;; R1
xload xmm1, [srcreg+32] ;; R2
xload xmm2, [srcreg+d1] ;; R3
xload xmm3, [srcreg+d1+32] ;; R4
xload xmm4, [srcreg+2*d1] ;; R5
xload xmm5, [srcreg+2*d1+32] ;; R6
x6r_unfft xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
xstore [srcreg], xmm4 ;; Save R1
xstore [srcreg+32], xmm0 ;; Save R4
xstore [srcreg+2*d1], xmm3 ;; Save R2
xstore [srcreg+2*d1+32], xmm1 ;; Save R5
xload xmm2, [srcreg+d1+16] ;; R3
xload xmm3, [srcreg+d1+48] ;; R4
xstore [srcreg+d1+16], xmm5 ;; Save R3
xstore [srcreg+d1+48], xmm7 ;; Save R6
xload xmm0, [srcreg+16] ;; R1
xload xmm1, [srcreg+48] ;; R2
xload xmm4, [srcreg+2*d1+16] ;; R5
xload xmm5, [srcreg+2*d1+48] ;; R6
x6r_unfft xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
xstore [srcreg+16], xmm3 ;; Save R2
xstore [srcreg+48], xmm1 ;; Save R5
xstore [srcreg+d1], xmm4 ;; Save R1
xstore [srcreg+d1+32], xmm0 ;; Save R4
xstore [srcreg+2*d1+16], xmm5 ;; Save R3
xstore [srcreg+2*d1+48], xmm7 ;; Save R6
bump srcreg, srcinc
ENDM
; Simplifying the pseudo code in pfa.mac we get:
; R1 + R2 (new R1)
; R1 - R2 (new R3)
; R3 + R5 (new R2)
; R3 - R5 (new R4)
; R4 + R6 (new I2)
; R4 - R6 (new I4)
; final R1 = R1 + R2
; final R3 = R1 - 0.5 * R2 + 0.866 * I2
; final R5 = R1 - 0.5 * R2 - 0.866 * I2
; final R2 = R3 + 0.5 * R4 + 0.866 * I4
; final R4 = R3 - R4
; final R6 = R3 + 0.5 * R4 - 0.866 * I4
x6r_unfft MACRO r1, r2, r3, r4, r5, r6, t1, t2
xcopy t1, r3
subpd r3, r5 ;; R3 - R5 (new R4)
addpd r5, t1 ;; R3 + R5 (new R2)
xcopy t2, r4
subpd r4, r6 ;; R4 - R6 (new I4)
addpd r6, t2 ;; R4 + R6 (new I2)
xload t2, XMM_HALF
mulpd t2, r3 ;; 0.5 * R4
xcopy t1, r1
subpd r1, r2 ;; R1 - R2 (new R3)
addpd r2, t1 ;; R1 + R2 (new R1)
xload t1, XMM_HALF
mulpd t1, r5 ;; 0.5 * R2
mulpd r4, XMM_P866 ;; 0.866 * I4
mulpd r6, XMM_P866 ;; 0.866 * I2
addpd t2, r1 ;; R3 + 0.5 * R4
addpd r5, r2 ;; final R1 = R1 + R2
subpd r2, t1 ;; R1 - 0.5 * R2
subpd r1, r3 ;; final R4 = R3 - R4
xcopy t1, r4 ;; Copy 0.866 * I4
addpd r4, t2 ;; final R2 = R3 + 0.5 * R4 + 0.866 * I4
subpd t2, t1 ;; final R6 = R3 + 0.5 * R4 - 0.866 * I4
xcopy r3, r6 ;; Copy 0.866 * I2
addpd r6, r2 ;; final R3 = R1 - 0.5 * R2 + 0.866 * I2
subpd r2, r3 ;; final R5 = R1 - 0.5 * R2 - 0.866 * I2
ENDM
xseven_reals_fft_preload MACRO
ENDM
s7cl_seven_reals_first_fft MACRO srcreg,srcinc,d1
shuffle_load xmm0,xmm7,[srcreg][rbx],[srcreg+16][rbx] ;; R1,R1
xstore [srcreg+16],xmm7 ;; Save it
xload xmm1, [srcreg+d1+16][rbx]
movlpd xmm1, Q [srcreg+d1+8][rbx] ;; R2
shuffle_load xmm2,xmm3,[srcreg+5*d1][rbx],[srcreg+5*d1+16][rbx] ;;R3,R4
low_load xmm4, [srcreg+d1+32][rbx], [srcreg+d1+48][rbx] ;; R5
shuffle_load xmm5,xmm6,[srcreg+3*d1+32][rbx],[srcreg+3*d1+48][rbx] ;;R6,R7
x7r_fft xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, [srcreg]
low_load xmm2, [srcreg+d1][rbx], [srcreg+d1+16][rbx] ;; R1
high_load xmm6, [srcreg+d1+32][rbx], [srcreg+d1+48][rbx] ;; R5
xstore [srcreg+d1], xmm0 ;; Save R2
xstore [srcreg+d1+32], xmm1 ;; Save R3
shuffle_load xmm1,xmm0,[srcreg+3*d1][rbx],[srcreg+3*d1+16][rbx] ;;R2,R3
xstore [srcreg+3*d1], xmm4 ;; Save R4
xstore [srcreg+3*d1+16], xmm5 ;; Save R5
xstore [srcreg+3*d1+32], xmm7 ;; Save R6
xstore [srcreg+3*d1+48], xmm3 ;; Save R7
shuffle_load xmm3,xmm7,[srcreg+32][rbx],[srcreg+48][rbx] ;; R4,R4
xstore [srcreg+48],xmm7 ;; Save it
shuffle_load xmm5,xmm4,[srcreg+5*d1+32][rbx],[srcreg+5*d1+48][rbx];;R6,R7
x7r_fft xmm2, xmm1, xmm0, xmm3, xmm6, xmm5, xmm4, xmm7, [srcreg+32]
xstore [srcreg+d1+16], xmm2 ;; Save R2
xstore [srcreg+d1+48], xmm1 ;; Save R3
xstore [srcreg+5*d1], xmm6 ;; Save R4
xstore [srcreg+5*d1+16], xmm5 ;; Save R5
xstore [srcreg+5*d1+32], xmm7 ;; Save R6
xstore [srcreg+5*d1+48], xmm3 ;; Save R7
xload xmm0, [srcreg+16] ;; R1
high_load xmm1, [srcreg+2*d1][rbx], [srcreg+2*d1+16][rbx] ;; R2
shuffle_load xmm2,xmm3,[srcreg+6*d1][rbx],[srcreg+6*d1+16][rbx];;R3,R4
low_load xmm4, [srcreg+2*d1+32][rbx], [srcreg+2*d1+48][rbx] ;; R5
shuffle_load xmm5,xmm6,[srcreg+4*d1+32][rbx],[srcreg+4*d1+48][rbx];;R6,R7
x7r_fft xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, [srcreg+16]
low_load xmm2, [srcreg+2*d1][rbx], [srcreg+2*d1+16][rbx] ;; R1
high_load xmm6, [srcreg+2*d1+32][rbx], [srcreg+2*d1+48][rbx]
xstore [srcreg+2*d1], xmm0 ;; Save R2
xstore [srcreg+2*d1+32], xmm1 ;; Save R3
shuffle_load xmm1,xmm0,[srcreg+4*d1][rbx],[srcreg+4*d1+16][rbx];;R2,R3
xstore [srcreg+4*d1], xmm4 ;; Save R4
xstore [srcreg+4*d1+16], xmm5 ;; Save R5
xstore [srcreg+4*d1+32], xmm7 ;; Save R6
xstore [srcreg+4*d1+48], xmm3 ;; Save R7
xload xmm3, [srcreg+48] ;; R4
shuffle_load xmm5,xmm4,[srcreg+6*d1+32][rbx],[srcreg+6*d1+48][rbx];;R6,R7
x7r_fft xmm2, xmm1, xmm0, xmm3, xmm6, xmm5, xmm4, xmm7, [srcreg+48]
xstore [srcreg+2*d1+16], xmm2 ;; Save R2
xstore [srcreg+2*d1+48], xmm1 ;; Save R3
xstore [srcreg+6*d1], xmm6 ;; Save R4
xstore [srcreg+6*d1+16], xmm5 ;; Save R5
xstore [srcreg+6*d1+32], xmm7 ;; Save R6
xstore [srcreg+6*d1+48], xmm3 ;; Save R7
bump srcreg, srcinc
ENDM
;; 215.55 clocks
x7cl_seven_reals_first_fft MACRO srcreg,srcinc,d1
xload xmm0, [srcreg][rbx] ;; Load R1
xload xmm1, [srcreg+d1+16][rbx];; Load R2
xload xmm2, [srcreg+5*d1][rbx];; Load R3
x7r_fft_mem [srcreg+5*d1+16][rbx], [srcreg+d1+32][rbx], [srcreg+3*d1+32][rbx], [srcreg+3*d1+48][rbx], [srcreg], [srcreg+3*d1+32], 0
xstore [srcreg+d1+32], xmm2 ;; Save I2
xload xmm2, [srcreg+3*d1+16][rbx];; Load R3
xstore [srcreg+3*d1+16], xmm1 ;; Save I3
xload xmm1, [srcreg+3*d1][rbx];; Load R2
xstore [srcreg+3*d1], xmm0 ;; Save R3
xload xmm0, [srcreg+d1][rbx] ;; Load R1
xstore [srcreg+d1], xmm4 ;; Save R2
xstore [srcreg+3*d1+48], xmm3 ;; Save I4
x7r_fft_mem [srcreg+32][rbx], [srcreg+d1+48][rbx], [srcreg+5*d1+32][rbx], [srcreg+5*d1+48][rbx], [srcreg+32], [srcreg+5*d1+32], 1
xstore [srcreg+d1+16], xmm4 ;; Save R2
xstore [srcreg+d1+48], xmm2 ;; Save I2
xstore [srcreg+5*d1], xmm0 ;; Save R3
xstore [srcreg+5*d1+16], xmm1 ;; Save I3
xstore [srcreg+5*d1+48], xmm3 ;; Save I4
xload xmm0, [srcreg+16][rbx] ;; Load R1
xload xmm1, [srcreg+2*d1+16][rbx];; Load R2
xload xmm2, [srcreg+6*d1][rbx];; Load R3
x7r_fft_mem [srcreg+6*d1+16][rbx], [srcreg+2*d1+32][rbx], [srcreg+4*d1+32][rbx], [srcreg+4*d1+48][rbx], [srcreg+16], [srcreg+4*d1+32], 0
xstore [srcreg+2*d1+32], xmm2 ;; Save I2
xload xmm2, [srcreg+4*d1+16][rbx];; Load R3
xstore [srcreg+4*d1+16], xmm1 ;; Save I3
xload xmm1, [srcreg+4*d1][rbx];; Load R2
xstore [srcreg+4*d1], xmm0 ;; Save R3
xload xmm0, [srcreg+2*d1][rbx];; Load R1
xstore [srcreg+2*d1], xmm4 ;; Save R2
xstore [srcreg+4*d1+48], xmm3 ;; Save I4
x7r_fft_mem [srcreg+48][rbx], [srcreg+2*d1+48][rbx], [srcreg+6*d1+32][rbx], [srcreg+6*d1+48][rbx], [srcreg+48], [srcreg+6*d1+32], 1
xstore [srcreg+2*d1+16], xmm4 ;; Save R2
xstore [srcreg+2*d1+48], xmm2 ;; Save I2
xstore [srcreg+6*d1], xmm0 ;; Save R3
xstore [srcreg+6*d1+16], xmm1 ;; Save I3
xstore [srcreg+6*d1+48], xmm3 ;; Save I4
bump srcreg, srcinc
ENDM
x7cl_seven_reals_fft MACRO srcreg,srcinc,d1
xload xmm0, [srcreg] ;; Load R1
xload xmm1, [srcreg+d1+16] ;; Load R2
xload xmm2, [srcreg+5*d1] ;; Load R3
x7r_fft_mem [srcreg+5*d1+16], [srcreg+d1+32], [srcreg+3*d1+32], [srcreg+3*d1+48], [srcreg], [srcreg+3*d1+32], 0
xstore [srcreg+d1+32], xmm2 ;; Save I2
xload xmm2, [srcreg+3*d1+16] ;; Load R3
xstore [srcreg+3*d1+16], xmm1 ;; Save I3
xload xmm1, [srcreg+3*d1] ;; Load R2
xstore [srcreg+3*d1], xmm0 ;; Save R3
xload xmm0, [srcreg+d1] ;; Load R1
xstore [srcreg+d1], xmm4 ;; Save R2
xstore [srcreg+3*d1+48], xmm3 ;; Save I4
x7r_fft_mem [srcreg+32], [srcreg+d1+48], [srcreg+5*d1+32], [srcreg+5*d1+48], [srcreg+32], [srcreg+5*d1+32], 1
xstore [srcreg+d1+16], xmm4 ;; Save R2
xstore [srcreg+d1+48], xmm2 ;; Save I2
xstore [srcreg+5*d1], xmm0 ;; Save R3
xstore [srcreg+5*d1+16], xmm1 ;; Save I3
xstore [srcreg+5*d1+48], xmm3 ;; Save I4
xload xmm0, [srcreg+16] ;; Load R1
xload xmm1, [srcreg+2*d1+16] ;; Load R2
xload xmm2, [srcreg+6*d1] ;; Load R3
x7r_fft_mem [srcreg+6*d1+16], [srcreg+2*d1+32], [srcreg+4*d1+32], [srcreg+4*d1+48], [srcreg+16], [srcreg+4*d1+32], 0
xstore [srcreg+2*d1+32], xmm2 ;; Save I2
xload xmm2, [srcreg+4*d1+16] ;; Load R3
xstore [srcreg+4*d1+16], xmm1 ;; Save I3
xload xmm1, [srcreg+4*d1] ;; Load R2
xstore [srcreg+4*d1], xmm0 ;; Save R3
xload xmm0, [srcreg+2*d1] ;; Load R1
xstore [srcreg+2*d1], xmm4 ;; Save R2
xstore [srcreg+4*d1+48], xmm3 ;; Save I4
x7r_fft_mem [srcreg+48], [srcreg+2*d1+48], [srcreg+6*d1+32], [srcreg+6*d1+48], [srcreg+48], [srcreg+6*d1+32], 1
xstore [srcreg+2*d1+16], xmm4 ;; Save R2
xstore [srcreg+2*d1+48], xmm2 ;; Save I2
xstore [srcreg+6*d1], xmm0 ;; Save R3
xstore [srcreg+6*d1+16], xmm1 ;; Save I3
xstore [srcreg+6*d1+48], xmm3 ;; Save I4
bump srcreg, srcinc
ENDM
g7cl_seven_reals_first_fft MACRO srcreg,srcinc,d1,dstreg,dstinc,e1
xload xmm0, [srcreg][rbx] ;; Load R1
xload xmm1, [srcreg+d1+16][rbx];; Load R2
xload xmm2, [srcreg+5*d1][rbx];; Load R3
x7r_fft_mem [srcreg+5*d1+16][rbx], [srcreg+d1+32][rbx], [srcreg+3*d1+32][rbx], [srcreg+3*d1+48][rbx], [dstreg], [dstreg+3*e1+32], 0
xstore [dstreg+e1+32], xmm2 ;; Save I2
xload xmm2, [srcreg+3*d1+16][rbx];; Load R3
xstore [dstreg+3*e1+16], xmm1 ;; Save I3
xload xmm1, [srcreg+3*d1][rbx];; Load R2
xstore [dstreg+3*e1], xmm0 ;; Save R3
xload xmm0, [srcreg+d1][rbx] ;; Load R1
xstore [dstreg+e1], xmm4 ;; Save R2
xstore [dstreg+3*e1+48], xmm3 ;; Save I4
x7r_fft_mem [srcreg+32][rbx], [srcreg+d1+48][rbx], [srcreg+5*d1+32][rbx], [srcreg+5*d1+48][rbx], [dstreg+32], [dstreg+5*e1+32], 1
xstore [dstreg+e1+16], xmm4 ;; Save R2
xstore [dstreg+e1+48], xmm2 ;; Save I2
xstore [dstreg+5*e1], xmm0 ;; Save R3
xstore [dstreg+5*e1+16], xmm1 ;; Save I3
xstore [dstreg+5*e1+48], xmm3 ;; Save I4
xload xmm0, [srcreg+16][rbx] ;; Load R1
xload xmm1, [srcreg+2*d1+16][rbx];; Load R2
xload xmm2, [srcreg+6*d1][rbx];; Load R3
x7r_fft_mem [srcreg+6*d1+16][rbx], [srcreg+2*d1+32][rbx], [srcreg+4*d1+32][rbx], [srcreg+4*d1+48][rbx], [dstreg+16], [dstreg+4*d1+32], 0
xstore [dstreg+2*e1+32], xmm2 ;; Save I2
xload xmm2, [srcreg+4*d1+16][rbx];; Load R3
xstore [dstreg+4*e1+16], xmm1 ;; Save I3
xload xmm1, [srcreg+4*d1][rbx];; Load R2
xstore [dstreg+4*e1], xmm0 ;; Save R3
xload xmm0, [srcreg+2*d1][rbx];; Load R1
xstore [dstreg+2*e1], xmm4 ;; Save R2
xstore [dstreg+4*e1+48], xmm3 ;; Save I4
x7r_fft_mem [srcreg+48][rbx], [srcreg+2*d1+48][rbx], [srcreg+6*d1+32][rbx], [srcreg+6*d1+48][rbx], [dstreg+48], [dstreg+6*d1+32], 1
bump srcreg, srcinc
xstore [dstreg+2*e1+16], xmm4 ;; Save R2
xstore [dstreg+2*e1+48], xmm2 ;; Save I2
xstore [dstreg+6*e1], xmm0 ;; Save R3
xstore [dstreg+6*e1+16], xmm1 ;; Save I3
xstore [dstreg+6*e1+48], xmm3 ;; Save I4
bump dstreg, dstinc
ENDM
;; xmm0, xmm1, xmm2 are preloaded with m1, m2, m3
;; destr1 may be same address as m4 (in that case set m4_conflict to one)
;; destr4 may be same address as m6
x7r_fft_mem MACRO m4, m5, m6, m7, destr1, destr4, m4_conflict
xload xmm3, m7 ;; T1 = R7
addpd xmm3, xmm1 ;;1-4 T1 = R2+R7
xload xmm4, m6 ;; T2 = R6
addpd xmm4, xmm2 ;;3-6 T2 = R3+R6
xload xmm5, m4 ;; T3 = R4
addpd xmm5, m5 ;;5-8 T3 = R4+R5
xload xmm6, XMM_P623
mulpd xmm6, xmm3 ;;6-11 T1 = T1 * .623
addpd xmm3, xmm0 ;;7-10 R1+T1
xload xmm7, XMM_P623
mulpd xmm7, xmm4 ;;8-13 T2 = T2 * .623
addpd xmm4, xmm5 ;;9-12 T2+T3
mulpd xmm5, XMM_P623 ;;10-15 T3 = T3 * .623
addpd xmm3, xmm4 ;;14-17 R1+T1+T2+T3 (final R1)
xcopy xmm4, xmm0 ;; newR2 = R1
addpd xmm4, xmm6 ;;12-15 newR2 = R1 + T1
mulpd xmm6, XMM_M358 ;;13-18 T1 = T1 * (-.223/.623)
IF m4_conflict EQ 1
xstore XMM_TMP1, xmm3 ;; Save R1
ELSE
xstore destr1, xmm3 ;; Save R1
ENDIF
xcopy xmm3, xmm0 ;; newR4 = R1
addpd xmm0, xmm5 ;;16-19 newR3 = R1 + T3
mulpd xmm5, XMM_M358 ;;17-22 T3 = T3 * (-.223/.623)
addpd xmm3, xmm7 ;;14-17 newR4 = R1 + T2
mulpd xmm7, XMM_M358 ;;15-20 T2 = T2 * (-.223/.623)
addpd xmm0, xmm6 ;;20-23 newR3 = newR3 + T1
mulpd xmm6, XMM_P404 ;;21-26 T1 = T1 * (-.901/-.223)
addpd xmm3, xmm5 ;;24-27 newR4 = newR4 + T3
mulpd xmm5, XMM_P404 ;;25-30 T3 = T3 * (-.901/-.223)
addpd xmm4, xmm7 ;;22-25 newR2 = newR2 + T2
mulpd xmm7, XMM_P404 ;;23-28 T2 = T2 * (-.901/-.223)
addpd xmm3, xmm6 ;;30-33 newR4 = newR4 + T1 (final R4)
addpd xmm0, xmm7 ;;34-37 newR3 = newR3 + T2 (final R3)
addpd xmm4, xmm5 ;;36-39 newR2 = newR2 + T3 (final R2)
subpd xmm1, m7 ;;28-31 S1 = R2-R7
mulpd xmm1, XMM_P975 ;;33-38 S1 = S1 * .975
subpd xmm2, m6 ;;26-29 S2 = R3-R6
mulpd xmm2, XMM_P975 ;;31-36 S2 = S2 * .975
xstore destr4, xmm3 ;; Save R4
xload xmm3, m4 ;; S3 = R4
subpd xmm3, m5 ;;32-35 S3 = R4-R5
mulpd xmm3, XMM_P975 ;;37-42 S3 = S3 * .975
xload xmm5, XMM_P445 ;; (.434/.975)
mulpd xmm5, xmm1 ;;41-46 S1 = S1 * (.434/.975), newI3=S1
xload xmm6, XMM_P445 ;; (.434/.975)
mulpd xmm6, xmm2 ;;39-44 S2 = S2 * (.434/.975), newI2=S2
xload xmm7, XMM_P445 ;; (.434/.975)
mulpd xmm7, xmm3 ;;43-48 S3 = S3 * (.434/.975), newI4=S3
subpd xmm1, xmm6 ;;45-48 newI3 = newI3 - S2
mulpd xmm6, XMM_P180 ;;46-51 S2 = S2 * (.782/.434)
addpd xmm3, xmm5 ;;47-50 newI4 = newI4 + S1
mulpd xmm5, XMM_P180 ;;48-53 S1 = S1 * (.782/.434)
addpd xmm2, xmm7 ;;49-52 newI2 = newI2 + S3
mulpd xmm7, XMM_P180 ;;50-55 S3 = S3 * (.782/.434)
subpd xmm3, xmm6 ;;52-55 newI4 = newI4 - S2 (final I4)
addpd xmm2, xmm5 ;;54-57 newI2 = newI2 + S1 (final I2)
subpd xmm1, xmm7 ;;56-59 newI3 = newI3 - S3 (final I3)
IF m4_conflict EQ 1
xload xmm6, XMM_TMP1 ;; Reload final R1
xstore destr1, xmm6 ;; Save final R1
ENDIF
ENDM
x7r_fft MACRO r1, r2, r3, r4, r5, r6, r7, t1, memr1
xcopy t1, r2
subpd r2, r7 ;; R2-R7
addpd r7, t1 ;; T1 = R2+R7
xcopy t1, r3
subpd r3, r6 ;; R3-R6
addpd r6, t1 ;; T2 = R3+R6
xcopy t1, r4
subpd r4, r5 ;; R4-R5
addpd r5, t1 ;; T3 = R4+R5
xcopy t1, r1 ;; R1
addpd t1, r7 ;; R1+T1
addpd t1, r6 ;; R1+T1+T2
addpd t1, r5 ;; R1+T1+T2+T3 (final R1)
xstore memr1, t1
mulpd r7, XMM_P623 ;; T1 = T1 * .623