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cpuid.c
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cpuid.c
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/*----------------------------------------------------------------------
| Copyright 1995-2021 Mersenne Research, Inc. All rights reserved
| Author: George Woltman
| Email: [email protected]
|
| This file contains routines to determine the CPU type and speed.
+---------------------------------------------------------------------*/
/* Include files */
#include <stdlib.h>
#include <math.h>
#include <memory.h>
#include <string.h>
#ifdef _WIN32
#include "windows.h"
#endif
#if defined (__FreeBSD__) || defined (__APPLE__)
#include <sys/param.h>
#include <sys/sysctl.h>
#endif
#ifdef __linux__
#include <stdio.h>
#endif
#ifdef __OS2__
#define INCL_DOSPROFILE
#include <os2.h>
#endif
#if defined (__HAIKU__)
#include <unistd.h>
#endif
#if defined (__linux__) || defined (__FreeBSD__) || defined (__APPLE__) || defined (__HAIKU__)
#include <sys/time.h>
#endif
#include "cpuid.h"
#include "gwthread.h"
#include "gwutil.h"
#define safe_strcpy(d,s) memmove (d, s, strlen (s) + 1)
/* Global variables describing the CPU we are running on */
char CPU_BRAND[49] = "";
double CPU_SPEED = 0.0;
unsigned int CPU_FLAGS = 0;
unsigned int CPU_CORES = 1; /* Number CPU cores */
unsigned int CPU_HYPERTHREADS = 1; /* Number of virtual processors */
/* that each CPU core supports. */
/* Total number logical processors */
/* is CPU_CORES * CPU_HYPERTHREADS */
int CPU_L1_CACHE_SIZE = -1;
int CPU_L2_CACHE_SIZE = -1;
int CPU_L3_CACHE_SIZE = -1;
int CPU_L1_CACHE_LINE_SIZE = -1;
int CPU_L2_CACHE_LINE_SIZE = -1;
int CPU_L3_CACHE_LINE_SIZE = -1;
int CPU_L1_DATA_TLBS = -1;
int CPU_L2_DATA_TLBS = -1;
int CPU_L3_DATA_TLBS = -1;
int CPU_L1_SET_ASSOCIATIVE = -1;
int CPU_L2_SET_ASSOCIATIVE = -1;
int CPU_L3_SET_ASSOCIATIVE = -1;
unsigned int CPU_SIGNATURE = 0; /* Vendor-specific family number, */
/* model number, stepping ID, etc. */
int CPU_ARCHITECTURE = 0; /* Our attempt to derive the CPU */
/* architecture. */
/* Masm routines to burn up a specific number of clocks */
void one_hundred_thousand_clocks_help ();
void one_million_clocks_help ();
/* Routines to burn up a specific number of clocks */
void one_hundred_thousand_clocks (void)
{
/* The helper function times dependent ROR instructions which have a throughput of 1 clock on Intel and AMD. */
/* If a future chip, needs to call a different helper routine, we'd make that choice here. */
one_hundred_thousand_clocks_help ();
}
void one_million_clocks (void)
{
/* The helper function times dependent ROR instructions which have a throughput of 1 clock on Intel and AMD. */
/* If a future chip, needs to call a different helper routine, we'd make that choice here. */
one_million_clocks_help ();
}
/* Return the number of CPUs in the system */
unsigned int num_cpus (void)
{
#if defined (_WIN32)
SYSTEM_INFO sys;
GetSystemInfo (&sys);
return (sys.dwNumberOfProcessors);
#elif defined (__APPLE__) || defined (__FreeBSD__)
int mib[2];
int ncpus;
size_t len;
mib[0] = CTL_HW;
mib[1] = HW_NCPU;
len = sizeof (ncpus);
sysctl (mib, 2, &ncpus, &len, NULL, 0);
return (ncpus);
#elif defined (__linux__)
FILE *fd;
char buf[200];
int count;
count = 0;
fd = fopen ("/proc/cpuinfo", "r");
if (fd != NULL) {
while (fgets (buf, sizeof (buf), fd) != NULL) {
buf[9] = 0;
if (strcmp (buf, "processor") == 0) count++;
}
fclose (fd);
}
if (count == 0) count = 1;
return (count);
#elif defined (__HAIKU__)
int ncpus;
ncpus = sysconf(_SC_NPROCESSORS_CONF);
return (ncpus);
#else
return (1);
#endif
}
/* The MS 64-bit compiler does not allow inline assembly. Fortunately, any */
/* CPU capable of running x86-64 bit code can execute these instructions. */
#ifdef X86_64
int canExecInstruction (
unsigned long cpu_flag)
{
return (TRUE);
}
#else
/* Internal routines to see if CPU-specific instructions (RDTSC, CMOV */
/* SSE, SSE2) are supported. CPUID could report them as supported yet */
/* the OS might not support them. Use signals in non-MSVC compiles. */
#if !defined(_MSC_VER) && !defined(__WATCOMC__)
#include <setjmp.h>
#include <signal.h>
int boom;
jmp_buf env;
void sigboom_handler (int i)
{
boom = TRUE;
longjmp (env, 1);
}
int canExecInstruction (
unsigned long cpu_flag)
{
boom = FALSE;
(void) signal (SIGILL, sigboom_handler);
if (setjmp (env) == 0) {
switch (cpu_flag) {
case CPU_RDTSC: /* RDTSC */
__asm__ __volatile__ (".byte 0x0F\n .byte 0x31\n");
break;
case CPU_CMOV: /* CMOV */
__asm__ __volatile__ (".byte 0x0F\n .byte 0x42\n .byte 0xC0\n");
break;
/* WARNING: On Mac OS X 64-bit executable, executing this PADDB instruction will cause */
/* the next call to log in math.h to return NaN. Submitted bug to Apple: Bug ID# 6478193. */
case CPU_MMX: /* PADDB */
__asm__ __volatile__ (".byte 0x0F\n .byte 0xFC\n .byte 0xC0\n");
break;
case CPU_SSE: /* ORPS */
__asm__ __volatile__ (".byte 0x0F\n .byte 0x56\n .byte 0xC0\n");
break;
case CPU_SSE2: /* ADDPD */
__asm__ __volatile__ (".byte 0x66\n .byte 0x0F\n .byte 0x58\n .byte 0xC0\n");
break;
case CPU_PREFETCH: /* PREFETCHT1 */
__asm__ __volatile__ (".byte 0x0F\n .byte 0x18\n .byte 0x16\n");
break;
case CPU_3DNOW: /* PREFETCHW */
__asm__ __volatile__ (".byte 0x0F\n .byte 0x0D\n .byte 0x0E\n");
break;
}
}
(void) signal (SIGILL, SIG_DFL);
fpu_init ();
return (!boom);
}
#else
#include <excpt.h>
#ifdef __WATCOMC__
#define __asm _asm
#define __emit db
#endif
int canExecInstruction (
unsigned long cpu_flag)
{
int succeeded;
__try {
switch (cpu_flag) {
case CPU_RDTSC: /* RDTSC */
__asm __emit 0x0F
__asm __emit 0x31
break;
case CPU_CMOV: /* CMOV */
__asm __emit 0x0F
__asm __emit 0x42
__asm __emit 0xC0
break;
case CPU_MMX: /* PADDB */
__asm __emit 0x0F
__asm __emit 0xFC
__asm __emit 0xC0
break;
case CPU_SSE: /* ORPS */
__asm __emit 0x0F
__asm __emit 0x56
__asm __emit 0xC0
break;
case CPU_SSE2: /* ADDPD */
__asm __emit 0x66
__asm __emit 0x0F
__asm __emit 0x58
__asm __emit 0xC0
break;
case CPU_PREFETCH: /* PREFETCHT1 */
__asm __emit 0x0F
__asm __emit 0x18
__asm __emit 0x16
break;
case CPU_3DNOW: /* PREFETCHW */
__asm __emit 0x0F
__asm __emit 0x0D
__asm __emit 0x0E
break;
}
succeeded = TRUE;
}
__except (EXCEPTION_EXECUTE_HANDLER) {
succeeded = FALSE;
}
fpu_init ();
return (succeeded);
}
#endif
#endif
/* Busy loop to keep CPU cores occupied. Used sometimes to aid */
/* in measuring CPU speed. */
int end_busy_loop = FALSE;
void busy_loop (void *arg)
{
while (!end_busy_loop) one_million_clocks ();
}
/* Work with CPUID instruction to guess the cpu type and features */
/* See Intel's document AP-485 for using CPUID on Intel processors */
/* AMD and VIA have similar documents */
void guessCpuType (void)
{
struct cpuid_data reg;
unsigned int num_logical_processors;
unsigned long max_cpuid_value;
unsigned long max_extended_cpuid_value;
unsigned long extended_family, extended_model, type, family_code;
unsigned long model_number, stepping_id, brand_index;
unsigned long family, model, retry_count;
char vendor_id[13];
static char * BRAND_NAMES[] = { /* From Intel Ap-485 */
"", /* brand_index = 0 */
"Intel(R) Celeron(R) processor",
"Intel(R) Pentium(R) III processor",
"Intel(R) Pentium(R) III Xeon(TM) processor",
"Intel(R) Pentium(R) III processor",
"", /* brand_index = 5 */
"Mobile Intel(R) Pentium(R) III Processor - M",
"Mobile Intel(R) Celeron(R) processor",
"Intel(R) Pentium(R) 4 processor",
"Intel(R) Pentium(R) 4 processor",
"Intel(R) Celeron(R) processor",
"Intel(R) Xeon(TM) processor",
"Intel(R) Xeon(TM) Processor MP",
"", /* brand_index = 13 */
"Mobile Intel(R) Pentium(R) 4 Processor - M",
"Mobile Intel(R) Celeron(R) processor",
"", /* brand_index = 16 */
"Mobile Intel(R) processor",
"Mobile Intel(R) Celeron(R) M processor",
"Mobile Intel(R) Celeron(R) processor",
"Intel(R) Celeron(R) processor",
"Mobile Intel(R) processor",
"Intel(R) Pentium(R) M processor"
"Mobile Intel(R) Celeron(R) processor"
};
#define NUM_BRAND_NAMES (sizeof (BRAND_NAMES) / sizeof (char *))
/* Get the number of logical processors */
num_logical_processors = num_cpus ();
/* Set up default values for features we cannot determine with CPUID */
CPU_BRAND[0] = 0;
CPU_SPEED = 100.0;
CPU_FLAGS = 0;
CPU_CORES = 1;
CPU_HYPERTHREADS = 1;
CPU_L1_CACHE_SIZE = -1;
CPU_L2_CACHE_SIZE = -1;
CPU_L3_CACHE_SIZE = -1;
CPU_L1_CACHE_LINE_SIZE = -1;
CPU_L2_CACHE_LINE_SIZE = -1;
CPU_L3_CACHE_LINE_SIZE = -1;
CPU_L1_DATA_TLBS = -1;
CPU_L2_DATA_TLBS = -1;
CPU_L3_DATA_TLBS = -1;
CPU_SIGNATURE = 0;
/* If CPUID instruction is not supported, assume we have a 486 (not all */
/* 486 chips supported CPUID. The CPU might be something else, but that */
/* isn't particularly important. */
if (! isCpuidSupported ()) {
strcpy (CPU_BRAND, "CPUID not supported - 486 CPU assumed");
return;
}
/* Call CPUID with 0 argument. It returns how highest argument CPUID */
/* can accept as well as the vendor string */
Cpuid (0, ®);
max_cpuid_value = reg.EAX;
memcpy (vendor_id, ®.EBX, 4);
memcpy (vendor_id+4, ®.EDX, 4);
memcpy (vendor_id+8, ®.ECX, 4);
vendor_id[12] = 0;
/* So far all vendors have adopted Intel's definition of CPUID with 1 as an */
/* argument. Let's assume future vendors will do the same. CPUID returns */
/* the processor family, stepping, etc. It also returns the feature flags. */
if (max_cpuid_value >= 1) {
Cpuid (1, ®);
CPU_SIGNATURE = reg.EAX & 0x0FFF3FFF;
extended_family = (reg.EAX >> 20) & 0xFF;
extended_model = (reg.EAX >> 16) & 0xF;
type = (reg.EAX >> 12) & 0x3;
family_code = (reg.EAX >> 8) & 0xF;
model_number = (reg.EAX >> 4) & 0xF;
stepping_id = reg.EAX & 0xF;
brand_index = reg.EBX & 0xFF;
if ((reg.EDX >> 4) & 0x1 && canExecInstruction (CPU_RDTSC))
CPU_FLAGS |= CPU_RDTSC;
if ((reg.EDX >> 15) & 0x1 && canExecInstruction (CPU_CMOV))
CPU_FLAGS |= CPU_CMOV;
if ((reg.EDX >> 23) & 0x1 && canExecInstruction (CPU_MMX))
CPU_FLAGS |= CPU_MMX;
if ((reg.EDX >> 25) & 0x1 && canExecInstruction (CPU_PREFETCH))
CPU_FLAGS |= CPU_PREFETCH;
if ((reg.EDX >> 25) & 0x1 && canExecInstruction (CPU_SSE))
CPU_FLAGS |= CPU_SSE;
if ((reg.EDX >> 26) & 0x1 && canExecInstruction (CPU_SSE2))
CPU_FLAGS |= CPU_SSE2;
if ((reg.ECX >> 0) & 0x1)
CPU_FLAGS |= CPU_SSE3;
if ((reg.ECX >> 9) & 0x1)
CPU_FLAGS |= CPU_SSSE3;
if ((reg.ECX >> 19) & 0x1)
CPU_FLAGS |= CPU_SSE41;
if ((reg.ECX >> 20) & 0x1)
CPU_FLAGS |= CPU_SSE42;
/* If hardware supports AVX that doesn't mean the OS supports AVX. */
/* See if OS supports XGETBV, then see if OS supports AVX, FMA, and AVX-512. */
if ((reg.ECX >> 27) & 0x1) {
struct cpuid_data getbv_reg;
Xgetbv (0, &getbv_reg);
if (((reg.ECX >> 28) & 0x1) && ((getbv_reg.EAX & 6) == 6)) CPU_FLAGS |= CPU_AVX;
if (((reg.ECX >> 12) & 0x1) && (CPU_FLAGS & CPU_AVX)) CPU_FLAGS |= CPU_FMA3;
/* Get more feature flags. Specifically the AVX2, AVX512F, AVX512PF and PREFETCHWT1 flags. */
if (max_cpuid_value >= 7) {
reg.ECX = 0;
Cpuid (7, ®);
if (((reg.EBX >> 5) & 0x1) && (CPU_FLAGS & CPU_AVX)) CPU_FLAGS |= CPU_AVX2;
if (((reg.EBX >> 16) & 0x1) && ((getbv_reg.EAX & 0xE0) == 0xE0)) CPU_FLAGS |= CPU_AVX512F;
if (((reg.EBX >> 26) & 0x1) && (CPU_FLAGS & CPU_AVX512F)) CPU_FLAGS |= CPU_AVX512PF;
if (reg.ECX & 0x1) CPU_FLAGS |= CPU_PREFETCHWT1;
}
}
}
/* Call CPUID with 0x80000000 argument. It tells us how many extended CPU */
/* functions are supported. */
Cpuid (0x80000000, ®);
max_extended_cpuid_value = reg.EAX;
/* Get more feature flags. Specifically the PREFETCHW flag and the flag that says */
/* RDTSC counts independently of CPU clock ticks Intel did this so that RDTSC */
/* would keep accurate real time regardless of the CPU core speed controlled by SpeedStep. */
if (max_extended_cpuid_value >= 0x80000001) {
reg.ECX = 0;
Cpuid (0x80000001, ®);
if ((reg.ECX >> 8) & 0x1)
CPU_FLAGS |= CPU_PREFETCHW;
}
if (max_extended_cpuid_value >= 0x80000007) {
Cpuid (0x80000007, ®);
if ((reg.EDX >> 8) & 0x1)
CPU_FLAGS |= CPU_TSC_INVARIANT;
}
/* Two users on the Mersenne forums have reported their Core 2 machines */
/* are not getting the brand string right after a reboot. How strange. */
/* The only way I can see this happening is if CPUID returns the wrong */
/* max_extended_cpuid_value or an empty brand string. In any attempt to */
/* "fix" this, I'll retry getting the brand string several times. */
/* Lookup Intel errata AZ64 in Core 45 nm specification. */
for (retry_count = 0; retry_count < 100; retry_count++) {
/* Although not guaranteed, all vendors have standardized on putting the */
/* brand string (if supported) at cpuid calls 0x8000002, 0x80000003, and */
/* 0x80000004. We'll assume future vendors will do the same. */
if (max_extended_cpuid_value >= 0x80000004) {
Cpuid (0x80000002, ®);
memcpy (CPU_BRAND, ®.EAX, 4);
memcpy (CPU_BRAND+4, ®.EBX, 4);
memcpy (CPU_BRAND+8, ®.ECX, 4);
memcpy (CPU_BRAND+12, ®.EDX, 4);
Cpuid (0x80000003, ®);
memcpy (CPU_BRAND+16, ®.EAX, 4);
memcpy (CPU_BRAND+20, ®.EBX, 4);
memcpy (CPU_BRAND+24, ®.ECX, 4);
memcpy (CPU_BRAND+28, ®.EDX, 4);
Cpuid (0x80000004, ®);
memcpy (CPU_BRAND+32, ®.EAX, 4);
memcpy (CPU_BRAND+36, ®.EBX, 4);
memcpy (CPU_BRAND+40, ®.ECX, 4);
memcpy (CPU_BRAND+44, ®.EDX, 4);
CPU_BRAND[48] = 0;
while (CPU_BRAND[0] == ' ') safe_strcpy (CPU_BRAND, CPU_BRAND+1);
}
/* If we got the brand string, or this is a very old CPU that perhaps */
/* doesn't support the brand string, then break the retry loop. */
if (CPU_BRAND[0] || ! (CPU_FLAGS & CPU_SSE2)) break;
if (max_extended_cpuid_value < 0x80000004)
max_extended_cpuid_value = 0x80000004;
}
/*-------------------------------------------------------------------+
| Check for INTEL vendor string. Perform INTEL-specific operations. |
+-------------------------------------------------------------------*/
if (strcmp ((const char *) vendor_id, "GenuineIntel") == 0) {
/* Intel wants us to start paying attention to extended family */
/* and extended model numbers. The AP-485 document isn't clear whether */
/* this should always be done (the documentation) or just done for */
/* families 6 and 15 (the sample code). */
if (family_code == 15)
family = extended_family + family_code;
else
family = family_code;
if (family_code == 15 || family_code == 6)
model = (extended_model << 4) + model_number;
else
model = model_number;
/* According to "Intel 64 and IA-32 Architectures Optimization Reference */
/* Manual", only early Pentium 4's require TLB priming during prefetch. */
if (family_code == 15 && model_number <= 2)
CPU_FLAGS |= CPU_TLB_PRIMING;
/* Try to determine the CPU architecture. See https://en.wikichip.org/wiki/intel/cpuid#Family_15 */
if (! (CPU_FLAGS & CPU_SSE2))
CPU_ARCHITECTURE = CPU_ARCHITECTURE_PRE_SSE2;
else if ((family == 15 && model <= 4) ||
(family == 15 && model == 6))
CPU_ARCHITECTURE = CPU_ARCHITECTURE_PENTIUM_4;
else if ((family == 6 && model == 9) ||
(family == 6 && model == 13))
CPU_ARCHITECTURE = CPU_ARCHITECTURE_PENTIUM_M;
else if (family == 6 && model == 14)
CPU_ARCHITECTURE = CPU_ARCHITECTURE_CORE;
else if ((family == 6 && model == 15) ||
(family == 6 && model == 22) ||
(family == 6 && model == 23) ||
(family == 6 && model == 29)) // Xeon MP (based on Core 2 technology)
CPU_ARCHITECTURE = CPU_ARCHITECTURE_CORE_2;
else if ((family == 6 && model == 26) || // Core i7
(family == 6 && model == 30) || // Core i5/i7
(family == 6 && model == 46) || // Xeon MP (based on Core i7 technology)
(family == 6 && model == 47) || // Xeon MP (based on Sandy Bridge technology)
(family == 6 && model == 69) || // Xeon MP (based on Haswell technology)
(family == 6 && model == 44) || // Core i7 (based on Sandy Bridge technology)
(family == 6 && model == 37) || // Core i3, mobile i5/i7 (based on Sandy Bridge technology)
(family == 6 && model == 42) || // Core i7 (based on Sandy Bridge technology)
(family == 6 && model == 45) || // Core i7 (based on Sandy Bridge-E technology)
(family == 6 && model == 58) || // Core i7 (based on Ivy Bridge technology)
(family == 6 && model == 62) || // Core i7 (based on Ivy Bridge-E technology)
(family == 6 && model == 60) || // Core i7 (based on Haswell technology)
(family == 6 && model == 63) || // Core i7 (based on Haswell-E technology)
(family == 6 && model == 69) || // Core i7, mobile (based on Haswell technology)
(family == 6 && model == 70) || // Core i7 (based on Haswell technology)
(family == 6 && model == 61) || // Core i7 (based on Broadwell technology)
(family == 6 && model == 79) || // Core i7 (based on Broadwell-E technology)
(family == 6 && model == 71) || // Core i7, mobile (based on Broadwell technology)
(family == 6 && model == 85) || // Core i9 (based on Skylake-X technology)
(family == 6 && model == 86) || // Core i7, mobile (based on Broadwell technology)
(family == 6 && model == 94) || // Core i7 (based on Skylake technology)
(family == 6 && model == 142) || // Core i7, (based on Kaby Lake technology)
(family == 6 && model == 158) || // Core i7, mobile (based on Coffee Lake technology)
(family == 6 && model == 168) || // Core i7, (based on Coffee Lake technology)
(family == 6 && model == 78) || // Core i3/i5/i7, mobile (based on Skylake technology)
(family == 6 && model == 102) || // Core i3/i5/i7, Cannon Lake
(family == 6 && model == 165) || // Core i3/i5/i7, Comet Lake
(family == 6 && model == 106) || // Core i3/i5/i7, Ice Lake
(family == 6 && model == 108) || // Core i3/i5/i7, Ice Lake
(family == 6 && model == 125) || // Core i3/i5/i7, Ice Lake
(family == 6 && model == 126) || // Core i3/i5/i7, Ice Lake
(family == 6 && model == 143) || // Core i3/i5/i7, Sapphire Rapids
(family == 6 && model == 140) || // Core i3/i5/i7, Tiger Lake
(family == 6 && model == 141) || // Core i3/i5/i7, Rocket Lake
(family == 6 && model == 167) || // Core i3/i5/i7, Tiger Lake
(family == 6 && model == 154) || // Core i3/i5/i7, Alder Lake
(family == 6 && model == 151)) // Core i3/i5/i7, Alder Lake
CPU_ARCHITECTURE = CPU_ARCHITECTURE_CORE_I7;
else if ((family == 6 && model == 28) ||
(family == 6 && model == 38) ||
(family == 6 && model == 39) ||
(family == 6 && model == 53) ||
(family == 6 && model == 54) ||
(family == 6 && model == 55) ||
(family == 6 && model == 74) || // Silvermont
(family == 6 && model == 77) ||
(family == 6 && model == 90) ||
(family == 6 && model == 93) ||
(family == 6 && model == 76) || // Airmont
(family == 6 && model == 92) || // Goldmont
(family == 6 && model == 95) ||
(family == 6 && model == 122) || // Goldmont+
(family == 6 && model == 134) || // Tremont
(family == 6 && model == 138) ||
(family == 6 && model == 150) ||
(family == 6 && model == 156))
CPU_ARCHITECTURE = CPU_ARCHITECTURE_ATOM;
else if ((family == 6 && model == 87) || // Knight's Landing
(family == 6 && model == 133)) // Knight's Mill
CPU_ARCHITECTURE = CPU_ARCHITECTURE_PHI;
else
CPU_ARCHITECTURE = CPU_ARCHITECTURE_INTEL_OTHER;
/* Try to determine if hyperthreading is supported. I think this code */
/* only tells us if the hardware supports hyperthreading. If the feature */
/* is turned off in the BIOS, we don't detect this. UPDATE: Detect some */
/* of these situations, by comparing number of cores to number of logical */
/* processors. This test fails if the machine has multiple physical CPUs. */
/* Nfortino has suggested using the new x2apic code below. It might correct */
/* some of the rare problems we were seeing on Core i7 machines. */
/* Determine if we should use leaf 11 topology enumeration. */
/* Otherwise, use leaf 1 + leaf 4 */
if (max_cpuid_value >= 11) {
reg.ECX = 0;
Cpuid (11, ®);
}
if (max_cpuid_value >= 11 && reg.EBX != 0) {
unsigned int i, cores;
CPU_HYPERTHREADS = reg.EBX & 0xFFFF;
for (i = 1; i < 5; i++) {
reg.ECX = i;
Cpuid (11, ®);
if ((reg.EBX & 0xFFFF) == 0) break;
cores = (reg.EBX & 0xFFFF) / CPU_HYPERTHREADS;
}
if (num_logical_processors <= cores) CPU_HYPERTHREADS = 1;
} else if (max_cpuid_value >= 1) {
Cpuid (1, ®);
if ((reg.EDX >> 28) & 0x1) {
CPU_HYPERTHREADS = (reg.EBX >> 16) & 0xFF;
if (CPU_HYPERTHREADS <= 1) CPU_HYPERTHREADS = 1;
else if (max_cpuid_value >= 4) {
unsigned int cores;
reg.ECX = 0;
Cpuid (4, ®);
cores = (reg.EAX >> 26) + 1;
CPU_HYPERTHREADS /= cores;
if (CPU_HYPERTHREADS < 2) CPU_HYPERTHREADS = 2;
if (num_logical_processors <= cores) CPU_HYPERTHREADS = 1;
}
else CPU_HYPERTHREADS = 2;
}
}
/* Call CPUID with 2 argument. It returns the cache size and structure */
/* in a series of 8-bit descriptors */
if (max_cpuid_value >= 2) {
Cpuid (2, ®);
if ((reg.EAX & 0xFF) > 0) {
unsigned int descriptors[15];
int i, count;
count = 0;
if (! (reg.EAX & 0x80000000)) {
descriptors[count++] = (reg.EAX >> 24) & 0xFF;
descriptors[count++] = (reg.EAX >> 16) & 0xFF;
descriptors[count++] = (reg.EAX >> 8) & 0xFF;
}
if (! (reg.EBX & 0x80000000)) {
descriptors[count++] = (reg.EBX >> 24) & 0xFF;
descriptors[count++] = (reg.EBX >> 16) & 0xFF;
descriptors[count++] = (reg.EBX >> 8) & 0xFF;
descriptors[count++] = reg.EBX & 0xFF;
}
if (! (reg.ECX & 0x80000000)) {
descriptors[count++] = (reg.ECX >> 24) & 0xFF;
descriptors[count++] = (reg.ECX >> 16) & 0xFF;
descriptors[count++] = (reg.ECX >> 8) & 0xFF;
descriptors[count++] = reg.ECX & 0xFF;
}
if (! (reg.EDX & 0x80000000)) {
descriptors[count++] = (reg.EDX >> 24) & 0xFF;
descriptors[count++] = (reg.EDX >> 16) & 0xFF;
descriptors[count++] = (reg.EDX >> 8) & 0xFF;
descriptors[count++] = reg.EDX & 0xFF;
}
for (i = 0; i < count; i++) {
switch (descriptors[i]) {
case 0x03:
CPU_L2_DATA_TLBS = 64;
break;
case 0x0A:
CPU_L1_CACHE_SIZE = 8;
CPU_L1_CACHE_LINE_SIZE = 32;
CPU_L1_SET_ASSOCIATIVE = 2;
break;
case 0x0C:
CPU_L1_CACHE_SIZE = 16;
CPU_L1_CACHE_LINE_SIZE = 32;
CPU_L1_SET_ASSOCIATIVE = 4;
break;
case 0x0D:
CPU_L1_CACHE_SIZE = 16;
CPU_L1_CACHE_LINE_SIZE = 64;
CPU_L1_SET_ASSOCIATIVE = 4;
break;
case 0x0E:
CPU_L1_CACHE_SIZE = 24;
CPU_L1_CACHE_LINE_SIZE = 64;
CPU_L1_SET_ASSOCIATIVE = 6;
break;
case 0x21:
CPU_L2_CACHE_SIZE = 256;
CPU_L2_CACHE_LINE_SIZE = 64;
CPU_L2_SET_ASSOCIATIVE = 8;
break;
case 0x22:
CPU_L3_CACHE_SIZE = 512;
CPU_L3_CACHE_LINE_SIZE = 64;
CPU_L3_SET_ASSOCIATIVE = 4;
break;
case 0x23:
CPU_L3_CACHE_SIZE = 1024;
CPU_L3_CACHE_LINE_SIZE = 64;
CPU_L3_SET_ASSOCIATIVE = 8;
break;
case 0x25:
CPU_L3_CACHE_SIZE = 2048;
CPU_L3_CACHE_LINE_SIZE = 64;
CPU_L3_SET_ASSOCIATIVE = 8;
break;
case 0x29:
CPU_L3_CACHE_SIZE = 4096;
CPU_L3_CACHE_LINE_SIZE = 64;
CPU_L3_SET_ASSOCIATIVE = 8;
break;
case 0x2C:
CPU_L1_CACHE_SIZE = 32;
CPU_L1_CACHE_LINE_SIZE = 64;
CPU_L1_SET_ASSOCIATIVE = 8;
break;
case 0x39:
CPU_L2_CACHE_SIZE = 128;
CPU_L2_CACHE_LINE_SIZE = 128;
CPU_L2_SET_ASSOCIATIVE = 4;
break;
case 0x3A:
CPU_L2_CACHE_SIZE = 192;
CPU_L2_CACHE_LINE_SIZE = 128;
CPU_L2_SET_ASSOCIATIVE = 6;
break;
case 0x3B:
CPU_L2_CACHE_SIZE = 128;
CPU_L2_CACHE_LINE_SIZE = 128;
CPU_L2_SET_ASSOCIATIVE = 2;
break;
case 0x3C:
CPU_L2_CACHE_SIZE = 256;
CPU_L2_CACHE_LINE_SIZE = 128;
CPU_L2_SET_ASSOCIATIVE = 4;
break;
case 0x3D:
CPU_L2_CACHE_SIZE = 384;
CPU_L2_CACHE_LINE_SIZE = 128;
CPU_L2_SET_ASSOCIATIVE = 6;
break;
case 0x3E:
CPU_L2_CACHE_SIZE = 512;
CPU_L2_CACHE_LINE_SIZE = 128;
CPU_L2_SET_ASSOCIATIVE = 6;
break;
case 0x40:
if (family == 15) {
/* no L3 cache */
} else {
CPU_L2_CACHE_SIZE = 0;
}
break;
case 0x41:
CPU_L2_CACHE_SIZE = 128;
CPU_L2_CACHE_LINE_SIZE = 32;
CPU_L2_SET_ASSOCIATIVE = 4;
break;
case 0x42:
CPU_L2_CACHE_SIZE = 256;
CPU_L2_CACHE_LINE_SIZE = 32;
CPU_L2_SET_ASSOCIATIVE = 4;
break;
case 0x43:
CPU_L2_CACHE_SIZE = 512;
CPU_L2_CACHE_LINE_SIZE = 32;
CPU_L2_SET_ASSOCIATIVE = 4;
break;
case 0x44:
CPU_L2_CACHE_SIZE = 1024;
CPU_L2_CACHE_LINE_SIZE = 32;
CPU_L2_SET_ASSOCIATIVE = 4;
break;
case 0x45:
CPU_L2_CACHE_SIZE = 2048;
CPU_L2_CACHE_LINE_SIZE = 32;
CPU_L2_SET_ASSOCIATIVE = 4;
break;
case 0x46:
CPU_L3_CACHE_SIZE = 4096;
CPU_L3_CACHE_LINE_SIZE = 64;
CPU_L3_SET_ASSOCIATIVE = 4;
break;
case 0x47:
CPU_L3_CACHE_SIZE = 8192;
CPU_L3_CACHE_LINE_SIZE = 64;
CPU_L3_SET_ASSOCIATIVE = 8;
break;
case 0x48:
CPU_L2_CACHE_SIZE = 3072;
CPU_L2_CACHE_LINE_SIZE = 64;
CPU_L2_SET_ASSOCIATIVE = 12;
break;
case 0x49:
if (family == 0x0F && model == 0x06) {
CPU_L3_CACHE_SIZE = 4096;
CPU_L3_CACHE_LINE_SIZE = 64;
CPU_L3_SET_ASSOCIATIVE = 16;
} else {
CPU_L2_CACHE_SIZE = 4096;
CPU_L2_CACHE_LINE_SIZE = 64;
CPU_L2_SET_ASSOCIATIVE = 16;
}
break;
case 0x4A:
CPU_L3_CACHE_SIZE = 6144;
CPU_L3_CACHE_LINE_SIZE = 64;
CPU_L3_SET_ASSOCIATIVE = 12;
break;
case 0x4B:
CPU_L3_CACHE_SIZE = 8192;
CPU_L3_CACHE_LINE_SIZE = 64;
CPU_L3_SET_ASSOCIATIVE = 16;
break;
case 0x4C:
CPU_L3_CACHE_SIZE = 12288;
CPU_L3_CACHE_LINE_SIZE = 64;
CPU_L3_SET_ASSOCIATIVE = 12;
break;
case 0x4D:
CPU_L3_CACHE_SIZE = 16384;
CPU_L3_CACHE_LINE_SIZE = 64;
CPU_L3_SET_ASSOCIATIVE = 16;
break;
case 0x4E:
CPU_L2_CACHE_SIZE = 6144;
CPU_L2_CACHE_LINE_SIZE = 64;
CPU_L2_SET_ASSOCIATIVE = 24;
break;
case 0x5B:
case 0xBA:
CPU_L2_DATA_TLBS = 64;
break;
case 0x5C:
case 0xB3:
CPU_L2_DATA_TLBS = 128;
break;
case 0x5D:
case 0xB4:
CPU_L2_DATA_TLBS = 256;
break;
case 0x60:
CPU_L1_CACHE_SIZE = 16;
CPU_L1_CACHE_LINE_SIZE = 64;
CPU_L1_SET_ASSOCIATIVE = 8;
break;
case 0x66:
CPU_L1_CACHE_SIZE = 8;
CPU_L1_CACHE_LINE_SIZE = 64;
CPU_L1_SET_ASSOCIATIVE = 4;
break;
case 0x67:
CPU_L1_CACHE_SIZE = 16;
CPU_L1_CACHE_LINE_SIZE = 64;
CPU_L1_SET_ASSOCIATIVE = 4;
break;
case 0x68:
CPU_L1_CACHE_SIZE = 32;
CPU_L1_CACHE_LINE_SIZE = 64;
CPU_L1_SET_ASSOCIATIVE = 4;
break;
case 0x78:
CPU_L2_CACHE_SIZE = 1024;
CPU_L2_CACHE_LINE_SIZE = 64;
CPU_L2_SET_ASSOCIATIVE = 4;
break;
case 0x79:
CPU_L2_CACHE_SIZE = 128;
CPU_L2_CACHE_LINE_SIZE = 128;
CPU_L2_SET_ASSOCIATIVE = 8;
break;
case 0x7A:
CPU_L2_CACHE_SIZE = 256;
CPU_L2_CACHE_LINE_SIZE = 128;
CPU_L2_SET_ASSOCIATIVE = 8;
break;
case 0x7B:
CPU_L2_CACHE_SIZE = 512;
CPU_L2_CACHE_LINE_SIZE = 128;
CPU_L2_SET_ASSOCIATIVE = 8;
break;
case 0x7C:
CPU_L2_CACHE_SIZE = 1024;
CPU_L2_CACHE_LINE_SIZE = 128;
CPU_L2_SET_ASSOCIATIVE = 8;
break;
case 0x7D:
CPU_L2_CACHE_SIZE = 2048;
CPU_L2_CACHE_LINE_SIZE = 64;
CPU_L2_SET_ASSOCIATIVE = 8;
break;
case 0x7F:
CPU_L2_CACHE_SIZE = 512;
CPU_L2_CACHE_LINE_SIZE = 64;
CPU_L2_SET_ASSOCIATIVE = 2;
break;
case 0x80:
CPU_L2_CACHE_SIZE = 512;
CPU_L2_CACHE_LINE_SIZE = 64;
CPU_L2_SET_ASSOCIATIVE = 8;
break;
case 0x82:
CPU_L2_CACHE_SIZE = 256;
CPU_L2_CACHE_LINE_SIZE = 32;
CPU_L2_SET_ASSOCIATIVE = 8;
break;
case 0x83:
CPU_L2_CACHE_SIZE = 512;
CPU_L2_CACHE_LINE_SIZE = 32;
CPU_L2_SET_ASSOCIATIVE = 8;
break;
case 0x84:
CPU_L2_CACHE_SIZE = 1024;
CPU_L2_CACHE_LINE_SIZE = 32;
CPU_L2_SET_ASSOCIATIVE = 8;
break;
case 0x85:
CPU_L2_CACHE_SIZE = 2048;
CPU_L2_CACHE_LINE_SIZE = 32;
CPU_L2_SET_ASSOCIATIVE = 8;
break;
case 0x86:
CPU_L2_CACHE_SIZE = 512;
CPU_L2_CACHE_LINE_SIZE = 64;
CPU_L2_SET_ASSOCIATIVE = 4;
break;
case 0x87:
CPU_L2_CACHE_SIZE = 1024;
CPU_L2_CACHE_LINE_SIZE = 64;
CPU_L2_SET_ASSOCIATIVE = 8;
break;
case 0xD0:
CPU_L3_CACHE_SIZE = 512;
CPU_L3_CACHE_LINE_SIZE = 64;
CPU_L3_SET_ASSOCIATIVE = 4;
break;
case 0xD1:
CPU_L3_CACHE_SIZE = 1024;
CPU_L3_CACHE_LINE_SIZE = 64;
CPU_L3_SET_ASSOCIATIVE = 4;
break;
case 0xD2:
CPU_L3_CACHE_SIZE = 2048;
CPU_L3_CACHE_LINE_SIZE = 64;
CPU_L3_SET_ASSOCIATIVE = 4;
break;
case 0xD6:
CPU_L3_CACHE_SIZE = 1024;
CPU_L3_CACHE_LINE_SIZE = 64;
CPU_L3_SET_ASSOCIATIVE = 8;
break;
case 0xD7:
CPU_L3_CACHE_SIZE = 2048;
CPU_L3_CACHE_LINE_SIZE = 64;
CPU_L3_SET_ASSOCIATIVE = 8;
break;
case 0xD8:
CPU_L3_CACHE_SIZE = 4096;
CPU_L3_CACHE_LINE_SIZE = 64;
CPU_L3_SET_ASSOCIATIVE = 8;
break;
case 0xDC:
CPU_L3_CACHE_SIZE = 1536;
CPU_L3_CACHE_LINE_SIZE = 64;
CPU_L3_SET_ASSOCIATIVE = 12;
break;
case 0xDD:
CPU_L3_CACHE_SIZE = 3072;
CPU_L3_CACHE_LINE_SIZE = 64;
CPU_L3_SET_ASSOCIATIVE = 12;
break;
case 0xDE:
CPU_L3_CACHE_SIZE = 6144;
CPU_L3_CACHE_LINE_SIZE = 64;
CPU_L3_SET_ASSOCIATIVE = 12;
break;
case 0xE2:
CPU_L3_CACHE_SIZE = 2048;
CPU_L3_CACHE_LINE_SIZE = 64;
CPU_L3_SET_ASSOCIATIVE = 16;
break;
case 0xE3:
CPU_L3_CACHE_SIZE = 4096;
CPU_L3_CACHE_LINE_SIZE = 64;
CPU_L3_SET_ASSOCIATIVE = 16;
break;
case 0xE4:
CPU_L3_CACHE_SIZE = 8192;
CPU_L3_CACHE_LINE_SIZE = 64;
CPU_L3_SET_ASSOCIATIVE = 16;
break;
case 0xEA:
CPU_L3_CACHE_SIZE = 12288;
CPU_L3_CACHE_LINE_SIZE = 64;
CPU_L3_SET_ASSOCIATIVE = 24;
break;
case 0xEB:
CPU_L3_CACHE_SIZE = 18432;
CPU_L3_CACHE_LINE_SIZE = 64;
CPU_L3_SET_ASSOCIATIVE = 24;
break;
case 0xEC:
CPU_L3_CACHE_SIZE = 24576;
CPU_L3_CACHE_LINE_SIZE = 64;