diff --git a/.gitignore b/.gitignore index 4c9346e..7d07c4e 100644 --- a/.gitignore +++ b/.gitignore @@ -1,4 +1,13 @@ -build +*.so +*.cmake +Makefile +CMakeFiles +CMakeCache.txt +tests/*_test +build/ .cproject .project -.settings +.settings/ +.vscode/ +.gdbinit +.cache diff --git a/CMakeLists.txt b/CMakeLists.txt index c0f21c8..d6358bc 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -7,6 +7,7 @@ project(synapse_core) set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -std=c++11 -Wall -Werror -Wno-sign-compare -fno-strict-aliasing") set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -pipe") +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) if (CMAKE_CXX_COMPILER_VERSION VERSION_LESS 8.0) set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-attributes") diff --git a/build.sh b/build.sh index 005bf77..e4412f9 100755 --- a/build.sh +++ b/build.sh @@ -23,8 +23,19 @@ set -e # then you need to define EXTRA_CMAKE_FLAGS as: # EXTRA_CMAKE_FLAGS=-DDRIVER_INCLUDE_PATH=$HOME/habanalabs/include/uapi +SECONDS=0; SRCDIR=`dirname $0` BUILDDIR="$SRCDIR/build" +build_type="Release" + +while [ -n "$1" ]; do + case $1 in + -debug) + build_type="Debug" + ;; + esac; + shift; +done if [ -d $BUILDDIR ]; then rm -rf $BUILDDIR @@ -41,5 +52,8 @@ fi cd "$BUILDDIR" -$CMAKE -DCMAKE_BUILD_TYPE="Release" ${EXTRA_CMAKE_FLAGS:-} .. +$CMAKE -DCMAKE_BUILD_TYPE=${build_type} ${EXTRA_CMAKE_FLAGS:-} .. make -j8 + +printf "\nElapsed time: %02u:%02u:%02u \n\n" $(($SECONDS / 3600)) $((($SECONDS / 60) % 60)) $(($SECONDS % 60)); + diff --git a/external_includes/SpecialFuncCoefficients.h b/external_includes/SpecialFuncCoefficients.h index 1e7cb22..9c01f4c 100644 --- a/external_includes/SpecialFuncCoefficients.h +++ b/external_includes/SpecialFuncCoefficients.h @@ -15,3 +15,10 @@ namespace tpc_gaudi { uint8_t *getLUTStartAddressFromFuncID(uint32_t funcID, uint8_t* baseAddr); uint32_t getCoefAddrFromOffset(uint8_t offset, bool isLOOKUP, uint32_t elementSize); } + +namespace tpc_gaudi2 +{ +void buildSpecialFunctionCoefficients(std::vector>& specialFunctionCoefficients); +uint8_t* getLUTStartAddressFromFuncID(uint32_t funcID, uint8_t* baseAddr); +uint32_t getCoefAddrFromOffset(uint8_t offset, bool isLOOKUP, uint32_t elementSize); +} // namespace tpc_gaudi2 diff --git a/external_includes/TensorDescriptor.h b/external_includes/TensorDescriptor.h index 2fbc10e..6bacda4 100644 --- a/external_includes/TensorDescriptor.h +++ b/external_includes/TensorDescriptor.h @@ -7,6 +7,7 @@ #pragma once +#include "synapse_common_types.h" #include #include @@ -42,7 +43,7 @@ DEF_PACK( typedef struct _TensorDescriptorBase TensorDescriptorBase; -struct TensorDescriptorGaudi : public TensorDescriptorBase +struct TensorDescriptor : public TensorDescriptorBase { /* for Gaudi: TENSOR_0_BASE_ADDR_LOW +0x00 32 0 Read/Write bits 31 to 0 of the base address no no no @@ -84,20 +85,40 @@ typedef enum TensorDataType_ uint32_t gen2_TensorDescriptorElementSizeType(uint32_t configuration); uint32_t gen2_TensorDescriptorValidDimMask(uint32_t configuration); uint32_t gen2_TensorDescriptorLastDim(uint32_t configuration); +uint32_t gen6_TensorDescriptorElementSizeType(uint32_t configuration); +uint32_t gen6_TensorDescriptorValidDimMask(uint32_t configuration); +uint32_t gen6_TensorDescriptorLastDim(uint32_t configuration); namespace tpc_gaudi { inline uint32_t get_TensorDescriptorLastDim(uint32_t configuration) { return gen2_TensorDescriptorLastDim(configuration); } - inline uint32_t get_TensorDescriptorElementSizeType(uint32_t configuration) - { - return gen2_TensorDescriptorElementSizeType(configuration); + inline uint32_t get_TensorDescriptorElementSizeType(uint32_t configuration) + { + return gen2_TensorDescriptorElementSizeType(configuration); } inline uint32_t get_TensorDescriptorValidDimMask(uint32_t configuration) - { + { return gen2_TensorDescriptorValidDimMask(configuration); } uint32_t TensorDescriptorConfiguration(uint32_t dataType, uint32_t validDimMask, uint32_t lastDim, uint32_t rmwSel, uint32_t rmwOp); uint32_t get_ElementSizeInBytesFromDataType(TensorDataType DataType); } + +namespace tpc_gaudi2 { + inline uint32_t get_TensorDescriptorLastDim(uint32_t configuration) + { + return gen6_TensorDescriptorLastDim(configuration); + } + inline uint32_t get_TensorDescriptorElementSizeType(uint32_t configuration) + { + return gen6_TensorDescriptorElementSizeType(configuration); + } + inline uint32_t get_TensorDescriptorValidDimMask(uint32_t configuration) + { + return gen6_TensorDescriptorValidDimMask(configuration); + } + uint32_t TensorDescriptorConfiguration(uint32_t dataType, uint32_t validDimMask, uint32_t lastDim, uint32_t rmwSel, uint32_t rmwOp); + uint32_t get_ElementSizeInBytesFromDataType(TensorDataType DataType); +} diff --git a/external_includes/SpecialFuncCoefficients_defGen2.h b/external_includes/gaudi/SpecialFuncCoefficients_defGen2.h similarity index 100% rename from external_includes/SpecialFuncCoefficients_defGen2.h rename to external_includes/gaudi/SpecialFuncCoefficients_defGen2.h diff --git a/external_includes/TPC_IO_REG_SPACE_GEN2.h b/external_includes/gaudi/TPC_IO_REG_SPACE_GEN2.h similarity index 100% rename from external_includes/TPC_IO_REG_SPACE_GEN2.h rename to external_includes/gaudi/TPC_IO_REG_SPACE_GEN2.h diff --git a/external_includes/asic_reg/gaudi_blocks.h b/external_includes/gaudi/asic_reg/gaudi_blocks.h similarity index 100% rename from external_includes/asic_reg/gaudi_blocks.h rename to external_includes/gaudi/asic_reg/gaudi_blocks.h diff --git a/external_includes/asic_reg_structs/dma_core_regs.h b/external_includes/gaudi/asic_reg_structs/dma_core_regs.h similarity index 99% rename from external_includes/asic_reg_structs/dma_core_regs.h rename to external_includes/gaudi/asic_reg_structs/dma_core_regs.h index e8710a8..d81ef01 100644 --- a/external_includes/asic_reg_structs/dma_core_regs.h +++ b/external_includes/gaudi/asic_reg_structs/dma_core_regs.h @@ -9,7 +9,8 @@ #include #pragma pack(push, 1) - +namespace gaudi +{ namespace dma_core { /* CFG_0 @@ -1039,6 +1040,6 @@ const offsetVal block_dma_core_defaults[] { 0x130 , 0x1 , 1 }, // wr_awuser_31_11 { 0x230 , 0x178 , 1 }, // dbg_sts }; - +} // namespace gaudi #pragma pack(pop) #endif /* ASIC_REG_STRUCTS_DMA_CORE_H_ */ diff --git a/external_includes/asic_reg_structs/gaudi_types.h b/external_includes/gaudi/asic_reg_structs/gaudi_types.h similarity index 91% rename from external_includes/asic_reg_structs/gaudi_types.h rename to external_includes/gaudi/asic_reg_structs/gaudi_types.h index d6eb51b..9c556b0 100644 --- a/external_includes/asic_reg_structs/gaudi_types.h +++ b/external_includes/gaudi/asic_reg_structs/gaudi_types.h @@ -10,6 +10,8 @@ #pragma pack(push, 1) +namespace gaudi +{ struct offsetVal { uint32_t offset; @@ -17,5 +19,6 @@ struct offsetVal int copies; }; +} // namespace gaudi #pragma pack(pop) #endif /* ASIC_REG_STRUCTS_GAUDI_TYPES_H_ */ diff --git a/external_includes/asic_reg_structs/qman_regs.h b/external_includes/gaudi/asic_reg_structs/qman_regs.h similarity index 99% rename from external_includes/asic_reg_structs/qman_regs.h rename to external_includes/gaudi/asic_reg_structs/qman_regs.h index e791e81..6b99d7b 100644 --- a/external_includes/asic_reg_structs/qman_regs.h +++ b/external_includes/gaudi/asic_reg_structs/qman_regs.h @@ -9,7 +9,8 @@ #include #pragma pack(push, 1) - +namespace gaudi +{ namespace qman { /* GLBL_CFG0 @@ -1954,7 +1955,10 @@ struct block_qman { uint32_t _pad3292[9]; struct qman::reg_glbl_mem_init_busy glbl_mem_init_busy; }; +} // namespace gaudi #include "gaudi_types.h" +namespace gaudi +{ const offsetVal block_qman_defaults[] { // offset // value @@ -1986,5 +1990,6 @@ const offsetVal block_qman_defaults[] { 0xc84 , 0x2000 , 1 }, // local_range_size }; +} //namespace gaudi #pragma pack(pop) #endif /* ASIC_REG_STRUCTS_QMAN_H_ */ diff --git a/external_includes/asic_reg_structs/sob_glbl_regs.h b/external_includes/gaudi/asic_reg_structs/sob_glbl_regs.h similarity index 96% rename from external_includes/asic_reg_structs/sob_glbl_regs.h rename to external_includes/gaudi/asic_reg_structs/sob_glbl_regs.h index 9fc9ba6..26e7691 100644 --- a/external_includes/asic_reg_structs/sob_glbl_regs.h +++ b/external_includes/gaudi/asic_reg_structs/sob_glbl_regs.h @@ -9,7 +9,8 @@ #include #pragma pack(push, 1) - +namespace gaudi +{ namespace sob_glbl { /* SM_SEI_MASK @@ -50,5 +51,6 @@ struct block_sob_glbl { struct sob_glbl::reg_sm_sei_cause sm_sei_cause; }; +} // namespace gaudi #pragma pack(pop) #endif /* ASIC_REG_STRUCTS_SOB_GLBL_H_ */ diff --git a/external_includes/asic_reg_structs/sob_objs_regs.h b/external_includes/gaudi/asic_reg_structs/sob_objs_regs.h similarity index 98% rename from external_includes/asic_reg_structs/sob_objs_regs.h rename to external_includes/gaudi/asic_reg_structs/sob_objs_regs.h index 591e659..600a125 100644 --- a/external_includes/asic_reg_structs/sob_objs_regs.h +++ b/external_includes/gaudi/asic_reg_structs/sob_objs_regs.h @@ -9,7 +9,8 @@ #include #pragma pack(push, 1) - +namespace gaudi +{ namespace sob_objs { /* SM_SEC @@ -127,5 +128,6 @@ struct block_sob_objs { struct sob_objs::reg_sm_sec sm_sec[256]; }; +} // namespace gaudi #pragma pack(pop) #endif /* ASIC_REG_STRUCTS_SOB_OBJS_H_ */ diff --git a/external_includes/asic_reg_structs/sync_mngr_regs.h b/external_includes/gaudi/asic_reg_structs/sync_mngr_regs.h similarity index 93% rename from external_includes/asic_reg_structs/sync_mngr_regs.h rename to external_includes/gaudi/asic_reg_structs/sync_mngr_regs.h index f09cf41..6fb9c00 100644 --- a/external_includes/asic_reg_structs/sync_mngr_regs.h +++ b/external_includes/gaudi/asic_reg_structs/sync_mngr_regs.h @@ -18,11 +18,14 @@ namespace sync_mngr { /* SYNC_MNGR block */ +namespace gaudi +{ struct block_sync_mngr { struct block_sob_glbl sync_mngr_glbl; uint32_t _pad8[1022]; struct block_sob_objs sync_mngr_objs; }; +} // namespace gaudi #pragma pack(pop) #endif /* ASIC_REG_STRUCTS_SYNC_MNGR_H_ */ diff --git a/external_includes/asic_reg_structs/sync_object_regs.h b/external_includes/gaudi/asic_reg_structs/sync_object_regs.h similarity index 96% rename from external_includes/asic_reg_structs/sync_object_regs.h rename to external_includes/gaudi/asic_reg_structs/sync_object_regs.h index 94a8b09..ca7cd42 100644 --- a/external_includes/asic_reg_structs/sync_object_regs.h +++ b/external_includes/gaudi/asic_reg_structs/sync_object_regs.h @@ -9,7 +9,8 @@ #include #pragma pack(push, 1) - +namespace gaudi +{ namespace sync_object { /* MESSAGE @@ -47,5 +48,6 @@ struct block_sync_object { struct sync_object::reg_addr addr; }; +} //namespace gaudi #pragma pack(pop) #endif /* ASIC_REG_STRUCTS_SYNC_OBJECT_H_ */ diff --git a/external_includes/asic_reg_structs/tpc_non_tensor_descriptor_regs.h b/external_includes/gaudi/asic_reg_structs/tpc_non_tensor_descriptor_regs.h similarity index 98% rename from external_includes/asic_reg_structs/tpc_non_tensor_descriptor_regs.h rename to external_includes/gaudi/asic_reg_structs/tpc_non_tensor_descriptor_regs.h index 4e0a83f..c24072f 100644 --- a/external_includes/asic_reg_structs/tpc_non_tensor_descriptor_regs.h +++ b/external_includes/gaudi/asic_reg_structs/tpc_non_tensor_descriptor_regs.h @@ -9,7 +9,8 @@ #include #pragma pack(push, 1) - +namespace gaudi +{ namespace tpc_non_tensor_descriptor { /* KERNEL_BASE_ADDRESS_LOW @@ -222,12 +223,16 @@ struct block_tpc_non_tensor_descriptor { struct tpc_non_tensor_descriptor::reg_kernel_id kernel_id; struct tpc_non_tensor_descriptor::reg_srf srf[32]; }; +} // namespace gaudi #include "gaudi_types.h" +namespace gaudi +{ const offsetVal block_tpc_non_tensor_descriptor_defaults[] { // offset // value { 0x30 , 0x60882 , 1 }, // kernel_config }; +} //namespace gaudi #pragma pack(pop) #endif /* ASIC_REG_STRUCTS_TPC_NON_TENSOR_DESCRIPTOR_H_ */ diff --git a/external_includes/asic_reg_structs/tpc_regs.h b/external_includes/gaudi/asic_reg_structs/tpc_regs.h similarity index 99% rename from external_includes/asic_reg_structs/tpc_regs.h rename to external_includes/gaudi/asic_reg_structs/tpc_regs.h index d50310d..24d8edd 100644 --- a/external_includes/asic_reg_structs/tpc_regs.h +++ b/external_includes/gaudi/asic_reg_structs/tpc_regs.h @@ -9,7 +9,8 @@ #include #pragma pack(push, 1) - +namespace gaudi +{ namespace tpc { /* CFG_BASE_ADDRESS_HIGH @@ -705,13 +706,15 @@ struct reg_irq_occoupy_cntr { }; static_assert((sizeof(struct reg_irq_occoupy_cntr) == 4), "reg_irq_occoupy_cntr size is not 32-bit"); } /* tpc namespace */ - +} //namespace gaudi #include "sync_object_regs.h" #include "tpc_non_tensor_descriptor_regs.h" #include "tpc_tensor_regs.h" /* TPC block */ +namespace gaudi +{ struct block_tpc { uint32_t _pad0[256]; struct block_tpc_tensor kernel_tensor_0; @@ -807,7 +810,10 @@ struct block_tpc { struct block_sync_object qm_sync_object; struct block_tpc_non_tensor_descriptor qm; }; +} // namespace gaudi #include "gaudi_types.h" +namespace gaudi +{ const offsetVal block_tpc_defaults[] { // offset // value @@ -863,6 +869,6 @@ const offsetVal block_tpc_defaults[] { 0xd54 , 0x50000 , 1 }, // tensor_config { 0xdb8 , 0x60882 , 1 }, // kernel_config }; - +} // namespace gaudi #pragma pack(pop) #endif /* ASIC_REG_STRUCTS_TPC_H_ */ diff --git a/external_includes/asic_reg_structs/tpc_tensor_regs.h b/external_includes/gaudi/asic_reg_structs/tpc_tensor_regs.h similarity index 98% rename from external_includes/asic_reg_structs/tpc_tensor_regs.h rename to external_includes/gaudi/asic_reg_structs/tpc_tensor_regs.h index 5345252..774873a 100644 --- a/external_includes/asic_reg_structs/tpc_tensor_regs.h +++ b/external_includes/gaudi/asic_reg_structs/tpc_tensor_regs.h @@ -9,7 +9,8 @@ #include #pragma pack(push, 1) - +namespace gaudi +{ namespace tpc_tensor { /* BASE_ADDR_LOW @@ -222,12 +223,16 @@ struct block_tpc_tensor { struct tpc_tensor::reg_dim_4_size dim_4_size; struct tpc_tensor::reg_dim_4_stride dim_4_stride; }; +} // namespace gaudi #include "gaudi_types.h" +namespace gaudi +{ const offsetVal block_tpc_tensor_defaults[] { // offset // value { 0xc , 0x50000 , 1 }, // tensor_config }; +} // namespace gaudi #pragma pack(pop) #endif /* ASIC_REG_STRUCTS_TPC_TENSOR_H_ */ diff --git a/external_includes/gaudi_packets.h b/external_includes/gaudi/gaudi_packets.h similarity index 99% rename from external_includes/gaudi_packets.h rename to external_includes/gaudi/gaudi_packets.h index 9882f4a..13d5265 100644 --- a/external_includes/gaudi_packets.h +++ b/external_includes/gaudi/gaudi_packets.h @@ -12,6 +12,8 @@ #define PACKET_HEADER_PACKET_ID_SHIFT 56 #define PACKET_HEADER_PACKET_ID_MASK 0x1F00000000000000ull +namespace gaudi +{ enum packet_id { PACKET_WREG_32 = 0x1, @@ -325,4 +327,5 @@ struct packet_cp_dma { __u64 src_addr; }; +} // namespace gaudi #endif /* GAUDI_PACKETS_H */ diff --git a/external_includes/gaudi_tpc_descriptor.h b/external_includes/gaudi/gaudi_tpc_descriptor.h similarity index 93% rename from external_includes/gaudi_tpc_descriptor.h rename to external_includes/gaudi/gaudi_tpc_descriptor.h index 224cb18..09968dd 100644 --- a/external_includes/gaudi_tpc_descriptor.h +++ b/external_includes/gaudi/gaudi_tpc_descriptor.h @@ -15,6 +15,8 @@ #pragma pack(push, 4) +namespace gaudi +{ struct GaudiTpcDesc { static const int c_max_tensor_dims = 5; @@ -25,5 +27,6 @@ struct GaudiTpcDesc block_tpc_non_tensor_descriptor m_desc; }; +} // namespace gaudi #pragma pack(pop) #endif // _GAUDI_TPC_DESC_H_ diff --git a/external_includes/gaudi2/SpecialFuncCoefficients_defGen6.h b/external_includes/gaudi2/SpecialFuncCoefficients_defGen6.h new file mode 100644 index 0000000..e28cf57 --- /dev/null +++ b/external_includes/gaudi2/SpecialFuncCoefficients_defGen6.h @@ -0,0 +1,340 @@ +/***************************************************************************** + * Copyright (C) 2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + * Unauthorized copying of this file, via any medium is strictly prohibited. + * Proprietary and confidential. + ****************************************************************************** + */ + +#ifndef SPECIALFUNCCOEFFICIENTS_DEF_GEN4_H_ +#define SPECIALFUNCCOEFFICIENTS_DEF_GEN4_H_ + +#define CACHE_LINE_SIZE_IN_BYTES 128 + +#define m2_val 2 +#define m3_val 3 +#define m4_val 4 +#define m5_val 5 +#define m6_val 6 +#define m7_val 7 + +// NumIntervals = 256 +// 0 +#define FUNC_ID_FP32_TANH 0b000000 +// 1 +#define FUNC_ID_FP32_RSQRT 0b000001 +// 2 +#define FUNC_ID_FP32_LOG2 0b000010 +// 3 +#define FUNC_ID_INT8_SQRT 0b000011 +// 4 +#define FUNC_ID_UINT16_SQUARE 0b000100 +// 5 +#define FUNC_ID_UINT32_POWER4 0b000101 +// 6 +#define FUNC_ID_INT8_SQRT_C0 0b000110 +// 7 +#define FUNC_ID_UINT16_SQUARE_C0 0b000111 +// 8 +#define FUNC_ID_FP32_ERF 0b001000 +// 9 +#define FUNC_ID_FP32_IMP_TANH 0b001001 +// NumIntervals = 128 +// 128 +#define FUNC_ID_FP32_SQRT 0b010000000 +// 129 +#define FUNC_ID_FP32_RCP 0b010000001 +// 130 +#define FUNC_ID_FP32_SINCOS 0b010000010 +// 131 +#define FUNC_ID_BF16_RCP_SCALAR_M7 0b010000011 + +// 132 +#define FUNC_ID_BF16_SINCOS_SCALAR_M7 0b010000100 +// 133 +#define FUNC_ID_BF16_SINCOS_LINEAR_M6 0b010000101 +// 134 +#define FUNC_ID_BF16_SINCOS_POLY2_M6_C2C1 0b010000110 +// 135 +#define FUNC_ID_BF16_SINCOS_POLY2_M6_C0 0b010000111 +// 136 +#define FUNC_ID_BF16_LOG2_LINEAR_INTERLEAVED_M5 0b010001000 +// 137 +#define FUNC_ID_BF16_LOG2_LINEAR_GAUDI2_M5 0b010001001 +// 138 +#define FUNC_ID_BF16_EXP 0b010001010 +// 139 +#define FUNC_ID_INT16_EXP_NEG_0_16_128ENTRIES 0b010001011 +// 140 +#define FUNC_ID_REDUCTION_16 0b010001100 +// 141 +#define FUNC_ID_REDUCTION_8 0b010001101 + +// NumIntervals = 64 +// 256 +#define FUNC_ID_FP32_POW2 0b100000000 +// 257 +#define FUNC_ID_BF16_TANH 0b100000001 +// 258 +#define FUNC_ID_INT16_TANH_0_8 0b100000010 +// 259 +#define FUNC_ID_INT16_SIGMOID_0_8 0b100000011 +// 260 +#define FUNC_ID_INT16_EXP_NEG_0_16 0b100000100 +// 261 +#define FUNC_ID_INT16_RECIP_1_4 0b100000101 +// 262 +#define FUNC_ID_INT8_TANH_0_8_LINEAR 0b100000110 +// 263 +#define FUNC_ID_INT8_SIGMOID_0_8_LINEAR 0b100000111 +// 264 +#define FUNC_ID_INT8_EXP_NEG_0_8_LINEAR 0b100001000 +// 265 +#define FUNC_ID_BF16_TANH_C0 0b100001001 +// 266 +#define FUNC_ID_INT16_TANH_0_8_C0 0b100001010 +// 267 +#define FUNC_ID_INT16_SIGMOID_0_8_C0 0b100001011 +// 268 +#define FUNC_ID_INT16_EXP_NEG_0_16_C0 0b100001100 +// 269 +#define FUNC_ID_INT16_RECIP_1_4_C0 0b100001101 +// 270 +#define FUNC_ID_INT8_TANH_0_8_LINEAR_C0 0b100001110 +// 271 +#define FUNC_ID_INT8_SIGMOID_0_8_LINEAR_C0 0b100001111 +// 272 +#define FUNC_ID_INT8_EXP_NEG_0_8_LINEAR_C0 0b100010000 +// 273 +#define FUNC_ID_BF16_TANH_LINEAR_M4 0b100010001 +// 274 +#define FUNC_ID_BF16_TANH_POLY2_M4_C2C1 0b100010010 +// 275 +#define FUNC_ID_BF16_TANH_POLY2_M4_C0 0b100010011 +// 276 +#define FUNC_ID_BF16_SQRT_SCALAR_M6 0b100010100 +// 277 +#define FUNC_ID_BF16_LOG2_LINEAR_M5 0b100010101 + +// 278 +#define FUNC_ID_BF16_SINCOS_LINEAR_M5 0b100010110 +// 279 +#define FUNC_ID_BF16_SINCOS_POLY2_M5_C2C1 0b100010111 +// 280 +#define FUNC_ID_BF16_SINCOS_POLY2_M5_C0 0b100011000 +// 281 +#define FUNC_ID_FP16_TANH 0b100011001 +// 282 +#define FUNC_ID_FP16_TANH_C0 0b100011010 +// 283 +#define FUNC_ID_BF16_RSQRT_SCALAR_M6 0b100011011 +// 284 +#define FUNC_ID_INT16_GELU_MINUS_RELU_0_4 0b100011100 +// 285 +#define FUNC_ID_FP16_GELU 0b100011101 +// 286 +#define FUNC_ID_FP16_GELU_C0 0b100011110 +// 287 +#define FUNC_ID_REDUCTION_32 0b100011111 +// 288 +#define FUNC_ID_BF16_C0_RECIP 0b100100000 +// 289 +#define FUNC_ID_SWIZZLE_32 0b100100001 + +// NumIntervals = 32 or less +// 384 +#define FUNC_ID_BF16_RSQRT 0b110000000 +// 385 +#define FUNC_ID_BF16_LOG2 0b110000001 +// 386 +#define FUNC_ID_BF16_SQRT 0b110000010 +// 387 +#define FUNC_ID_BF16_RCP 0b110000011 +// 388 +#define FUNC_ID_BF16_SINCOS 0b110000100 +// 389 +#define FUNC_ID_BF16_POW2 0b110000101 +// 390 +#define FUNC_ID_INT8_TANH 0b110000110 +// 391 +#define FUNC_ID_BF16_RSQRT_C0 0b110000111 +// 392 +#define FUNC_ID_BF16_LOG2_C0 0b110001000 +// 393 +#define FUNC_ID_BF16_SQRT_C0 0b110001001 +// 394 +#define FUNC_ID_BF16_RCP_C0 0b110001010 +// 395 +#define FUNC_ID_BF16_SINCOS_C0 0b110001011 +// 396 +#define FUNC_ID_BF16_POW2_C0 0b110001100 +// 397 +#define FUNC_ID_INT8_TANH_C0 0b110001101 +// 398 +#define FUNC_ID_FP16_RCP 0b110001110 +// 399 +#define FUNC_ID_BF16_RCP_LINEAR_M2 0b110001111 +// 400 +#define FUNC_ID_BF16_RCP_LINEAR_M3 0b110010000 +// 401 +#define FUNC_ID_BF16_RCP_LINEAR_M4 0b110010001 +// 402 +#define FUNC_ID_BF16_RCP_POLY2_M2_C2C1 0b110010010 +// 403 +#define FUNC_ID_BF16_RCP_POLY2_M3_C2C1 0b110010011 +// 404 +#define FUNC_ID_BF16_RCP_POLY2_M4_C2C1 0b110010100 +// 405 +#define FUNC_ID_BF16_RCP_POLY2_M2_C0 0b110010101 +// 406 +#define FUNC_ID_BF16_RCP_POLY2_M3_C0 0b110010110 +// 407 +#define FUNC_ID_BF16_RCP_POLY2_M4_C0 0b110010111 +// 408 +#define FUNC_ID_FP16_RCP_C0 0b110011000 +// 409 +#define FUNC_ID_BF16_SQRT_LINEAR_M2 0b110011001 +// 410 +#define FUNC_ID_BF16_SQRT_LINEAR_M3 0b110011010 +// 411 +#define FUNC_ID_BF16_SQRT_LINEAR_M4 0b110011011 +// 412 +#define FUNC_ID_BF16_SQRT_POLY2_M2_C2C1 0b110011100 +// 413 +#define FUNC_ID_BF16_SQRT_POLY2_M3_C2C1 0b110011101 +// 414 +#define FUNC_ID_BF16_SQRT_POLY2_M4_C2C1 0b110011110 +// 415 +#define FUNC_ID_BF16_SQRT_POLY2_M2_C0 0b110011111 +// 416 +#define FUNC_ID_BF16_SQRT_POLY2_M3_C0 0b110100000 +// 417 +#define FUNC_ID_BF16_SQRT_POLY2_M4_C0 0b110100001 + +// 418 +#define FUNC_ID_BF16_TANH_LINEAR_M2 0b110100010 +// 419 +#define FUNC_ID_BF16_TANH_LINEAR_M3 0b110100011 + +// 421 +#define FUNC_ID_BF16_TANH_POLY2_M2_C2C1 0b110100101 +// 422 +#define FUNC_ID_BF16_TANH_POLY2_M3_C2C1 0b110100110 + +// 424 +#define FUNC_ID_BF16_TANH_POLY2_M2_C0 0b110101000 +// 425 +#define FUNC_ID_BF16_TANH_POLY2_M3_C0 0b110101001 + +// 426 +#define FUNC_ID_BF16_LOG2ML_LINEAR_M4_0_075 0b110101010 + +// 427 +#define FUNC_ID_BF16_SINCOS_LINEAR_M2 0b110101011 +// 428 +#define FUNC_ID_BF16_SINCOS_LINEAR_M3 0b110101100 +// 429 +#define FUNC_ID_BF16_SINCOS_LINEAR_M4 0b110101101 +// 430 +#define FUNC_ID_BF16_SINCOS_POLY2_M2_C2C1 0b110101110 +// 431 +#define FUNC_ID_BF16_SINCOS_POLY2_M2_C0 0b110101111 +// 432 +#define FUNC_ID_BF16_SINCOS_POLY2_M3_C2C1 0b110110000 +// 433 +#define FUNC_ID_BF16_SINCOS_POLY2_M3_C0 0b110110001 +// 434 +#define FUNC_ID_BF16_SINCOS_POLY2_M4_C2C1 0b110110010 +// 435 +#define FUNC_ID_BF16_SINCOS_POLY2_M4_C0 0b110110011 + +// 436 +#define FUNC_ID_FP16_LOG2 0b110110100 +// 437 +#define FUNC_ID_FP16_LOG2_C0 0b110110101 +// 438 +#define FUNC_ID_FP16_SQRT 0b110110110 +// 439 +#define FUNC_ID_FP16_SQRT_C0 0b110110111 +// 440 +#define FUNC_ID_FP16_RSQRT 0b110111000 +// 441 +#define FUNC_ID_FP16_RSQRT_C0 0b110111001 +// 442 +#define FUNC_ID_FP16_SINCOS 0b110111010 +// 443 +#define FUNC_ID_FP16_SINCOS_C0 0b110111011 +// 444 +#define FUNC_ID_FP16_POW2 0b110111100 +// 445 +#define FUNC_ID_FP16_POW2_C0 0b110111101 +// 446 +#define FUNC_ID_BF16_RSQRT_LINEAR_M2 0b110111110 +// 447 +#define FUNC_ID_BF16_RSQRT_LINEAR_M3 0b110111111 +// 448 +#define FUNC_ID_BF16_RSQRT_LINEAR_M4 0b111000000 +// 449 +#define FUNC_ID_BF16_RSQRT_POLY2_M2_C2C1 0b111000001 +// 450 +#define FUNC_ID_BF16_RSQRT_POLY2_M3_C2C1 0b111000010 +// 451 +#define FUNC_ID_BF16_RSQRT_POLY2_M4_C2C1 0b111000011 +// 452 +#define FUNC_ID_BF16_RSQRT_POLY2_M2_C0 0b111000100 +// 453 +#define FUNC_ID_BF16_RSQRT_POLY2_M3_C0 0b111000101 +// 454 +#define FUNC_ID_BF16_RSQRT_POLY2_M4_C0 0b111000110 + +#define FUNC_ID_UNUSED 0xFFFFFFFF + +#define SPECIAL_FUNC_NUM_TABLES_PER_TYPE 128 // 16 //16*8 (+3bits to func_ID) +#define SPECIAL_FUNC_NUM_ELEMENTS_IN_ENTRY 3 +#define SPECIAL_FUNC_BYTES_IN_ENTRY (SPECIAL_FUNC_NUM_ELEMENTS_IN_ENTRY * sizeof(float)) + +#define SPECIAL_FUNC_NUM_OF_DIFFERENT_INTERVALS 4 // 256/128/64/32 +#define SPECIAL_FUNC_256_ENTRIES 0b00 +#define SPECIAL_FUNC_128_ENTRIES 0b01 +#define SPECIAL_FUNC_64_ENTRIES 0b10 +#define SPECIAL_FUNC_32_ENTRIES 0b11 + +#define SPECIAL_FUNC_NUM_ENTRIES_IN_FUNCID_OFFSET 7 // 4 //4+3 (+3bits to func_ID) + +// We have room for 16 functions of each type of the following: +// 256 entries, 128 entries, 64 entries, 32 entries or less. +// In order to align data in cache line each entry type has it's own number of cache lines +// needed to store coefficietns (See TPC_Overview:TCACHE) +#define SPECIAL_FUNCS_NUM_OF_INTERVALS_IN_CACHE_LINE 10 +#define SPECIAL_FUNCS_CACHE_LINE_PADDING \ + (CACHE_LINE_SIZE_IN_BYTES - (SPECIAL_FUNCS_NUM_OF_INTERVALS_IN_CACHE_LINE * SPECIAL_FUNC_BYTES_IN_ENTRY)) +#define SPECIAL_FUNCS_NUM_OF_CACHE_LINES_IN_FUNC_256 26 +#define SPECIAL_FUNCS_NUM_OF_CACHE_LINES_IN_FUNC_128 13 +#define SPECIAL_FUNCS_NUM_OF_CACHE_LINES_IN_FUNC_64 7 +#define SPECIAL_FUNCS_NUM_OF_CACHE_LINES_IN_FUNC_32 4 +#define SPECIAL_FUNC256_SIZE_BYTES \ + (SPECIAL_FUNCS_NUM_OF_CACHE_LINES_IN_FUNC_256 * CACHE_LINE_SIZE_IN_BYTES * SPECIAL_FUNC_NUM_TABLES_PER_TYPE) +#define SPECIAL_FUNC128_SIZE_BYTES \ + (SPECIAL_FUNCS_NUM_OF_CACHE_LINES_IN_FUNC_128 * CACHE_LINE_SIZE_IN_BYTES * SPECIAL_FUNC_NUM_TABLES_PER_TYPE) +#define SPECIAL_FUNC64_SIZE_BYTES \ + (SPECIAL_FUNCS_NUM_OF_CACHE_LINES_IN_FUNC_64 * CACHE_LINE_SIZE_IN_BYTES * SPECIAL_FUNC_NUM_TABLES_PER_TYPE) +#define SPECIAL_FUNC32_SIZE_BYTES \ + (SPECIAL_FUNCS_NUM_OF_CACHE_LINES_IN_FUNC_32 * CACHE_LINE_SIZE_IN_BYTES * SPECIAL_FUNC_NUM_TABLES_PER_TYPE) + +#define SPECIAL_FUNCS_BLOB_SIZE_BYTES \ + (SPECIAL_FUNC256_SIZE_BYTES + SPECIAL_FUNC128_SIZE_BYTES + SPECIAL_FUNC64_SIZE_BYTES + SPECIAL_FUNC32_SIZE_BYTES) +// these base addresses are configurable in TPC, but in simulator it doesn't matter since we don't simulate cache/actual +// addresses +#define SPECIAL_FUNCS_INTERVAL256_BASE_ADDR 0 +#define SPECIAL_FUNCS_INTERVAL128_BASE_ADDR \ + (SPECIAL_FUNCS_INTERVAL256_BASE_ADDR + \ + (SPECIAL_FUNCS_NUM_OF_CACHE_LINES_IN_FUNC_256 * CACHE_LINE_SIZE_IN_BYTES * SPECIAL_FUNC_NUM_TABLES_PER_TYPE)) +#define SPECIAL_FUNCS_INTERVAL64_BASE_ADDR \ + (SPECIAL_FUNCS_INTERVAL128_BASE_ADDR + \ + (SPECIAL_FUNCS_NUM_OF_CACHE_LINES_IN_FUNC_128 * CACHE_LINE_SIZE_IN_BYTES * SPECIAL_FUNC_NUM_TABLES_PER_TYPE)) +#define SPECIAL_FUNCS_INTERVAL32_BASE_ADDR \ + (SPECIAL_FUNCS_INTERVAL64_BASE_ADDR + \ + (SPECIAL_FUNCS_NUM_OF_CACHE_LINES_IN_FUNC_64 * CACHE_LINE_SIZE_IN_BYTES * SPECIAL_FUNC_NUM_TABLES_PER_TYPE)) + +#endif // SPECIALFUNCCOEFFICIENTS_DEF_GEN4_H_ diff --git a/external_includes/gaudi2/TPC_IO_REG_SPACE_GEN6.h b/external_includes/gaudi2/TPC_IO_REG_SPACE_GEN6.h new file mode 100644 index 0000000..da4639e --- /dev/null +++ b/external_includes/gaudi2/TPC_IO_REG_SPACE_GEN6.h @@ -0,0 +1,6270 @@ +/* + * Copyright 2016-2017 HabanaLabs, Ltd. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef TPC_IO_REG_SPACE_GEN4_H_ +#define TPC_IO_REG_SPACE_GEN4_H_ + +/* + ***************************************** + * DCORE0_TPC0_CFG (Prototype: TPC) + ***************************************** + */ +#define ECC_SERR_INJ 0xF10 +#define ECC_SERR_INJ_SHIFT 0 +#define ECC_SERR_INJ_MASK 0xFF + +#define ECC_DERR_INJ 0xF14 +#define ECC_DERR_INJ_SHIFT 0 +#define ECC_DERR_INJ_MASK 0xFF + +#define ECC_MEM_SEL 0xF18 +#define ECC_MEM_SEL_SHIFT 0 +#define ECC_MEM_SEL_MASK 0xFF + +#define ECC_ADDR 0xF1C +#define ECC_ADDR_SHIFT 0 +#define ECC_ADDR_MASK 0xFFFF + +#define ECC_SYND 0xF20 +#define ECC_SYND_SHIFT 0 +#define ECC_SYND_MASK 0xFFFF + +#define ECC_TYPE 0xF24 +#define ECC_TYPE_SHIFT 0 +#define ECC_TYPE_MASK 0x1 + +#define ECC_SERR_0 0xF30 +#define ECC_SERR_SHIFT_0 0 +#define ECC_SERR_MASK_0 0xFFFFFFFF + +#define ECC_SERR_1 0xF34 +#define ECC_SERR_SHIFT_1 0 +#define ECC_SERR_MASK_1 0xFFFFFFFF + +#define ECC_SERR_2 0xF38 +#define ECC_SERR_SHIFT_2 0 +#define ECC_SERR_MASK_2 0x7FFF + +#define ECC_DERR_0 0xF40 +#define ECC_DERR_SHIFT_0 0 +#define ECC_DERR_MASK_0 0xFFFFFFFF + +#define ECC_DERR_1 0xF44 +#define ECC_DERR_SHIFT_1 0 +#define ECC_DERR_MASK_1 0xFFFFFFFF + +#define ECC_DERR_2 0xF48 +#define ECC_DERR_SHIFT_2 0 +#define ECC_DERR_MASK_2 0x7FFF + +#define KERNEL_TENSOR_0_BASE_ADDR_LOW 0x000 + +#define KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0 +#define KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_0_BASE_ADDR_HIGH 0x004 + +#define KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0 +#define KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_0_PADDING_VALUE 0x008 + +#define KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT 0 +#define KERNEL_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_0_TENSOR_CONFIG 0x00C + +#define KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define KERNEL_TENSOR_0_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define KERNEL_TENSOR_0_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define KERNEL_TENSOR_0_TENSOR_CONFIG_L0CD_SHIFT 25 +#define KERNEL_TENSOR_0_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define KERNEL_TENSOR_0_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define KERNEL_TENSOR_0_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define KERNEL_TENSOR_0_DIM_0_SIZE 0x010 + +#define KERNEL_TENSOR_0_DIM_0_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_0_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_0_DIM_0_STRIDE 0x014 + +#define KERNEL_TENSOR_0_DIM_0_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_0_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_0_DIM_1_SIZE 0x018 + +#define KERNEL_TENSOR_0_DIM_1_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_0_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_0_DIM_1_STRIDE 0x01C + +#define KERNEL_TENSOR_0_DIM_1_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_0_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_0_DIM_2_SIZE 0x020 + +#define KERNEL_TENSOR_0_DIM_2_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_0_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_0_DIM_2_STRIDE 0x024 + +#define KERNEL_TENSOR_0_DIM_2_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_0_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_0_DIM_3_SIZE 0x028 + +#define KERNEL_TENSOR_0_DIM_3_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_0_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_0_DIM_3_STRIDE 0x02C + +#define KERNEL_TENSOR_0_DIM_3_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_0_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_0_DIM_4_SIZE 0x030 + +#define KERNEL_TENSOR_0_DIM_4_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_0_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_0_DIM_4_STRIDE 0x034 + +#define KERNEL_TENSOR_0_DIM_4_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_0_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_0_PREF_STRIDE 0x038 + +#define KERNEL_TENSOR_0_PREF_STRIDE_VAL_SHIFT 0 +#define KERNEL_TENSOR_0_PREF_STRIDE_VAL_MASK 0xFFFF + +#define KERNEL_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH 0x03C + +#define KERNEL_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH 0x040 + +#define KERNEL_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH 0x044 + +#define KERNEL_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH 0x048 + +#define KERNEL_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH 0x04C + +#define KERNEL_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_1_BASE_ADDR_LOW 0x050 + +#define KERNEL_TENSOR_1_BASE_ADDR_LOW_V_SHIFT 0 +#define KERNEL_TENSOR_1_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_1_BASE_ADDR_HIGH 0x054 + +#define KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT 0 +#define KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_1_PADDING_VALUE 0x058 + +#define KERNEL_TENSOR_1_PADDING_VALUE_V_SHIFT 0 +#define KERNEL_TENSOR_1_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_1_TENSOR_CONFIG 0x05C + +#define KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define KERNEL_TENSOR_1_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define KERNEL_TENSOR_1_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define KERNEL_TENSOR_1_TENSOR_CONFIG_L0CD_SHIFT 25 +#define KERNEL_TENSOR_1_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define KERNEL_TENSOR_1_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define KERNEL_TENSOR_1_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define KERNEL_TENSOR_1_DIM_0_SIZE 0x060 + +#define KERNEL_TENSOR_1_DIM_0_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_1_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_1_DIM_0_STRIDE 0x064 + +#define KERNEL_TENSOR_1_DIM_0_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_1_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_1_DIM_1_SIZE 0x068 + +#define KERNEL_TENSOR_1_DIM_1_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_1_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_1_DIM_1_STRIDE 0x06C + +#define KERNEL_TENSOR_1_DIM_1_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_1_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_1_DIM_2_SIZE 0x070 + +#define KERNEL_TENSOR_1_DIM_2_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_1_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_1_DIM_2_STRIDE 0x074 + +#define KERNEL_TENSOR_1_DIM_2_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_1_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_1_DIM_3_SIZE 0x078 + +#define KERNEL_TENSOR_1_DIM_3_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_1_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_1_DIM_3_STRIDE 0x07C + +#define KERNEL_TENSOR_1_DIM_3_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_1_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_1_DIM_4_SIZE 0x080 + +#define KERNEL_TENSOR_1_DIM_4_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_1_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_1_DIM_4_STRIDE 0x084 + +#define KERNEL_TENSOR_1_DIM_4_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_1_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_1_PREF_STRIDE 0x088 + +#define KERNEL_TENSOR_1_PREF_STRIDE_VAL_SHIFT 0 +#define KERNEL_TENSOR_1_PREF_STRIDE_VAL_MASK 0xFFFF + +#define KERNEL_TENSOR_1_DIM_0_SIZE_STRIDE_HIGH 0x08C + +#define KERNEL_TENSOR_1_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_1_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_1_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_1_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_1_DIM_1_SIZE_STRIDE_HIGH 0x090 + +#define KERNEL_TENSOR_1_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_1_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_1_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_1_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_1_DIM_2_SIZE_STRIDE_HIGH 0x094 + +#define KERNEL_TENSOR_1_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_1_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_1_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_1_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_1_DIM_3_SIZE_STRIDE_HIGH 0x098 + +#define KERNEL_TENSOR_1_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_1_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_1_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_1_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_1_DIM_4_SIZE_STRIDE_HIGH 0x09C + +#define KERNEL_TENSOR_1_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_1_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_1_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_1_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_2_BASE_ADDR_LOW 0x0A0 + +#define KERNEL_TENSOR_2_BASE_ADDR_LOW_V_SHIFT 0 +#define KERNEL_TENSOR_2_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_2_BASE_ADDR_HIGH 0x0A4 + +#define KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT 0 +#define KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_2_PADDING_VALUE 0x0A8 + +#define KERNEL_TENSOR_2_PADDING_VALUE_V_SHIFT 0 +#define KERNEL_TENSOR_2_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_2_TENSOR_CONFIG 0x0AC + +#define KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define KERNEL_TENSOR_2_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define KERNEL_TENSOR_2_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define KERNEL_TENSOR_2_TENSOR_CONFIG_L0CD_SHIFT 25 +#define KERNEL_TENSOR_2_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define KERNEL_TENSOR_2_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define KERNEL_TENSOR_2_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define KERNEL_TENSOR_2_DIM_0_SIZE 0x0B0 + +#define KERNEL_TENSOR_2_DIM_0_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_2_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_2_DIM_0_STRIDE 0x0B4 + +#define KERNEL_TENSOR_2_DIM_0_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_2_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_2_DIM_1_SIZE 0x0B8 + +#define KERNEL_TENSOR_2_DIM_1_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_2_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_2_DIM_1_STRIDE 0x0BC + +#define KERNEL_TENSOR_2_DIM_1_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_2_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_2_DIM_2_SIZE 0x0C0 + +#define KERNEL_TENSOR_2_DIM_2_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_2_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_2_DIM_2_STRIDE 0x0C4 + +#define KERNEL_TENSOR_2_DIM_2_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_2_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_2_DIM_3_SIZE 0x0C8 + +#define KERNEL_TENSOR_2_DIM_3_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_2_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_2_DIM_3_STRIDE 0x0CC + +#define KERNEL_TENSOR_2_DIM_3_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_2_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_2_DIM_4_SIZE 0x0D0 + +#define KERNEL_TENSOR_2_DIM_4_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_2_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_2_DIM_4_STRIDE 0x0D4 + +#define KERNEL_TENSOR_2_DIM_4_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_2_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_2_PREF_STRIDE 0x0D8 + +#define KERNEL_TENSOR_2_PREF_STRIDE_VAL_SHIFT 0 +#define KERNEL_TENSOR_2_PREF_STRIDE_VAL_MASK 0xFFFF + +#define KERNEL_TENSOR_2_DIM_0_SIZE_STRIDE_HIGH 0x0DC + +#define KERNEL_TENSOR_2_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_2_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_2_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_2_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_2_DIM_1_SIZE_STRIDE_HIGH 0x0E0 + +#define KERNEL_TENSOR_2_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_2_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_2_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_2_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_2_DIM_2_SIZE_STRIDE_HIGH 0x0E4 + +#define KERNEL_TENSOR_2_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_2_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_2_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_2_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_2_DIM_3_SIZE_STRIDE_HIGH 0x0E8 + +#define KERNEL_TENSOR_2_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_2_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_2_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_2_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_2_DIM_4_SIZE_STRIDE_HIGH 0x0EC + +#define KERNEL_TENSOR_2_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_2_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_2_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_2_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_3_BASE_ADDR_LOW 0x0F0 + +#define KERNEL_TENSOR_3_BASE_ADDR_LOW_V_SHIFT 0 +#define KERNEL_TENSOR_3_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_3_BASE_ADDR_HIGH 0x0F4 + +#define KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT 0 +#define KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_3_PADDING_VALUE 0x0F8 + +#define KERNEL_TENSOR_3_PADDING_VALUE_V_SHIFT 0 +#define KERNEL_TENSOR_3_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_3_TENSOR_CONFIG 0x0FC + +#define KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define KERNEL_TENSOR_3_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define KERNEL_TENSOR_3_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define KERNEL_TENSOR_3_TENSOR_CONFIG_L0CD_SHIFT 25 +#define KERNEL_TENSOR_3_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define KERNEL_TENSOR_3_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define KERNEL_TENSOR_3_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define KERNEL_TENSOR_3_DIM_0_SIZE 0x100 + +#define KERNEL_TENSOR_3_DIM_0_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_3_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_3_DIM_0_STRIDE 0x104 + +#define KERNEL_TENSOR_3_DIM_0_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_3_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_3_DIM_1_SIZE 0x108 + +#define KERNEL_TENSOR_3_DIM_1_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_3_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_3_DIM_1_STRIDE 0x10C + +#define KERNEL_TENSOR_3_DIM_1_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_3_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_3_DIM_2_SIZE 0x110 + +#define KERNEL_TENSOR_3_DIM_2_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_3_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_3_DIM_2_STRIDE 0x114 + +#define KERNEL_TENSOR_3_DIM_2_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_3_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_3_DIM_3_SIZE 0x118 + +#define KERNEL_TENSOR_3_DIM_3_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_3_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_3_DIM_3_STRIDE 0x11C + +#define KERNEL_TENSOR_3_DIM_3_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_3_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_3_DIM_4_SIZE 0x120 + +#define KERNEL_TENSOR_3_DIM_4_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_3_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_3_DIM_4_STRIDE 0x124 + +#define KERNEL_TENSOR_3_DIM_4_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_3_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_3_PREF_STRIDE 0x128 + +#define KERNEL_TENSOR_3_PREF_STRIDE_VAL_SHIFT 0 +#define KERNEL_TENSOR_3_PREF_STRIDE_VAL_MASK 0xFFFF + +#define KERNEL_TENSOR_3_DIM_0_SIZE_STRIDE_HIGH 0x12C + +#define KERNEL_TENSOR_3_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_3_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_3_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_3_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_3_DIM_1_SIZE_STRIDE_HIGH 0x130 + +#define KERNEL_TENSOR_3_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_3_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_3_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_3_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_3_DIM_2_SIZE_STRIDE_HIGH 0x134 + +#define KERNEL_TENSOR_3_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_3_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_3_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_3_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_3_DIM_3_SIZE_STRIDE_HIGH 0x138 + +#define KERNEL_TENSOR_3_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_3_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_3_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_3_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_3_DIM_4_SIZE_STRIDE_HIGH 0x13C + +#define KERNEL_TENSOR_3_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_3_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_3_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_3_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_4_BASE_ADDR_LOW 0x140 + +#define KERNEL_TENSOR_4_BASE_ADDR_LOW_V_SHIFT 0 +#define KERNEL_TENSOR_4_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_4_BASE_ADDR_HIGH 0x144 + +#define KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT 0 +#define KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_4_PADDING_VALUE 0x148 + +#define KERNEL_TENSOR_4_PADDING_VALUE_V_SHIFT 0 +#define KERNEL_TENSOR_4_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_4_TENSOR_CONFIG 0x14C + +#define KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define KERNEL_TENSOR_4_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define KERNEL_TENSOR_4_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define KERNEL_TENSOR_4_TENSOR_CONFIG_L0CD_SHIFT 25 +#define KERNEL_TENSOR_4_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define KERNEL_TENSOR_4_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define KERNEL_TENSOR_4_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define KERNEL_TENSOR_4_DIM_0_SIZE 0x150 + +#define KERNEL_TENSOR_4_DIM_0_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_4_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_4_DIM_0_STRIDE 0x154 + +#define KERNEL_TENSOR_4_DIM_0_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_4_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_4_DIM_1_SIZE 0x158 + +#define KERNEL_TENSOR_4_DIM_1_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_4_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_4_DIM_1_STRIDE 0x15C + +#define KERNEL_TENSOR_4_DIM_1_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_4_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_4_DIM_2_SIZE 0x160 + +#define KERNEL_TENSOR_4_DIM_2_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_4_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_4_DIM_2_STRIDE 0x164 + +#define KERNEL_TENSOR_4_DIM_2_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_4_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_4_DIM_3_SIZE 0x168 + +#define KERNEL_TENSOR_4_DIM_3_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_4_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_4_DIM_3_STRIDE 0x16C + +#define KERNEL_TENSOR_4_DIM_3_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_4_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_4_DIM_4_SIZE 0x170 + +#define KERNEL_TENSOR_4_DIM_4_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_4_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_4_DIM_4_STRIDE 0x174 + +#define KERNEL_TENSOR_4_DIM_4_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_4_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_4_PREF_STRIDE 0x178 + +#define KERNEL_TENSOR_4_PREF_STRIDE_VAL_SHIFT 0 +#define KERNEL_TENSOR_4_PREF_STRIDE_VAL_MASK 0xFFFF + +#define KERNEL_TENSOR_4_DIM_0_SIZE_STRIDE_HIGH 0x17C + +#define KERNEL_TENSOR_4_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_4_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_4_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_4_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_4_DIM_1_SIZE_STRIDE_HIGH 0x180 + +#define KERNEL_TENSOR_4_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_4_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_4_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_4_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_4_DIM_2_SIZE_STRIDE_HIGH 0x184 + +#define KERNEL_TENSOR_4_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_4_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_4_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_4_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_4_DIM_3_SIZE_STRIDE_HIGH 0x188 + +#define KERNEL_TENSOR_4_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_4_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_4_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_4_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_4_DIM_4_SIZE_STRIDE_HIGH 0x18C + +#define KERNEL_TENSOR_4_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_4_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_4_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_4_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_5_BASE_ADDR_LOW 0x190 + +#define KERNEL_TENSOR_5_BASE_ADDR_LOW_V_SHIFT 0 +#define KERNEL_TENSOR_5_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_5_BASE_ADDR_HIGH 0x194 + +#define KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT 0 +#define KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_5_PADDING_VALUE 0x198 + +#define KERNEL_TENSOR_5_PADDING_VALUE_V_SHIFT 0 +#define KERNEL_TENSOR_5_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_5_TENSOR_CONFIG 0x19C + +#define KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define KERNEL_TENSOR_5_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define KERNEL_TENSOR_5_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define KERNEL_TENSOR_5_TENSOR_CONFIG_L0CD_SHIFT 25 +#define KERNEL_TENSOR_5_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define KERNEL_TENSOR_5_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define KERNEL_TENSOR_5_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define KERNEL_TENSOR_5_DIM_0_SIZE 0x1A0 + +#define KERNEL_TENSOR_5_DIM_0_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_5_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_5_DIM_0_STRIDE 0x1A4 + +#define KERNEL_TENSOR_5_DIM_0_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_5_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_5_DIM_1_SIZE 0x1A8 + +#define KERNEL_TENSOR_5_DIM_1_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_5_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_5_DIM_1_STRIDE 0x1AC + +#define KERNEL_TENSOR_5_DIM_1_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_5_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_5_DIM_2_SIZE 0x1B0 + +#define KERNEL_TENSOR_5_DIM_2_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_5_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_5_DIM_2_STRIDE 0x1B4 + +#define KERNEL_TENSOR_5_DIM_2_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_5_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_5_DIM_3_SIZE 0x1B8 + +#define KERNEL_TENSOR_5_DIM_3_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_5_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_5_DIM_3_STRIDE 0x1BC + +#define KERNEL_TENSOR_5_DIM_3_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_5_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_5_DIM_4_SIZE 0x1C0 + +#define KERNEL_TENSOR_5_DIM_4_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_5_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_5_DIM_4_STRIDE 0x1C4 + +#define KERNEL_TENSOR_5_DIM_4_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_5_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_5_PREF_STRIDE 0x1C8 + +#define KERNEL_TENSOR_5_PREF_STRIDE_VAL_SHIFT 0 +#define KERNEL_TENSOR_5_PREF_STRIDE_VAL_MASK 0xFFFF + +#define KERNEL_TENSOR_5_DIM_0_SIZE_STRIDE_HIGH 0x1CC + +#define KERNEL_TENSOR_5_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_5_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_5_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_5_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_5_DIM_1_SIZE_STRIDE_HIGH 0x1D0 + +#define KERNEL_TENSOR_5_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_5_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_5_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_5_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_5_DIM_2_SIZE_STRIDE_HIGH 0x1D4 + +#define KERNEL_TENSOR_5_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_5_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_5_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_5_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_5_DIM_3_SIZE_STRIDE_HIGH 0x1D8 + +#define KERNEL_TENSOR_5_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_5_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_5_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_5_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_5_DIM_4_SIZE_STRIDE_HIGH 0x1DC + +#define KERNEL_TENSOR_5_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_5_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_5_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_5_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_6_BASE_ADDR_LOW 0x1E0 + +#define KERNEL_TENSOR_6_BASE_ADDR_LOW_V_SHIFT 0 +#define KERNEL_TENSOR_6_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_6_BASE_ADDR_HIGH 0x1E4 + +#define KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT 0 +#define KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_6_PADDING_VALUE 0x1E8 + +#define KERNEL_TENSOR_6_PADDING_VALUE_V_SHIFT 0 +#define KERNEL_TENSOR_6_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_6_TENSOR_CONFIG 0x1EC + +#define KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define KERNEL_TENSOR_6_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define KERNEL_TENSOR_6_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define KERNEL_TENSOR_6_TENSOR_CONFIG_L0CD_SHIFT 25 +#define KERNEL_TENSOR_6_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define KERNEL_TENSOR_6_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define KERNEL_TENSOR_6_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define KERNEL_TENSOR_6_DIM_0_SIZE 0x1F0 + +#define KERNEL_TENSOR_6_DIM_0_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_6_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_6_DIM_0_STRIDE 0x1F4 + +#define KERNEL_TENSOR_6_DIM_0_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_6_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_6_DIM_1_SIZE 0x1F8 + +#define KERNEL_TENSOR_6_DIM_1_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_6_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_6_DIM_1_STRIDE 0x1FC + +#define KERNEL_TENSOR_6_DIM_1_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_6_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_6_DIM_2_SIZE 0x200 + +#define KERNEL_TENSOR_6_DIM_2_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_6_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_6_DIM_2_STRIDE 0x204 + +#define KERNEL_TENSOR_6_DIM_2_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_6_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_6_DIM_3_SIZE 0x208 + +#define KERNEL_TENSOR_6_DIM_3_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_6_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_6_DIM_3_STRIDE 0x20C + +#define KERNEL_TENSOR_6_DIM_3_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_6_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_6_DIM_4_SIZE 0x210 + +#define KERNEL_TENSOR_6_DIM_4_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_6_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_6_DIM_4_STRIDE 0x214 + +#define KERNEL_TENSOR_6_DIM_4_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_6_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_6_PREF_STRIDE 0x218 + +#define KERNEL_TENSOR_6_PREF_STRIDE_VAL_SHIFT 0 +#define KERNEL_TENSOR_6_PREF_STRIDE_VAL_MASK 0xFFFF + +#define KERNEL_TENSOR_6_DIM_0_SIZE_STRIDE_HIGH 0x21C + +#define KERNEL_TENSOR_6_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_6_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_6_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_6_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_6_DIM_1_SIZE_STRIDE_HIGH 0x220 + +#define KERNEL_TENSOR_6_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_6_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_6_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_6_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_6_DIM_2_SIZE_STRIDE_HIGH 0x224 + +#define KERNEL_TENSOR_6_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_6_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_6_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_6_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_6_DIM_3_SIZE_STRIDE_HIGH 0x228 + +#define KERNEL_TENSOR_6_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_6_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_6_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_6_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_6_DIM_4_SIZE_STRIDE_HIGH 0x22C + +#define KERNEL_TENSOR_6_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_6_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_6_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_6_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_7_BASE_ADDR_LOW 0x230 + +#define KERNEL_TENSOR_7_BASE_ADDR_LOW_V_SHIFT 0 +#define KERNEL_TENSOR_7_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_7_BASE_ADDR_HIGH 0x234 + +#define KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT 0 +#define KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_7_PADDING_VALUE 0x238 + +#define KERNEL_TENSOR_7_PADDING_VALUE_V_SHIFT 0 +#define KERNEL_TENSOR_7_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_7_TENSOR_CONFIG 0x23C + +#define KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define KERNEL_TENSOR_7_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define KERNEL_TENSOR_7_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define KERNEL_TENSOR_7_TENSOR_CONFIG_L0CD_SHIFT 25 +#define KERNEL_TENSOR_7_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define KERNEL_TENSOR_7_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define KERNEL_TENSOR_7_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define KERNEL_TENSOR_7_DIM_0_SIZE 0x240 + +#define KERNEL_TENSOR_7_DIM_0_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_7_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_7_DIM_0_STRIDE 0x244 + +#define KERNEL_TENSOR_7_DIM_0_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_7_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_7_DIM_1_SIZE 0x248 + +#define KERNEL_TENSOR_7_DIM_1_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_7_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_7_DIM_1_STRIDE 0x24C + +#define KERNEL_TENSOR_7_DIM_1_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_7_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_7_DIM_2_SIZE 0x250 + +#define KERNEL_TENSOR_7_DIM_2_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_7_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_7_DIM_2_STRIDE 0x254 + +#define KERNEL_TENSOR_7_DIM_2_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_7_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_7_DIM_3_SIZE 0x258 + +#define KERNEL_TENSOR_7_DIM_3_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_7_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_7_DIM_3_STRIDE 0x25C + +#define KERNEL_TENSOR_7_DIM_3_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_7_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_7_DIM_4_SIZE 0x260 + +#define KERNEL_TENSOR_7_DIM_4_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_7_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_7_DIM_4_STRIDE 0x264 + +#define KERNEL_TENSOR_7_DIM_4_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_7_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_7_PREF_STRIDE 0x268 + +#define KERNEL_TENSOR_7_PREF_STRIDE_VAL_SHIFT 0 +#define KERNEL_TENSOR_7_PREF_STRIDE_VAL_MASK 0xFFFF + +#define KERNEL_TENSOR_7_DIM_0_SIZE_STRIDE_HIGH 0x26C + +#define KERNEL_TENSOR_7_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_7_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_7_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_7_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_7_DIM_1_SIZE_STRIDE_HIGH 0x270 + +#define KERNEL_TENSOR_7_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_7_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_7_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_7_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_7_DIM_2_SIZE_STRIDE_HIGH 0x274 + +#define KERNEL_TENSOR_7_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_7_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_7_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_7_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_7_DIM_3_SIZE_STRIDE_HIGH 0x278 + +#define KERNEL_TENSOR_7_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_7_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_7_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_7_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_7_DIM_4_SIZE_STRIDE_HIGH 0x27C + +#define KERNEL_TENSOR_7_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_7_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_7_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_7_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_8_BASE_ADDR_LOW 0x280 + +#define KERNEL_TENSOR_8_BASE_ADDR_LOW_V_SHIFT 0 +#define KERNEL_TENSOR_8_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_8_BASE_ADDR_HIGH 0x284 + +#define KERNEL_TENSOR_8_BASE_ADDR_HIGH_V_SHIFT 0 +#define KERNEL_TENSOR_8_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_8_PADDING_VALUE 0x288 + +#define KERNEL_TENSOR_8_PADDING_VALUE_V_SHIFT 0 +#define KERNEL_TENSOR_8_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_8_TENSOR_CONFIG 0x28C + +#define KERNEL_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define KERNEL_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define KERNEL_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define KERNEL_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define KERNEL_TENSOR_8_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define KERNEL_TENSOR_8_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define KERNEL_TENSOR_8_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define KERNEL_TENSOR_8_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define KERNEL_TENSOR_8_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define KERNEL_TENSOR_8_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define KERNEL_TENSOR_8_TENSOR_CONFIG_L0CD_SHIFT 25 +#define KERNEL_TENSOR_8_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define KERNEL_TENSOR_8_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define KERNEL_TENSOR_8_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define KERNEL_TENSOR_8_DIM_0_SIZE 0x290 + +#define KERNEL_TENSOR_8_DIM_0_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_8_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_8_DIM_0_STRIDE 0x294 + +#define KERNEL_TENSOR_8_DIM_0_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_8_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_8_DIM_1_SIZE 0x298 + +#define KERNEL_TENSOR_8_DIM_1_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_8_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_8_DIM_1_STRIDE 0x29C + +#define KERNEL_TENSOR_8_DIM_1_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_8_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_8_DIM_2_SIZE 0x2A0 + +#define KERNEL_TENSOR_8_DIM_2_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_8_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_8_DIM_2_STRIDE 0x2A4 + +#define KERNEL_TENSOR_8_DIM_2_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_8_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_8_DIM_3_SIZE 0x2A8 + +#define KERNEL_TENSOR_8_DIM_3_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_8_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_8_DIM_3_STRIDE 0x2AC + +#define KERNEL_TENSOR_8_DIM_3_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_8_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_8_DIM_4_SIZE 0x2B0 + +#define KERNEL_TENSOR_8_DIM_4_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_8_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_8_DIM_4_STRIDE 0x2B4 + +#define KERNEL_TENSOR_8_DIM_4_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_8_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_8_PREF_STRIDE 0x2B8 + +#define KERNEL_TENSOR_8_PREF_STRIDE_VAL_SHIFT 0 +#define KERNEL_TENSOR_8_PREF_STRIDE_VAL_MASK 0xFFFF + +#define KERNEL_TENSOR_8_DIM_0_SIZE_STRIDE_HIGH 0x2BC + +#define KERNEL_TENSOR_8_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_8_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_8_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_8_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_8_DIM_1_SIZE_STRIDE_HIGH 0x2C0 + +#define KERNEL_TENSOR_8_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_8_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_8_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_8_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_8_DIM_2_SIZE_STRIDE_HIGH 0x2C4 + +#define KERNEL_TENSOR_8_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_8_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_8_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_8_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_8_DIM_3_SIZE_STRIDE_HIGH 0x2C8 + +#define KERNEL_TENSOR_8_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_8_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_8_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_8_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_8_DIM_4_SIZE_STRIDE_HIGH 0x2CC + +#define KERNEL_TENSOR_8_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_8_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_8_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_8_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_9_BASE_ADDR_LOW 0x2D0 + +#define KERNEL_TENSOR_9_BASE_ADDR_LOW_V_SHIFT 0 +#define KERNEL_TENSOR_9_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_9_BASE_ADDR_HIGH 0x2D4 + +#define KERNEL_TENSOR_9_BASE_ADDR_HIGH_V_SHIFT 0 +#define KERNEL_TENSOR_9_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_9_PADDING_VALUE 0x2D8 + +#define KERNEL_TENSOR_9_PADDING_VALUE_V_SHIFT 0 +#define KERNEL_TENSOR_9_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_9_TENSOR_CONFIG 0x2DC + +#define KERNEL_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define KERNEL_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define KERNEL_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define KERNEL_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define KERNEL_TENSOR_9_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define KERNEL_TENSOR_9_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define KERNEL_TENSOR_9_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define KERNEL_TENSOR_9_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define KERNEL_TENSOR_9_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define KERNEL_TENSOR_9_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define KERNEL_TENSOR_9_TENSOR_CONFIG_L0CD_SHIFT 25 +#define KERNEL_TENSOR_9_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define KERNEL_TENSOR_9_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define KERNEL_TENSOR_9_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define KERNEL_TENSOR_9_DIM_0_SIZE 0x2E0 + +#define KERNEL_TENSOR_9_DIM_0_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_9_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_9_DIM_0_STRIDE 0x2E4 + +#define KERNEL_TENSOR_9_DIM_0_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_9_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_9_DIM_1_SIZE 0x2E8 + +#define KERNEL_TENSOR_9_DIM_1_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_9_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_9_DIM_1_STRIDE 0x2EC + +#define KERNEL_TENSOR_9_DIM_1_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_9_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_9_DIM_2_SIZE 0x2F0 + +#define KERNEL_TENSOR_9_DIM_2_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_9_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_9_DIM_2_STRIDE 0x2F4 + +#define KERNEL_TENSOR_9_DIM_2_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_9_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_9_DIM_3_SIZE 0x2F8 + +#define KERNEL_TENSOR_9_DIM_3_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_9_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_9_DIM_3_STRIDE 0x2FC + +#define KERNEL_TENSOR_9_DIM_3_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_9_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_9_DIM_4_SIZE 0x300 + +#define KERNEL_TENSOR_9_DIM_4_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_9_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_9_DIM_4_STRIDE 0x304 + +#define KERNEL_TENSOR_9_DIM_4_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_9_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_9_PREF_STRIDE 0x308 + +#define KERNEL_TENSOR_9_PREF_STRIDE_VAL_SHIFT 0 +#define KERNEL_TENSOR_9_PREF_STRIDE_VAL_MASK 0xFFFF + +#define KERNEL_TENSOR_9_DIM_0_SIZE_STRIDE_HIGH 0x30C + +#define KERNEL_TENSOR_9_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_9_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_9_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_9_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_9_DIM_1_SIZE_STRIDE_HIGH 0x310 + +#define KERNEL_TENSOR_9_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_9_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_9_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_9_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_9_DIM_2_SIZE_STRIDE_HIGH 0x314 + +#define KERNEL_TENSOR_9_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_9_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_9_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_9_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_9_DIM_3_SIZE_STRIDE_HIGH 0x318 + +#define KERNEL_TENSOR_9_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_9_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_9_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_9_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_9_DIM_4_SIZE_STRIDE_HIGH 0x31C + +#define KERNEL_TENSOR_9_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_9_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_9_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_9_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_10_BASE_ADDR_LOW 0x320 + +#define KERNEL_TENSOR_10_BASE_ADDR_LOW_V_SHIFT 0 +#define KERNEL_TENSOR_10_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_10_BASE_ADDR_HIGH 0x324 + +#define KERNEL_TENSOR_10_BASE_ADDR_HIGH_V_SHIFT 0 +#define KERNEL_TENSOR_10_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_10_PADDING_VALUE 0x328 + +#define KERNEL_TENSOR_10_PADDING_VALUE_V_SHIFT 0 +#define KERNEL_TENSOR_10_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_10_TENSOR_CONFIG 0x32C + +#define KERNEL_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define KERNEL_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define KERNEL_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define KERNEL_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define KERNEL_TENSOR_10_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define KERNEL_TENSOR_10_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define KERNEL_TENSOR_10_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define KERNEL_TENSOR_10_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define KERNEL_TENSOR_10_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define KERNEL_TENSOR_10_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define KERNEL_TENSOR_10_TENSOR_CONFIG_L0CD_SHIFT 25 +#define KERNEL_TENSOR_10_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define KERNEL_TENSOR_10_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define KERNEL_TENSOR_10_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define KERNEL_TENSOR_10_DIM_0_SIZE 0x330 + +#define KERNEL_TENSOR_10_DIM_0_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_10_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_10_DIM_0_STRIDE 0x334 + +#define KERNEL_TENSOR_10_DIM_0_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_10_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_10_DIM_1_SIZE 0x338 + +#define KERNEL_TENSOR_10_DIM_1_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_10_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_10_DIM_1_STRIDE 0x33C + +#define KERNEL_TENSOR_10_DIM_1_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_10_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_10_DIM_2_SIZE 0x340 + +#define KERNEL_TENSOR_10_DIM_2_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_10_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_10_DIM_2_STRIDE 0x344 + +#define KERNEL_TENSOR_10_DIM_2_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_10_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_10_DIM_3_SIZE 0x348 + +#define KERNEL_TENSOR_10_DIM_3_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_10_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_10_DIM_3_STRIDE 0x34C + +#define KERNEL_TENSOR_10_DIM_3_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_10_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_10_DIM_4_SIZE 0x350 + +#define KERNEL_TENSOR_10_DIM_4_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_10_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_10_DIM_4_STRIDE 0x354 + +#define KERNEL_TENSOR_10_DIM_4_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_10_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_10_PREF_STRIDE 0x358 + +#define KERNEL_TENSOR_10_PREF_STRIDE_VAL_SHIFT 0 +#define KERNEL_TENSOR_10_PREF_STRIDE_VAL_MASK 0xFFFF + +#define KERNEL_TENSOR_10_DIM_0_SIZE_STRIDE_HIGH 0x35C + +#define KERNEL_TENSOR_10_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_10_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_10_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_10_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_10_DIM_1_SIZE_STRIDE_HIGH 0x360 + +#define KERNEL_TENSOR_10_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_10_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_10_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_10_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_10_DIM_2_SIZE_STRIDE_HIGH 0x364 + +#define KERNEL_TENSOR_10_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_10_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_10_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_10_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_10_DIM_3_SIZE_STRIDE_HIGH 0x368 + +#define KERNEL_TENSOR_10_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_10_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_10_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_10_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_10_DIM_4_SIZE_STRIDE_HIGH 0x36C + +#define KERNEL_TENSOR_10_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_10_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_10_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_10_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_11_BASE_ADDR_LOW 0x370 + +#define KERNEL_TENSOR_11_BASE_ADDR_LOW_V_SHIFT 0 +#define KERNEL_TENSOR_11_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_11_BASE_ADDR_HIGH 0x374 + +#define KERNEL_TENSOR_11_BASE_ADDR_HIGH_V_SHIFT 0 +#define KERNEL_TENSOR_11_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_11_PADDING_VALUE 0x378 + +#define KERNEL_TENSOR_11_PADDING_VALUE_V_SHIFT 0 +#define KERNEL_TENSOR_11_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_11_TENSOR_CONFIG 0x37C + +#define KERNEL_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define KERNEL_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define KERNEL_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define KERNEL_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define KERNEL_TENSOR_11_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define KERNEL_TENSOR_11_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define KERNEL_TENSOR_11_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define KERNEL_TENSOR_11_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define KERNEL_TENSOR_11_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define KERNEL_TENSOR_11_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define KERNEL_TENSOR_11_TENSOR_CONFIG_L0CD_SHIFT 25 +#define KERNEL_TENSOR_11_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define KERNEL_TENSOR_11_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define KERNEL_TENSOR_11_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define KERNEL_TENSOR_11_DIM_0_SIZE 0x380 + +#define KERNEL_TENSOR_11_DIM_0_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_11_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_11_DIM_0_STRIDE 0x384 + +#define KERNEL_TENSOR_11_DIM_0_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_11_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_11_DIM_1_SIZE 0x388 + +#define KERNEL_TENSOR_11_DIM_1_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_11_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_11_DIM_1_STRIDE 0x38C + +#define KERNEL_TENSOR_11_DIM_1_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_11_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_11_DIM_2_SIZE 0x390 + +#define KERNEL_TENSOR_11_DIM_2_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_11_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_11_DIM_2_STRIDE 0x394 + +#define KERNEL_TENSOR_11_DIM_2_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_11_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_11_DIM_3_SIZE 0x398 + +#define KERNEL_TENSOR_11_DIM_3_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_11_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_11_DIM_3_STRIDE 0x39C + +#define KERNEL_TENSOR_11_DIM_3_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_11_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_11_DIM_4_SIZE 0x3A0 + +#define KERNEL_TENSOR_11_DIM_4_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_11_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_11_DIM_4_STRIDE 0x3A4 + +#define KERNEL_TENSOR_11_DIM_4_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_11_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_11_PREF_STRIDE 0x3A8 + +#define KERNEL_TENSOR_11_PREF_STRIDE_VAL_SHIFT 0 +#define KERNEL_TENSOR_11_PREF_STRIDE_VAL_MASK 0xFFFF + +#define KERNEL_TENSOR_11_DIM_0_SIZE_STRIDE_HIGH 0x3AC + +#define KERNEL_TENSOR_11_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_11_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_11_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_11_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_11_DIM_1_SIZE_STRIDE_HIGH 0x3B0 + +#define KERNEL_TENSOR_11_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_11_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_11_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_11_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_11_DIM_2_SIZE_STRIDE_HIGH 0x3B4 + +#define KERNEL_TENSOR_11_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_11_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_11_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_11_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_11_DIM_3_SIZE_STRIDE_HIGH 0x3B8 + +#define KERNEL_TENSOR_11_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_11_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_11_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_11_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_11_DIM_4_SIZE_STRIDE_HIGH 0x3BC + +#define KERNEL_TENSOR_11_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_11_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_11_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_11_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_12_BASE_ADDR_LOW 0x3C0 + +#define KERNEL_TENSOR_12_BASE_ADDR_LOW_V_SHIFT 0 +#define KERNEL_TENSOR_12_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_12_BASE_ADDR_HIGH 0x3C4 + +#define KERNEL_TENSOR_12_BASE_ADDR_HIGH_V_SHIFT 0 +#define KERNEL_TENSOR_12_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_12_PADDING_VALUE 0x3C8 + +#define KERNEL_TENSOR_12_PADDING_VALUE_V_SHIFT 0 +#define KERNEL_TENSOR_12_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_12_TENSOR_CONFIG 0x3CC + +#define KERNEL_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define KERNEL_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define KERNEL_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define KERNEL_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define KERNEL_TENSOR_12_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define KERNEL_TENSOR_12_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define KERNEL_TENSOR_12_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define KERNEL_TENSOR_12_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define KERNEL_TENSOR_12_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define KERNEL_TENSOR_12_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define KERNEL_TENSOR_12_TENSOR_CONFIG_L0CD_SHIFT 25 +#define KERNEL_TENSOR_12_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define KERNEL_TENSOR_12_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define KERNEL_TENSOR_12_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define KERNEL_TENSOR_12_DIM_0_SIZE 0x3D0 + +#define KERNEL_TENSOR_12_DIM_0_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_12_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_12_DIM_0_STRIDE 0x3D4 + +#define KERNEL_TENSOR_12_DIM_0_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_12_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_12_DIM_1_SIZE 0x3D8 + +#define KERNEL_TENSOR_12_DIM_1_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_12_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_12_DIM_1_STRIDE 0x3DC + +#define KERNEL_TENSOR_12_DIM_1_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_12_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_12_DIM_2_SIZE 0x3E0 + +#define KERNEL_TENSOR_12_DIM_2_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_12_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_12_DIM_2_STRIDE 0x3E4 + +#define KERNEL_TENSOR_12_DIM_2_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_12_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_12_DIM_3_SIZE 0x3E8 + +#define KERNEL_TENSOR_12_DIM_3_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_12_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_12_DIM_3_STRIDE 0x3EC + +#define KERNEL_TENSOR_12_DIM_3_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_12_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_12_DIM_4_SIZE 0x3F0 + +#define KERNEL_TENSOR_12_DIM_4_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_12_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_12_DIM_4_STRIDE 0x3F4 + +#define KERNEL_TENSOR_12_DIM_4_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_12_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_12_PREF_STRIDE 0x3F8 + +#define KERNEL_TENSOR_12_PREF_STRIDE_VAL_SHIFT 0 +#define KERNEL_TENSOR_12_PREF_STRIDE_VAL_MASK 0xFFFF + +#define KERNEL_TENSOR_12_DIM_0_SIZE_STRIDE_HIGH 0x3FC + +#define KERNEL_TENSOR_12_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_12_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_12_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_12_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_12_DIM_1_SIZE_STRIDE_HIGH 0x400 + +#define KERNEL_TENSOR_12_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_12_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_12_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_12_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_12_DIM_2_SIZE_STRIDE_HIGH 0x404 + +#define KERNEL_TENSOR_12_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_12_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_12_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_12_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_12_DIM_3_SIZE_STRIDE_HIGH 0x408 + +#define KERNEL_TENSOR_12_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_12_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_12_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_12_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_12_DIM_4_SIZE_STRIDE_HIGH 0x40C + +#define KERNEL_TENSOR_12_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_12_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_12_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_12_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_13_BASE_ADDR_LOW 0x410 + +#define KERNEL_TENSOR_13_BASE_ADDR_LOW_V_SHIFT 0 +#define KERNEL_TENSOR_13_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_13_BASE_ADDR_HIGH 0x414 + +#define KERNEL_TENSOR_13_BASE_ADDR_HIGH_V_SHIFT 0 +#define KERNEL_TENSOR_13_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_13_PADDING_VALUE 0x418 + +#define KERNEL_TENSOR_13_PADDING_VALUE_V_SHIFT 0 +#define KERNEL_TENSOR_13_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_13_TENSOR_CONFIG 0x41C + +#define KERNEL_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define KERNEL_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define KERNEL_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define KERNEL_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define KERNEL_TENSOR_13_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define KERNEL_TENSOR_13_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define KERNEL_TENSOR_13_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define KERNEL_TENSOR_13_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define KERNEL_TENSOR_13_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define KERNEL_TENSOR_13_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define KERNEL_TENSOR_13_TENSOR_CONFIG_L0CD_SHIFT 25 +#define KERNEL_TENSOR_13_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define KERNEL_TENSOR_13_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define KERNEL_TENSOR_13_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define KERNEL_TENSOR_13_DIM_0_SIZE 0x420 + +#define KERNEL_TENSOR_13_DIM_0_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_13_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_13_DIM_0_STRIDE 0x424 + +#define KERNEL_TENSOR_13_DIM_0_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_13_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_13_DIM_1_SIZE 0x428 + +#define KERNEL_TENSOR_13_DIM_1_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_13_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_13_DIM_1_STRIDE 0x42C + +#define KERNEL_TENSOR_13_DIM_1_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_13_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_13_DIM_2_SIZE 0x430 + +#define KERNEL_TENSOR_13_DIM_2_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_13_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_13_DIM_2_STRIDE 0x434 + +#define KERNEL_TENSOR_13_DIM_2_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_13_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_13_DIM_3_SIZE 0x438 + +#define KERNEL_TENSOR_13_DIM_3_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_13_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_13_DIM_3_STRIDE 0x43C + +#define KERNEL_TENSOR_13_DIM_3_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_13_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_13_DIM_4_SIZE 0x440 + +#define KERNEL_TENSOR_13_DIM_4_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_13_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_13_DIM_4_STRIDE 0x444 + +#define KERNEL_TENSOR_13_DIM_4_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_13_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_13_PREF_STRIDE 0x448 + +#define KERNEL_TENSOR_13_PREF_STRIDE_VAL_SHIFT 0 +#define KERNEL_TENSOR_13_PREF_STRIDE_VAL_MASK 0xFFFF + +#define KERNEL_TENSOR_13_DIM_0_SIZE_STRIDE_HIGH 0x44C + +#define KERNEL_TENSOR_13_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_13_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_13_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_13_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_13_DIM_1_SIZE_STRIDE_HIGH 0x450 + +#define KERNEL_TENSOR_13_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_13_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_13_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_13_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_13_DIM_2_SIZE_STRIDE_HIGH 0x454 + +#define KERNEL_TENSOR_13_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_13_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_13_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_13_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_13_DIM_3_SIZE_STRIDE_HIGH 0x458 + +#define KERNEL_TENSOR_13_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_13_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_13_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_13_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_13_DIM_4_SIZE_STRIDE_HIGH 0x45C + +#define KERNEL_TENSOR_13_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_13_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_13_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_13_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_14_BASE_ADDR_LOW 0x460 + +#define KERNEL_TENSOR_14_BASE_ADDR_LOW_V_SHIFT 0 +#define KERNEL_TENSOR_14_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_14_BASE_ADDR_HIGH 0x464 + +#define KERNEL_TENSOR_14_BASE_ADDR_HIGH_V_SHIFT 0 +#define KERNEL_TENSOR_14_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_14_PADDING_VALUE 0x468 + +#define KERNEL_TENSOR_14_PADDING_VALUE_V_SHIFT 0 +#define KERNEL_TENSOR_14_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_14_TENSOR_CONFIG 0x46C + +#define KERNEL_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define KERNEL_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define KERNEL_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define KERNEL_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define KERNEL_TENSOR_14_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define KERNEL_TENSOR_14_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define KERNEL_TENSOR_14_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define KERNEL_TENSOR_14_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define KERNEL_TENSOR_14_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define KERNEL_TENSOR_14_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define KERNEL_TENSOR_14_TENSOR_CONFIG_L0CD_SHIFT 25 +#define KERNEL_TENSOR_14_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define KERNEL_TENSOR_14_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define KERNEL_TENSOR_14_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define KERNEL_TENSOR_14_DIM_0_SIZE 0x470 + +#define KERNEL_TENSOR_14_DIM_0_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_14_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_14_DIM_0_STRIDE 0x474 + +#define KERNEL_TENSOR_14_DIM_0_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_14_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_14_DIM_1_SIZE 0x478 + +#define KERNEL_TENSOR_14_DIM_1_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_14_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_14_DIM_1_STRIDE 0x47C + +#define KERNEL_TENSOR_14_DIM_1_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_14_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_14_DIM_2_SIZE 0x480 + +#define KERNEL_TENSOR_14_DIM_2_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_14_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_14_DIM_2_STRIDE 0x484 + +#define KERNEL_TENSOR_14_DIM_2_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_14_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_14_DIM_3_SIZE 0x488 + +#define KERNEL_TENSOR_14_DIM_3_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_14_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_14_DIM_3_STRIDE 0x48C + +#define KERNEL_TENSOR_14_DIM_3_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_14_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_14_DIM_4_SIZE 0x490 + +#define KERNEL_TENSOR_14_DIM_4_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_14_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_14_DIM_4_STRIDE 0x494 + +#define KERNEL_TENSOR_14_DIM_4_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_14_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_14_PREF_STRIDE 0x498 + +#define KERNEL_TENSOR_14_PREF_STRIDE_VAL_SHIFT 0 +#define KERNEL_TENSOR_14_PREF_STRIDE_VAL_MASK 0xFFFF + +#define KERNEL_TENSOR_14_DIM_0_SIZE_STRIDE_HIGH 0x49C + +#define KERNEL_TENSOR_14_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_14_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_14_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_14_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_14_DIM_1_SIZE_STRIDE_HIGH 0x4A0 + +#define KERNEL_TENSOR_14_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_14_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_14_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_14_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_14_DIM_2_SIZE_STRIDE_HIGH 0x4A4 + +#define KERNEL_TENSOR_14_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_14_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_14_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_14_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_14_DIM_3_SIZE_STRIDE_HIGH 0x4A8 + +#define KERNEL_TENSOR_14_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_14_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_14_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_14_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_14_DIM_4_SIZE_STRIDE_HIGH 0x4AC + +#define KERNEL_TENSOR_14_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_14_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_14_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_14_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_15_BASE_ADDR_LOW 0x4B0 + +#define KERNEL_TENSOR_15_BASE_ADDR_LOW_V_SHIFT 0 +#define KERNEL_TENSOR_15_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_15_BASE_ADDR_HIGH 0x4B4 + +#define KERNEL_TENSOR_15_BASE_ADDR_HIGH_V_SHIFT 0 +#define KERNEL_TENSOR_15_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_15_PADDING_VALUE 0x4B8 + +#define KERNEL_TENSOR_15_PADDING_VALUE_V_SHIFT 0 +#define KERNEL_TENSOR_15_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_15_TENSOR_CONFIG 0x4BC + +#define KERNEL_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define KERNEL_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define KERNEL_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define KERNEL_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define KERNEL_TENSOR_15_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define KERNEL_TENSOR_15_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define KERNEL_TENSOR_15_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define KERNEL_TENSOR_15_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define KERNEL_TENSOR_15_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define KERNEL_TENSOR_15_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define KERNEL_TENSOR_15_TENSOR_CONFIG_L0CD_SHIFT 25 +#define KERNEL_TENSOR_15_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define KERNEL_TENSOR_15_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define KERNEL_TENSOR_15_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define KERNEL_TENSOR_15_DIM_0_SIZE 0x4C0 + +#define KERNEL_TENSOR_15_DIM_0_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_15_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_15_DIM_0_STRIDE 0x4C4 + +#define KERNEL_TENSOR_15_DIM_0_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_15_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_15_DIM_1_SIZE 0x4C8 + +#define KERNEL_TENSOR_15_DIM_1_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_15_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_15_DIM_1_STRIDE 0x4CC + +#define KERNEL_TENSOR_15_DIM_1_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_15_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_15_DIM_2_SIZE 0x4D0 + +#define KERNEL_TENSOR_15_DIM_2_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_15_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_15_DIM_2_STRIDE 0x4D4 + +#define KERNEL_TENSOR_15_DIM_2_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_15_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_15_DIM_3_SIZE 0x4D8 + +#define KERNEL_TENSOR_15_DIM_3_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_15_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_15_DIM_3_STRIDE 0x4DC + +#define KERNEL_TENSOR_15_DIM_3_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_15_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_15_DIM_4_SIZE 0x4E0 + +#define KERNEL_TENSOR_15_DIM_4_SIZE_V_SHIFT 0 +#define KERNEL_TENSOR_15_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_15_DIM_4_STRIDE 0x4E4 + +#define KERNEL_TENSOR_15_DIM_4_STRIDE_V_SHIFT 0 +#define KERNEL_TENSOR_15_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define KERNEL_TENSOR_15_PREF_STRIDE 0x4E8 + +#define KERNEL_TENSOR_15_PREF_STRIDE_VAL_SHIFT 0 +#define KERNEL_TENSOR_15_PREF_STRIDE_VAL_MASK 0xFFFF + +#define KERNEL_TENSOR_15_DIM_0_SIZE_STRIDE_HIGH 0x4EC + +#define KERNEL_TENSOR_15_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_15_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_15_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_15_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_15_DIM_1_SIZE_STRIDE_HIGH 0x4F0 + +#define KERNEL_TENSOR_15_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_15_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_15_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_15_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_15_DIM_2_SIZE_STRIDE_HIGH 0x4F4 + +#define KERNEL_TENSOR_15_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_15_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_15_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_15_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_15_DIM_3_SIZE_STRIDE_HIGH 0x4F8 + +#define KERNEL_TENSOR_15_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_15_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_15_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_15_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TENSOR_15_DIM_4_SIZE_STRIDE_HIGH 0x4FC + +#define KERNEL_TENSOR_15_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define KERNEL_TENSOR_15_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define KERNEL_TENSOR_15_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define KERNEL_TENSOR_15_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_SYNC_OBJECT_MESSAGE 0x500 + +#define KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0 +#define KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF +#define KERNEL_SYNC_OBJECT_MESSAGE_RSV_SHIFT 16 +#define KERNEL_SYNC_OBJECT_MESSAGE_RSV_MASK 0x1FFF0000 +#define KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 29 +#define KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0xE0000000 + +#define KERNEL_SYNC_OBJECT_ADDR 0x504 + +#define KERNEL_SYNC_OBJECT_ADDR_V_SHIFT 0 +#define KERNEL_SYNC_OBJECT_ADDR_V_MASK 0xFFFFFFFF + +#define KERNEL_KERNEL_BASE_ADDRESS_LOW 0x508 + +#define KERNEL_KERNEL_BASE_ADDRESS_LOW_V_SHIFT 0 +#define KERNEL_KERNEL_BASE_ADDRESS_LOW_V_MASK 0xFFFFFFFF + +#define KERNEL_KERNEL_BASE_ADDRESS_HIGH 0x50C + +#define KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +#define KERNEL_TID_BASE_DIM_0 0x510 + +#define KERNEL_TID_BASE_DIM_0_V_SHIFT 0 +#define KERNEL_TID_BASE_DIM_0_V_MASK 0xFFFFFFFF + +#define KERNEL_TID_SIZE_DIM_0 0x514 + +#define KERNEL_TID_SIZE_DIM_0_V_SHIFT 0 +#define KERNEL_TID_SIZE_DIM_0_V_MASK 0xFFFFFFFF + +#define KERNEL_TID_BASE_DIM_1 0x518 + +#define KERNEL_TID_BASE_DIM_1_V_SHIFT 0 +#define KERNEL_TID_BASE_DIM_1_V_MASK 0xFFFFFFFF + +#define KERNEL_TID_SIZE_DIM_1 0x51C + +#define KERNEL_TID_SIZE_DIM_1_V_SHIFT 0 +#define KERNEL_TID_SIZE_DIM_1_V_MASK 0xFFFFFFFF + +#define KERNEL_TID_BASE_DIM_2 0x520 + +#define KERNEL_TID_BASE_DIM_2_V_SHIFT 0 +#define KERNEL_TID_BASE_DIM_2_V_MASK 0xFFFFFFFF + +#define KERNEL_TID_SIZE_DIM_2 0x524 + +#define KERNEL_TID_SIZE_DIM_2_V_SHIFT 0 +#define KERNEL_TID_SIZE_DIM_2_V_MASK 0xFFFFFFFF + +#define KERNEL_TID_BASE_DIM_3 0x528 + +#define KERNEL_TID_BASE_DIM_3_V_SHIFT 0 +#define KERNEL_TID_BASE_DIM_3_V_MASK 0xFFFFFFFF + +#define KERNEL_TID_SIZE_DIM_3 0x52C + +#define KERNEL_TID_SIZE_DIM_3_V_SHIFT 0 +#define KERNEL_TID_SIZE_DIM_3_V_MASK 0xFFFFFFFF + +#define KERNEL_TID_BASE_DIM_4 0x530 + +#define KERNEL_TID_BASE_DIM_4_V_SHIFT 0 +#define KERNEL_TID_BASE_DIM_4_V_MASK 0xFFFFFFFF + +#define KERNEL_TID_SIZE_DIM_4 0x534 + +#define KERNEL_TID_SIZE_DIM_4_V_SHIFT 0 +#define KERNEL_TID_SIZE_DIM_4_V_MASK 0xFFFFFFFF + +#define KERNEL_KERNEL_CONFIG 0x538 + +#define KERNEL_KERNEL_CONFIG_SMALL_VLM_SHIFT 0 +#define KERNEL_KERNEL_CONFIG_SMALL_VLM_MASK 0x1 +#define KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT 1 +#define KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_MASK 0x2 +#define KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT 2 +#define KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_MASK 0xFC +#define KERNEL_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_SHIFT 8 +#define KERNEL_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_MASK 0xFF00 +#define KERNEL_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_SHIFT 16 +#define KERNEL_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_MASK 0xFF0000 +#define KERNEL_KERNEL_CONFIG_IRF_32BIT_COMPATIBILITY_SHIFT 24 +#define KERNEL_KERNEL_CONFIG_IRF_32BIT_COMPATIBILITY_MASK 0x1000000 + +#define KERNEL_KERNEL_ID 0x53C + +#define KERNEL_KERNEL_ID_V_SHIFT 0 +#define KERNEL_KERNEL_ID_V_MASK 0xFFFF + +#define KERNEL_POWER_LOOP 0x540 + +#define KERNEL_POWER_LOOP_START_EN_SHIFT 0 +#define KERNEL_POWER_LOOP_START_EN_MASK 0x1 +#define KERNEL_POWER_LOOP_END_EN_SHIFT 1 +#define KERNEL_POWER_LOOP_END_EN_MASK 0x2 +#define KERNEL_POWER_LOOP_PAYLOAD_SHIFT 4 +#define KERNEL_POWER_LOOP_PAYLOAD_MASK 0xFF0 + +#define KERNEL_SRF_0 0x544 + +#define KERNEL_SRF_0_V_SHIFT 0 +#define KERNEL_SRF_0_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_1 0x548 + +#define KERNEL_SRF_1_V_SHIFT 0 +#define KERNEL_SRF_1_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_2 0x54C + +#define KERNEL_SRF_2_V_SHIFT 0 +#define KERNEL_SRF_2_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_3 0x550 + +#define KERNEL_SRF_3_V_SHIFT 0 +#define KERNEL_SRF_3_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_4 0x554 + +#define KERNEL_SRF_4_V_SHIFT 0 +#define KERNEL_SRF_4_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_5 0x558 + +#define KERNEL_SRF_5_V_SHIFT 0 +#define KERNEL_SRF_5_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_6 0x55C + +#define KERNEL_SRF_6_V_SHIFT 0 +#define KERNEL_SRF_6_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_7 0x560 + +#define KERNEL_SRF_7_V_SHIFT 0 +#define KERNEL_SRF_7_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_8 0x564 + +#define KERNEL_SRF_8_V_SHIFT 0 +#define KERNEL_SRF_8_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_9 0x568 + +#define KERNEL_SRF_9_V_SHIFT 0 +#define KERNEL_SRF_9_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_10 0x56C + +#define KERNEL_SRF_10_V_SHIFT 0 +#define KERNEL_SRF_10_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_11 0x570 + +#define KERNEL_SRF_11_V_SHIFT 0 +#define KERNEL_SRF_11_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_12 0x574 + +#define KERNEL_SRF_12_V_SHIFT 0 +#define KERNEL_SRF_12_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_13 0x578 + +#define KERNEL_SRF_13_V_SHIFT 0 +#define KERNEL_SRF_13_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_14 0x57C + +#define KERNEL_SRF_14_V_SHIFT 0 +#define KERNEL_SRF_14_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_15 0x580 + +#define KERNEL_SRF_15_V_SHIFT 0 +#define KERNEL_SRF_15_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_16 0x584 + +#define KERNEL_SRF_16_V_SHIFT 0 +#define KERNEL_SRF_16_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_17 0x588 + +#define KERNEL_SRF_17_V_SHIFT 0 +#define KERNEL_SRF_17_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_18 0x58C + +#define KERNEL_SRF_18_V_SHIFT 0 +#define KERNEL_SRF_18_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_19 0x590 + +#define KERNEL_SRF_19_V_SHIFT 0 +#define KERNEL_SRF_19_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_20 0x594 + +#define KERNEL_SRF_20_V_SHIFT 0 +#define KERNEL_SRF_20_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_21 0x598 + +#define KERNEL_SRF_21_V_SHIFT 0 +#define KERNEL_SRF_21_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_22 0x59C + +#define KERNEL_SRF_22_V_SHIFT 0 +#define KERNEL_SRF_22_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_23 0x5A0 + +#define KERNEL_SRF_23_V_SHIFT 0 +#define KERNEL_SRF_23_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_24 0x5A4 + +#define KERNEL_SRF_24_V_SHIFT 0 +#define KERNEL_SRF_24_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_25 0x5A8 + +#define KERNEL_SRF_25_V_SHIFT 0 +#define KERNEL_SRF_25_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_26 0x5AC + +#define KERNEL_SRF_26_V_SHIFT 0 +#define KERNEL_SRF_26_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_27 0x5B0 + +#define KERNEL_SRF_27_V_SHIFT 0 +#define KERNEL_SRF_27_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_28 0x5B4 + +#define KERNEL_SRF_28_V_SHIFT 0 +#define KERNEL_SRF_28_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_29 0x5B8 + +#define KERNEL_SRF_29_V_SHIFT 0 +#define KERNEL_SRF_29_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_30 0x5BC + +#define KERNEL_SRF_30_V_SHIFT 0 +#define KERNEL_SRF_30_V_MASK 0xFFFFFFFF + +#define KERNEL_SRF_31 0x5C0 + +#define KERNEL_SRF_31_V_SHIFT 0 +#define KERNEL_SRF_31_V_MASK 0xFFFFFFFF + +#define KERNEL_KERNEL_ID_INC 0x5C4 + +#define KERNEL_KERNEL_ID_INC_V_SHIFT 0 +#define KERNEL_KERNEL_ID_INC_V_MASK 0xFF + +#define KERNEL_TID_BASE_SIZE_HIGH_DIM_0 0x5C8 + +#define KERNEL_TID_BASE_SIZE_HIGH_DIM_0_BASE_HIGH_SHIFT 0 +#define KERNEL_TID_BASE_SIZE_HIGH_DIM_0_BASE_HIGH_MASK 0xFFF +#define KERNEL_TID_BASE_SIZE_HIGH_DIM_0_SIZE_HIGH_SHIFT 16 +#define KERNEL_TID_BASE_SIZE_HIGH_DIM_0_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TID_BASE_SIZE_HIGH_DIM_1 0x5CC + +#define KERNEL_TID_BASE_SIZE_HIGH_DIM_1_BASE_HIGH_SHIFT 0 +#define KERNEL_TID_BASE_SIZE_HIGH_DIM_1_BASE_HIGH_MASK 0xFFF +#define KERNEL_TID_BASE_SIZE_HIGH_DIM_1_SIZE_HIGH_SHIFT 16 +#define KERNEL_TID_BASE_SIZE_HIGH_DIM_1_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TID_BASE_SIZE_HIGH_DIM_2 0x5D0 + +#define KERNEL_TID_BASE_SIZE_HIGH_DIM_2_BASE_HIGH_SHIFT 0 +#define KERNEL_TID_BASE_SIZE_HIGH_DIM_2_BASE_HIGH_MASK 0xFFF +#define KERNEL_TID_BASE_SIZE_HIGH_DIM_2_SIZE_HIGH_SHIFT 16 +#define KERNEL_TID_BASE_SIZE_HIGH_DIM_2_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TID_BASE_SIZE_HIGH_DIM_3 0x5D4 + +#define KERNEL_TID_BASE_SIZE_HIGH_DIM_3_BASE_HIGH_SHIFT 0 +#define KERNEL_TID_BASE_SIZE_HIGH_DIM_3_BASE_HIGH_MASK 0xFFF +#define KERNEL_TID_BASE_SIZE_HIGH_DIM_3_SIZE_HIGH_SHIFT 16 +#define KERNEL_TID_BASE_SIZE_HIGH_DIM_3_SIZE_HIGH_MASK 0xFFF0000 + +#define KERNEL_TID_BASE_SIZE_HIGH_DIM_4 0x5D8 + +#define KERNEL_TID_BASE_SIZE_HIGH_DIM_4_BASE_HIGH_SHIFT 0 +#define KERNEL_TID_BASE_SIZE_HIGH_DIM_4_BASE_HIGH_MASK 0xFFF +#define KERNEL_TID_BASE_SIZE_HIGH_DIM_4_SIZE_HIGH_SHIFT 16 +#define KERNEL_TID_BASE_SIZE_HIGH_DIM_4_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_0_BASE_ADDR_LOW 0x5DC + +#define QM_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0 +#define QM_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_0_BASE_ADDR_HIGH 0x5E0 + +#define QM_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0 +#define QM_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_0_PADDING_VALUE 0x5E4 + +#define QM_TENSOR_0_PADDING_VALUE_V_SHIFT 0 +#define QM_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_0_TENSOR_CONFIG 0x5E8 + +#define QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define QM_TENSOR_0_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define QM_TENSOR_0_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define QM_TENSOR_0_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define QM_TENSOR_0_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define QM_TENSOR_0_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define QM_TENSOR_0_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define QM_TENSOR_0_TENSOR_CONFIG_L0CD_SHIFT 25 +#define QM_TENSOR_0_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define QM_TENSOR_0_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define QM_TENSOR_0_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define QM_TENSOR_0_DIM_0_SIZE 0x5EC + +#define QM_TENSOR_0_DIM_0_SIZE_V_SHIFT 0 +#define QM_TENSOR_0_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_0_DIM_0_STRIDE 0x5F0 + +#define QM_TENSOR_0_DIM_0_STRIDE_V_SHIFT 0 +#define QM_TENSOR_0_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_0_DIM_1_SIZE 0x5F4 + +#define QM_TENSOR_0_DIM_1_SIZE_V_SHIFT 0 +#define QM_TENSOR_0_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_0_DIM_1_STRIDE 0x5F8 + +#define QM_TENSOR_0_DIM_1_STRIDE_V_SHIFT 0 +#define QM_TENSOR_0_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_0_DIM_2_SIZE 0x5FC + +#define QM_TENSOR_0_DIM_2_SIZE_V_SHIFT 0 +#define QM_TENSOR_0_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_0_DIM_2_STRIDE 0x600 + +#define QM_TENSOR_0_DIM_2_STRIDE_V_SHIFT 0 +#define QM_TENSOR_0_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_0_DIM_3_SIZE 0x604 + +#define QM_TENSOR_0_DIM_3_SIZE_V_SHIFT 0 +#define QM_TENSOR_0_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_0_DIM_3_STRIDE 0x608 + +#define QM_TENSOR_0_DIM_3_STRIDE_V_SHIFT 0 +#define QM_TENSOR_0_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_0_DIM_4_SIZE 0x60C + +#define QM_TENSOR_0_DIM_4_SIZE_V_SHIFT 0 +#define QM_TENSOR_0_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_0_DIM_4_STRIDE 0x610 + +#define QM_TENSOR_0_DIM_4_STRIDE_V_SHIFT 0 +#define QM_TENSOR_0_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_0_PREF_STRIDE 0x614 + +#define QM_TENSOR_0_PREF_STRIDE_VAL_SHIFT 0 +#define QM_TENSOR_0_PREF_STRIDE_VAL_MASK 0xFFFF + +#define QM_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH 0x618 + +#define QM_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH 0x61C + +#define QM_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH 0x620 + +#define QM_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH 0x624 + +#define QM_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH 0x628 + +#define QM_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_1_BASE_ADDR_LOW 0x62C + +#define QM_TENSOR_1_BASE_ADDR_LOW_V_SHIFT 0 +#define QM_TENSOR_1_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_1_BASE_ADDR_HIGH 0x630 + +#define QM_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT 0 +#define QM_TENSOR_1_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_1_PADDING_VALUE 0x634 + +#define QM_TENSOR_1_PADDING_VALUE_V_SHIFT 0 +#define QM_TENSOR_1_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_1_TENSOR_CONFIG 0x638 + +#define QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define QM_TENSOR_1_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define QM_TENSOR_1_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define QM_TENSOR_1_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define QM_TENSOR_1_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define QM_TENSOR_1_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define QM_TENSOR_1_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define QM_TENSOR_1_TENSOR_CONFIG_L0CD_SHIFT 25 +#define QM_TENSOR_1_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define QM_TENSOR_1_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define QM_TENSOR_1_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define QM_TENSOR_1_DIM_0_SIZE 0x63C + +#define QM_TENSOR_1_DIM_0_SIZE_V_SHIFT 0 +#define QM_TENSOR_1_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_1_DIM_0_STRIDE 0x640 + +#define QM_TENSOR_1_DIM_0_STRIDE_V_SHIFT 0 +#define QM_TENSOR_1_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_1_DIM_1_SIZE 0x644 + +#define QM_TENSOR_1_DIM_1_SIZE_V_SHIFT 0 +#define QM_TENSOR_1_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_1_DIM_1_STRIDE 0x648 + +#define QM_TENSOR_1_DIM_1_STRIDE_V_SHIFT 0 +#define QM_TENSOR_1_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_1_DIM_2_SIZE 0x64C + +#define QM_TENSOR_1_DIM_2_SIZE_V_SHIFT 0 +#define QM_TENSOR_1_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_1_DIM_2_STRIDE 0x650 + +#define QM_TENSOR_1_DIM_2_STRIDE_V_SHIFT 0 +#define QM_TENSOR_1_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_1_DIM_3_SIZE 0x654 + +#define QM_TENSOR_1_DIM_3_SIZE_V_SHIFT 0 +#define QM_TENSOR_1_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_1_DIM_3_STRIDE 0x658 + +#define QM_TENSOR_1_DIM_3_STRIDE_V_SHIFT 0 +#define QM_TENSOR_1_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_1_DIM_4_SIZE 0x65C + +#define QM_TENSOR_1_DIM_4_SIZE_V_SHIFT 0 +#define QM_TENSOR_1_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_1_DIM_4_STRIDE 0x660 + +#define QM_TENSOR_1_DIM_4_STRIDE_V_SHIFT 0 +#define QM_TENSOR_1_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_1_PREF_STRIDE 0x664 + +#define QM_TENSOR_1_PREF_STRIDE_VAL_SHIFT 0 +#define QM_TENSOR_1_PREF_STRIDE_VAL_MASK 0xFFFF + +#define QM_TENSOR_1_DIM_0_SIZE_STRIDE_HIGH 0x668 + +#define QM_TENSOR_1_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_1_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_1_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_1_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_1_DIM_1_SIZE_STRIDE_HIGH 0x66C + +#define QM_TENSOR_1_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_1_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_1_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_1_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_1_DIM_2_SIZE_STRIDE_HIGH 0x670 + +#define QM_TENSOR_1_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_1_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_1_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_1_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_1_DIM_3_SIZE_STRIDE_HIGH 0x674 + +#define QM_TENSOR_1_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_1_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_1_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_1_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_1_DIM_4_SIZE_STRIDE_HIGH 0x678 + +#define QM_TENSOR_1_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_1_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_1_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_1_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_2_BASE_ADDR_LOW 0x67C + +#define QM_TENSOR_2_BASE_ADDR_LOW_V_SHIFT 0 +#define QM_TENSOR_2_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_2_BASE_ADDR_HIGH 0x680 + +#define QM_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT 0 +#define QM_TENSOR_2_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_2_PADDING_VALUE 0x684 + +#define QM_TENSOR_2_PADDING_VALUE_V_SHIFT 0 +#define QM_TENSOR_2_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_2_TENSOR_CONFIG 0x688 + +#define QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define QM_TENSOR_2_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define QM_TENSOR_2_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define QM_TENSOR_2_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define QM_TENSOR_2_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define QM_TENSOR_2_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define QM_TENSOR_2_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define QM_TENSOR_2_TENSOR_CONFIG_L0CD_SHIFT 25 +#define QM_TENSOR_2_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define QM_TENSOR_2_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define QM_TENSOR_2_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define QM_TENSOR_2_DIM_0_SIZE 0x68C + +#define QM_TENSOR_2_DIM_0_SIZE_V_SHIFT 0 +#define QM_TENSOR_2_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_2_DIM_0_STRIDE 0x690 + +#define QM_TENSOR_2_DIM_0_STRIDE_V_SHIFT 0 +#define QM_TENSOR_2_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_2_DIM_1_SIZE 0x694 + +#define QM_TENSOR_2_DIM_1_SIZE_V_SHIFT 0 +#define QM_TENSOR_2_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_2_DIM_1_STRIDE 0x698 + +#define QM_TENSOR_2_DIM_1_STRIDE_V_SHIFT 0 +#define QM_TENSOR_2_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_2_DIM_2_SIZE 0x69C + +#define QM_TENSOR_2_DIM_2_SIZE_V_SHIFT 0 +#define QM_TENSOR_2_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_2_DIM_2_STRIDE 0x6A0 + +#define QM_TENSOR_2_DIM_2_STRIDE_V_SHIFT 0 +#define QM_TENSOR_2_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_2_DIM_3_SIZE 0x6A4 + +#define QM_TENSOR_2_DIM_3_SIZE_V_SHIFT 0 +#define QM_TENSOR_2_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_2_DIM_3_STRIDE 0x6A8 + +#define QM_TENSOR_2_DIM_3_STRIDE_V_SHIFT 0 +#define QM_TENSOR_2_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_2_DIM_4_SIZE 0x6AC + +#define QM_TENSOR_2_DIM_4_SIZE_V_SHIFT 0 +#define QM_TENSOR_2_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_2_DIM_4_STRIDE 0x6B0 + +#define QM_TENSOR_2_DIM_4_STRIDE_V_SHIFT 0 +#define QM_TENSOR_2_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_2_PREF_STRIDE 0x6B4 + +#define QM_TENSOR_2_PREF_STRIDE_VAL_SHIFT 0 +#define QM_TENSOR_2_PREF_STRIDE_VAL_MASK 0xFFFF + +#define QM_TENSOR_2_DIM_0_SIZE_STRIDE_HIGH 0x6B8 + +#define QM_TENSOR_2_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_2_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_2_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_2_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_2_DIM_1_SIZE_STRIDE_HIGH 0x6BC + +#define QM_TENSOR_2_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_2_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_2_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_2_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_2_DIM_2_SIZE_STRIDE_HIGH 0x6C0 + +#define QM_TENSOR_2_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_2_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_2_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_2_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_2_DIM_3_SIZE_STRIDE_HIGH 0x6C4 + +#define QM_TENSOR_2_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_2_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_2_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_2_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_2_DIM_4_SIZE_STRIDE_HIGH 0x6C8 + +#define QM_TENSOR_2_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_2_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_2_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_2_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_3_BASE_ADDR_LOW 0x6CC + +#define QM_TENSOR_3_BASE_ADDR_LOW_V_SHIFT 0 +#define QM_TENSOR_3_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_3_BASE_ADDR_HIGH 0x6D0 + +#define QM_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT 0 +#define QM_TENSOR_3_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_3_PADDING_VALUE 0x6D4 + +#define QM_TENSOR_3_PADDING_VALUE_V_SHIFT 0 +#define QM_TENSOR_3_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_3_TENSOR_CONFIG 0x6D8 + +#define QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define QM_TENSOR_3_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define QM_TENSOR_3_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define QM_TENSOR_3_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define QM_TENSOR_3_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define QM_TENSOR_3_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define QM_TENSOR_3_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define QM_TENSOR_3_TENSOR_CONFIG_L0CD_SHIFT 25 +#define QM_TENSOR_3_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define QM_TENSOR_3_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define QM_TENSOR_3_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define QM_TENSOR_3_DIM_0_SIZE 0x6DC + +#define QM_TENSOR_3_DIM_0_SIZE_V_SHIFT 0 +#define QM_TENSOR_3_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_3_DIM_0_STRIDE 0x6E0 + +#define QM_TENSOR_3_DIM_0_STRIDE_V_SHIFT 0 +#define QM_TENSOR_3_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_3_DIM_1_SIZE 0x6E4 + +#define QM_TENSOR_3_DIM_1_SIZE_V_SHIFT 0 +#define QM_TENSOR_3_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_3_DIM_1_STRIDE 0x6E8 + +#define QM_TENSOR_3_DIM_1_STRIDE_V_SHIFT 0 +#define QM_TENSOR_3_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_3_DIM_2_SIZE 0x6EC + +#define QM_TENSOR_3_DIM_2_SIZE_V_SHIFT 0 +#define QM_TENSOR_3_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_3_DIM_2_STRIDE 0x6F0 + +#define QM_TENSOR_3_DIM_2_STRIDE_V_SHIFT 0 +#define QM_TENSOR_3_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_3_DIM_3_SIZE 0x6F4 + +#define QM_TENSOR_3_DIM_3_SIZE_V_SHIFT 0 +#define QM_TENSOR_3_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_3_DIM_3_STRIDE 0x6F8 + +#define QM_TENSOR_3_DIM_3_STRIDE_V_SHIFT 0 +#define QM_TENSOR_3_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_3_DIM_4_SIZE 0x6FC + +#define QM_TENSOR_3_DIM_4_SIZE_V_SHIFT 0 +#define QM_TENSOR_3_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_3_DIM_4_STRIDE 0x700 + +#define QM_TENSOR_3_DIM_4_STRIDE_V_SHIFT 0 +#define QM_TENSOR_3_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_3_PREF_STRIDE 0x704 + +#define QM_TENSOR_3_PREF_STRIDE_VAL_SHIFT 0 +#define QM_TENSOR_3_PREF_STRIDE_VAL_MASK 0xFFFF + +#define QM_TENSOR_3_DIM_0_SIZE_STRIDE_HIGH 0x708 + +#define QM_TENSOR_3_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_3_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_3_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_3_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_3_DIM_1_SIZE_STRIDE_HIGH 0x70C + +#define QM_TENSOR_3_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_3_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_3_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_3_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_3_DIM_2_SIZE_STRIDE_HIGH 0x710 + +#define QM_TENSOR_3_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_3_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_3_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_3_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_3_DIM_3_SIZE_STRIDE_HIGH 0x714 + +#define QM_TENSOR_3_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_3_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_3_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_3_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_3_DIM_4_SIZE_STRIDE_HIGH 0x718 + +#define QM_TENSOR_3_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_3_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_3_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_3_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_4_BASE_ADDR_LOW 0x71C + +#define QM_TENSOR_4_BASE_ADDR_LOW_V_SHIFT 0 +#define QM_TENSOR_4_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_4_BASE_ADDR_HIGH 0x720 + +#define QM_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT 0 +#define QM_TENSOR_4_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_4_PADDING_VALUE 0x724 + +#define QM_TENSOR_4_PADDING_VALUE_V_SHIFT 0 +#define QM_TENSOR_4_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_4_TENSOR_CONFIG 0x728 + +#define QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define QM_TENSOR_4_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define QM_TENSOR_4_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define QM_TENSOR_4_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define QM_TENSOR_4_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define QM_TENSOR_4_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define QM_TENSOR_4_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define QM_TENSOR_4_TENSOR_CONFIG_L0CD_SHIFT 25 +#define QM_TENSOR_4_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define QM_TENSOR_4_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define QM_TENSOR_4_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define QM_TENSOR_4_DIM_0_SIZE 0x72C + +#define QM_TENSOR_4_DIM_0_SIZE_V_SHIFT 0 +#define QM_TENSOR_4_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_4_DIM_0_STRIDE 0x730 + +#define QM_TENSOR_4_DIM_0_STRIDE_V_SHIFT 0 +#define QM_TENSOR_4_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_4_DIM_1_SIZE 0x734 + +#define QM_TENSOR_4_DIM_1_SIZE_V_SHIFT 0 +#define QM_TENSOR_4_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_4_DIM_1_STRIDE 0x738 + +#define QM_TENSOR_4_DIM_1_STRIDE_V_SHIFT 0 +#define QM_TENSOR_4_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_4_DIM_2_SIZE 0x73C + +#define QM_TENSOR_4_DIM_2_SIZE_V_SHIFT 0 +#define QM_TENSOR_4_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_4_DIM_2_STRIDE 0x740 + +#define QM_TENSOR_4_DIM_2_STRIDE_V_SHIFT 0 +#define QM_TENSOR_4_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_4_DIM_3_SIZE 0x744 + +#define QM_TENSOR_4_DIM_3_SIZE_V_SHIFT 0 +#define QM_TENSOR_4_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_4_DIM_3_STRIDE 0x748 + +#define QM_TENSOR_4_DIM_3_STRIDE_V_SHIFT 0 +#define QM_TENSOR_4_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_4_DIM_4_SIZE 0x74C + +#define QM_TENSOR_4_DIM_4_SIZE_V_SHIFT 0 +#define QM_TENSOR_4_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_4_DIM_4_STRIDE 0x750 + +#define QM_TENSOR_4_DIM_4_STRIDE_V_SHIFT 0 +#define QM_TENSOR_4_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_4_PREF_STRIDE 0x754 + +#define QM_TENSOR_4_PREF_STRIDE_VAL_SHIFT 0 +#define QM_TENSOR_4_PREF_STRIDE_VAL_MASK 0xFFFF + +#define QM_TENSOR_4_DIM_0_SIZE_STRIDE_HIGH 0x758 + +#define QM_TENSOR_4_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_4_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_4_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_4_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_4_DIM_1_SIZE_STRIDE_HIGH 0x75C + +#define QM_TENSOR_4_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_4_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_4_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_4_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_4_DIM_2_SIZE_STRIDE_HIGH 0x760 + +#define QM_TENSOR_4_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_4_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_4_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_4_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_4_DIM_3_SIZE_STRIDE_HIGH 0x764 + +#define QM_TENSOR_4_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_4_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_4_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_4_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_4_DIM_4_SIZE_STRIDE_HIGH 0x768 + +#define QM_TENSOR_4_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_4_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_4_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_4_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_5_BASE_ADDR_LOW 0x76C + +#define QM_TENSOR_5_BASE_ADDR_LOW_V_SHIFT 0 +#define QM_TENSOR_5_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_5_BASE_ADDR_HIGH 0x770 + +#define QM_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT 0 +#define QM_TENSOR_5_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_5_PADDING_VALUE 0x774 + +#define QM_TENSOR_5_PADDING_VALUE_V_SHIFT 0 +#define QM_TENSOR_5_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_5_TENSOR_CONFIG 0x778 + +#define QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define QM_TENSOR_5_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define QM_TENSOR_5_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define QM_TENSOR_5_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define QM_TENSOR_5_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define QM_TENSOR_5_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define QM_TENSOR_5_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define QM_TENSOR_5_TENSOR_CONFIG_L0CD_SHIFT 25 +#define QM_TENSOR_5_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define QM_TENSOR_5_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define QM_TENSOR_5_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define QM_TENSOR_5_DIM_0_SIZE 0x77C + +#define QM_TENSOR_5_DIM_0_SIZE_V_SHIFT 0 +#define QM_TENSOR_5_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_5_DIM_0_STRIDE 0x780 + +#define QM_TENSOR_5_DIM_0_STRIDE_V_SHIFT 0 +#define QM_TENSOR_5_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_5_DIM_1_SIZE 0x784 + +#define QM_TENSOR_5_DIM_1_SIZE_V_SHIFT 0 +#define QM_TENSOR_5_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_5_DIM_1_STRIDE 0x788 + +#define QM_TENSOR_5_DIM_1_STRIDE_V_SHIFT 0 +#define QM_TENSOR_5_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_5_DIM_2_SIZE 0x78C + +#define QM_TENSOR_5_DIM_2_SIZE_V_SHIFT 0 +#define QM_TENSOR_5_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_5_DIM_2_STRIDE 0x790 + +#define QM_TENSOR_5_DIM_2_STRIDE_V_SHIFT 0 +#define QM_TENSOR_5_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_5_DIM_3_SIZE 0x794 + +#define QM_TENSOR_5_DIM_3_SIZE_V_SHIFT 0 +#define QM_TENSOR_5_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_5_DIM_3_STRIDE 0x798 + +#define QM_TENSOR_5_DIM_3_STRIDE_V_SHIFT 0 +#define QM_TENSOR_5_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_5_DIM_4_SIZE 0x79C + +#define QM_TENSOR_5_DIM_4_SIZE_V_SHIFT 0 +#define QM_TENSOR_5_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_5_DIM_4_STRIDE 0x7A0 + +#define QM_TENSOR_5_DIM_4_STRIDE_V_SHIFT 0 +#define QM_TENSOR_5_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_5_PREF_STRIDE 0x7A4 + +#define QM_TENSOR_5_PREF_STRIDE_VAL_SHIFT 0 +#define QM_TENSOR_5_PREF_STRIDE_VAL_MASK 0xFFFF + +#define QM_TENSOR_5_DIM_0_SIZE_STRIDE_HIGH 0x7A8 + +#define QM_TENSOR_5_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_5_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_5_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_5_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_5_DIM_1_SIZE_STRIDE_HIGH 0x7AC + +#define QM_TENSOR_5_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_5_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_5_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_5_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_5_DIM_2_SIZE_STRIDE_HIGH 0x7B0 + +#define QM_TENSOR_5_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_5_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_5_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_5_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_5_DIM_3_SIZE_STRIDE_HIGH 0x7B4 + +#define QM_TENSOR_5_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_5_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_5_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_5_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_5_DIM_4_SIZE_STRIDE_HIGH 0x7B8 + +#define QM_TENSOR_5_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_5_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_5_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_5_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_6_BASE_ADDR_LOW 0x7BC + +#define QM_TENSOR_6_BASE_ADDR_LOW_V_SHIFT 0 +#define QM_TENSOR_6_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_6_BASE_ADDR_HIGH 0x7C0 + +#define QM_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT 0 +#define QM_TENSOR_6_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_6_PADDING_VALUE 0x7C4 + +#define QM_TENSOR_6_PADDING_VALUE_V_SHIFT 0 +#define QM_TENSOR_6_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_6_TENSOR_CONFIG 0x7C8 + +#define QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define QM_TENSOR_6_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define QM_TENSOR_6_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define QM_TENSOR_6_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define QM_TENSOR_6_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define QM_TENSOR_6_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define QM_TENSOR_6_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define QM_TENSOR_6_TENSOR_CONFIG_L0CD_SHIFT 25 +#define QM_TENSOR_6_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define QM_TENSOR_6_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define QM_TENSOR_6_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define QM_TENSOR_6_DIM_0_SIZE 0x7CC + +#define QM_TENSOR_6_DIM_0_SIZE_V_SHIFT 0 +#define QM_TENSOR_6_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_6_DIM_0_STRIDE 0x7D0 + +#define QM_TENSOR_6_DIM_0_STRIDE_V_SHIFT 0 +#define QM_TENSOR_6_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_6_DIM_1_SIZE 0x7D4 + +#define QM_TENSOR_6_DIM_1_SIZE_V_SHIFT 0 +#define QM_TENSOR_6_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_6_DIM_1_STRIDE 0x7D8 + +#define QM_TENSOR_6_DIM_1_STRIDE_V_SHIFT 0 +#define QM_TENSOR_6_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_6_DIM_2_SIZE 0x7DC + +#define QM_TENSOR_6_DIM_2_SIZE_V_SHIFT 0 +#define QM_TENSOR_6_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_6_DIM_2_STRIDE 0x7E0 + +#define QM_TENSOR_6_DIM_2_STRIDE_V_SHIFT 0 +#define QM_TENSOR_6_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_6_DIM_3_SIZE 0x7E4 + +#define QM_TENSOR_6_DIM_3_SIZE_V_SHIFT 0 +#define QM_TENSOR_6_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_6_DIM_3_STRIDE 0x7E8 + +#define QM_TENSOR_6_DIM_3_STRIDE_V_SHIFT 0 +#define QM_TENSOR_6_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_6_DIM_4_SIZE 0x7EC + +#define QM_TENSOR_6_DIM_4_SIZE_V_SHIFT 0 +#define QM_TENSOR_6_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_6_DIM_4_STRIDE 0x7F0 + +#define QM_TENSOR_6_DIM_4_STRIDE_V_SHIFT 0 +#define QM_TENSOR_6_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_6_PREF_STRIDE 0x7F4 + +#define QM_TENSOR_6_PREF_STRIDE_VAL_SHIFT 0 +#define QM_TENSOR_6_PREF_STRIDE_VAL_MASK 0xFFFF + +#define QM_TENSOR_6_DIM_0_SIZE_STRIDE_HIGH 0x7F8 + +#define QM_TENSOR_6_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_6_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_6_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_6_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_6_DIM_1_SIZE_STRIDE_HIGH 0x7FC + +#define QM_TENSOR_6_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_6_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_6_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_6_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_6_DIM_2_SIZE_STRIDE_HIGH 0x800 + +#define QM_TENSOR_6_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_6_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_6_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_6_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_6_DIM_3_SIZE_STRIDE_HIGH 0x804 + +#define QM_TENSOR_6_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_6_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_6_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_6_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_6_DIM_4_SIZE_STRIDE_HIGH 0x808 + +#define QM_TENSOR_6_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_6_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_6_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_6_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_7_BASE_ADDR_LOW 0x80C + +#define QM_TENSOR_7_BASE_ADDR_LOW_V_SHIFT 0 +#define QM_TENSOR_7_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_7_BASE_ADDR_HIGH 0x810 + +#define QM_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT 0 +#define QM_TENSOR_7_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_7_PADDING_VALUE 0x814 + +#define QM_TENSOR_7_PADDING_VALUE_V_SHIFT 0 +#define QM_TENSOR_7_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_7_TENSOR_CONFIG 0x818 + +#define QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define QM_TENSOR_7_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define QM_TENSOR_7_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define QM_TENSOR_7_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define QM_TENSOR_7_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define QM_TENSOR_7_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define QM_TENSOR_7_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define QM_TENSOR_7_TENSOR_CONFIG_L0CD_SHIFT 25 +#define QM_TENSOR_7_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define QM_TENSOR_7_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define QM_TENSOR_7_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define QM_TENSOR_7_DIM_0_SIZE 0x81C + +#define QM_TENSOR_7_DIM_0_SIZE_V_SHIFT 0 +#define QM_TENSOR_7_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_7_DIM_0_STRIDE 0x820 + +#define QM_TENSOR_7_DIM_0_STRIDE_V_SHIFT 0 +#define QM_TENSOR_7_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_7_DIM_1_SIZE 0x824 + +#define QM_TENSOR_7_DIM_1_SIZE_V_SHIFT 0 +#define QM_TENSOR_7_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_7_DIM_1_STRIDE 0x828 + +#define QM_TENSOR_7_DIM_1_STRIDE_V_SHIFT 0 +#define QM_TENSOR_7_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_7_DIM_2_SIZE 0x82C + +#define QM_TENSOR_7_DIM_2_SIZE_V_SHIFT 0 +#define QM_TENSOR_7_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_7_DIM_2_STRIDE 0x830 + +#define QM_TENSOR_7_DIM_2_STRIDE_V_SHIFT 0 +#define QM_TENSOR_7_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_7_DIM_3_SIZE 0x834 + +#define QM_TENSOR_7_DIM_3_SIZE_V_SHIFT 0 +#define QM_TENSOR_7_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_7_DIM_3_STRIDE 0x838 + +#define QM_TENSOR_7_DIM_3_STRIDE_V_SHIFT 0 +#define QM_TENSOR_7_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_7_DIM_4_SIZE 0x83C + +#define QM_TENSOR_7_DIM_4_SIZE_V_SHIFT 0 +#define QM_TENSOR_7_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_7_DIM_4_STRIDE 0x840 + +#define QM_TENSOR_7_DIM_4_STRIDE_V_SHIFT 0 +#define QM_TENSOR_7_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_7_PREF_STRIDE 0x844 + +#define QM_TENSOR_7_PREF_STRIDE_VAL_SHIFT 0 +#define QM_TENSOR_7_PREF_STRIDE_VAL_MASK 0xFFFF + +#define QM_TENSOR_7_DIM_0_SIZE_STRIDE_HIGH 0x848 + +#define QM_TENSOR_7_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_7_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_7_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_7_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_7_DIM_1_SIZE_STRIDE_HIGH 0x84C + +#define QM_TENSOR_7_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_7_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_7_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_7_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_7_DIM_2_SIZE_STRIDE_HIGH 0x850 + +#define QM_TENSOR_7_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_7_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_7_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_7_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_7_DIM_3_SIZE_STRIDE_HIGH 0x854 + +#define QM_TENSOR_7_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_7_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_7_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_7_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_7_DIM_4_SIZE_STRIDE_HIGH 0x858 + +#define QM_TENSOR_7_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_7_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_7_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_7_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_8_BASE_ADDR_LOW 0x85C + +#define QM_TENSOR_8_BASE_ADDR_LOW_V_SHIFT 0 +#define QM_TENSOR_8_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_8_BASE_ADDR_HIGH 0x860 + +#define QM_TENSOR_8_BASE_ADDR_HIGH_V_SHIFT 0 +#define QM_TENSOR_8_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_8_PADDING_VALUE 0x864 + +#define QM_TENSOR_8_PADDING_VALUE_V_SHIFT 0 +#define QM_TENSOR_8_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_8_TENSOR_CONFIG 0x868 + +#define QM_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define QM_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define QM_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define QM_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define QM_TENSOR_8_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define QM_TENSOR_8_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define QM_TENSOR_8_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define QM_TENSOR_8_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define QM_TENSOR_8_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define QM_TENSOR_8_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define QM_TENSOR_8_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define QM_TENSOR_8_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define QM_TENSOR_8_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define QM_TENSOR_8_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define QM_TENSOR_8_TENSOR_CONFIG_L0CD_SHIFT 25 +#define QM_TENSOR_8_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define QM_TENSOR_8_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define QM_TENSOR_8_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define QM_TENSOR_8_DIM_0_SIZE 0x86C + +#define QM_TENSOR_8_DIM_0_SIZE_V_SHIFT 0 +#define QM_TENSOR_8_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_8_DIM_0_STRIDE 0x870 + +#define QM_TENSOR_8_DIM_0_STRIDE_V_SHIFT 0 +#define QM_TENSOR_8_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_8_DIM_1_SIZE 0x874 + +#define QM_TENSOR_8_DIM_1_SIZE_V_SHIFT 0 +#define QM_TENSOR_8_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_8_DIM_1_STRIDE 0x878 + +#define QM_TENSOR_8_DIM_1_STRIDE_V_SHIFT 0 +#define QM_TENSOR_8_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_8_DIM_2_SIZE 0x87C + +#define QM_TENSOR_8_DIM_2_SIZE_V_SHIFT 0 +#define QM_TENSOR_8_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_8_DIM_2_STRIDE 0x880 + +#define QM_TENSOR_8_DIM_2_STRIDE_V_SHIFT 0 +#define QM_TENSOR_8_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_8_DIM_3_SIZE 0x884 + +#define QM_TENSOR_8_DIM_3_SIZE_V_SHIFT 0 +#define QM_TENSOR_8_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_8_DIM_3_STRIDE 0x888 + +#define QM_TENSOR_8_DIM_3_STRIDE_V_SHIFT 0 +#define QM_TENSOR_8_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_8_DIM_4_SIZE 0x88C + +#define QM_TENSOR_8_DIM_4_SIZE_V_SHIFT 0 +#define QM_TENSOR_8_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_8_DIM_4_STRIDE 0x890 + +#define QM_TENSOR_8_DIM_4_STRIDE_V_SHIFT 0 +#define QM_TENSOR_8_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_8_PREF_STRIDE 0x894 + +#define QM_TENSOR_8_PREF_STRIDE_VAL_SHIFT 0 +#define QM_TENSOR_8_PREF_STRIDE_VAL_MASK 0xFFFF + +#define QM_TENSOR_8_DIM_0_SIZE_STRIDE_HIGH 0x898 + +#define QM_TENSOR_8_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_8_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_8_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_8_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_8_DIM_1_SIZE_STRIDE_HIGH 0x89C + +#define QM_TENSOR_8_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_8_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_8_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_8_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_8_DIM_2_SIZE_STRIDE_HIGH 0x8A0 + +#define QM_TENSOR_8_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_8_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_8_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_8_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_8_DIM_3_SIZE_STRIDE_HIGH 0x8A4 + +#define QM_TENSOR_8_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_8_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_8_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_8_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_8_DIM_4_SIZE_STRIDE_HIGH 0x8A8 + +#define QM_TENSOR_8_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_8_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_8_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_8_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_9_BASE_ADDR_LOW 0x8AC + +#define QM_TENSOR_9_BASE_ADDR_LOW_V_SHIFT 0 +#define QM_TENSOR_9_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_9_BASE_ADDR_HIGH 0x8B0 + +#define QM_TENSOR_9_BASE_ADDR_HIGH_V_SHIFT 0 +#define QM_TENSOR_9_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_9_PADDING_VALUE 0x8B4 + +#define QM_TENSOR_9_PADDING_VALUE_V_SHIFT 0 +#define QM_TENSOR_9_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_9_TENSOR_CONFIG 0x8B8 + +#define QM_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define QM_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define QM_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define QM_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define QM_TENSOR_9_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define QM_TENSOR_9_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define QM_TENSOR_9_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define QM_TENSOR_9_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define QM_TENSOR_9_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define QM_TENSOR_9_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define QM_TENSOR_9_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define QM_TENSOR_9_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define QM_TENSOR_9_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define QM_TENSOR_9_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define QM_TENSOR_9_TENSOR_CONFIG_L0CD_SHIFT 25 +#define QM_TENSOR_9_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define QM_TENSOR_9_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define QM_TENSOR_9_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define QM_TENSOR_9_DIM_0_SIZE 0x8BC + +#define QM_TENSOR_9_DIM_0_SIZE_V_SHIFT 0 +#define QM_TENSOR_9_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_9_DIM_0_STRIDE 0x8C0 + +#define QM_TENSOR_9_DIM_0_STRIDE_V_SHIFT 0 +#define QM_TENSOR_9_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_9_DIM_1_SIZE 0x8C4 + +#define QM_TENSOR_9_DIM_1_SIZE_V_SHIFT 0 +#define QM_TENSOR_9_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_9_DIM_1_STRIDE 0x8C8 + +#define QM_TENSOR_9_DIM_1_STRIDE_V_SHIFT 0 +#define QM_TENSOR_9_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_9_DIM_2_SIZE 0x8CC + +#define QM_TENSOR_9_DIM_2_SIZE_V_SHIFT 0 +#define QM_TENSOR_9_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_9_DIM_2_STRIDE 0x8D0 + +#define QM_TENSOR_9_DIM_2_STRIDE_V_SHIFT 0 +#define QM_TENSOR_9_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_9_DIM_3_SIZE 0x8D4 + +#define QM_TENSOR_9_DIM_3_SIZE_V_SHIFT 0 +#define QM_TENSOR_9_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_9_DIM_3_STRIDE 0x8D8 + +#define QM_TENSOR_9_DIM_3_STRIDE_V_SHIFT 0 +#define QM_TENSOR_9_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_9_DIM_4_SIZE 0x8DC + +#define QM_TENSOR_9_DIM_4_SIZE_V_SHIFT 0 +#define QM_TENSOR_9_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_9_DIM_4_STRIDE 0x8E0 + +#define QM_TENSOR_9_DIM_4_STRIDE_V_SHIFT 0 +#define QM_TENSOR_9_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_9_PREF_STRIDE 0x8E4 + +#define QM_TENSOR_9_PREF_STRIDE_VAL_SHIFT 0 +#define QM_TENSOR_9_PREF_STRIDE_VAL_MASK 0xFFFF + +#define QM_TENSOR_9_DIM_0_SIZE_STRIDE_HIGH 0x8E8 + +#define QM_TENSOR_9_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_9_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_9_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_9_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_9_DIM_1_SIZE_STRIDE_HIGH 0x8EC + +#define QM_TENSOR_9_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_9_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_9_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_9_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_9_DIM_2_SIZE_STRIDE_HIGH 0x8F0 + +#define QM_TENSOR_9_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_9_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_9_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_9_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_9_DIM_3_SIZE_STRIDE_HIGH 0x8F4 + +#define QM_TENSOR_9_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_9_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_9_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_9_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_9_DIM_4_SIZE_STRIDE_HIGH 0x8F8 + +#define QM_TENSOR_9_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_9_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_9_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_9_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_10_BASE_ADDR_LOW 0x8FC + +#define QM_TENSOR_10_BASE_ADDR_LOW_V_SHIFT 0 +#define QM_TENSOR_10_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_10_BASE_ADDR_HIGH 0x900 + +#define QM_TENSOR_10_BASE_ADDR_HIGH_V_SHIFT 0 +#define QM_TENSOR_10_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_10_PADDING_VALUE 0x904 + +#define QM_TENSOR_10_PADDING_VALUE_V_SHIFT 0 +#define QM_TENSOR_10_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_10_TENSOR_CONFIG 0x908 + +#define QM_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define QM_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define QM_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define QM_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define QM_TENSOR_10_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define QM_TENSOR_10_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define QM_TENSOR_10_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define QM_TENSOR_10_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define QM_TENSOR_10_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define QM_TENSOR_10_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define QM_TENSOR_10_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define QM_TENSOR_10_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define QM_TENSOR_10_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define QM_TENSOR_10_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define QM_TENSOR_10_TENSOR_CONFIG_L0CD_SHIFT 25 +#define QM_TENSOR_10_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define QM_TENSOR_10_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define QM_TENSOR_10_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define QM_TENSOR_10_DIM_0_SIZE 0x90C + +#define QM_TENSOR_10_DIM_0_SIZE_V_SHIFT 0 +#define QM_TENSOR_10_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_10_DIM_0_STRIDE 0x910 + +#define QM_TENSOR_10_DIM_0_STRIDE_V_SHIFT 0 +#define QM_TENSOR_10_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_10_DIM_1_SIZE 0x914 + +#define QM_TENSOR_10_DIM_1_SIZE_V_SHIFT 0 +#define QM_TENSOR_10_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_10_DIM_1_STRIDE 0x918 + +#define QM_TENSOR_10_DIM_1_STRIDE_V_SHIFT 0 +#define QM_TENSOR_10_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_10_DIM_2_SIZE 0x91C + +#define QM_TENSOR_10_DIM_2_SIZE_V_SHIFT 0 +#define QM_TENSOR_10_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_10_DIM_2_STRIDE 0x920 + +#define QM_TENSOR_10_DIM_2_STRIDE_V_SHIFT 0 +#define QM_TENSOR_10_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_10_DIM_3_SIZE 0x924 + +#define QM_TENSOR_10_DIM_3_SIZE_V_SHIFT 0 +#define QM_TENSOR_10_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_10_DIM_3_STRIDE 0x928 + +#define QM_TENSOR_10_DIM_3_STRIDE_V_SHIFT 0 +#define QM_TENSOR_10_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_10_DIM_4_SIZE 0x92C + +#define QM_TENSOR_10_DIM_4_SIZE_V_SHIFT 0 +#define QM_TENSOR_10_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_10_DIM_4_STRIDE 0x930 + +#define QM_TENSOR_10_DIM_4_STRIDE_V_SHIFT 0 +#define QM_TENSOR_10_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_10_PREF_STRIDE 0x934 + +#define QM_TENSOR_10_PREF_STRIDE_VAL_SHIFT 0 +#define QM_TENSOR_10_PREF_STRIDE_VAL_MASK 0xFFFF + +#define QM_TENSOR_10_DIM_0_SIZE_STRIDE_HIGH 0x938 + +#define QM_TENSOR_10_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_10_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_10_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_10_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_10_DIM_1_SIZE_STRIDE_HIGH 0x93C + +#define QM_TENSOR_10_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_10_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_10_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_10_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_10_DIM_2_SIZE_STRIDE_HIGH 0x940 + +#define QM_TENSOR_10_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_10_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_10_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_10_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_10_DIM_3_SIZE_STRIDE_HIGH 0x944 + +#define QM_TENSOR_10_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_10_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_10_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_10_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_10_DIM_4_SIZE_STRIDE_HIGH 0x948 + +#define QM_TENSOR_10_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_10_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_10_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_10_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_11_BASE_ADDR_LOW 0x94C + +#define QM_TENSOR_11_BASE_ADDR_LOW_V_SHIFT 0 +#define QM_TENSOR_11_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_11_BASE_ADDR_HIGH 0x950 + +#define QM_TENSOR_11_BASE_ADDR_HIGH_V_SHIFT 0 +#define QM_TENSOR_11_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_11_PADDING_VALUE 0x954 + +#define QM_TENSOR_11_PADDING_VALUE_V_SHIFT 0 +#define QM_TENSOR_11_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_11_TENSOR_CONFIG 0x958 + +#define QM_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define QM_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define QM_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define QM_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define QM_TENSOR_11_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define QM_TENSOR_11_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define QM_TENSOR_11_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define QM_TENSOR_11_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define QM_TENSOR_11_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define QM_TENSOR_11_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define QM_TENSOR_11_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define QM_TENSOR_11_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define QM_TENSOR_11_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define QM_TENSOR_11_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define QM_TENSOR_11_TENSOR_CONFIG_L0CD_SHIFT 25 +#define QM_TENSOR_11_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define QM_TENSOR_11_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define QM_TENSOR_11_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define QM_TENSOR_11_DIM_0_SIZE 0x95C + +#define QM_TENSOR_11_DIM_0_SIZE_V_SHIFT 0 +#define QM_TENSOR_11_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_11_DIM_0_STRIDE 0x960 + +#define QM_TENSOR_11_DIM_0_STRIDE_V_SHIFT 0 +#define QM_TENSOR_11_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_11_DIM_1_SIZE 0x964 + +#define QM_TENSOR_11_DIM_1_SIZE_V_SHIFT 0 +#define QM_TENSOR_11_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_11_DIM_1_STRIDE 0x968 + +#define QM_TENSOR_11_DIM_1_STRIDE_V_SHIFT 0 +#define QM_TENSOR_11_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_11_DIM_2_SIZE 0x96C + +#define QM_TENSOR_11_DIM_2_SIZE_V_SHIFT 0 +#define QM_TENSOR_11_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_11_DIM_2_STRIDE 0x970 + +#define QM_TENSOR_11_DIM_2_STRIDE_V_SHIFT 0 +#define QM_TENSOR_11_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_11_DIM_3_SIZE 0x974 + +#define QM_TENSOR_11_DIM_3_SIZE_V_SHIFT 0 +#define QM_TENSOR_11_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_11_DIM_3_STRIDE 0x978 + +#define QM_TENSOR_11_DIM_3_STRIDE_V_SHIFT 0 +#define QM_TENSOR_11_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_11_DIM_4_SIZE 0x97C + +#define QM_TENSOR_11_DIM_4_SIZE_V_SHIFT 0 +#define QM_TENSOR_11_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_11_DIM_4_STRIDE 0x980 + +#define QM_TENSOR_11_DIM_4_STRIDE_V_SHIFT 0 +#define QM_TENSOR_11_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_11_PREF_STRIDE 0x984 + +#define QM_TENSOR_11_PREF_STRIDE_VAL_SHIFT 0 +#define QM_TENSOR_11_PREF_STRIDE_VAL_MASK 0xFFFF + +#define QM_TENSOR_11_DIM_0_SIZE_STRIDE_HIGH 0x988 + +#define QM_TENSOR_11_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_11_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_11_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_11_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_11_DIM_1_SIZE_STRIDE_HIGH 0x98C + +#define QM_TENSOR_11_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_11_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_11_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_11_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_11_DIM_2_SIZE_STRIDE_HIGH 0x990 + +#define QM_TENSOR_11_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_11_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_11_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_11_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_11_DIM_3_SIZE_STRIDE_HIGH 0x994 + +#define QM_TENSOR_11_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_11_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_11_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_11_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_11_DIM_4_SIZE_STRIDE_HIGH 0x998 + +#define QM_TENSOR_11_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_11_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_11_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_11_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_12_BASE_ADDR_LOW 0x99C + +#define QM_TENSOR_12_BASE_ADDR_LOW_V_SHIFT 0 +#define QM_TENSOR_12_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_12_BASE_ADDR_HIGH 0x9A0 + +#define QM_TENSOR_12_BASE_ADDR_HIGH_V_SHIFT 0 +#define QM_TENSOR_12_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_12_PADDING_VALUE 0x9A4 + +#define QM_TENSOR_12_PADDING_VALUE_V_SHIFT 0 +#define QM_TENSOR_12_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_12_TENSOR_CONFIG 0x9A8 + +#define QM_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define QM_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define QM_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define QM_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define QM_TENSOR_12_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define QM_TENSOR_12_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define QM_TENSOR_12_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define QM_TENSOR_12_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define QM_TENSOR_12_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define QM_TENSOR_12_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define QM_TENSOR_12_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define QM_TENSOR_12_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define QM_TENSOR_12_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define QM_TENSOR_12_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define QM_TENSOR_12_TENSOR_CONFIG_L0CD_SHIFT 25 +#define QM_TENSOR_12_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define QM_TENSOR_12_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define QM_TENSOR_12_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define QM_TENSOR_12_DIM_0_SIZE 0x9AC + +#define QM_TENSOR_12_DIM_0_SIZE_V_SHIFT 0 +#define QM_TENSOR_12_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_12_DIM_0_STRIDE 0x9B0 + +#define QM_TENSOR_12_DIM_0_STRIDE_V_SHIFT 0 +#define QM_TENSOR_12_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_12_DIM_1_SIZE 0x9B4 + +#define QM_TENSOR_12_DIM_1_SIZE_V_SHIFT 0 +#define QM_TENSOR_12_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_12_DIM_1_STRIDE 0x9B8 + +#define QM_TENSOR_12_DIM_1_STRIDE_V_SHIFT 0 +#define QM_TENSOR_12_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_12_DIM_2_SIZE 0x9BC + +#define QM_TENSOR_12_DIM_2_SIZE_V_SHIFT 0 +#define QM_TENSOR_12_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_12_DIM_2_STRIDE 0x9C0 + +#define QM_TENSOR_12_DIM_2_STRIDE_V_SHIFT 0 +#define QM_TENSOR_12_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_12_DIM_3_SIZE 0x9C4 + +#define QM_TENSOR_12_DIM_3_SIZE_V_SHIFT 0 +#define QM_TENSOR_12_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_12_DIM_3_STRIDE 0x9C8 + +#define QM_TENSOR_12_DIM_3_STRIDE_V_SHIFT 0 +#define QM_TENSOR_12_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_12_DIM_4_SIZE 0x9CC + +#define QM_TENSOR_12_DIM_4_SIZE_V_SHIFT 0 +#define QM_TENSOR_12_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_12_DIM_4_STRIDE 0x9D0 + +#define QM_TENSOR_12_DIM_4_STRIDE_V_SHIFT 0 +#define QM_TENSOR_12_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_12_PREF_STRIDE 0x9D4 + +#define QM_TENSOR_12_PREF_STRIDE_VAL_SHIFT 0 +#define QM_TENSOR_12_PREF_STRIDE_VAL_MASK 0xFFFF + +#define QM_TENSOR_12_DIM_0_SIZE_STRIDE_HIGH 0x9D8 + +#define QM_TENSOR_12_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_12_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_12_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_12_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_12_DIM_1_SIZE_STRIDE_HIGH 0x9DC + +#define QM_TENSOR_12_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_12_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_12_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_12_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_12_DIM_2_SIZE_STRIDE_HIGH 0x9E0 + +#define QM_TENSOR_12_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_12_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_12_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_12_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_12_DIM_3_SIZE_STRIDE_HIGH 0x9E4 + +#define QM_TENSOR_12_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_12_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_12_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_12_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_12_DIM_4_SIZE_STRIDE_HIGH 0x9E8 + +#define QM_TENSOR_12_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_12_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_12_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_12_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_13_BASE_ADDR_LOW 0x9EC + +#define QM_TENSOR_13_BASE_ADDR_LOW_V_SHIFT 0 +#define QM_TENSOR_13_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_13_BASE_ADDR_HIGH 0x9F0 + +#define QM_TENSOR_13_BASE_ADDR_HIGH_V_SHIFT 0 +#define QM_TENSOR_13_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_13_PADDING_VALUE 0x9F4 + +#define QM_TENSOR_13_PADDING_VALUE_V_SHIFT 0 +#define QM_TENSOR_13_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_13_TENSOR_CONFIG 0x9F8 + +#define QM_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define QM_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define QM_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define QM_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define QM_TENSOR_13_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define QM_TENSOR_13_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define QM_TENSOR_13_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define QM_TENSOR_13_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define QM_TENSOR_13_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define QM_TENSOR_13_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define QM_TENSOR_13_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define QM_TENSOR_13_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define QM_TENSOR_13_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define QM_TENSOR_13_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define QM_TENSOR_13_TENSOR_CONFIG_L0CD_SHIFT 25 +#define QM_TENSOR_13_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define QM_TENSOR_13_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define QM_TENSOR_13_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define QM_TENSOR_13_DIM_0_SIZE 0x9FC + +#define QM_TENSOR_13_DIM_0_SIZE_V_SHIFT 0 +#define QM_TENSOR_13_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_13_DIM_0_STRIDE 0xA00 + +#define QM_TENSOR_13_DIM_0_STRIDE_V_SHIFT 0 +#define QM_TENSOR_13_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_13_DIM_1_SIZE 0xA04 + +#define QM_TENSOR_13_DIM_1_SIZE_V_SHIFT 0 +#define QM_TENSOR_13_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_13_DIM_1_STRIDE 0xA08 + +#define QM_TENSOR_13_DIM_1_STRIDE_V_SHIFT 0 +#define QM_TENSOR_13_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_13_DIM_2_SIZE 0xA0C + +#define QM_TENSOR_13_DIM_2_SIZE_V_SHIFT 0 +#define QM_TENSOR_13_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_13_DIM_2_STRIDE 0xA10 + +#define QM_TENSOR_13_DIM_2_STRIDE_V_SHIFT 0 +#define QM_TENSOR_13_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_13_DIM_3_SIZE 0xA14 + +#define QM_TENSOR_13_DIM_3_SIZE_V_SHIFT 0 +#define QM_TENSOR_13_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_13_DIM_3_STRIDE 0xA18 + +#define QM_TENSOR_13_DIM_3_STRIDE_V_SHIFT 0 +#define QM_TENSOR_13_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_13_DIM_4_SIZE 0xA1C + +#define QM_TENSOR_13_DIM_4_SIZE_V_SHIFT 0 +#define QM_TENSOR_13_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_13_DIM_4_STRIDE 0xA20 + +#define QM_TENSOR_13_DIM_4_STRIDE_V_SHIFT 0 +#define QM_TENSOR_13_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_13_PREF_STRIDE 0xA24 + +#define QM_TENSOR_13_PREF_STRIDE_VAL_SHIFT 0 +#define QM_TENSOR_13_PREF_STRIDE_VAL_MASK 0xFFFF + +#define QM_TENSOR_13_DIM_0_SIZE_STRIDE_HIGH 0xA28 + +#define QM_TENSOR_13_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_13_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_13_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_13_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_13_DIM_1_SIZE_STRIDE_HIGH 0xA2C + +#define QM_TENSOR_13_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_13_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_13_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_13_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_13_DIM_2_SIZE_STRIDE_HIGH 0xA30 + +#define QM_TENSOR_13_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_13_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_13_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_13_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_13_DIM_3_SIZE_STRIDE_HIGH 0xA34 + +#define QM_TENSOR_13_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_13_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_13_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_13_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_13_DIM_4_SIZE_STRIDE_HIGH 0xA38 + +#define QM_TENSOR_13_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_13_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_13_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_13_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_14_BASE_ADDR_LOW 0xA3C + +#define QM_TENSOR_14_BASE_ADDR_LOW_V_SHIFT 0 +#define QM_TENSOR_14_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_14_BASE_ADDR_HIGH 0xA40 + +#define QM_TENSOR_14_BASE_ADDR_HIGH_V_SHIFT 0 +#define QM_TENSOR_14_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_14_PADDING_VALUE 0xA44 + +#define QM_TENSOR_14_PADDING_VALUE_V_SHIFT 0 +#define QM_TENSOR_14_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_14_TENSOR_CONFIG 0xA48 + +#define QM_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define QM_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define QM_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define QM_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define QM_TENSOR_14_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define QM_TENSOR_14_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define QM_TENSOR_14_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define QM_TENSOR_14_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define QM_TENSOR_14_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define QM_TENSOR_14_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define QM_TENSOR_14_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define QM_TENSOR_14_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define QM_TENSOR_14_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define QM_TENSOR_14_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define QM_TENSOR_14_TENSOR_CONFIG_L0CD_SHIFT 25 +#define QM_TENSOR_14_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define QM_TENSOR_14_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define QM_TENSOR_14_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define QM_TENSOR_14_DIM_0_SIZE 0xA4C + +#define QM_TENSOR_14_DIM_0_SIZE_V_SHIFT 0 +#define QM_TENSOR_14_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_14_DIM_0_STRIDE 0xA50 + +#define QM_TENSOR_14_DIM_0_STRIDE_V_SHIFT 0 +#define QM_TENSOR_14_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_14_DIM_1_SIZE 0xA54 + +#define QM_TENSOR_14_DIM_1_SIZE_V_SHIFT 0 +#define QM_TENSOR_14_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_14_DIM_1_STRIDE 0xA58 + +#define QM_TENSOR_14_DIM_1_STRIDE_V_SHIFT 0 +#define QM_TENSOR_14_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_14_DIM_2_SIZE 0xA5C + +#define QM_TENSOR_14_DIM_2_SIZE_V_SHIFT 0 +#define QM_TENSOR_14_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_14_DIM_2_STRIDE 0xA60 + +#define QM_TENSOR_14_DIM_2_STRIDE_V_SHIFT 0 +#define QM_TENSOR_14_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_14_DIM_3_SIZE 0xA64 + +#define QM_TENSOR_14_DIM_3_SIZE_V_SHIFT 0 +#define QM_TENSOR_14_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_14_DIM_3_STRIDE 0xA68 + +#define QM_TENSOR_14_DIM_3_STRIDE_V_SHIFT 0 +#define QM_TENSOR_14_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_14_DIM_4_SIZE 0xA6C + +#define QM_TENSOR_14_DIM_4_SIZE_V_SHIFT 0 +#define QM_TENSOR_14_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_14_DIM_4_STRIDE 0xA70 + +#define QM_TENSOR_14_DIM_4_STRIDE_V_SHIFT 0 +#define QM_TENSOR_14_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_14_PREF_STRIDE 0xA74 + +#define QM_TENSOR_14_PREF_STRIDE_VAL_SHIFT 0 +#define QM_TENSOR_14_PREF_STRIDE_VAL_MASK 0xFFFF + +#define QM_TENSOR_14_DIM_0_SIZE_STRIDE_HIGH 0xA78 + +#define QM_TENSOR_14_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_14_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_14_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_14_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_14_DIM_1_SIZE_STRIDE_HIGH 0xA7C + +#define QM_TENSOR_14_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_14_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_14_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_14_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_14_DIM_2_SIZE_STRIDE_HIGH 0xA80 + +#define QM_TENSOR_14_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_14_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_14_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_14_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_14_DIM_3_SIZE_STRIDE_HIGH 0xA84 + +#define QM_TENSOR_14_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_14_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_14_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_14_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_14_DIM_4_SIZE_STRIDE_HIGH 0xA88 + +#define QM_TENSOR_14_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_14_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_14_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_14_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_15_BASE_ADDR_LOW 0xA8C + +#define QM_TENSOR_15_BASE_ADDR_LOW_V_SHIFT 0 +#define QM_TENSOR_15_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_15_BASE_ADDR_HIGH 0xA90 + +#define QM_TENSOR_15_BASE_ADDR_HIGH_V_SHIFT 0 +#define QM_TENSOR_15_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_15_PADDING_VALUE 0xA94 + +#define QM_TENSOR_15_PADDING_VALUE_V_SHIFT 0 +#define QM_TENSOR_15_PADDING_VALUE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_15_TENSOR_CONFIG 0xA98 + +#define QM_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 +#define QM_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_MASK 0xF +#define QM_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 +#define QM_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 +#define QM_TENSOR_15_TENSOR_CONFIG_LAST_DIM64_SHIFT 13 +#define QM_TENSOR_15_TENSOR_CONFIG_LAST_DIM64_MASK 0x2000 +#define QM_TENSOR_15_TENSOR_CONFIG_LAST_DIM_SHIFT 16 +#define QM_TENSOR_15_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 +#define QM_TENSOR_15_TENSOR_CONFIG_RMW_SET_SHIFT 19 +#define QM_TENSOR_15_TENSOR_CONFIG_RMW_SET_MASK 0x80000 +#define QM_TENSOR_15_TENSOR_CONFIG_RMW_OP_SHIFT 21 +#define QM_TENSOR_15_TENSOR_CONFIG_RMW_OP_MASK 0xE00000 +#define QM_TENSOR_15_TENSOR_CONFIG_DUP_OOB_SHIFT 24 +#define QM_TENSOR_15_TENSOR_CONFIG_DUP_OOB_MASK 0x1000000 +#define QM_TENSOR_15_TENSOR_CONFIG_L0CD_SHIFT 25 +#define QM_TENSOR_15_TENSOR_CONFIG_L0CD_MASK 0x2000000 +#define QM_TENSOR_15_TENSOR_CONFIG_T_PREF_DIS_SHIFT 26 +#define QM_TENSOR_15_TENSOR_CONFIG_T_PREF_DIS_MASK 0x4000000 + +#define QM_TENSOR_15_DIM_0_SIZE 0xA9C + +#define QM_TENSOR_15_DIM_0_SIZE_V_SHIFT 0 +#define QM_TENSOR_15_DIM_0_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_15_DIM_0_STRIDE 0xAA0 + +#define QM_TENSOR_15_DIM_0_STRIDE_V_SHIFT 0 +#define QM_TENSOR_15_DIM_0_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_15_DIM_1_SIZE 0xAA4 + +#define QM_TENSOR_15_DIM_1_SIZE_V_SHIFT 0 +#define QM_TENSOR_15_DIM_1_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_15_DIM_1_STRIDE 0xAA8 + +#define QM_TENSOR_15_DIM_1_STRIDE_V_SHIFT 0 +#define QM_TENSOR_15_DIM_1_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_15_DIM_2_SIZE 0xAAC + +#define QM_TENSOR_15_DIM_2_SIZE_V_SHIFT 0 +#define QM_TENSOR_15_DIM_2_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_15_DIM_2_STRIDE 0xAB0 + +#define QM_TENSOR_15_DIM_2_STRIDE_V_SHIFT 0 +#define QM_TENSOR_15_DIM_2_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_15_DIM_3_SIZE 0xAB4 + +#define QM_TENSOR_15_DIM_3_SIZE_V_SHIFT 0 +#define QM_TENSOR_15_DIM_3_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_15_DIM_3_STRIDE 0xAB8 + +#define QM_TENSOR_15_DIM_3_STRIDE_V_SHIFT 0 +#define QM_TENSOR_15_DIM_3_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_15_DIM_4_SIZE 0xABC + +#define QM_TENSOR_15_DIM_4_SIZE_V_SHIFT 0 +#define QM_TENSOR_15_DIM_4_SIZE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_15_DIM_4_STRIDE 0xAC0 + +#define QM_TENSOR_15_DIM_4_STRIDE_V_SHIFT 0 +#define QM_TENSOR_15_DIM_4_STRIDE_V_MASK 0xFFFFFFFF + +#define QM_TENSOR_15_PREF_STRIDE 0xAC4 + +#define QM_TENSOR_15_PREF_STRIDE_VAL_SHIFT 0 +#define QM_TENSOR_15_PREF_STRIDE_VAL_MASK 0xFFFF + +#define QM_TENSOR_15_DIM_0_SIZE_STRIDE_HIGH 0xAC8 + +#define QM_TENSOR_15_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_15_DIM_0_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_15_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_15_DIM_0_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_15_DIM_1_SIZE_STRIDE_HIGH 0xACC + +#define QM_TENSOR_15_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_15_DIM_1_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_15_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_15_DIM_1_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_15_DIM_2_SIZE_STRIDE_HIGH 0xAD0 + +#define QM_TENSOR_15_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_15_DIM_2_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_15_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_15_DIM_2_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_15_DIM_3_SIZE_STRIDE_HIGH 0xAD4 + +#define QM_TENSOR_15_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_15_DIM_3_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_15_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_15_DIM_3_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TENSOR_15_DIM_4_SIZE_STRIDE_HIGH 0xAD8 + +#define QM_TENSOR_15_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_SHIFT 0 +#define QM_TENSOR_15_DIM_4_SIZE_STRIDE_HIGH_STRIDE_HIGH_MASK 0xFFF +#define QM_TENSOR_15_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_SHIFT 16 +#define QM_TENSOR_15_DIM_4_SIZE_STRIDE_HIGH_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_SYNC_OBJECT_MESSAGE 0xADC + +#define QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0 +#define QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF +#define QM_SYNC_OBJECT_MESSAGE_RSV_SHIFT 16 +#define QM_SYNC_OBJECT_MESSAGE_RSV_MASK 0x1FFF0000 +#define QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 29 +#define QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0xE0000000 + +#define QM_SYNC_OBJECT_ADDR 0xAE0 + +#define QM_SYNC_OBJECT_ADDR_V_SHIFT 0 +#define QM_SYNC_OBJECT_ADDR_V_MASK 0xFFFFFFFF + +#define QM_KERNEL_BASE_ADDRESS_LOW 0xAE4 + +#define QM_KERNEL_BASE_ADDRESS_LOW_V_SHIFT 0 +#define QM_KERNEL_BASE_ADDRESS_LOW_V_MASK 0xFFFFFFFF + +#define QM_KERNEL_BASE_ADDRESS_HIGH 0xAE8 + +#define QM_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define QM_KERNEL_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +#define QM_TID_BASE_DIM_0 0xAEC + +#define QM_TID_BASE_DIM_0_V_SHIFT 0 +#define QM_TID_BASE_DIM_0_V_MASK 0xFFFFFFFF + +#define QM_TID_SIZE_DIM_0 0xAF0 + +#define QM_TID_SIZE_DIM_0_V_SHIFT 0 +#define QM_TID_SIZE_DIM_0_V_MASK 0xFFFFFFFF + +#define QM_TID_BASE_DIM_1 0xAF4 + +#define QM_TID_BASE_DIM_1_V_SHIFT 0 +#define QM_TID_BASE_DIM_1_V_MASK 0xFFFFFFFF + +#define QM_TID_SIZE_DIM_1 0xAF8 + +#define QM_TID_SIZE_DIM_1_V_SHIFT 0 +#define QM_TID_SIZE_DIM_1_V_MASK 0xFFFFFFFF + +#define QM_TID_BASE_DIM_2 0xAFC + +#define QM_TID_BASE_DIM_2_V_SHIFT 0 +#define QM_TID_BASE_DIM_2_V_MASK 0xFFFFFFFF + +#define QM_TID_SIZE_DIM_2 0xB00 + +#define QM_TID_SIZE_DIM_2_V_SHIFT 0 +#define QM_TID_SIZE_DIM_2_V_MASK 0xFFFFFFFF + +#define QM_TID_BASE_DIM_3 0xB04 + +#define QM_TID_BASE_DIM_3_V_SHIFT 0 +#define QM_TID_BASE_DIM_3_V_MASK 0xFFFFFFFF + +#define QM_TID_SIZE_DIM_3 0xB08 + +#define QM_TID_SIZE_DIM_3_V_SHIFT 0 +#define QM_TID_SIZE_DIM_3_V_MASK 0xFFFFFFFF + +#define QM_TID_BASE_DIM_4 0xB0C + +#define QM_TID_BASE_DIM_4_V_SHIFT 0 +#define QM_TID_BASE_DIM_4_V_MASK 0xFFFFFFFF + +#define QM_TID_SIZE_DIM_4 0xB10 + +#define QM_TID_SIZE_DIM_4_V_SHIFT 0 +#define QM_TID_SIZE_DIM_4_V_MASK 0xFFFFFFFF + +#define QM_KERNEL_CONFIG 0xB14 + +#define QM_KERNEL_CONFIG_SMALL_VLM_SHIFT 0 +#define QM_KERNEL_CONFIG_SMALL_VLM_MASK 0x1 +#define QM_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT 1 +#define QM_KERNEL_CONFIG_ASO_EVICT_L0_MASK 0x2 +#define QM_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT 2 +#define QM_KERNEL_CONFIG_NUM_VALID_SRFS_MASK 0xFC +#define QM_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_SHIFT 8 +#define QM_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_MASK 0xFF00 +#define QM_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_SHIFT 16 +#define QM_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_MASK 0xFF0000 +#define QM_KERNEL_CONFIG_IRF_32BIT_COMPATIBILITY_SHIFT 24 +#define QM_KERNEL_CONFIG_IRF_32BIT_COMPATIBILITY_MASK 0x1000000 + +#define QM_KERNEL_ID 0xB18 + +#define QM_KERNEL_ID_V_SHIFT 0 +#define QM_KERNEL_ID_V_MASK 0xFFFF + +#define QM_POWER_LOOP 0xB1C + +#define QM_POWER_LOOP_START_EN_SHIFT 0 +#define QM_POWER_LOOP_START_EN_MASK 0x1 +#define QM_POWER_LOOP_END_EN_SHIFT 1 +#define QM_POWER_LOOP_END_EN_MASK 0x2 +#define QM_POWER_LOOP_PAYLOAD_SHIFT 4 +#define QM_POWER_LOOP_PAYLOAD_MASK 0xFF0 + +#define QM_SRF_0 0xB20 + +#define QM_SRF_0_V_SHIFT 0 +#define QM_SRF_0_V_MASK 0xFFFFFFFF + +#define QM_SRF_1 0xB24 + +#define QM_SRF_1_V_SHIFT 0 +#define QM_SRF_1_V_MASK 0xFFFFFFFF + +#define QM_SRF_2 0xB28 + +#define QM_SRF_2_V_SHIFT 0 +#define QM_SRF_2_V_MASK 0xFFFFFFFF + +#define QM_SRF_3 0xB2C + +#define QM_SRF_3_V_SHIFT 0 +#define QM_SRF_3_V_MASK 0xFFFFFFFF + +#define QM_SRF_4 0xB30 + +#define QM_SRF_4_V_SHIFT 0 +#define QM_SRF_4_V_MASK 0xFFFFFFFF + +#define QM_SRF_5 0xB34 + +#define QM_SRF_5_V_SHIFT 0 +#define QM_SRF_5_V_MASK 0xFFFFFFFF + +#define QM_SRF_6 0xB38 + +#define QM_SRF_6_V_SHIFT 0 +#define QM_SRF_6_V_MASK 0xFFFFFFFF + +#define QM_SRF_7 0xB3C + +#define QM_SRF_7_V_SHIFT 0 +#define QM_SRF_7_V_MASK 0xFFFFFFFF + +#define QM_SRF_8 0xB40 + +#define QM_SRF_8_V_SHIFT 0 +#define QM_SRF_8_V_MASK 0xFFFFFFFF + +#define QM_SRF_9 0xB44 + +#define QM_SRF_9_V_SHIFT 0 +#define QM_SRF_9_V_MASK 0xFFFFFFFF + +#define QM_SRF_10 0xB48 + +#define QM_SRF_10_V_SHIFT 0 +#define QM_SRF_10_V_MASK 0xFFFFFFFF + +#define QM_SRF_11 0xB4C + +#define QM_SRF_11_V_SHIFT 0 +#define QM_SRF_11_V_MASK 0xFFFFFFFF + +#define QM_SRF_12 0xB50 + +#define QM_SRF_12_V_SHIFT 0 +#define QM_SRF_12_V_MASK 0xFFFFFFFF + +#define QM_SRF_13 0xB54 + +#define QM_SRF_13_V_SHIFT 0 +#define QM_SRF_13_V_MASK 0xFFFFFFFF + +#define QM_SRF_14 0xB58 + +#define QM_SRF_14_V_SHIFT 0 +#define QM_SRF_14_V_MASK 0xFFFFFFFF + +#define QM_SRF_15 0xB5C + +#define QM_SRF_15_V_SHIFT 0 +#define QM_SRF_15_V_MASK 0xFFFFFFFF + +#define QM_SRF_16 0xB60 + +#define QM_SRF_16_V_SHIFT 0 +#define QM_SRF_16_V_MASK 0xFFFFFFFF + +#define QM_SRF_17 0xB64 + +#define QM_SRF_17_V_SHIFT 0 +#define QM_SRF_17_V_MASK 0xFFFFFFFF + +#define QM_SRF_18 0xB68 + +#define QM_SRF_18_V_SHIFT 0 +#define QM_SRF_18_V_MASK 0xFFFFFFFF + +#define QM_SRF_19 0xB6C + +#define QM_SRF_19_V_SHIFT 0 +#define QM_SRF_19_V_MASK 0xFFFFFFFF + +#define QM_SRF_20 0xB70 + +#define QM_SRF_20_V_SHIFT 0 +#define QM_SRF_20_V_MASK 0xFFFFFFFF + +#define QM_SRF_21 0xB74 + +#define QM_SRF_21_V_SHIFT 0 +#define QM_SRF_21_V_MASK 0xFFFFFFFF + +#define QM_SRF_22 0xB78 + +#define QM_SRF_22_V_SHIFT 0 +#define QM_SRF_22_V_MASK 0xFFFFFFFF + +#define QM_SRF_23 0xB7C + +#define QM_SRF_23_V_SHIFT 0 +#define QM_SRF_23_V_MASK 0xFFFFFFFF + +#define QM_SRF_24 0xB80 + +#define QM_SRF_24_V_SHIFT 0 +#define QM_SRF_24_V_MASK 0xFFFFFFFF + +#define QM_SRF_25 0xB84 + +#define QM_SRF_25_V_SHIFT 0 +#define QM_SRF_25_V_MASK 0xFFFFFFFF + +#define QM_SRF_26 0xB88 + +#define QM_SRF_26_V_SHIFT 0 +#define QM_SRF_26_V_MASK 0xFFFFFFFF + +#define QM_SRF_27 0xB8C + +#define QM_SRF_27_V_SHIFT 0 +#define QM_SRF_27_V_MASK 0xFFFFFFFF + +#define QM_SRF_28 0xB90 + +#define QM_SRF_28_V_SHIFT 0 +#define QM_SRF_28_V_MASK 0xFFFFFFFF + +#define QM_SRF_29 0xB94 + +#define QM_SRF_29_V_SHIFT 0 +#define QM_SRF_29_V_MASK 0xFFFFFFFF + +#define QM_SRF_30 0xB98 + +#define QM_SRF_30_V_SHIFT 0 +#define QM_SRF_30_V_MASK 0xFFFFFFFF + +#define QM_SRF_31 0xB9C + +#define QM_SRF_31_V_SHIFT 0 +#define QM_SRF_31_V_MASK 0xFFFFFFFF + +#define QM_KERNEL_ID_INC 0xBA0 + +#define QM_KERNEL_ID_INC_V_SHIFT 0 +#define QM_KERNEL_ID_INC_V_MASK 0xFF + +#define QM_TID_BASE_SIZE_HIGH_DIM_0 0xBA4 + +#define QM_TID_BASE_SIZE_HIGH_DIM_0_BASE_HIGH_SHIFT 0 +#define QM_TID_BASE_SIZE_HIGH_DIM_0_BASE_HIGH_MASK 0xFFF +#define QM_TID_BASE_SIZE_HIGH_DIM_0_SIZE_HIGH_SHIFT 16 +#define QM_TID_BASE_SIZE_HIGH_DIM_0_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TID_BASE_SIZE_HIGH_DIM_1 0xBA8 + +#define QM_TID_BASE_SIZE_HIGH_DIM_1_BASE_HIGH_SHIFT 0 +#define QM_TID_BASE_SIZE_HIGH_DIM_1_BASE_HIGH_MASK 0xFFF +#define QM_TID_BASE_SIZE_HIGH_DIM_1_SIZE_HIGH_SHIFT 16 +#define QM_TID_BASE_SIZE_HIGH_DIM_1_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TID_BASE_SIZE_HIGH_DIM_2 0xBAC + +#define QM_TID_BASE_SIZE_HIGH_DIM_2_BASE_HIGH_SHIFT 0 +#define QM_TID_BASE_SIZE_HIGH_DIM_2_BASE_HIGH_MASK 0xFFF +#define QM_TID_BASE_SIZE_HIGH_DIM_2_SIZE_HIGH_SHIFT 16 +#define QM_TID_BASE_SIZE_HIGH_DIM_2_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TID_BASE_SIZE_HIGH_DIM_3 0xBB0 + +#define QM_TID_BASE_SIZE_HIGH_DIM_3_BASE_HIGH_SHIFT 0 +#define QM_TID_BASE_SIZE_HIGH_DIM_3_BASE_HIGH_MASK 0xFFF +#define QM_TID_BASE_SIZE_HIGH_DIM_3_SIZE_HIGH_SHIFT 16 +#define QM_TID_BASE_SIZE_HIGH_DIM_3_SIZE_HIGH_MASK 0xFFF0000 + +#define QM_TID_BASE_SIZE_HIGH_DIM_4 0xBB4 + +#define QM_TID_BASE_SIZE_HIGH_DIM_4_BASE_HIGH_SHIFT 0 +#define QM_TID_BASE_SIZE_HIGH_DIM_4_BASE_HIGH_MASK 0xFFF +#define QM_TID_BASE_SIZE_HIGH_DIM_4_SIZE_HIGH_SHIFT 16 +#define QM_TID_BASE_SIZE_HIGH_DIM_4_SIZE_HIGH_MASK 0xFFF0000 + +#define TPC_COUNT 0xC18 + +#define TPC_COUNT_V_SHIFT 0 +#define TPC_COUNT_V_MASK 0xFFFFFFFF + +#define TPC_ID 0xC1C + +#define TPC_ID_V_SHIFT 0 +#define TPC_ID_V_MASK 0xFFFFFFFF + +#define STALL_ON_ERR 0xC20 + +#define STALL_ON_ERR_V_SHIFT 0 +#define STALL_ON_ERR_V_MASK 0x1 + +#define CLK_EN 0xC24 + +#define CLK_EN_LBW_CFG_DIS_SHIFT 0 +#define CLK_EN_LBW_CFG_DIS_MASK 0x1 +#define CLK_EN_DBG_CFG_DIS_SHIFT 4 +#define CLK_EN_DBG_CFG_DIS_MASK 0x10 + +#define IQ_RL_EN 0xC28 + +#define IQ_RL_EN_V_SHIFT 0 +#define IQ_RL_EN_V_MASK 0x1 + +#define IQ_RL_SAT 0xC2C + +#define IQ_RL_SAT_V_SHIFT 0 +#define IQ_RL_SAT_V_MASK 0xFF + +#define IQ_RL_RST_TOKEN 0xC30 + +#define IQ_RL_RST_TOKEN_V_SHIFT 0 +#define IQ_RL_RST_TOKEN_V_MASK 0xFF + +#define IQ_RL_TIMEOUT 0xC34 + +#define IQ_RL_TIMEOUT_V_SHIFT 0 +#define IQ_RL_TIMEOUT_V_MASK 0xFF + +#define TSB_CFG_MTRR_2_0 0xC38 + +#define TSB_CFG_MTRR_2_0_PHY_BASE_ADD_LO_SHIFT 0 +#define TSB_CFG_MTRR_2_0_PHY_BASE_ADD_LO_MASK 0xFFFFFF + +#define TSB_CFG_MTRR_2_1 0xC3C + +#define TSB_CFG_MTRR_2_1_PHY_BASE_ADD_LO_SHIFT 0 +#define TSB_CFG_MTRR_2_1_PHY_BASE_ADD_LO_MASK 0xFFFFFF + +#define TSB_CFG_MTRR_2_2 0xC40 + +#define TSB_CFG_MTRR_2_2_PHY_BASE_ADD_LO_SHIFT 0 +#define TSB_CFG_MTRR_2_2_PHY_BASE_ADD_LO_MASK 0xFFFFFF + +#define TSB_CFG_MTRR_2_3 0xC44 + +#define TSB_CFG_MTRR_2_3_PHY_BASE_ADD_LO_SHIFT 0 +#define TSB_CFG_MTRR_2_3_PHY_BASE_ADD_LO_MASK 0xFFFFFF + +#define IQ_LBW_CLK_EN 0xC48 + +#define IQ_LBW_CLK_EN_V_SHIFT 0 +#define IQ_LBW_CLK_EN_V_MASK 0x1 + +#define TPC_LOCK_VALUE_0 0xC4C + +#define TPC_LOCK_VALUE_0_VALUE_SHIFT 0 +#define TPC_LOCK_VALUE_0_VALUE_MASK 0xFFFFFFFF + +#define TPC_LOCK_VALUE_1 0xC50 + +#define TPC_LOCK_VALUE_1_VALUE_SHIFT 0 +#define TPC_LOCK_VALUE_1_VALUE_MASK 0xFFFFFFFF + +#define TPC_LOCK_VALUE_2 0xC54 + +#define TPC_LOCK_VALUE_2_VALUE_SHIFT 0 +#define TPC_LOCK_VALUE_2_VALUE_MASK 0xFFFFFFFF + +#define TPC_LOCK_VALUE_3 0xC58 + +#define TPC_LOCK_VALUE_3_VALUE_SHIFT 0 +#define TPC_LOCK_VALUE_3_VALUE_MASK 0xFFFFFFFF + +#define TPC_LOCK_0 0xC5C + +#define TPC_LOCK_0_LOCK_SHIFT 0 +#define TPC_LOCK_0_LOCK_MASK 0x1 + +#define TPC_LOCK_1 0xC60 + +#define TPC_LOCK_1_LOCK_SHIFT 0 +#define TPC_LOCK_1_LOCK_MASK 0x1 + +#define TPC_LOCK_2 0xC64 + +#define TPC_LOCK_2_LOCK_SHIFT 0 +#define TPC_LOCK_2_LOCK_MASK 0x1 + +#define TPC_LOCK_3 0xC68 + +#define TPC_LOCK_3_LOCK_SHIFT 0 +#define TPC_LOCK_3_LOCK_MASK 0x1 + +#define CGU_SB 0xC6C + +#define CGU_SB_TSB_DISABLE_SHIFT 0 +#define CGU_SB_TSB_DISABLE_MASK 0x1 + +#define CGU_CNT 0xC70 + +#define CGU_CNT_DCACHE_DISABLE_SHIFT 0 +#define CGU_CNT_DCACHE_DISABLE_MASK 0x1 +#define CGU_CNT_WQ_DISABLE_SHIFT 1 +#define CGU_CNT_WQ_DISABLE_MASK 0x2 +#define CGU_CNT_SPU_AGU_ADDSUB_0_DISABLE_SHIFT 2 +#define CGU_CNT_SPU_AGU_ADDSUB_0_DISABLE_MASK 0x4 +#define CGU_CNT_SPU_AGU_ADDSUB_1_DISABLE_SHIFT 3 +#define CGU_CNT_SPU_AGU_ADDSUB_1_DISABLE_MASK 0x8 +#define CGU_CNT_SPU_AGU_ADDSUB_2_DISABLE_SHIFT 4 +#define CGU_CNT_SPU_AGU_ADDSUB_2_DISABLE_MASK 0x10 +#define CGU_CNT_SPU_AGU_ADDSUB_3_DISABLE_SHIFT 5 +#define CGU_CNT_SPU_AGU_ADDSUB_3_DISABLE_MASK 0x20 +#define CGU_CNT_SPU_AGU_ADDSUB_4_DISABLE_SHIFT 6 +#define CGU_CNT_SPU_AGU_ADDSUB_4_DISABLE_MASK 0x40 +#define CGU_CNT_SPU_AGU_CMP_0_DISABLE_SHIFT 7 +#define CGU_CNT_SPU_AGU_CMP_0_DISABLE_MASK 0x80 +#define CGU_CNT_SPU_AGU_CMP_1_DISABLE_SHIFT 8 +#define CGU_CNT_SPU_AGU_CMP_1_DISABLE_MASK 0x100 +#define CGU_CNT_SPU_AGU_CMP_2_DISABLE_SHIFT 9 +#define CGU_CNT_SPU_AGU_CMP_2_DISABLE_MASK 0x200 +#define CGU_CNT_SPU_AGU_CMP_3_DISABLE_SHIFT 10 +#define CGU_CNT_SPU_AGU_CMP_3_DISABLE_MASK 0x400 +#define CGU_CNT_SPU_AGU_CMP_4_DISABLE_SHIFT 11 +#define CGU_CNT_SPU_AGU_CMP_4_DISABLE_MASK 0x800 +#define CGU_CNT_MSAC_DISABLE_SHIFT 12 +#define CGU_CNT_MSAC_DISABLE_MASK 0x1000 +#define CGU_CNT_CONV_DISABLE_SHIFT 13 +#define CGU_CNT_CONV_DISABLE_MASK 0x2000 +#define CGU_CNT_NEARBYINT_DISABLE_SHIFT 14 +#define CGU_CNT_NEARBYINT_DISABLE_MASK 0x4000 +#define CGU_CNT_CMP_DISABLE_SHIFT 15 +#define CGU_CNT_CMP_DISABLE_MASK 0x8000 +#define CGU_CNT_FP_MAC_DISABLE_SHIFT 16 +#define CGU_CNT_FP_MAC_DISABLE_MASK 0x10000 +#define CGU_CNT_SOPS_SRC_A_D2_DISABLE_SHIFT 17 +#define CGU_CNT_SOPS_SRC_A_D2_DISABLE_MASK 0x20000 +#define CGU_CNT_SOPS_SRC_B_D2_DISABLE_SHIFT 18 +#define CGU_CNT_SOPS_SRC_B_D2_DISABLE_MASK 0x40000 +#define CGU_CNT_SOPS_SRC_E_D2_DISABLE_SHIFT 19 +#define CGU_CNT_SOPS_SRC_E_D2_DISABLE_MASK 0x80000 +#define CGU_CNT_SOPS_FMA_SRC_C_E1_DISABLE_SHIFT 20 +#define CGU_CNT_SOPS_FMA_SRC_C_E1_DISABLE_MASK 0x100000 +#define CGU_CNT_LD_SOPS_SRC_A_D2_DISABLE_SHIFT 21 +#define CGU_CNT_LD_SOPS_SRC_A_D2_DISABLE_MASK 0x200000 +#define CGU_CNT_ST_SOPS_SRC_A_D2_DISABLE_SHIFT 22 +#define CGU_CNT_ST_SOPS_SRC_A_D2_DISABLE_MASK 0x400000 +#define CGU_CNT_FP_ADDSUB_DISABLE_SHIFT 23 +#define CGU_CNT_FP_ADDSUB_DISABLE_MASK 0x800000 + +#define CGU_CPE_0 0xC74 + +#define CGU_CPE_0_NEARBYINT_DISABLE_SHIFT 0 +#define CGU_CPE_0_NEARBYINT_DISABLE_MASK 0x1 +#define CGU_CPE_0_SOPS_SRC_A_DISABLE_SHIFT 1 +#define CGU_CPE_0_SOPS_SRC_A_DISABLE_MASK 0x2 +#define CGU_CPE_0_SOPS_SRC_B_DISABLE_SHIFT 2 +#define CGU_CPE_0_SOPS_SRC_B_DISABLE_MASK 0x4 +#define CGU_CPE_0_SOPS_SRC_E_DISABLE_SHIFT 3 +#define CGU_CPE_0_SOPS_SRC_E_DISABLE_MASK 0x8 +#define CGU_CPE_0_SOPS_SRC_D_DISABLE_SHIFT 4 +#define CGU_CPE_0_SOPS_SRC_D_DISABLE_MASK 0x10 +#define CGU_CPE_0_SOPS_SRC_C_DISABLE_SHIFT 5 +#define CGU_CPE_0_SOPS_SRC_C_DISABLE_MASK 0x20 +#define CGU_CPE_0_LD_SOPS_SRC_A_DISABLE_SHIFT 6 +#define CGU_CPE_0_LD_SOPS_SRC_A_DISABLE_MASK 0x40 +#define CGU_CPE_0_MSAC_DISABLE_SHIFT 7 +#define CGU_CPE_0_MSAC_DISABLE_MASK 0x80 +#define CGU_CPE_0_ADDSUB_DISABLE_SHIFT 8 +#define CGU_CPE_0_ADDSUB_DISABLE_MASK 0x100 +#define CGU_CPE_0_SHIFT_DISABLE_SHIFT 9 +#define CGU_CPE_0_SHIFT_DISABLE_MASK 0x200 +#define CGU_CPE_0_GLE_DISABLE_SHIFT 10 +#define CGU_CPE_0_GLE_DISABLE_MASK 0x400 +#define CGU_CPE_0_CMP_DISABLE_SHIFT 11 +#define CGU_CPE_0_CMP_DISABLE_MASK 0x800 +#define CGU_CPE_0_CONV_DISABLE_SHIFT 12 +#define CGU_CPE_0_CONV_DISABLE_MASK 0x1000 +#define CGU_CPE_0_SB_DISABLE_SHIFT 13 +#define CGU_CPE_0_SB_DISABLE_MASK 0x2000 +#define CGU_CPE_0_TBUF_DISABLE_SHIFT 14 +#define CGU_CPE_0_TBUF_DISABLE_MASK 0x4000 +#define CGU_CPE_0_ST_G_DISABLE_SHIFT 15 +#define CGU_CPE_0_ST_G_DISABLE_MASK 0x8000 +#define CGU_CPE_0_FP_MAC_0_DISABLE_SHIFT 16 +#define CGU_CPE_0_FP_MAC_0_DISABLE_MASK 0x10000 +#define CGU_CPE_0_FP_MAC_1_DISABLE_SHIFT 17 +#define CGU_CPE_0_FP_MAC_1_DISABLE_MASK 0x20000 +#define CGU_CPE_0_FP_ADDSUB_DISABLE_SHIFT 18 +#define CGU_CPE_0_FP_ADDSUB_DISABLE_MASK 0x40000 +#define CGU_CPE_0_ST_SOPS_SRC_C_DISABLE_SHIFT 19 +#define CGU_CPE_0_ST_SOPS_SRC_C_DISABLE_MASK 0x80000 + +#define CGU_CPE_1 0xC78 + +#define CGU_CPE_1_NEARBYINT_DISABLE_SHIFT 0 +#define CGU_CPE_1_NEARBYINT_DISABLE_MASK 0x1 +#define CGU_CPE_1_SOPS_SRC_A_DISABLE_SHIFT 1 +#define CGU_CPE_1_SOPS_SRC_A_DISABLE_MASK 0x2 +#define CGU_CPE_1_SOPS_SRC_B_DISABLE_SHIFT 2 +#define CGU_CPE_1_SOPS_SRC_B_DISABLE_MASK 0x4 +#define CGU_CPE_1_SOPS_SRC_E_DISABLE_SHIFT 3 +#define CGU_CPE_1_SOPS_SRC_E_DISABLE_MASK 0x8 +#define CGU_CPE_1_SOPS_SRC_D_DISABLE_SHIFT 4 +#define CGU_CPE_1_SOPS_SRC_D_DISABLE_MASK 0x10 +#define CGU_CPE_1_SOPS_SRC_C_DISABLE_SHIFT 5 +#define CGU_CPE_1_SOPS_SRC_C_DISABLE_MASK 0x20 +#define CGU_CPE_1_LD_SOPS_SRC_A_DISABLE_SHIFT 6 +#define CGU_CPE_1_LD_SOPS_SRC_A_DISABLE_MASK 0x40 +#define CGU_CPE_1_MSAC_DISABLE_SHIFT 7 +#define CGU_CPE_1_MSAC_DISABLE_MASK 0x80 +#define CGU_CPE_1_ADDSUB_DISABLE_SHIFT 8 +#define CGU_CPE_1_ADDSUB_DISABLE_MASK 0x100 +#define CGU_CPE_1_SHIFT_DISABLE_SHIFT 9 +#define CGU_CPE_1_SHIFT_DISABLE_MASK 0x200 +#define CGU_CPE_1_GLE_DISABLE_SHIFT 10 +#define CGU_CPE_1_GLE_DISABLE_MASK 0x400 +#define CGU_CPE_1_CMP_DISABLE_SHIFT 11 +#define CGU_CPE_1_CMP_DISABLE_MASK 0x800 +#define CGU_CPE_1_CONV_DISABLE_SHIFT 12 +#define CGU_CPE_1_CONV_DISABLE_MASK 0x1000 +#define CGU_CPE_1_SB_DISABLE_SHIFT 13 +#define CGU_CPE_1_SB_DISABLE_MASK 0x2000 +#define CGU_CPE_1_TBUF_DISABLE_SHIFT 14 +#define CGU_CPE_1_TBUF_DISABLE_MASK 0x4000 +#define CGU_CPE_1_ST_G_DISABLE_SHIFT 15 +#define CGU_CPE_1_ST_G_DISABLE_MASK 0x8000 +#define CGU_CPE_1_FP_MAC_0_DISABLE_SHIFT 16 +#define CGU_CPE_1_FP_MAC_0_DISABLE_MASK 0x10000 +#define CGU_CPE_1_FP_MAC_1_DISABLE_SHIFT 17 +#define CGU_CPE_1_FP_MAC_1_DISABLE_MASK 0x20000 +#define CGU_CPE_1_FP_ADDSUB_DISABLE_SHIFT 18 +#define CGU_CPE_1_FP_ADDSUB_DISABLE_MASK 0x40000 +#define CGU_CPE_1_ST_SOPS_SRC_C_DISABLE_SHIFT 19 +#define CGU_CPE_1_ST_SOPS_SRC_C_DISABLE_MASK 0x80000 + +#define CGU_CPE_2 0xC7C + +#define CGU_CPE_2_NEARBYINT_DISABLE_SHIFT 0 +#define CGU_CPE_2_NEARBYINT_DISABLE_MASK 0x1 +#define CGU_CPE_2_SOPS_SRC_A_DISABLE_SHIFT 1 +#define CGU_CPE_2_SOPS_SRC_A_DISABLE_MASK 0x2 +#define CGU_CPE_2_SOPS_SRC_B_DISABLE_SHIFT 2 +#define CGU_CPE_2_SOPS_SRC_B_DISABLE_MASK 0x4 +#define CGU_CPE_2_SOPS_SRC_E_DISABLE_SHIFT 3 +#define CGU_CPE_2_SOPS_SRC_E_DISABLE_MASK 0x8 +#define CGU_CPE_2_SOPS_SRC_D_DISABLE_SHIFT 4 +#define CGU_CPE_2_SOPS_SRC_D_DISABLE_MASK 0x10 +#define CGU_CPE_2_SOPS_SRC_C_DISABLE_SHIFT 5 +#define CGU_CPE_2_SOPS_SRC_C_DISABLE_MASK 0x20 +#define CGU_CPE_2_LD_SOPS_SRC_A_DISABLE_SHIFT 6 +#define CGU_CPE_2_LD_SOPS_SRC_A_DISABLE_MASK 0x40 +#define CGU_CPE_2_MSAC_DISABLE_SHIFT 7 +#define CGU_CPE_2_MSAC_DISABLE_MASK 0x80 +#define CGU_CPE_2_ADDSUB_DISABLE_SHIFT 8 +#define CGU_CPE_2_ADDSUB_DISABLE_MASK 0x100 +#define CGU_CPE_2_SHIFT_DISABLE_SHIFT 9 +#define CGU_CPE_2_SHIFT_DISABLE_MASK 0x200 +#define CGU_CPE_2_GLE_DISABLE_SHIFT 10 +#define CGU_CPE_2_GLE_DISABLE_MASK 0x400 +#define CGU_CPE_2_CMP_DISABLE_SHIFT 11 +#define CGU_CPE_2_CMP_DISABLE_MASK 0x800 +#define CGU_CPE_2_CONV_DISABLE_SHIFT 12 +#define CGU_CPE_2_CONV_DISABLE_MASK 0x1000 +#define CGU_CPE_2_SB_DISABLE_SHIFT 13 +#define CGU_CPE_2_SB_DISABLE_MASK 0x2000 +#define CGU_CPE_2_TBUF_DISABLE_SHIFT 14 +#define CGU_CPE_2_TBUF_DISABLE_MASK 0x4000 +#define CGU_CPE_2_ST_G_DISABLE_SHIFT 15 +#define CGU_CPE_2_ST_G_DISABLE_MASK 0x8000 +#define CGU_CPE_2_FP_MAC_0_DISABLE_SHIFT 16 +#define CGU_CPE_2_FP_MAC_0_DISABLE_MASK 0x10000 +#define CGU_CPE_2_FP_MAC_1_DISABLE_SHIFT 17 +#define CGU_CPE_2_FP_MAC_1_DISABLE_MASK 0x20000 +#define CGU_CPE_2_FP_ADDSUB_DISABLE_SHIFT 18 +#define CGU_CPE_2_FP_ADDSUB_DISABLE_MASK 0x40000 +#define CGU_CPE_2_ST_SOPS_SRC_C_DISABLE_SHIFT 19 +#define CGU_CPE_2_ST_SOPS_SRC_C_DISABLE_MASK 0x80000 + +#define CGU_CPE_3 0xC80 + +#define CGU_CPE_3_NEARBYINT_DISABLE_SHIFT 0 +#define CGU_CPE_3_NEARBYINT_DISABLE_MASK 0x1 +#define CGU_CPE_3_SOPS_SRC_A_DISABLE_SHIFT 1 +#define CGU_CPE_3_SOPS_SRC_A_DISABLE_MASK 0x2 +#define CGU_CPE_3_SOPS_SRC_B_DISABLE_SHIFT 2 +#define CGU_CPE_3_SOPS_SRC_B_DISABLE_MASK 0x4 +#define CGU_CPE_3_SOPS_SRC_E_DISABLE_SHIFT 3 +#define CGU_CPE_3_SOPS_SRC_E_DISABLE_MASK 0x8 +#define CGU_CPE_3_SOPS_SRC_D_DISABLE_SHIFT 4 +#define CGU_CPE_3_SOPS_SRC_D_DISABLE_MASK 0x10 +#define CGU_CPE_3_SOPS_SRC_C_DISABLE_SHIFT 5 +#define CGU_CPE_3_SOPS_SRC_C_DISABLE_MASK 0x20 +#define CGU_CPE_3_LD_SOPS_SRC_A_DISABLE_SHIFT 6 +#define CGU_CPE_3_LD_SOPS_SRC_A_DISABLE_MASK 0x40 +#define CGU_CPE_3_MSAC_DISABLE_SHIFT 7 +#define CGU_CPE_3_MSAC_DISABLE_MASK 0x80 +#define CGU_CPE_3_ADDSUB_DISABLE_SHIFT 8 +#define CGU_CPE_3_ADDSUB_DISABLE_MASK 0x100 +#define CGU_CPE_3_SHIFT_DISABLE_SHIFT 9 +#define CGU_CPE_3_SHIFT_DISABLE_MASK 0x200 +#define CGU_CPE_3_GLE_DISABLE_SHIFT 10 +#define CGU_CPE_3_GLE_DISABLE_MASK 0x400 +#define CGU_CPE_3_CMP_DISABLE_SHIFT 11 +#define CGU_CPE_3_CMP_DISABLE_MASK 0x800 +#define CGU_CPE_3_CONV_DISABLE_SHIFT 12 +#define CGU_CPE_3_CONV_DISABLE_MASK 0x1000 +#define CGU_CPE_3_SB_DISABLE_SHIFT 13 +#define CGU_CPE_3_SB_DISABLE_MASK 0x2000 +#define CGU_CPE_3_TBUF_DISABLE_SHIFT 14 +#define CGU_CPE_3_TBUF_DISABLE_MASK 0x4000 +#define CGU_CPE_3_ST_G_DISABLE_SHIFT 15 +#define CGU_CPE_3_ST_G_DISABLE_MASK 0x8000 +#define CGU_CPE_3_FP_MAC_0_DISABLE_SHIFT 16 +#define CGU_CPE_3_FP_MAC_0_DISABLE_MASK 0x10000 +#define CGU_CPE_3_FP_MAC_1_DISABLE_SHIFT 17 +#define CGU_CPE_3_FP_MAC_1_DISABLE_MASK 0x20000 +#define CGU_CPE_3_FP_ADDSUB_DISABLE_SHIFT 18 +#define CGU_CPE_3_FP_ADDSUB_DISABLE_MASK 0x40000 +#define CGU_CPE_3_ST_SOPS_SRC_C_DISABLE_SHIFT 19 +#define CGU_CPE_3_ST_SOPS_SRC_C_DISABLE_MASK 0x80000 + +#define CGU_CPE_4 0xC84 + +#define CGU_CPE_4_NEARBYINT_DISABLE_SHIFT 0 +#define CGU_CPE_4_NEARBYINT_DISABLE_MASK 0x1 +#define CGU_CPE_4_SOPS_SRC_A_DISABLE_SHIFT 1 +#define CGU_CPE_4_SOPS_SRC_A_DISABLE_MASK 0x2 +#define CGU_CPE_4_SOPS_SRC_B_DISABLE_SHIFT 2 +#define CGU_CPE_4_SOPS_SRC_B_DISABLE_MASK 0x4 +#define CGU_CPE_4_SOPS_SRC_E_DISABLE_SHIFT 3 +#define CGU_CPE_4_SOPS_SRC_E_DISABLE_MASK 0x8 +#define CGU_CPE_4_SOPS_SRC_D_DISABLE_SHIFT 4 +#define CGU_CPE_4_SOPS_SRC_D_DISABLE_MASK 0x10 +#define CGU_CPE_4_SOPS_SRC_C_DISABLE_SHIFT 5 +#define CGU_CPE_4_SOPS_SRC_C_DISABLE_MASK 0x20 +#define CGU_CPE_4_LD_SOPS_SRC_A_DISABLE_SHIFT 6 +#define CGU_CPE_4_LD_SOPS_SRC_A_DISABLE_MASK 0x40 +#define CGU_CPE_4_MSAC_DISABLE_SHIFT 7 +#define CGU_CPE_4_MSAC_DISABLE_MASK 0x80 +#define CGU_CPE_4_ADDSUB_DISABLE_SHIFT 8 +#define CGU_CPE_4_ADDSUB_DISABLE_MASK 0x100 +#define CGU_CPE_4_SHIFT_DISABLE_SHIFT 9 +#define CGU_CPE_4_SHIFT_DISABLE_MASK 0x200 +#define CGU_CPE_4_GLE_DISABLE_SHIFT 10 +#define CGU_CPE_4_GLE_DISABLE_MASK 0x400 +#define CGU_CPE_4_CMP_DISABLE_SHIFT 11 +#define CGU_CPE_4_CMP_DISABLE_MASK 0x800 +#define CGU_CPE_4_CONV_DISABLE_SHIFT 12 +#define CGU_CPE_4_CONV_DISABLE_MASK 0x1000 +#define CGU_CPE_4_SB_DISABLE_SHIFT 13 +#define CGU_CPE_4_SB_DISABLE_MASK 0x2000 +#define CGU_CPE_4_TBUF_DISABLE_SHIFT 14 +#define CGU_CPE_4_TBUF_DISABLE_MASK 0x4000 +#define CGU_CPE_4_ST_G_DISABLE_SHIFT 15 +#define CGU_CPE_4_ST_G_DISABLE_MASK 0x8000 +#define CGU_CPE_4_FP_MAC_0_DISABLE_SHIFT 16 +#define CGU_CPE_4_FP_MAC_0_DISABLE_MASK 0x10000 +#define CGU_CPE_4_FP_MAC_1_DISABLE_SHIFT 17 +#define CGU_CPE_4_FP_MAC_1_DISABLE_MASK 0x20000 +#define CGU_CPE_4_FP_ADDSUB_DISABLE_SHIFT 18 +#define CGU_CPE_4_FP_ADDSUB_DISABLE_MASK 0x40000 +#define CGU_CPE_4_ST_SOPS_SRC_C_DISABLE_SHIFT 19 +#define CGU_CPE_4_ST_SOPS_SRC_C_DISABLE_MASK 0x80000 + +#define CGU_CPE_5 0xC88 + +#define CGU_CPE_5_NEARBYINT_DISABLE_SHIFT 0 +#define CGU_CPE_5_NEARBYINT_DISABLE_MASK 0x1 +#define CGU_CPE_5_SOPS_SRC_A_DISABLE_SHIFT 1 +#define CGU_CPE_5_SOPS_SRC_A_DISABLE_MASK 0x2 +#define CGU_CPE_5_SOPS_SRC_B_DISABLE_SHIFT 2 +#define CGU_CPE_5_SOPS_SRC_B_DISABLE_MASK 0x4 +#define CGU_CPE_5_SOPS_SRC_E_DISABLE_SHIFT 3 +#define CGU_CPE_5_SOPS_SRC_E_DISABLE_MASK 0x8 +#define CGU_CPE_5_SOPS_SRC_D_DISABLE_SHIFT 4 +#define CGU_CPE_5_SOPS_SRC_D_DISABLE_MASK 0x10 +#define CGU_CPE_5_SOPS_SRC_C_DISABLE_SHIFT 5 +#define CGU_CPE_5_SOPS_SRC_C_DISABLE_MASK 0x20 +#define CGU_CPE_5_LD_SOPS_SRC_A_DISABLE_SHIFT 6 +#define CGU_CPE_5_LD_SOPS_SRC_A_DISABLE_MASK 0x40 +#define CGU_CPE_5_MSAC_DISABLE_SHIFT 7 +#define CGU_CPE_5_MSAC_DISABLE_MASK 0x80 +#define CGU_CPE_5_ADDSUB_DISABLE_SHIFT 8 +#define CGU_CPE_5_ADDSUB_DISABLE_MASK 0x100 +#define CGU_CPE_5_SHIFT_DISABLE_SHIFT 9 +#define CGU_CPE_5_SHIFT_DISABLE_MASK 0x200 +#define CGU_CPE_5_GLE_DISABLE_SHIFT 10 +#define CGU_CPE_5_GLE_DISABLE_MASK 0x400 +#define CGU_CPE_5_CMP_DISABLE_SHIFT 11 +#define CGU_CPE_5_CMP_DISABLE_MASK 0x800 +#define CGU_CPE_5_CONV_DISABLE_SHIFT 12 +#define CGU_CPE_5_CONV_DISABLE_MASK 0x1000 +#define CGU_CPE_5_SB_DISABLE_SHIFT 13 +#define CGU_CPE_5_SB_DISABLE_MASK 0x2000 +#define CGU_CPE_5_TBUF_DISABLE_SHIFT 14 +#define CGU_CPE_5_TBUF_DISABLE_MASK 0x4000 +#define CGU_CPE_5_ST_G_DISABLE_SHIFT 15 +#define CGU_CPE_5_ST_G_DISABLE_MASK 0x8000 +#define CGU_CPE_5_FP_MAC_0_DISABLE_SHIFT 16 +#define CGU_CPE_5_FP_MAC_0_DISABLE_MASK 0x10000 +#define CGU_CPE_5_FP_MAC_1_DISABLE_SHIFT 17 +#define CGU_CPE_5_FP_MAC_1_DISABLE_MASK 0x20000 +#define CGU_CPE_5_FP_ADDSUB_DISABLE_SHIFT 18 +#define CGU_CPE_5_FP_ADDSUB_DISABLE_MASK 0x40000 +#define CGU_CPE_5_ST_SOPS_SRC_C_DISABLE_SHIFT 19 +#define CGU_CPE_5_ST_SOPS_SRC_C_DISABLE_MASK 0x80000 + +#define CGU_CPE_6 0xC8C + +#define CGU_CPE_6_NEARBYINT_DISABLE_SHIFT 0 +#define CGU_CPE_6_NEARBYINT_DISABLE_MASK 0x1 +#define CGU_CPE_6_SOPS_SRC_A_DISABLE_SHIFT 1 +#define CGU_CPE_6_SOPS_SRC_A_DISABLE_MASK 0x2 +#define CGU_CPE_6_SOPS_SRC_B_DISABLE_SHIFT 2 +#define CGU_CPE_6_SOPS_SRC_B_DISABLE_MASK 0x4 +#define CGU_CPE_6_SOPS_SRC_E_DISABLE_SHIFT 3 +#define CGU_CPE_6_SOPS_SRC_E_DISABLE_MASK 0x8 +#define CGU_CPE_6_SOPS_SRC_D_DISABLE_SHIFT 4 +#define CGU_CPE_6_SOPS_SRC_D_DISABLE_MASK 0x10 +#define CGU_CPE_6_SOPS_SRC_C_DISABLE_SHIFT 5 +#define CGU_CPE_6_SOPS_SRC_C_DISABLE_MASK 0x20 +#define CGU_CPE_6_LD_SOPS_SRC_A_DISABLE_SHIFT 6 +#define CGU_CPE_6_LD_SOPS_SRC_A_DISABLE_MASK 0x40 +#define CGU_CPE_6_MSAC_DISABLE_SHIFT 7 +#define CGU_CPE_6_MSAC_DISABLE_MASK 0x80 +#define CGU_CPE_6_ADDSUB_DISABLE_SHIFT 8 +#define CGU_CPE_6_ADDSUB_DISABLE_MASK 0x100 +#define CGU_CPE_6_SHIFT_DISABLE_SHIFT 9 +#define CGU_CPE_6_SHIFT_DISABLE_MASK 0x200 +#define CGU_CPE_6_GLE_DISABLE_SHIFT 10 +#define CGU_CPE_6_GLE_DISABLE_MASK 0x400 +#define CGU_CPE_6_CMP_DISABLE_SHIFT 11 +#define CGU_CPE_6_CMP_DISABLE_MASK 0x800 +#define CGU_CPE_6_CONV_DISABLE_SHIFT 12 +#define CGU_CPE_6_CONV_DISABLE_MASK 0x1000 +#define CGU_CPE_6_SB_DISABLE_SHIFT 13 +#define CGU_CPE_6_SB_DISABLE_MASK 0x2000 +#define CGU_CPE_6_TBUF_DISABLE_SHIFT 14 +#define CGU_CPE_6_TBUF_DISABLE_MASK 0x4000 +#define CGU_CPE_6_ST_G_DISABLE_SHIFT 15 +#define CGU_CPE_6_ST_G_DISABLE_MASK 0x8000 +#define CGU_CPE_6_FP_MAC_0_DISABLE_SHIFT 16 +#define CGU_CPE_6_FP_MAC_0_DISABLE_MASK 0x10000 +#define CGU_CPE_6_FP_MAC_1_DISABLE_SHIFT 17 +#define CGU_CPE_6_FP_MAC_1_DISABLE_MASK 0x20000 +#define CGU_CPE_6_FP_ADDSUB_DISABLE_SHIFT 18 +#define CGU_CPE_6_FP_ADDSUB_DISABLE_MASK 0x40000 +#define CGU_CPE_6_ST_SOPS_SRC_C_DISABLE_SHIFT 19 +#define CGU_CPE_6_ST_SOPS_SRC_C_DISABLE_MASK 0x80000 + +#define CGU_CPE_7 0xC90 + +#define CGU_CPE_7_NEARBYINT_DISABLE_SHIFT 0 +#define CGU_CPE_7_NEARBYINT_DISABLE_MASK 0x1 +#define CGU_CPE_7_SOPS_SRC_A_DISABLE_SHIFT 1 +#define CGU_CPE_7_SOPS_SRC_A_DISABLE_MASK 0x2 +#define CGU_CPE_7_SOPS_SRC_B_DISABLE_SHIFT 2 +#define CGU_CPE_7_SOPS_SRC_B_DISABLE_MASK 0x4 +#define CGU_CPE_7_SOPS_SRC_E_DISABLE_SHIFT 3 +#define CGU_CPE_7_SOPS_SRC_E_DISABLE_MASK 0x8 +#define CGU_CPE_7_SOPS_SRC_D_DISABLE_SHIFT 4 +#define CGU_CPE_7_SOPS_SRC_D_DISABLE_MASK 0x10 +#define CGU_CPE_7_SOPS_SRC_C_DISABLE_SHIFT 5 +#define CGU_CPE_7_SOPS_SRC_C_DISABLE_MASK 0x20 +#define CGU_CPE_7_LD_SOPS_SRC_A_DISABLE_SHIFT 6 +#define CGU_CPE_7_LD_SOPS_SRC_A_DISABLE_MASK 0x40 +#define CGU_CPE_7_MSAC_DISABLE_SHIFT 7 +#define CGU_CPE_7_MSAC_DISABLE_MASK 0x80 +#define CGU_CPE_7_ADDSUB_DISABLE_SHIFT 8 +#define CGU_CPE_7_ADDSUB_DISABLE_MASK 0x100 +#define CGU_CPE_7_SHIFT_DISABLE_SHIFT 9 +#define CGU_CPE_7_SHIFT_DISABLE_MASK 0x200 +#define CGU_CPE_7_GLE_DISABLE_SHIFT 10 +#define CGU_CPE_7_GLE_DISABLE_MASK 0x400 +#define CGU_CPE_7_CMP_DISABLE_SHIFT 11 +#define CGU_CPE_7_CMP_DISABLE_MASK 0x800 +#define CGU_CPE_7_CONV_DISABLE_SHIFT 12 +#define CGU_CPE_7_CONV_DISABLE_MASK 0x1000 +#define CGU_CPE_7_SB_DISABLE_SHIFT 13 +#define CGU_CPE_7_SB_DISABLE_MASK 0x2000 +#define CGU_CPE_7_TBUF_DISABLE_SHIFT 14 +#define CGU_CPE_7_TBUF_DISABLE_MASK 0x4000 +#define CGU_CPE_7_ST_G_DISABLE_SHIFT 15 +#define CGU_CPE_7_ST_G_DISABLE_MASK 0x8000 +#define CGU_CPE_7_FP_MAC_0_DISABLE_SHIFT 16 +#define CGU_CPE_7_FP_MAC_0_DISABLE_MASK 0x10000 +#define CGU_CPE_7_FP_MAC_1_DISABLE_SHIFT 17 +#define CGU_CPE_7_FP_MAC_1_DISABLE_MASK 0x20000 +#define CGU_CPE_7_FP_ADDSUB_DISABLE_SHIFT 18 +#define CGU_CPE_7_FP_ADDSUB_DISABLE_MASK 0x40000 +#define CGU_CPE_7_ST_SOPS_SRC_C_DISABLE_SHIFT 19 +#define CGU_CPE_7_ST_SOPS_SRC_C_DISABLE_MASK 0x80000 + +#define FP16_FTZ_IN 0xC94 + +#define FP16_FTZ_IN_MODE_SHIFT 0 +#define FP16_FTZ_IN_MODE_MASK 0x1 + +#define DCACHE_CFG 0xC98 + +#define DCACHE_CFG_G_PREF_DIS_SHIFT 0 +#define DCACHE_CFG_G_PREF_DIS_MASK 0x1 +#define DCACHE_CFG_G_PREF_VLD_CLR_SHIFT 1 +#define DCACHE_CFG_G_PREF_VLD_CLR_MASK 0x2 +#define DCACHE_CFG_HALT_FLUSH_SHIFT 2 +#define DCACHE_CFG_HALT_FLUSH_MASK 0x4 +#define DCACHE_CFG_DEALIGN_DIS_SHIFT 3 +#define DCACHE_CFG_DEALIGN_DIS_MASK 0x8 + +#define E2E_CRDT_TOP 0xC9C + +#define E2E_CRDT_TOP_FORCE_EN_SHIFT 0 +#define E2E_CRDT_TOP_FORCE_EN_MASK 0x1 +#define E2E_CRDT_TOP_Y_X_FORCE_SHIFT 4 +#define E2E_CRDT_TOP_Y_X_FORCE_MASK 0x1FF0 + +#define TPC_DCACHE_L0CD 0xCA0 + +#define TPC_DCACHE_L0CD_VAL_SHIFT 0 +#define TPC_DCACHE_L0CD_VAL_MASK 0x1 + +#define TPC_SB_L0CD 0xCA4 + +#define TPC_SB_L0CD_VAL_SHIFT 0 +#define TPC_SB_L0CD_VAL_MASK 0x1 + +#define CONV_ROUND_CSR 0xCA8 + +#define CONV_ROUND_CSR_MODE_SHIFT 0 +#define CONV_ROUND_CSR_MODE_MASK 0x7 + +#define TSB_OCCUPANCY 0xCAC + +#define TSB_OCCUPANCY_V_SHIFT 0 +#define TSB_OCCUPANCY_V_MASK 0xFFFFFFFF + +#define ARB_QNT_HBW_WEIGHT 0xCB0 + +#define ARB_QNT_HBW_WEIGHT_AR_SHIFT 0 +#define ARB_QNT_HBW_WEIGHT_AR_MASK 0xFFF +#define ARB_QNT_HBW_WEIGHT_AW_SHIFT 12 +#define ARB_QNT_HBW_WEIGHT_AW_MASK 0xFF000 + +#define ARB_QNT_LBW_WEIGHT 0xCB4 + +#define ARB_QNT_LBW_WEIGHT_AW_SHIFT 0 +#define ARB_QNT_LBW_WEIGHT_AW_MASK 0xFF +#define ARB_QNT_LBW_WEIGHT_AR_SHIFT 8 +#define ARB_QNT_LBW_WEIGHT_AR_MASK 0xFF00 + +#define ARB_CNT_HBW_WEIGHT 0xCB8 + +#define ARB_CNT_HBW_WEIGHT_AR_SHIFT 0 +#define ARB_CNT_HBW_WEIGHT_AR_MASK 0xFFF +#define ARB_CNT_HBW_WEIGHT_AW_SHIFT 12 +#define ARB_CNT_HBW_WEIGHT_AW_MASK 0xFFF000 + +#define ARB_CNT_LBW_WEIGHT 0xCBC + +#define ARB_CNT_LBW_WEIGHT_AR_SHIFT 0 +#define ARB_CNT_LBW_WEIGHT_AR_MASK 0xFF +#define ARB_CNT_LBW_WEIGHT_AW_SHIFT 8 +#define ARB_CNT_LBW_WEIGHT_AW_MASK 0xFFF00 + +#define LUT_FUNC32_BASE2_ADDR_LO 0xCC0 + +#define LUT_FUNC32_BASE2_ADDR_LO_V_SHIFT 0 +#define LUT_FUNC32_BASE2_ADDR_LO_V_MASK 0xFFFFFFFF + +#define LUT_FUNC32_BASE2_ADDR_HI 0xCC4 + +#define LUT_FUNC32_BASE2_ADDR_HI_V_SHIFT 0 +#define LUT_FUNC32_BASE2_ADDR_HI_V_MASK 0xFFFFFFFF + +#define LUT_FUNC64_BASE2_ADDR_LO 0xCC8 + +#define LUT_FUNC64_BASE2_ADDR_LO_V_SHIFT 0 +#define LUT_FUNC64_BASE2_ADDR_LO_V_MASK 0xFFFFFFFF + +#define LUT_FUNC64_BASE2_ADDR_HI 0xCCC + +#define LUT_FUNC64_BASE2_ADDR_HI_V_SHIFT 0 +#define LUT_FUNC64_BASE2_ADDR_HI_V_MASK 0xFFFFFFFF + +#define LUT_FUNC128_BASE2_ADDR_LO 0xCD0 + +#define LUT_FUNC128_BASE2_ADDR_LO_V_SHIFT 0 +#define LUT_FUNC128_BASE2_ADDR_LO_V_MASK 0xFFFFFFFF + +#define LUT_FUNC128_BASE2_ADDR_HI 0xCD4 + +#define LUT_FUNC128_BASE2_ADDR_HI_V_SHIFT 0 +#define LUT_FUNC128_BASE2_ADDR_HI_V_MASK 0xFFFFFFFF + +#define LUT_FUNC256_BASE2_ADDR_LO 0xCD8 + +#define LUT_FUNC256_BASE2_ADDR_LO_V_SHIFT 0 +#define LUT_FUNC256_BASE2_ADDR_LO_V_MASK 0xFFFFFFFF + +#define LUT_FUNC256_BASE2_ADDR_HI 0xCDC + +#define LUT_FUNC256_BASE2_ADDR_HI_V_SHIFT 0 +#define LUT_FUNC256_BASE2_ADDR_HI_V_MASK 0xFFFFFFFF + +#define SPE_LFSR_POLYNOM 0xCE0 + +#define SPE_LFSR_POLYNOM_V_SHIFT 0 +#define SPE_LFSR_POLYNOM_V_MASK 0xFFFFFFFF + +#define TSB_CFG_MTRR_GLBL 0xCE4 + +#define TSB_CFG_MTRR_GLBL_EN_SHIFT 0 +#define TSB_CFG_MTRR_GLBL_EN_MASK 0x1 +#define TSB_CFG_MTRR_GLBL_DEFAULT_MEMORY_TYPE_SHIFT 4 +#define TSB_CFG_MTRR_GLBL_DEFAULT_MEMORY_TYPE_MASK 0x10 + +#define TSB_CFG_MTRR_0 0xCE8 + +#define TSB_CFG_MTRR_0_VALID_SHIFT 0 +#define TSB_CFG_MTRR_0_VALID_MASK 0x1 +#define TSB_CFG_MTRR_0_MEMORY_TYPE_SHIFT 4 +#define TSB_CFG_MTRR_0_MEMORY_TYPE_MASK 0x10 +#define TSB_CFG_MTRR_0_PHY_BASE_ADD_SHIFT 8 +#define TSB_CFG_MTRR_0_PHY_BASE_ADD_MASK 0xFFFF00 + +#define TSB_CFG_MTRR_1 0xCEC + +#define TSB_CFG_MTRR_1_VALID_SHIFT 0 +#define TSB_CFG_MTRR_1_VALID_MASK 0x1 +#define TSB_CFG_MTRR_1_MEMORY_TYPE_SHIFT 4 +#define TSB_CFG_MTRR_1_MEMORY_TYPE_MASK 0x10 +#define TSB_CFG_MTRR_1_PHY_BASE_ADD_SHIFT 8 +#define TSB_CFG_MTRR_1_PHY_BASE_ADD_MASK 0xFFFF00 + +#define TSB_CFG_MTRR_2 0xCF0 + +#define TSB_CFG_MTRR_2_VALID_SHIFT 0 +#define TSB_CFG_MTRR_2_VALID_MASK 0x1 +#define TSB_CFG_MTRR_2_MEMORY_TYPE_SHIFT 4 +#define TSB_CFG_MTRR_2_MEMORY_TYPE_MASK 0x10 +#define TSB_CFG_MTRR_2_PHY_BASE_ADD_SHIFT 8 +#define TSB_CFG_MTRR_2_PHY_BASE_ADD_MASK 0xFFFF00 + +#define TSB_CFG_MTRR_3 0xCF4 + +#define TSB_CFG_MTRR_3_VALID_SHIFT 0 +#define TSB_CFG_MTRR_3_VALID_MASK 0x1 +#define TSB_CFG_MTRR_3_MEMORY_TYPE_SHIFT 4 +#define TSB_CFG_MTRR_3_MEMORY_TYPE_MASK 0x10 +#define TSB_CFG_MTRR_3_PHY_BASE_ADD_SHIFT 8 +#define TSB_CFG_MTRR_3_PHY_BASE_ADD_MASK 0xFFFF00 + +#define TSB_CFG_MTRR_MASK_LO_0 0xCF8 + +#define TSB_CFG_MTRR_MASK_LO_0_V_SHIFT 0 +#define TSB_CFG_MTRR_MASK_LO_0_V_MASK 0xFFFFFFFF + +#define TSB_CFG_MTRR_MASK_LO_1 0xCFC + +#define TSB_CFG_MTRR_MASK_LO_1_V_SHIFT 0 +#define TSB_CFG_MTRR_MASK_LO_1_V_MASK 0xFFFFFFFF + +#define TSB_CFG_MTRR_MASK_LO_2 0xD00 + +#define TSB_CFG_MTRR_MASK_LO_2_V_SHIFT 0 +#define TSB_CFG_MTRR_MASK_LO_2_V_MASK 0xFFFFFFFF + +#define TSB_CFG_MTRR_MASK_LO_3 0xD04 + +#define TSB_CFG_MTRR_MASK_LO_3_V_SHIFT 0 +#define TSB_CFG_MTRR_MASK_LO_3_V_MASK 0xFFFFFFFF + +#define TSB_CFG_MTRR_MASK_HI_0 0xD08 + +#define TSB_CFG_MTRR_MASK_HI_0_V_SHIFT 0 +#define TSB_CFG_MTRR_MASK_HI_0_V_MASK 0xFF + +#define TSB_CFG_MTRR_MASK_HI_1 0xD0C + +#define TSB_CFG_MTRR_MASK_HI_1_V_SHIFT 0 +#define TSB_CFG_MTRR_MASK_HI_1_V_MASK 0xFF + +#define TSB_CFG_MTRR_MASK_HI_2 0xD10 + +#define TSB_CFG_MTRR_MASK_HI_2_V_SHIFT 0 +#define TSB_CFG_MTRR_MASK_HI_2_V_MASK 0xFF + +#define TSB_CFG_MTRR_MASK_HI_3 0xD14 + +#define TSB_CFG_MTRR_MASK_HI_3_V_SHIFT 0 +#define TSB_CFG_MTRR_MASK_HI_3_V_MASK 0xFF + +#define FP8_143_BIAS 0xD64 + +#define FP8_143_BIAS_BIAS_143_SHIFT 0 +#define FP8_143_BIAS_BIAS_143_MASK 0xF + +#define ROUND_CSR 0xD68 + +#define ROUND_CSR_MODE_SHIFT 0 +#define ROUND_CSR_MODE_MASK 0x7 + +#define HB_PROT 0xD6C + +#define HB_PROT_AWPROT_SHIFT 0 +#define HB_PROT_AWPROT_MASK 0x7 +#define HB_PROT_ARPROT_SHIFT 3 +#define HB_PROT_ARPROT_MASK 0x38 + +#define LB_PROT 0xD70 + +#define LB_PROT_AWPROT_SHIFT 0 +#define LB_PROT_AWPROT_MASK 0x7 +#define LB_PROT_ARPROT_SHIFT 3 +#define LB_PROT_ARPROT_MASK 0x38 + +#define SEMAPHORE 0xD74 + +#define SEMAPHORE_V_SHIFT 0 +#define SEMAPHORE_V_MASK 0xFFFFFFFF + +#define VFLAGS 0xD78 + +#define VFLAGS_V_SHIFT 0 +#define VFLAGS_V_MASK 0x7F + +#define SFLAGS 0xD7C + +#define SFLAGS_V_SHIFT 0 +#define SFLAGS_V_MASK 0x7F + +#define LFSR_POLYNOM 0xD80 + +#define LFSR_POLYNOM_V_SHIFT 0 +#define LFSR_POLYNOM_V_MASK 0xFFFFFFFF + +#define STATUS 0xD84 + +#define STATUS_SCALAR_PIPE_EMPTY_SHIFT 1 +#define STATUS_SCALAR_PIPE_EMPTY_MASK 0x2 +#define STATUS_VECTOR_PIPE_EMPTY_SHIFT 2 +#define STATUS_VECTOR_PIPE_EMPTY_MASK 0x4 +#define STATUS_IQ_EMPTY_SHIFT 3 +#define STATUS_IQ_EMPTY_MASK 0x8 +#define STATUS_SB_EMPTY_SHIFT 5 +#define STATUS_SB_EMPTY_MASK 0x20 +#define STATUS_QM_IDLE_SHIFT 6 +#define STATUS_QM_IDLE_MASK 0x40 +#define STATUS_QM_RDY_SHIFT 7 +#define STATUS_QM_RDY_MASK 0x80 + +#define CFG_BASE_ADDRESS_HIGH 0xD88 + +#define CFG_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define CFG_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +#define CFG_SUBTRACT_VALUE 0xD8C + +#define CFG_SUBTRACT_VALUE_V_SHIFT 0 +#define CFG_SUBTRACT_VALUE_V_MASK 0xFFFFFFFF + +#define SM_BASE_ADDRESS_HIGH 0xD90 + +#define SM_BASE_ADDRESS_HIGH_V_SHIFT 0 +#define SM_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF + +#define TPC_CMD 0xD94 + +#define TPC_CMD_ICACHE_INVALIDATE_SHIFT 0 +#define TPC_CMD_ICACHE_INVALIDATE_MASK 0x1 +#define TPC_CMD_DCACHE_INVALIDATE_SHIFT 1 +#define TPC_CMD_DCACHE_INVALIDATE_MASK 0x2 +#define TPC_CMD_LCACHE_INVALIDATE_SHIFT 2 +#define TPC_CMD_LCACHE_INVALIDATE_MASK 0x4 +#define TPC_CMD_TCACHE_INVALIDATE_SHIFT 3 +#define TPC_CMD_TCACHE_INVALIDATE_MASK 0x8 +#define TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT 4 +#define TPC_CMD_ICACHE_PREFETCH_64KB_MASK 0x10 +#define TPC_CMD_ICACHE_PREFETCH_32KB_SHIFT 5 +#define TPC_CMD_ICACHE_PREFETCH_32KB_MASK 0x20 +#define TPC_CMD_QMAN_STOP_SHIFT 6 +#define TPC_CMD_QMAN_STOP_MASK 0x40 + +#define TPC_EXECUTE 0xD98 + +#define TPC_EXECUTE_V_SHIFT 0 +#define TPC_EXECUTE_V_MASK 0x1 + +#define TPC_STALL 0xD9C + +#define TPC_STALL_V_SHIFT 0 +#define TPC_STALL_V_MASK 0x1 + +#define ICACHE_BASE_ADDERESS_LOW 0xDA0 + +#define ICACHE_BASE_ADDERESS_LOW_V_SHIFT 0 +#define ICACHE_BASE_ADDERESS_LOW_V_MASK 0xFFFFFFFF + +#define ICACHE_BASE_ADDERESS_HIGH 0xDA4 + +#define ICACHE_BASE_ADDERESS_HIGH_V_SHIFT 0 +#define ICACHE_BASE_ADDERESS_HIGH_V_MASK 0xFFFFFFFF + +#define RD_RATE_LIMIT 0xDA8 + +#define RD_RATE_LIMIT_ENABLE_SHIFT 0 +#define RD_RATE_LIMIT_ENABLE_MASK 0x1 +#define RD_RATE_LIMIT_SATURATION_SHIFT 1 +#define RD_RATE_LIMIT_SATURATION_MASK 0x1FE +#define RD_RATE_LIMIT_TIMEOUT_SHIFT 9 +#define RD_RATE_LIMIT_TIMEOUT_MASK 0x1FE00 + +#define WR_RATE_LIMIT 0xDAC + +#define WR_RATE_LIMIT_ENABLE_SHIFT 0 +#define WR_RATE_LIMIT_ENABLE_MASK 0x1 +#define WR_RATE_LIMIT_SATURATION_SHIFT 1 +#define WR_RATE_LIMIT_SATURATION_MASK 0x1FE +#define WR_RATE_LIMIT_TIMEOUT_SHIFT 9 +#define WR_RATE_LIMIT_TIMEOUT_MASK 0x1FE00 + +#define MSS_CONFIG 0xDB0 + +#define MSS_CONFIG_AWCACHE_SHIFT 0 +#define MSS_CONFIG_AWCACHE_MASK 0xF +#define MSS_CONFIG_ARCACHE_SHIFT 4 +#define MSS_CONFIG_ARCACHE_MASK 0xF0 +#define MSS_CONFIG_ICACHE_FETCH_LINE_NUM_SHIFT 8 +#define MSS_CONFIG_ICACHE_FETCH_LINE_NUM_MASK 0x300 +#define MSS_CONFIG_EXPOSED_PIPE_DIS_SHIFT 10 +#define MSS_CONFIG_EXPOSED_PIPE_DIS_MASK 0x400 +#define MSS_CONFIG_DCACHE_PREFETCH_DIS_SHIFT 11 +#define MSS_CONFIG_DCACHE_PREFETCH_DIS_MASK 0x800 + +#define TPC_INTR_CAUSE 0xDB4 + +#define TPC_INTR_CAUSE_CAUSE_SHIFT 0 +#define TPC_INTR_CAUSE_CAUSE_MASK 0xFFFFFFFF + +#define TPC_INTR_MASK 0xDB8 + +#define TPC_INTR_MASK_MASK_SHIFT 0 +#define TPC_INTR_MASK_MASK_MASK 0xFFFFFFFF + +#define WQ_CREDITS 0xDBC + +#define WQ_CREDITS_ST_G_SHIFT 0 +#define WQ_CREDITS_ST_G_MASK 0xF +#define WQ_CREDITS_KERNEL_FIFO_SHIFT 4 +#define WQ_CREDITS_KERNEL_FIFO_MASK 0x70 + +#define OPCODE_EXEC 0xDC0 + +#define OPCODE_EXEC_SPU_OP_SHIFT 0 +#define OPCODE_EXEC_SPU_OP_MASK 0x7F +#define OPCODE_EXEC_SPU_EN_SHIFT 7 +#define OPCODE_EXEC_SPU_EN_MASK 0x80 +#define OPCODE_EXEC_VPU_OP_SHIFT 8 +#define OPCODE_EXEC_VPU_OP_MASK 0x7F00 +#define OPCODE_EXEC_VPU_EN_SHIFT 15 +#define OPCODE_EXEC_VPU_EN_MASK 0x8000 +#define OPCODE_EXEC_LD_OP_SHIFT 16 +#define OPCODE_EXEC_LD_OP_MASK 0x7F0000 +#define OPCODE_EXEC_LD_EN_SHIFT 23 +#define OPCODE_EXEC_LD_EN_MASK 0x800000 +#define OPCODE_EXEC_ST_OP_SHIFT 24 +#define OPCODE_EXEC_ST_OP_MASK 0x7F000000 +#define OPCODE_EXEC_ST_EN_SHIFT 31 +#define OPCODE_EXEC_ST_EN_MASK 0x80000000 + +#define LUT_FUNC32_BASE_ADDR_LO 0xDC4 + +#define LUT_FUNC32_BASE_ADDR_LO_V_SHIFT 0 +#define LUT_FUNC32_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +#define LUT_FUNC32_BASE_ADDR_HI 0xDC8 + +#define LUT_FUNC32_BASE_ADDR_HI_V_SHIFT 0 +#define LUT_FUNC32_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +#define LUT_FUNC64_BASE_ADDR_LO 0xDCC + +#define LUT_FUNC64_BASE_ADDR_LO_V_SHIFT 0 +#define LUT_FUNC64_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +#define LUT_FUNC64_BASE_ADDR_HI 0xDD0 + +#define LUT_FUNC64_BASE_ADDR_HI_V_SHIFT 0 +#define LUT_FUNC64_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +#define LUT_FUNC128_BASE_ADDR_LO 0xDD4 + +#define LUT_FUNC128_BASE_ADDR_LO_V_SHIFT 0 +#define LUT_FUNC128_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +#define LUT_FUNC128_BASE_ADDR_HI 0xDD8 + +#define LUT_FUNC128_BASE_ADDR_HI_V_SHIFT 0 +#define LUT_FUNC128_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +#define LUT_FUNC256_BASE_ADDR_LO 0xDDC + +#define LUT_FUNC256_BASE_ADDR_LO_V_SHIFT 0 +#define LUT_FUNC256_BASE_ADDR_LO_V_MASK 0xFFFFFFFF + +#define LUT_FUNC256_BASE_ADDR_HI 0xDE0 + +#define LUT_FUNC256_BASE_ADDR_HI_V_SHIFT 0 +#define LUT_FUNC256_BASE_ADDR_HI_V_MASK 0xFFFFFFFF + +#define TSB_CFG_MAX_SIZE 0xDE4 + +#define TSB_CFG_MAX_SIZE_DATA_SHIFT 0 +#define TSB_CFG_MAX_SIZE_DATA_MASK 0xFFFF +#define TSB_CFG_MAX_SIZE_MD_SHIFT 16 +#define TSB_CFG_MAX_SIZE_MD_MASK 0xFFFF0000 + +#define TSB_CFG 0xDE8 + +#define TSB_CFG_CACHE_DISABLE_SHIFT 0 +#define TSB_CFG_CACHE_DISABLE_MASK 0x1 +#define TSB_CFG_MAX_OS_SHIFT 1 +#define TSB_CFG_MAX_OS_MASK 0x1FFFE +#define TSB_CFG_ENABLE_CGATE_SHIFT 17 +#define TSB_CFG_ENABLE_CGATE_MASK 0x20000 + +#define TSB_INFLIGHT_CNTR 0xDEC + +#define TSB_INFLIGHT_CNTR_V_SHIFT 0 +#define TSB_INFLIGHT_CNTR_V_MASK 0xFFFFFFFF + +#define WQ_INFLIGHT_CNTR 0xDF0 + +#define WQ_INFLIGHT_CNTR_HBW_SHIFT 0 +#define WQ_INFLIGHT_CNTR_HBW_MASK 0xFFFF +#define WQ_INFLIGHT_CNTR_LBW_SHIFT 16 +#define WQ_INFLIGHT_CNTR_LBW_MASK 0x1FF0000 + +#define WQ_LBW_TOTAL_CNTR 0xDF4 + +#define WQ_LBW_TOTAL_CNTR_V_SHIFT 0 +#define WQ_LBW_TOTAL_CNTR_V_MASK 0xFFFFFFFF + +#define WQ_HBW_TOTAL_CNTR 0xDF8 + +#define WQ_HBW_TOTAL_CNTR_V_SHIFT 0 +#define WQ_HBW_TOTAL_CNTR_V_MASK 0xFFFFFFFF + +#define IRQ_OCCOUPY_CNTR 0xDFC + +#define IRQ_OCCOUPY_CNTR_V_SHIFT 0 +#define IRQ_OCCOUPY_CNTR_V_MASK 0xFFFFFFFF + +#define AXUSER_HB_ASID 0xE00 + +#define AXUSER_HB_ASID_WR_SHIFT 0 +#define AXUSER_HB_ASID_WR_MASK 0x3FF +#define AXUSER_HB_ASID_RD_SHIFT 16 +#define AXUSER_HB_ASID_RD_MASK 0x3FF0000 + +#define AXUSER_HB_MMU_BP 0xE04 + +#define AXUSER_HB_MMU_BP_WR_SHIFT 0 +#define AXUSER_HB_MMU_BP_WR_MASK 0x1 +#define AXUSER_HB_MMU_BP_RD_SHIFT 4 +#define AXUSER_HB_MMU_BP_RD_MASK 0x10 + +#define AXUSER_HB_STRONG_ORDER 0xE08 + +#define AXUSER_HB_STRONG_ORDER_WR_SHIFT 0 +#define AXUSER_HB_STRONG_ORDER_WR_MASK 0x1 +#define AXUSER_HB_STRONG_ORDER_RD_SHIFT 4 +#define AXUSER_HB_STRONG_ORDER_RD_MASK 0x10 + +#define AXUSER_HB_NO_SNOOP 0xE0C + +#define AXUSER_HB_NO_SNOOP_WR_SHIFT 0 +#define AXUSER_HB_NO_SNOOP_WR_MASK 0x1 +#define AXUSER_HB_NO_SNOOP_RD_SHIFT 4 +#define AXUSER_HB_NO_SNOOP_RD_MASK 0x10 + +#define AXUSER_HB_WR_REDUCTION 0xE10 + +#define AXUSER_HB_WR_REDUCTION_IND_SHIFT 0 +#define AXUSER_HB_WR_REDUCTION_IND_MASK 0x1 +#define AXUSER_HB_WR_REDUCTION_DTYPE_SHIFT 4 +#define AXUSER_HB_WR_REDUCTION_DTYPE_MASK 0xF0 +#define AXUSER_HB_WR_REDUCTION_OP_SHIFT 8 +#define AXUSER_HB_WR_REDUCTION_OP_MASK 0x300 +#define AXUSER_HB_WR_REDUCTION_ROUND_SHIFT 12 +#define AXUSER_HB_WR_REDUCTION_ROUND_MASK 0x3000 +#define AXUSER_HB_WR_REDUCTION_MAX_SHIFT 16 +#define AXUSER_HB_WR_REDUCTION_MAX_MASK 0x10000 + +#define AXUSER_HB_RD_ATOMIC 0xE14 + +#define AXUSER_HB_RD_ATOMIC_IND_SHIFT 0 +#define AXUSER_HB_RD_ATOMIC_IND_MASK 0x3 +#define AXUSER_HB_RD_ATOMIC_ADDITION_SIZE_SHIFT 4 +#define AXUSER_HB_RD_ATOMIC_ADDITION_SIZE_MASK 0xFF0 +#define AXUSER_HB_RD_ATOMIC_MSB_MASK_SHIFT 12 +#define AXUSER_HB_RD_ATOMIC_MSB_MASK_MASK 0x1F000 + +#define AXUSER_HB_QOS 0xE18 + +#define AXUSER_HB_QOS_WR_SHIFT 0 +#define AXUSER_HB_QOS_WR_MASK 0xF +#define AXUSER_HB_QOS_RD_SHIFT 4 +#define AXUSER_HB_QOS_RD_MASK 0x70 + +#define AXUSER_HB_RSVD 0xE1C + +#define AXUSER_HB_RSVD_WR_BIT_27_SHIFT 0 +#define AXUSER_HB_RSVD_WR_BIT_27_MASK 0x1 +#define AXUSER_HB_RSVD_WR_BIT_28_SHIFT 1 +#define AXUSER_HB_RSVD_WR_BIT_28_MASK 0x2 +#define AXUSER_HB_RSVD_WR_BIT_30_SHIFT 2 +#define AXUSER_HB_RSVD_WR_BIT_30_MASK 0x4 +#define AXUSER_HB_RSVD_WR_BIT_31_SHIFT 3 +#define AXUSER_HB_RSVD_WR_BIT_31_MASK 0x8 + +#define AXUSER_HB_EMEM_CPAGE 0xE20 + +#define AXUSER_HB_EMEM_CPAGE_WR_SHIFT 0 +#define AXUSER_HB_EMEM_CPAGE_WR_MASK 0x1 +#define AXUSER_HB_EMEM_CPAGE_RD_SHIFT 4 +#define AXUSER_HB_EMEM_CPAGE_RD_MASK 0x10 + +#define AXUSER_HB_CORE 0xE24 + +#define AXUSER_HB_CORE_WR_SHIFT 0 +#define AXUSER_HB_CORE_WR_MASK 0x1 +#define AXUSER_HB_CORE_RD_SHIFT 4 +#define AXUSER_HB_CORE_RD_MASK 0x10 + +#define AXUSER_E2E_COORD 0xE28 + +#define AXUSER_E2E_COORD_X_SHIFT 0 +#define AXUSER_E2E_COORD_X_MASK 0x1F +#define AXUSER_E2E_COORD_Y_SHIFT 8 +#define AXUSER_E2E_COORD_Y_MASK 0xF00 + +#define AXUSER_HB_WR_OVRD_LO 0xE30 + +#define AXUSER_HB_WR_OVRD_LO_VAL_SHIFT 0 +#define AXUSER_HB_WR_OVRD_LO_VAL_MASK 0xFFFFFFFF + +#define AXUSER_HB_WR_OVRD_HI 0xE34 + +#define AXUSER_HB_WR_OVRD_HI_VAL_SHIFT 0 +#define AXUSER_HB_WR_OVRD_HI_VAL_MASK 0x3FF + +#define AXUSER_HB_RD_OVRD_LO 0xE38 + +#define AXUSER_HB_RD_OVRD_LO_VAL_SHIFT 0 +#define AXUSER_HB_RD_OVRD_LO_VAL_MASK 0xFFFFFFFF + +#define AXUSER_HB_RD_OVRD_HI 0xE3C + +#define AXUSER_HB_RD_OVRD_HI_VAL_SHIFT 0 +#define AXUSER_HB_RD_OVRD_HI_VAL_MASK 0x3FF + +#define AXUSER_LB_COORD 0xE40 + +#define AXUSER_LB_COORD_VAL_SHIFT 0 +#define AXUSER_LB_COORD_VAL_MASK 0x3FF + +#define AXUSER_LB_LOCK 0xE44 + +#define AXUSER_LB_LOCK_VAL_SHIFT 0 +#define AXUSER_LB_LOCK_VAL_MASK 0x1 + +#define AXUSER_LB_RSVD 0xE48 + +#define AXUSER_LB_RSVD_BIT_21_11_SHIFT 0 +#define AXUSER_LB_RSVD_BIT_21_11_MASK 0x7FF +#define AXUSER_LB_RSVD_BIT_22_SHIFT 12 +#define AXUSER_LB_RSVD_BIT_22_MASK 0x1000 + +#define AXUSER_LB_OVRD 0xE4C + +#define AXUSER_LB_OVRD_VAL_SHIFT 0 +#define AXUSER_LB_OVRD_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_0 0xE80 + +#define SPECIAL_GLBL_PRIV_0_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_0_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_1 0xE84 + +#define SPECIAL_GLBL_PRIV_1_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_1_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_2 0xE88 + +#define SPECIAL_GLBL_PRIV_2_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_2_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_3 0xE8C + +#define SPECIAL_GLBL_PRIV_3_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_3_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_4 0xE90 + +#define SPECIAL_GLBL_PRIV_4_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_4_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_5 0xE94 + +#define SPECIAL_GLBL_PRIV_5_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_5_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_6 0xE98 + +#define SPECIAL_GLBL_PRIV_6_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_6_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_7 0xE9C + +#define SPECIAL_GLBL_PRIV_7_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_7_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_8 0xEA0 + +#define SPECIAL_GLBL_PRIV_8_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_8_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_9 0xEA4 + +#define SPECIAL_GLBL_PRIV_9_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_9_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_10 0xEA8 + +#define SPECIAL_GLBL_PRIV_10_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_10_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_11 0xEAC + +#define SPECIAL_GLBL_PRIV_11_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_11_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_12 0xEB0 + +#define SPECIAL_GLBL_PRIV_12_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_12_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_13 0xEB4 + +#define SPECIAL_GLBL_PRIV_13_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_13_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_14 0xEB8 + +#define SPECIAL_GLBL_PRIV_14_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_14_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_15 0xEBC + +#define SPECIAL_GLBL_PRIV_15_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_15_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_16 0xEC0 + +#define SPECIAL_GLBL_PRIV_16_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_16_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_17 0xEC4 + +#define SPECIAL_GLBL_PRIV_17_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_17_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_18 0xEC8 + +#define SPECIAL_GLBL_PRIV_18_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_18_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_19 0xECC + +#define SPECIAL_GLBL_PRIV_19_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_19_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_20 0xED0 + +#define SPECIAL_GLBL_PRIV_20_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_20_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_21 0xED4 + +#define SPECIAL_GLBL_PRIV_21_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_21_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_22 0xED8 + +#define SPECIAL_GLBL_PRIV_22_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_22_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_23 0xEDC + +#define SPECIAL_GLBL_PRIV_23_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_23_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_24 0xEE0 + +#define SPECIAL_GLBL_PRIV_24_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_24_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_25 0xEE4 + +#define SPECIAL_GLBL_PRIV_25_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_25_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_26 0xEE8 + +#define SPECIAL_GLBL_PRIV_26_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_26_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_27 0xEEC + +#define SPECIAL_GLBL_PRIV_27_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_27_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_28 0xEF0 + +#define SPECIAL_GLBL_PRIV_28_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_28_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_29 0xEF4 + +#define SPECIAL_GLBL_PRIV_29_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_29_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_30 0xEF8 + +#define SPECIAL_GLBL_PRIV_30_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_30_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_PRIV_31 0xEFC + +#define SPECIAL_GLBL_PRIV_31_VAL_SHIFT 0 +#define SPECIAL_GLBL_PRIV_31_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_MEM_GW_DATA 0xF00 + +#define SPECIAL_MEM_GW_DATA_VAL_SHIFT 0 +#define SPECIAL_MEM_GW_DATA_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_MEM_GW_REQ 0xF04 + +#define SPECIAL_MEM_GW_REQ_ADDR_SHIFT 0 +#define SPECIAL_MEM_GW_REQ_ADDR_MASK 0x3FFFFF +#define SPECIAL_MEM_GW_REQ_MID_SHIFT 22 +#define SPECIAL_MEM_GW_REQ_MID_MASK 0x3FC00000 +#define SPECIAL_MEM_GW_REQ_WNR_SHIFT 30 +#define SPECIAL_MEM_GW_REQ_WNR_MASK 0x40000000 +#define SPECIAL_MEM_GW_REQ_VLD_SHIFT 31 +#define SPECIAL_MEM_GW_REQ_VLD_MASK 0x80000000 + +#define SPECIAL_MEM_NUMOF 0xF0C + +#define SPECIAL_MEM_NUMOF_VAL_SHIFT 0 +#define SPECIAL_MEM_NUMOF_VAL_MASK 0xFF + +#define SPECIAL_MEM_ECC_SEL 0xF10 + +#define SPECIAL_MEM_ECC_SEL_VAL_SHIFT 0 +#define SPECIAL_MEM_ECC_SEL_VAL_MASK 0xFF + +#define SPECIAL_MEM_ECC_CTL 0xF14 + +#define SPECIAL_MEM_ECC_CTL_SERR_INJ_SHIFT 0 +#define SPECIAL_MEM_ECC_CTL_SERR_INJ_MASK 0x1 +#define SPECIAL_MEM_ECC_CTL_DERR_INJ_SHIFT 1 +#define SPECIAL_MEM_ECC_CTL_DERR_INJ_MASK 0x2 +#define SPECIAL_MEM_ECC_CTL_SERR_CLR_SHIFT 2 +#define SPECIAL_MEM_ECC_CTL_SERR_CLR_MASK 0x4 +#define SPECIAL_MEM_ECC_CTL_DERR_CLR_SHIFT 3 +#define SPECIAL_MEM_ECC_CTL_DERR_CLR_MASK 0x8 + +#define SPECIAL_MEM_ECC_ERR_MASK 0xF18 + +#define SPECIAL_MEM_ECC_ERR_MASK_SERR_SHIFT 0 +#define SPECIAL_MEM_ECC_ERR_MASK_SERR_MASK 0x1 +#define SPECIAL_MEM_ECC_ERR_MASK_DERR_SHIFT 1 +#define SPECIAL_MEM_ECC_ERR_MASK_DERR_MASK 0x2 + +#define SPECIAL_MEM_ECC_GLBL_ERR_MASK 0xF1C + +#define SPECIAL_MEM_ECC_GLBL_ERR_MASK_SERR_SHIFT 0 +#define SPECIAL_MEM_ECC_GLBL_ERR_MASK_SERR_MASK 0x1 +#define SPECIAL_MEM_ECC_GLBL_ERR_MASK_DERR_SHIFT 1 +#define SPECIAL_MEM_ECC_GLBL_ERR_MASK_DERR_MASK 0x2 + +#define SPECIAL_MEM_ECC_ERR_STS 0xF20 + +#define SPECIAL_MEM_ECC_ERR_STS_SYND_SHIFT 0 +#define SPECIAL_MEM_ECC_ERR_STS_SYND_MASK 0xFFFF +#define SPECIAL_MEM_ECC_ERR_STS_SERR_SHIFT 16 +#define SPECIAL_MEM_ECC_ERR_STS_SERR_MASK 0x10000 +#define SPECIAL_MEM_ECC_ERR_STS_DERR_SHIFT 17 +#define SPECIAL_MEM_ECC_ERR_STS_DERR_MASK 0x20000 + +#define SPECIAL_MEM_ECC_ERR_ADDR 0xF24 + +#define SPECIAL_MEM_ECC_ERR_ADDR_VAL_SHIFT 0 +#define SPECIAL_MEM_ECC_ERR_ADDR_VAL_MASK 0xFFFF + +#define SPECIAL_MEM_RM 0xF28 + +#define SPECIAL_MEM_RM_VAL_SHIFT 0 +#define SPECIAL_MEM_RM_VAL_MASK 0x3FFFFFFF + +#define SPECIAL_GLBL_ERR_MASK 0xF40 + +#define SPECIAL_GLBL_ERR_MASK_APB_PRIV_RD_SHIFT 0 +#define SPECIAL_GLBL_ERR_MASK_APB_PRIV_RD_MASK 0x1 +#define SPECIAL_GLBL_ERR_MASK_APB_SEC_RD_SHIFT 1 +#define SPECIAL_GLBL_ERR_MASK_APB_SEC_RD_MASK 0x2 +#define SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_RD_SHIFT 2 +#define SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_RD_MASK 0x4 +#define SPECIAL_GLBL_ERR_MASK_APB_PRIV_WR_SHIFT 3 +#define SPECIAL_GLBL_ERR_MASK_APB_PRIV_WR_MASK 0x8 +#define SPECIAL_GLBL_ERR_MASK_APB_SEC_WR_SHIFT 4 +#define SPECIAL_GLBL_ERR_MASK_APB_SEC_WR_MASK 0x10 +#define SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_WR_SHIFT 5 +#define SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_WR_MASK 0x20 +#define SPECIAL_GLBL_ERR_MASK_EXT_SEC_WR_SHIFT 16 +#define SPECIAL_GLBL_ERR_MASK_EXT_SEC_WR_MASK 0x10000 +#define SPECIAL_GLBL_ERR_MASK_EXT_UNMAPPED_WR_SHIFT 17 +#define SPECIAL_GLBL_ERR_MASK_EXT_UNMAPPED_WR_MASK 0x20000 + +#define SPECIAL_GLBL_ERR_ADDR 0xF44 + +#define SPECIAL_GLBL_ERR_ADDR_VAL_SHIFT 0 +#define SPECIAL_GLBL_ERR_ADDR_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_ERR_CAUSE 0xF48 + +#define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD_SHIFT 0 +#define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD_MASK 0x1 +#define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD_SHIFT 1 +#define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD_MASK 0x2 +#define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD_SHIFT 2 +#define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD_MASK 0x4 +#define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR_SHIFT 3 +#define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR_MASK 0x8 +#define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR_SHIFT 4 +#define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR_MASK 0x10 +#define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR_SHIFT 5 +#define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR_MASK 0x20 +#define SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR_SHIFT 16 +#define SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR_MASK 0x10000 +#define SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR_SHIFT 17 +#define SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR_MASK 0x20000 + +#define SPECIAL_GLBL_SPARE_0 0xF60 + +#define SPECIAL_GLBL_SPARE_0_R_SHIFT 0 +#define SPECIAL_GLBL_SPARE_0_R_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SPARE_1 0xF64 + +#define SPECIAL_GLBL_SPARE_1_R_SHIFT 0 +#define SPECIAL_GLBL_SPARE_1_R_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SPARE_2 0xF68 + +#define SPECIAL_GLBL_SPARE_2_R_SHIFT 0 +#define SPECIAL_GLBL_SPARE_2_R_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SPARE_3 0xF6C + +#define SPECIAL_GLBL_SPARE_3_R_SHIFT 0 +#define SPECIAL_GLBL_SPARE_3_R_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_0 0xF80 + +#define SPECIAL_GLBL_SEC_0_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_0_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_1 0xF84 + +#define SPECIAL_GLBL_SEC_1_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_1_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_2 0xF88 + +#define SPECIAL_GLBL_SEC_2_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_2_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_3 0xF8C + +#define SPECIAL_GLBL_SEC_3_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_3_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_4 0xF90 + +#define SPECIAL_GLBL_SEC_4_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_4_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_5 0xF94 + +#define SPECIAL_GLBL_SEC_5_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_5_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_6 0xF98 + +#define SPECIAL_GLBL_SEC_6_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_6_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_7 0xF9C + +#define SPECIAL_GLBL_SEC_7_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_7_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_8 0xFA0 + +#define SPECIAL_GLBL_SEC_8_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_8_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_9 0xFA4 + +#define SPECIAL_GLBL_SEC_9_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_9_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_10 0xFA8 + +#define SPECIAL_GLBL_SEC_10_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_10_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_11 0xFAC + +#define SPECIAL_GLBL_SEC_11_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_11_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_12 0xFB0 + +#define SPECIAL_GLBL_SEC_12_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_12_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_13 0xFB4 + +#define SPECIAL_GLBL_SEC_13_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_13_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_14 0xFB8 + +#define SPECIAL_GLBL_SEC_14_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_14_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_15 0xFBC + +#define SPECIAL_GLBL_SEC_15_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_15_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_16 0xFC0 + +#define SPECIAL_GLBL_SEC_16_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_16_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_17 0xFC4 + +#define SPECIAL_GLBL_SEC_17_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_17_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_18 0xFC8 + +#define SPECIAL_GLBL_SEC_18_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_18_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_19 0xFCC + +#define SPECIAL_GLBL_SEC_19_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_19_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_20 0xFD0 + +#define SPECIAL_GLBL_SEC_20_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_20_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_21 0xFD4 + +#define SPECIAL_GLBL_SEC_21_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_21_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_22 0xFD8 + +#define SPECIAL_GLBL_SEC_22_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_22_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_23 0xFDC + +#define SPECIAL_GLBL_SEC_23_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_23_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_24 0xFE0 + +#define SPECIAL_GLBL_SEC_24_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_24_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_25 0xFE4 + +#define SPECIAL_GLBL_SEC_25_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_25_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_26 0xFE8 + +#define SPECIAL_GLBL_SEC_26_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_26_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_27 0xFEC + +#define SPECIAL_GLBL_SEC_27_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_27_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_28 0xFF0 + +#define SPECIAL_GLBL_SEC_28_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_28_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_29 0xFF4 + +#define SPECIAL_GLBL_SEC_29_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_29_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_30 0xFF8 + +#define SPECIAL_GLBL_SEC_30_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_30_VAL_MASK 0xFFFFFFFF + +#define SPECIAL_GLBL_SEC_31 0xFFC + +#define SPECIAL_GLBL_SEC_31_VAL_SHIFT 0 +#define SPECIAL_GLBL_SEC_31_VAL_MASK 0xFFFFFFFF + +#endif /* TPC_IO_REG_SPACE_GEN4_H_ */ diff --git a/external_includes/gaudi2/asic_reg/gaudi2_blocks.h b/external_includes/gaudi2/asic_reg/gaudi2_blocks.h new file mode 100644 index 0000000..d0f59f4 --- /dev/null +++ b/external_includes/gaudi2/asic_reg/gaudi2_blocks.h @@ -0,0 +1,54594 @@ +/* SPDX-License-Identifier: MIT + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef GAUDI2_BLOCKS_H_ +#define GAUDI2_BLOCKS_H_ + + +#define mmDCORE0_TPC0_ROM_TABLE_BASE 0x1000007FF8000000ull +#define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000 + +#define mmDCORE0_TPC0_EML_SPMU_BASE 0x1000007FF8001000ull +#define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_SPMU_SECTION 0x1000 + +#define mmDCORE0_TPC0_EML_ETF_BASE 0x1000007FF8002000ull +#define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_ETF_SECTION 0x1000 + +#define mmDCORE0_TPC0_EML_STM_BASE 0x1000007FF8003000ull +#define DCORE0_TPC0_EML_STM_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_STM_SECTION 0x2000 + +#define mmDCORE0_TPC0_EML_CTI_BASE 0x1000007FF8005000ull +#define DCORE0_TPC0_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_CTI_SECTION 0x1000 + +#define mmDCORE0_TPC0_EML_FUNNEL_BASE 0x1000007FF8006000ull +#define DCORE0_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_FUNNEL_SECTION 0x1000 + +#define mmDCORE0_TPC0_EML_BUSMON_0_BASE 0x1000007FF8007000ull +#define DCORE0_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_BUSMON_0_SECTION 0x1000 + +#define mmDCORE0_TPC0_EML_BUSMON_1_BASE 0x1000007FF8008000ull +#define DCORE0_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_BUSMON_1_SECTION 0x1000 + +#define mmDCORE0_TPC0_EML_BUSMON_2_BASE 0x1000007FF8009000ull +#define DCORE0_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_BUSMON_2_SECTION 0x1000 + +#define mmDCORE0_TPC0_EML_BUSMON_3_BASE 0x1000007FF800A000ull +#define DCORE0_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_BUSMON_3_SECTION 0x1000 + +#define mmDCORE0_TPC0_QM_ARC_RTT_BASE 0x1000007FF800B000ull +#define DCORE0_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_TPC0_QM_ARC_RTT_SECTION 0x35000 + +#define mmDCORE0_TPC0_EML_CFG_BASE 0x1000007FF8040000ull +#define DCORE0_TPC0_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_CFG_SECTION 0xE800 + +#define mmDCORE0_TPC0_EML_CFG_SPECIAL_BASE 0x1000007FF8040E80ull +#define DCORE0_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1000007FF8041000ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC0_EML_TPC_CFG_BASE 0x1000007FF8041000ull +#define DCORE0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_TPC_CFG_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1000007FF8041050ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1000007FF80410A0ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1000007FF80410F0ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1000007FF8041140ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1000007FF8041190ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1000007FF80411E0ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1000007FF8041230ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1000007FF8041280ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1000007FF80412D0ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1000007FF8041320ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1000007FF8041370ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1000007FF80413C0ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1000007FF8041410ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1000007FF8041460ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1000007FF80414B0ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FF8041500ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_BASE 0x1000007FF8041508ull +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1000007FF80415DCull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1000007FF804162Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1000007FF804167Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1000007FF80416CCull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1000007FF804171Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1000007FF804176Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1000007FF80417BCull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1000007FF804180Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1000007FF804185Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1000007FF80418ACull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1000007FF80418FCull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1000007FF804194Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1000007FF804199Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1000007FF80419ECull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1000007FF8041A3Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1000007FF8041A8Cull +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1000007FF8041ADCull +#define DCORE0_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_QM_BASE 0x1000007FF8041AE4ull +#define DCORE0_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0 + +#define mmDCORE0_TPC0_EML_TPC_CFG_AXUSER_BASE 0x1000007FF8041E00ull +#define DCORE0_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE0_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x1000007FF8041E80ull +#define DCORE0_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC0_EML_QM_DCCM_BASE 0x1000007FF8042000ull +#define DCORE0_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC0_EML_QM_DCCM_SECTION 0x8000 + +#define mmDCORE0_TPC0_EML_QM_ARCAUX_BASE 0x1000007FF804A000ull +#define DCORE0_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_QM_ARCAUX_SECTION 0xE800 + +#define mmDCORE0_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x1000007FF804AE80ull +#define DCORE0_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE0_TPC0_EML_TPC_QM_BASE 0x1000007FF804C000ull +#define DCORE0_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_TPC_QM_SECTION 0x9000 + +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FF804C900ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FF804C908ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FF804C910ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FF804C918ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FF804C920ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FF804C928ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FF804C930ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FF804C938ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FF804C940ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FF804C948ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE \ +0x1000007FF804C950ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE \ +0x1000007FF804C958ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE \ +0x1000007FF804C960ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE \ +0x1000007FF804C968ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE \ +0x1000007FF804C970ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE \ +0x1000007FF804C978ull +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE0_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x1000007FF804CB00ull +#define DCORE0_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE0_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1000007FF804CB80ull +#define DCORE0_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE0_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x1000007FF804CC00ull +#define DCORE0_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x1000007FF804CC80ull +#define DCORE0_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE0_TPC0_EML_TPC_QM_CGM_BASE 0x1000007FF804CD80ull +#define DCORE0_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC0_EML_TPC_QM_CGM_SECTION 0x1000 + +#define mmDCORE0_TPC0_EML_TPC_QM_SPECIAL_BASE 0x1000007FF804CE80ull +#define DCORE0_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 + +#define mmDCORE0_TPC0_EML_CS_BASE 0x1000007FF81FF000ull +#define DCORE0_TPC0_EML_CS_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_EML_CS_SECTION 0x1000 + +#define mmDCORE0_TPC1_ROM_TABLE_BASE 0x1000007FF8200000ull +#define DCORE0_TPC1_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_ROM_TABLE_SECTION 0x1000 + +#define mmDCORE0_TPC1_EML_SPMU_BASE 0x1000007FF8201000ull +#define DCORE0_TPC1_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_SPMU_SECTION 0x1000 + +#define mmDCORE0_TPC1_EML_ETF_BASE 0x1000007FF8202000ull +#define DCORE0_TPC1_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_ETF_SECTION 0x1000 + +#define mmDCORE0_TPC1_EML_STM_BASE 0x1000007FF8203000ull +#define DCORE0_TPC1_EML_STM_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_STM_SECTION 0x2000 + +#define mmDCORE0_TPC1_EML_CTI_BASE 0x1000007FF8205000ull +#define DCORE0_TPC1_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_CTI_SECTION 0x1000 + +#define mmDCORE0_TPC1_EML_FUNNEL_BASE 0x1000007FF8206000ull +#define DCORE0_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_FUNNEL_SECTION 0x1000 + +#define mmDCORE0_TPC1_EML_BUSMON_0_BASE 0x1000007FF8207000ull +#define DCORE0_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_BUSMON_0_SECTION 0x1000 + +#define mmDCORE0_TPC1_EML_BUSMON_1_BASE 0x1000007FF8208000ull +#define DCORE0_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_BUSMON_1_SECTION 0x1000 + +#define mmDCORE0_TPC1_EML_BUSMON_2_BASE 0x1000007FF8209000ull +#define DCORE0_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_BUSMON_2_SECTION 0x1000 + +#define mmDCORE0_TPC1_EML_BUSMON_3_BASE 0x1000007FF820A000ull +#define DCORE0_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_BUSMON_3_SECTION 0x1000 + +#define mmDCORE0_TPC1_QM_ARC_RTT_BASE 0x1000007FF820B000ull +#define DCORE0_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_TPC1_QM_ARC_RTT_SECTION 0x35000 + +#define mmDCORE0_TPC1_EML_CFG_BASE 0x1000007FF8240000ull +#define DCORE0_TPC1_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_CFG_SECTION 0xE800 + +#define mmDCORE0_TPC1_EML_CFG_SPECIAL_BASE 0x1000007FF8240E80ull +#define DCORE0_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1000007FF8241000ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC1_EML_TPC_CFG_BASE 0x1000007FF8241000ull +#define DCORE0_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_TPC_CFG_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1000007FF8241050ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1000007FF82410A0ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1000007FF82410F0ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1000007FF8241140ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1000007FF8241190ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1000007FF82411E0ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1000007FF8241230ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1000007FF8241280ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1000007FF82412D0ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1000007FF8241320ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1000007FF8241370ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1000007FF82413C0ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1000007FF8241410ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1000007FF8241460ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1000007FF82414B0ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FF8241500ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_BASE 0x1000007FF8241508ull +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1000007FF82415DCull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1000007FF824162Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1000007FF824167Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1000007FF82416CCull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1000007FF824171Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1000007FF824176Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1000007FF82417BCull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1000007FF824180Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1000007FF824185Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1000007FF82418ACull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1000007FF82418FCull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1000007FF824194Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1000007FF824199Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1000007FF82419ECull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1000007FF8241A3Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1000007FF8241A8Cull +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1000007FF8241ADCull +#define DCORE0_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_QM_BASE 0x1000007FF8241AE4ull +#define DCORE0_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0 + +#define mmDCORE0_TPC1_EML_TPC_CFG_AXUSER_BASE 0x1000007FF8241E00ull +#define DCORE0_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE0_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x1000007FF8241E80ull +#define DCORE0_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC1_EML_QM_DCCM_BASE 0x1000007FF8242000ull +#define DCORE0_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC1_EML_QM_DCCM_SECTION 0x8000 + +#define mmDCORE0_TPC1_EML_QM_ARCAUX_BASE 0x1000007FF824A000ull +#define DCORE0_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_QM_ARCAUX_SECTION 0xE800 + +#define mmDCORE0_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x1000007FF824AE80ull +#define DCORE0_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE0_TPC1_EML_TPC_QM_BASE 0x1000007FF824C000ull +#define DCORE0_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_TPC_QM_SECTION 0x9000 + +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FF824C900ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FF824C908ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FF824C910ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FF824C918ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FF824C920ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FF824C928ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FF824C930ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FF824C938ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FF824C940ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FF824C948ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE \ +0x1000007FF824C950ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE \ +0x1000007FF824C958ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE \ +0x1000007FF824C960ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE \ +0x1000007FF824C968ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE \ +0x1000007FF824C970ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE \ +0x1000007FF824C978ull +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE0_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x1000007FF824CB00ull +#define DCORE0_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE0_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1000007FF824CB80ull +#define DCORE0_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE0_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x1000007FF824CC00ull +#define DCORE0_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x1000007FF824CC80ull +#define DCORE0_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE0_TPC1_EML_TPC_QM_CGM_BASE 0x1000007FF824CD80ull +#define DCORE0_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC1_EML_TPC_QM_CGM_SECTION 0x1000 + +#define mmDCORE0_TPC1_EML_TPC_QM_SPECIAL_BASE 0x1000007FF824CE80ull +#define DCORE0_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 + +#define mmDCORE0_TPC1_EML_CS_BASE 0x1000007FF83FF000ull +#define DCORE0_TPC1_EML_CS_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_EML_CS_SECTION 0x1000 + +#define mmDCORE0_TPC2_ROM_TABLE_BASE 0x1000007FF8400000ull +#define DCORE0_TPC2_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_ROM_TABLE_SECTION 0x1000 + +#define mmDCORE0_TPC2_EML_SPMU_BASE 0x1000007FF8401000ull +#define DCORE0_TPC2_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_SPMU_SECTION 0x1000 + +#define mmDCORE0_TPC2_EML_ETF_BASE 0x1000007FF8402000ull +#define DCORE0_TPC2_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_ETF_SECTION 0x1000 + +#define mmDCORE0_TPC2_EML_STM_BASE 0x1000007FF8403000ull +#define DCORE0_TPC2_EML_STM_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_STM_SECTION 0x2000 + +#define mmDCORE0_TPC2_EML_CTI_BASE 0x1000007FF8405000ull +#define DCORE0_TPC2_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_CTI_SECTION 0x1000 + +#define mmDCORE0_TPC2_EML_FUNNEL_BASE 0x1000007FF8406000ull +#define DCORE0_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_FUNNEL_SECTION 0x1000 + +#define mmDCORE0_TPC2_EML_BUSMON_0_BASE 0x1000007FF8407000ull +#define DCORE0_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_BUSMON_0_SECTION 0x1000 + +#define mmDCORE0_TPC2_EML_BUSMON_1_BASE 0x1000007FF8408000ull +#define DCORE0_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_BUSMON_1_SECTION 0x1000 + +#define mmDCORE0_TPC2_EML_BUSMON_2_BASE 0x1000007FF8409000ull +#define DCORE0_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_BUSMON_2_SECTION 0x1000 + +#define mmDCORE0_TPC2_EML_BUSMON_3_BASE 0x1000007FF840A000ull +#define DCORE0_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_BUSMON_3_SECTION 0x1000 + +#define mmDCORE0_TPC2_QM_ARC_RTT_BASE 0x1000007FF840B000ull +#define DCORE0_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_TPC2_QM_ARC_RTT_SECTION 0x35000 + +#define mmDCORE0_TPC2_EML_CFG_BASE 0x1000007FF8440000ull +#define DCORE0_TPC2_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_CFG_SECTION 0xE800 + +#define mmDCORE0_TPC2_EML_CFG_SPECIAL_BASE 0x1000007FF8440E80ull +#define DCORE0_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1000007FF8441000ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC2_EML_TPC_CFG_BASE 0x1000007FF8441000ull +#define DCORE0_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_TPC_CFG_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1000007FF8441050ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1000007FF84410A0ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1000007FF84410F0ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1000007FF8441140ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1000007FF8441190ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1000007FF84411E0ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1000007FF8441230ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1000007FF8441280ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1000007FF84412D0ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1000007FF8441320ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1000007FF8441370ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1000007FF84413C0ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1000007FF8441410ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1000007FF8441460ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1000007FF84414B0ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FF8441500ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_BASE 0x1000007FF8441508ull +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1000007FF84415DCull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1000007FF844162Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1000007FF844167Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1000007FF84416CCull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1000007FF844171Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1000007FF844176Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1000007FF84417BCull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1000007FF844180Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1000007FF844185Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1000007FF84418ACull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1000007FF84418FCull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1000007FF844194Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1000007FF844199Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1000007FF84419ECull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1000007FF8441A3Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1000007FF8441A8Cull +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1000007FF8441ADCull +#define DCORE0_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_QM_BASE 0x1000007FF8441AE4ull +#define DCORE0_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0 + +#define mmDCORE0_TPC2_EML_TPC_CFG_AXUSER_BASE 0x1000007FF8441E00ull +#define DCORE0_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE0_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x1000007FF8441E80ull +#define DCORE0_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC2_EML_QM_DCCM_BASE 0x1000007FF8442000ull +#define DCORE0_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC2_EML_QM_DCCM_SECTION 0x8000 + +#define mmDCORE0_TPC2_EML_QM_ARCAUX_BASE 0x1000007FF844A000ull +#define DCORE0_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_QM_ARCAUX_SECTION 0xE800 + +#define mmDCORE0_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x1000007FF844AE80ull +#define DCORE0_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE0_TPC2_EML_TPC_QM_BASE 0x1000007FF844C000ull +#define DCORE0_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_TPC_QM_SECTION 0x9000 + +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FF844C900ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FF844C908ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FF844C910ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FF844C918ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FF844C920ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FF844C928ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FF844C930ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FF844C938ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FF844C940ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FF844C948ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE \ +0x1000007FF844C950ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE \ +0x1000007FF844C958ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE \ +0x1000007FF844C960ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE \ +0x1000007FF844C968ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE \ +0x1000007FF844C970ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE \ +0x1000007FF844C978ull +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE0_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x1000007FF844CB00ull +#define DCORE0_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE0_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1000007FF844CB80ull +#define DCORE0_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE0_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x1000007FF844CC00ull +#define DCORE0_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x1000007FF844CC80ull +#define DCORE0_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE0_TPC2_EML_TPC_QM_CGM_BASE 0x1000007FF844CD80ull +#define DCORE0_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC2_EML_TPC_QM_CGM_SECTION 0x1000 + +#define mmDCORE0_TPC2_EML_TPC_QM_SPECIAL_BASE 0x1000007FF844CE80ull +#define DCORE0_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 + +#define mmDCORE0_TPC2_EML_CS_BASE 0x1000007FF85FF000ull +#define DCORE0_TPC2_EML_CS_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_EML_CS_SECTION 0x1000 + +#define mmDCORE0_TPC3_ROM_TABLE_BASE 0x1000007FF8600000ull +#define DCORE0_TPC3_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_ROM_TABLE_SECTION 0x1000 + +#define mmDCORE0_TPC3_EML_SPMU_BASE 0x1000007FF8601000ull +#define DCORE0_TPC3_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_SPMU_SECTION 0x1000 + +#define mmDCORE0_TPC3_EML_ETF_BASE 0x1000007FF8602000ull +#define DCORE0_TPC3_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_ETF_SECTION 0x1000 + +#define mmDCORE0_TPC3_EML_STM_BASE 0x1000007FF8603000ull +#define DCORE0_TPC3_EML_STM_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_STM_SECTION 0x2000 + +#define mmDCORE0_TPC3_EML_CTI_BASE 0x1000007FF8605000ull +#define DCORE0_TPC3_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_CTI_SECTION 0x1000 + +#define mmDCORE0_TPC3_EML_FUNNEL_BASE 0x1000007FF8606000ull +#define DCORE0_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_FUNNEL_SECTION 0x1000 + +#define mmDCORE0_TPC3_EML_BUSMON_0_BASE 0x1000007FF8607000ull +#define DCORE0_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_BUSMON_0_SECTION 0x1000 + +#define mmDCORE0_TPC3_EML_BUSMON_1_BASE 0x1000007FF8608000ull +#define DCORE0_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_BUSMON_1_SECTION 0x1000 + +#define mmDCORE0_TPC3_EML_BUSMON_2_BASE 0x1000007FF8609000ull +#define DCORE0_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_BUSMON_2_SECTION 0x1000 + +#define mmDCORE0_TPC3_EML_BUSMON_3_BASE 0x1000007FF860A000ull +#define DCORE0_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_BUSMON_3_SECTION 0x1000 + +#define mmDCORE0_TPC3_QM_ARC_RTT_BASE 0x1000007FF860B000ull +#define DCORE0_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_TPC3_QM_ARC_RTT_SECTION 0x35000 + +#define mmDCORE0_TPC3_EML_CFG_BASE 0x1000007FF8640000ull +#define DCORE0_TPC3_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_CFG_SECTION 0xE800 + +#define mmDCORE0_TPC3_EML_CFG_SPECIAL_BASE 0x1000007FF8640E80ull +#define DCORE0_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1000007FF8641000ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC3_EML_TPC_CFG_BASE 0x1000007FF8641000ull +#define DCORE0_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_TPC_CFG_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1000007FF8641050ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1000007FF86410A0ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1000007FF86410F0ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1000007FF8641140ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1000007FF8641190ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1000007FF86411E0ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1000007FF8641230ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1000007FF8641280ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1000007FF86412D0ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1000007FF8641320ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1000007FF8641370ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1000007FF86413C0ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1000007FF8641410ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1000007FF8641460ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1000007FF86414B0ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FF8641500ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_BASE 0x1000007FF8641508ull +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1000007FF86415DCull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1000007FF864162Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1000007FF864167Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1000007FF86416CCull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1000007FF864171Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1000007FF864176Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1000007FF86417BCull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1000007FF864180Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1000007FF864185Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1000007FF86418ACull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1000007FF86418FCull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1000007FF864194Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1000007FF864199Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1000007FF86419ECull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1000007FF8641A3Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1000007FF8641A8Cull +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1000007FF8641ADCull +#define DCORE0_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_QM_BASE 0x1000007FF8641AE4ull +#define DCORE0_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0 + +#define mmDCORE0_TPC3_EML_TPC_CFG_AXUSER_BASE 0x1000007FF8641E00ull +#define DCORE0_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE0_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x1000007FF8641E80ull +#define DCORE0_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC3_EML_QM_DCCM_BASE 0x1000007FF8642000ull +#define DCORE0_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC3_EML_QM_DCCM_SECTION 0x8000 + +#define mmDCORE0_TPC3_EML_QM_ARCAUX_BASE 0x1000007FF864A000ull +#define DCORE0_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_QM_ARCAUX_SECTION 0xE800 + +#define mmDCORE0_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x1000007FF864AE80ull +#define DCORE0_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE0_TPC3_EML_TPC_QM_BASE 0x1000007FF864C000ull +#define DCORE0_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_TPC_QM_SECTION 0x9000 + +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FF864C900ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FF864C908ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FF864C910ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FF864C918ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FF864C920ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FF864C928ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FF864C930ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FF864C938ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FF864C940ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FF864C948ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE \ +0x1000007FF864C950ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE \ +0x1000007FF864C958ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE \ +0x1000007FF864C960ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE \ +0x1000007FF864C968ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE \ +0x1000007FF864C970ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE \ +0x1000007FF864C978ull +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE0_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x1000007FF864CB00ull +#define DCORE0_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE0_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1000007FF864CB80ull +#define DCORE0_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE0_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x1000007FF864CC00ull +#define DCORE0_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x1000007FF864CC80ull +#define DCORE0_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE0_TPC3_EML_TPC_QM_CGM_BASE 0x1000007FF864CD80ull +#define DCORE0_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC3_EML_TPC_QM_CGM_SECTION 0x1000 + +#define mmDCORE0_TPC3_EML_TPC_QM_SPECIAL_BASE 0x1000007FF864CE80ull +#define DCORE0_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 + +#define mmDCORE0_TPC3_EML_CS_BASE 0x1000007FF87FF000ull +#define DCORE0_TPC3_EML_CS_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_EML_CS_SECTION 0x1000 + +#define mmDCORE0_TPC4_ROM_TABLE_BASE 0x1000007FF8800000ull +#define DCORE0_TPC4_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_ROM_TABLE_SECTION 0x1000 + +#define mmDCORE0_TPC4_EML_SPMU_BASE 0x1000007FF8801000ull +#define DCORE0_TPC4_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_SPMU_SECTION 0x1000 + +#define mmDCORE0_TPC4_EML_ETF_BASE 0x1000007FF8802000ull +#define DCORE0_TPC4_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_ETF_SECTION 0x1000 + +#define mmDCORE0_TPC4_EML_STM_BASE 0x1000007FF8803000ull +#define DCORE0_TPC4_EML_STM_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_STM_SECTION 0x2000 + +#define mmDCORE0_TPC4_EML_CTI_BASE 0x1000007FF8805000ull +#define DCORE0_TPC4_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_CTI_SECTION 0x1000 + +#define mmDCORE0_TPC4_EML_FUNNEL_BASE 0x1000007FF8806000ull +#define DCORE0_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_FUNNEL_SECTION 0x1000 + +#define mmDCORE0_TPC4_EML_BUSMON_0_BASE 0x1000007FF8807000ull +#define DCORE0_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_BUSMON_0_SECTION 0x1000 + +#define mmDCORE0_TPC4_EML_BUSMON_1_BASE 0x1000007FF8808000ull +#define DCORE0_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_BUSMON_1_SECTION 0x1000 + +#define mmDCORE0_TPC4_EML_BUSMON_2_BASE 0x1000007FF8809000ull +#define DCORE0_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_BUSMON_2_SECTION 0x1000 + +#define mmDCORE0_TPC4_EML_BUSMON_3_BASE 0x1000007FF880A000ull +#define DCORE0_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_BUSMON_3_SECTION 0x1000 + +#define mmDCORE0_TPC4_QM_ARC_RTT_BASE 0x1000007FF880B000ull +#define DCORE0_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_TPC4_QM_ARC_RTT_SECTION 0x35000 + +#define mmDCORE0_TPC4_EML_CFG_BASE 0x1000007FF8840000ull +#define DCORE0_TPC4_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_CFG_SECTION 0xE800 + +#define mmDCORE0_TPC4_EML_CFG_SPECIAL_BASE 0x1000007FF8840E80ull +#define DCORE0_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1000007FF8841000ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC4_EML_TPC_CFG_BASE 0x1000007FF8841000ull +#define DCORE0_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_TPC_CFG_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1000007FF8841050ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1000007FF88410A0ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1000007FF88410F0ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1000007FF8841140ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1000007FF8841190ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1000007FF88411E0ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1000007FF8841230ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1000007FF8841280ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1000007FF88412D0ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1000007FF8841320ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1000007FF8841370ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1000007FF88413C0ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1000007FF8841410ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1000007FF8841460ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1000007FF88414B0ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FF8841500ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_BASE 0x1000007FF8841508ull +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1000007FF88415DCull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1000007FF884162Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1000007FF884167Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1000007FF88416CCull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1000007FF884171Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1000007FF884176Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1000007FF88417BCull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1000007FF884180Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1000007FF884185Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1000007FF88418ACull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1000007FF88418FCull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1000007FF884194Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1000007FF884199Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1000007FF88419ECull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1000007FF8841A3Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1000007FF8841A8Cull +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1000007FF8841ADCull +#define DCORE0_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_QM_BASE 0x1000007FF8841AE4ull +#define DCORE0_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0 + +#define mmDCORE0_TPC4_EML_TPC_CFG_AXUSER_BASE 0x1000007FF8841E00ull +#define DCORE0_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE0_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x1000007FF8841E80ull +#define DCORE0_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC4_EML_QM_DCCM_BASE 0x1000007FF8842000ull +#define DCORE0_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC4_EML_QM_DCCM_SECTION 0x8000 + +#define mmDCORE0_TPC4_EML_QM_ARCAUX_BASE 0x1000007FF884A000ull +#define DCORE0_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_QM_ARCAUX_SECTION 0xE800 + +#define mmDCORE0_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x1000007FF884AE80ull +#define DCORE0_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE0_TPC4_EML_TPC_QM_BASE 0x1000007FF884C000ull +#define DCORE0_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_TPC_QM_SECTION 0x9000 + +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FF884C900ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FF884C908ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FF884C910ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FF884C918ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FF884C920ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FF884C928ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FF884C930ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FF884C938ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FF884C940ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FF884C948ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE \ +0x1000007FF884C950ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE \ +0x1000007FF884C958ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE \ +0x1000007FF884C960ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE \ +0x1000007FF884C968ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE \ +0x1000007FF884C970ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE \ +0x1000007FF884C978ull +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE0_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x1000007FF884CB00ull +#define DCORE0_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE0_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1000007FF884CB80ull +#define DCORE0_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE0_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x1000007FF884CC00ull +#define DCORE0_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x1000007FF884CC80ull +#define DCORE0_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE0_TPC4_EML_TPC_QM_CGM_BASE 0x1000007FF884CD80ull +#define DCORE0_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC4_EML_TPC_QM_CGM_SECTION 0x1000 + +#define mmDCORE0_TPC4_EML_TPC_QM_SPECIAL_BASE 0x1000007FF884CE80ull +#define DCORE0_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 + +#define mmDCORE0_TPC4_EML_CS_BASE 0x1000007FF89FF000ull +#define DCORE0_TPC4_EML_CS_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_EML_CS_SECTION 0x1000 + +#define mmDCORE0_TPC5_ROM_TABLE_BASE 0x1000007FF8A00000ull +#define DCORE0_TPC5_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_ROM_TABLE_SECTION 0x1000 + +#define mmDCORE0_TPC5_EML_SPMU_BASE 0x1000007FF8A01000ull +#define DCORE0_TPC5_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_SPMU_SECTION 0x1000 + +#define mmDCORE0_TPC5_EML_ETF_BASE 0x1000007FF8A02000ull +#define DCORE0_TPC5_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_ETF_SECTION 0x1000 + +#define mmDCORE0_TPC5_EML_STM_BASE 0x1000007FF8A03000ull +#define DCORE0_TPC5_EML_STM_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_STM_SECTION 0x2000 + +#define mmDCORE0_TPC5_EML_CTI_BASE 0x1000007FF8A05000ull +#define DCORE0_TPC5_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_CTI_SECTION 0x1000 + +#define mmDCORE0_TPC5_EML_FUNNEL_BASE 0x1000007FF8A06000ull +#define DCORE0_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_FUNNEL_SECTION 0x1000 + +#define mmDCORE0_TPC5_EML_BUSMON_0_BASE 0x1000007FF8A07000ull +#define DCORE0_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_BUSMON_0_SECTION 0x1000 + +#define mmDCORE0_TPC5_EML_BUSMON_1_BASE 0x1000007FF8A08000ull +#define DCORE0_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_BUSMON_1_SECTION 0x1000 + +#define mmDCORE0_TPC5_EML_BUSMON_2_BASE 0x1000007FF8A09000ull +#define DCORE0_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_BUSMON_2_SECTION 0x1000 + +#define mmDCORE0_TPC5_EML_BUSMON_3_BASE 0x1000007FF8A0A000ull +#define DCORE0_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_BUSMON_3_SECTION 0x1000 + +#define mmDCORE0_TPC5_QM_ARC_RTT_BASE 0x1000007FF8A0B000ull +#define DCORE0_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_TPC5_QM_ARC_RTT_SECTION 0x35000 + +#define mmDCORE0_TPC5_EML_CFG_BASE 0x1000007FF8A40000ull +#define DCORE0_TPC5_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_CFG_SECTION 0xE800 + +#define mmDCORE0_TPC5_EML_CFG_SPECIAL_BASE 0x1000007FF8A40E80ull +#define DCORE0_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1000007FF8A41000ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC5_EML_TPC_CFG_BASE 0x1000007FF8A41000ull +#define DCORE0_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_TPC_CFG_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1000007FF8A41050ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1000007FF8A410A0ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1000007FF8A410F0ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1000007FF8A41140ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1000007FF8A41190ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1000007FF8A411E0ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1000007FF8A41230ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1000007FF8A41280ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1000007FF8A412D0ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1000007FF8A41320ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1000007FF8A41370ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1000007FF8A413C0ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1000007FF8A41410ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1000007FF8A41460ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1000007FF8A414B0ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FF8A41500ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_BASE 0x1000007FF8A41508ull +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1000007FF8A415DCull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1000007FF8A4162Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1000007FF8A4167Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1000007FF8A416CCull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1000007FF8A4171Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1000007FF8A4176Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1000007FF8A417BCull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1000007FF8A4180Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1000007FF8A4185Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1000007FF8A418ACull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1000007FF8A418FCull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1000007FF8A4194Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1000007FF8A4199Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1000007FF8A419ECull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1000007FF8A41A3Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1000007FF8A41A8Cull +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1000007FF8A41ADCull +#define DCORE0_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_QM_BASE 0x1000007FF8A41AE4ull +#define DCORE0_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0 + +#define mmDCORE0_TPC5_EML_TPC_CFG_AXUSER_BASE 0x1000007FF8A41E00ull +#define DCORE0_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE0_TPC5_EML_TPC_CFG_SPECIAL_BASE 0x1000007FF8A41E80ull +#define DCORE0_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC5_EML_QM_DCCM_BASE 0x1000007FF8A42000ull +#define DCORE0_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC5_EML_QM_DCCM_SECTION 0x8000 + +#define mmDCORE0_TPC5_EML_QM_ARCAUX_BASE 0x1000007FF8A4A000ull +#define DCORE0_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_QM_ARCAUX_SECTION 0xE800 + +#define mmDCORE0_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0x1000007FF8A4AE80ull +#define DCORE0_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE0_TPC5_EML_TPC_QM_BASE 0x1000007FF8A4C000ull +#define DCORE0_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_TPC_QM_SECTION 0x9000 + +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FF8A4C900ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FF8A4C908ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FF8A4C910ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FF8A4C918ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FF8A4C920ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FF8A4C928ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FF8A4C930ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FF8A4C938ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FF8A4C940ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FF8A4C948ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE \ +0x1000007FF8A4C950ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE \ +0x1000007FF8A4C958ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE \ +0x1000007FF8A4C960ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE \ +0x1000007FF8A4C968ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE \ +0x1000007FF8A4C970ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE \ +0x1000007FF8A4C978ull +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE0_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0x1000007FF8A4CB00ull +#define DCORE0_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE0_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1000007FF8A4CB80ull +#define DCORE0_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE0_TPC5_EML_TPC_QM_DBG_HBW_BASE 0x1000007FF8A4CC00ull +#define DCORE0_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_TPC5_EML_TPC_QM_DBG_LBW_BASE 0x1000007FF8A4CC80ull +#define DCORE0_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE0_TPC5_EML_TPC_QM_CGM_BASE 0x1000007FF8A4CD80ull +#define DCORE0_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC5_EML_TPC_QM_CGM_SECTION 0x1000 + +#define mmDCORE0_TPC5_EML_TPC_QM_SPECIAL_BASE 0x1000007FF8A4CE80ull +#define DCORE0_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 + +#define mmDCORE0_TPC5_EML_CS_BASE 0x1000007FF8BFF000ull +#define DCORE0_TPC5_EML_CS_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_EML_CS_SECTION 0x1000 + +#define mmDCORE0_TPC6_ROM_TABLE_BASE 0x1000007FF8C00000ull +#define DCORE0_TPC6_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_ROM_TABLE_SECTION 0x1000 + +#define mmDCORE0_TPC6_EML_SPMU_BASE 0x1000007FF8C01000ull +#define DCORE0_TPC6_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_SPMU_SECTION 0x1000 + +#define mmDCORE0_TPC6_EML_ETF_BASE 0x1000007FF8C02000ull +#define DCORE0_TPC6_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_ETF_SECTION 0x1000 + +#define mmDCORE0_TPC6_EML_STM_BASE 0x1000007FF8C03000ull +#define DCORE0_TPC6_EML_STM_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_STM_SECTION 0x2000 + +#define mmDCORE0_TPC6_EML_CTI_BASE 0x1000007FF8C05000ull +#define DCORE0_TPC6_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_CTI_SECTION 0x1000 + +#define mmDCORE0_TPC6_EML_FUNNEL_BASE 0x1000007FF8C06000ull +#define DCORE0_TPC6_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_FUNNEL_SECTION 0x1000 + +#define mmDCORE0_TPC6_EML_BUSMON_0_BASE 0x1000007FF8C07000ull +#define DCORE0_TPC6_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_BUSMON_0_SECTION 0x1000 + +#define mmDCORE0_TPC6_EML_BUSMON_1_BASE 0x1000007FF8C08000ull +#define DCORE0_TPC6_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_BUSMON_1_SECTION 0x1000 + +#define mmDCORE0_TPC6_EML_BUSMON_2_BASE 0x1000007FF8C09000ull +#define DCORE0_TPC6_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_BUSMON_2_SECTION 0x1000 + +#define mmDCORE0_TPC6_EML_BUSMON_3_BASE 0x1000007FF8C0A000ull +#define DCORE0_TPC6_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_BUSMON_3_SECTION 0x1000 + +#define mmDCORE0_TPC6_QM_ARC_RTT_BASE 0x1000007FF8C0B000ull +#define DCORE0_TPC6_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_TPC6_QM_ARC_RTT_SECTION 0x35000 + +#define mmDCORE0_TPC6_EML_CFG_BASE 0x1000007FF8C40000ull +#define DCORE0_TPC6_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_CFG_SECTION 0xE800 + +#define mmDCORE0_TPC6_EML_CFG_SPECIAL_BASE 0x1000007FF8C40E80ull +#define DCORE0_TPC6_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC6_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1000007FF8C41000ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC6_EML_TPC_CFG_BASE 0x1000007FF8C41000ull +#define DCORE0_TPC6_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_TPC_CFG_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1000007FF8C41050ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1000007FF8C410A0ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1000007FF8C410F0ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1000007FF8C41140ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1000007FF8C41190ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1000007FF8C411E0ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1000007FF8C41230ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1000007FF8C41280ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1000007FF8C412D0ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1000007FF8C41320ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1000007FF8C41370ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1000007FF8C413C0ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1000007FF8C41410ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1000007FF8C41460ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1000007FF8C414B0ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FF8C41500ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_BASE 0x1000007FF8C41508ull +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC6_EML_TPC_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1000007FF8C415DCull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1000007FF8C4162Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1000007FF8C4167Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1000007FF8C416CCull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1000007FF8C4171Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1000007FF8C4176Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1000007FF8C417BCull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1000007FF8C4180Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1000007FF8C4185Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1000007FF8C418ACull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1000007FF8C418FCull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1000007FF8C4194Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1000007FF8C4199Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1000007FF8C419ECull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1000007FF8C41A3Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1000007FF8C41A8Cull +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1000007FF8C41ADCull +#define DCORE0_TPC6_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_QM_BASE 0x1000007FF8C41AE4ull +#define DCORE0_TPC6_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC6_EML_TPC_CFG_QM_SECTION 0x31C0 + +#define mmDCORE0_TPC6_EML_TPC_CFG_AXUSER_BASE 0x1000007FF8C41E00ull +#define DCORE0_TPC6_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE0_TPC6_EML_TPC_CFG_SPECIAL_BASE 0x1000007FF8C41E80ull +#define DCORE0_TPC6_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC6_EML_TPC_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC6_EML_QM_DCCM_BASE 0x1000007FF8C42000ull +#define DCORE0_TPC6_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC6_EML_QM_DCCM_SECTION 0x8000 + +#define mmDCORE0_TPC6_EML_QM_ARCAUX_BASE 0x1000007FF8C4A000ull +#define DCORE0_TPC6_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_QM_ARCAUX_SECTION 0xE800 + +#define mmDCORE0_TPC6_EML_QM_ARCAUX_SPECIAL_BASE 0x1000007FF8C4AE80ull +#define DCORE0_TPC6_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC6_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE0_TPC6_EML_TPC_QM_BASE 0x1000007FF8C4C000ull +#define DCORE0_TPC6_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_TPC_QM_SECTION 0x9000 + +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FF8C4C900ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FF8C4C908ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FF8C4C910ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FF8C4C918ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FF8C4C920ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FF8C4C928ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FF8C4C930ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FF8C4C938ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FF8C4C940ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FF8C4C948ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE \ +0x1000007FF8C4C950ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE \ +0x1000007FF8C4C958ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE \ +0x1000007FF8C4C960ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE \ +0x1000007FF8C4C968ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE \ +0x1000007FF8C4C970ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE \ +0x1000007FF8C4C978ull +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE0_TPC6_EML_TPC_QM_AXUSER_SECURED_BASE 0x1000007FF8C4CB00ull +#define DCORE0_TPC6_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE0_TPC6_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1000007FF8C4CB80ull +#define DCORE0_TPC6_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE0_TPC6_EML_TPC_QM_DBG_HBW_BASE 0x1000007FF8C4CC00ull +#define DCORE0_TPC6_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC6_EML_TPC_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_TPC6_EML_TPC_QM_DBG_LBW_BASE 0x1000007FF8C4CC80ull +#define DCORE0_TPC6_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC6_EML_TPC_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE0_TPC6_EML_TPC_QM_CGM_BASE 0x1000007FF8C4CD80ull +#define DCORE0_TPC6_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC6_EML_TPC_QM_CGM_SECTION 0x1000 + +#define mmDCORE0_TPC6_EML_TPC_QM_SPECIAL_BASE 0x1000007FF8C4CE80ull +#define DCORE0_TPC6_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC6_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 + +#define mmDCORE0_TPC6_EML_CS_BASE 0x1000007FF8DFF000ull +#define DCORE0_TPC6_EML_CS_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_EML_CS_SECTION 0x201000 + +#define mmDCORE1_TPC0_ROM_TABLE_BASE 0x1000007FF9000000ull +#define DCORE1_TPC0_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_ROM_TABLE_SECTION 0x1000 + +#define mmDCORE1_TPC0_EML_SPMU_BASE 0x1000007FF9001000ull +#define DCORE1_TPC0_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_SPMU_SECTION 0x1000 + +#define mmDCORE1_TPC0_EML_ETF_BASE 0x1000007FF9002000ull +#define DCORE1_TPC0_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_ETF_SECTION 0x1000 + +#define mmDCORE1_TPC0_EML_STM_BASE 0x1000007FF9003000ull +#define DCORE1_TPC0_EML_STM_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_STM_SECTION 0x2000 + +#define mmDCORE1_TPC0_EML_CTI_BASE 0x1000007FF9005000ull +#define DCORE1_TPC0_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_CTI_SECTION 0x1000 + +#define mmDCORE1_TPC0_EML_FUNNEL_BASE 0x1000007FF9006000ull +#define DCORE1_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_FUNNEL_SECTION 0x1000 + +#define mmDCORE1_TPC0_EML_BUSMON_0_BASE 0x1000007FF9007000ull +#define DCORE1_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_BUSMON_0_SECTION 0x1000 + +#define mmDCORE1_TPC0_EML_BUSMON_1_BASE 0x1000007FF9008000ull +#define DCORE1_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_BUSMON_1_SECTION 0x1000 + +#define mmDCORE1_TPC0_EML_BUSMON_2_BASE 0x1000007FF9009000ull +#define DCORE1_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_BUSMON_2_SECTION 0x1000 + +#define mmDCORE1_TPC0_EML_BUSMON_3_BASE 0x1000007FF900A000ull +#define DCORE1_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_BUSMON_3_SECTION 0x1000 + +#define mmDCORE1_TPC0_QM_ARC_RTT_BASE 0x1000007FF900B000ull +#define DCORE1_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_TPC0_QM_ARC_RTT_SECTION 0x35000 + +#define mmDCORE1_TPC0_EML_CFG_BASE 0x1000007FF9040000ull +#define DCORE1_TPC0_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_CFG_SECTION 0xE800 + +#define mmDCORE1_TPC0_EML_CFG_SPECIAL_BASE 0x1000007FF9040E80ull +#define DCORE1_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1000007FF9041000ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC0_EML_TPC_CFG_BASE 0x1000007FF9041000ull +#define DCORE1_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_TPC_CFG_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1000007FF9041050ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1000007FF90410A0ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1000007FF90410F0ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1000007FF9041140ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1000007FF9041190ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1000007FF90411E0ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1000007FF9041230ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1000007FF9041280ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1000007FF90412D0ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1000007FF9041320ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1000007FF9041370ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1000007FF90413C0ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1000007FF9041410ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1000007FF9041460ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1000007FF90414B0ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FF9041500ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_BASE 0x1000007FF9041508ull +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1000007FF90415DCull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1000007FF904162Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1000007FF904167Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1000007FF90416CCull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1000007FF904171Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1000007FF904176Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1000007FF90417BCull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1000007FF904180Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1000007FF904185Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1000007FF90418ACull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1000007FF90418FCull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1000007FF904194Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1000007FF904199Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1000007FF90419ECull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1000007FF9041A3Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1000007FF9041A8Cull +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1000007FF9041ADCull +#define DCORE1_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_QM_BASE 0x1000007FF9041AE4ull +#define DCORE1_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0 + +#define mmDCORE1_TPC0_EML_TPC_CFG_AXUSER_BASE 0x1000007FF9041E00ull +#define DCORE1_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE1_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x1000007FF9041E80ull +#define DCORE1_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC0_EML_QM_DCCM_BASE 0x1000007FF9042000ull +#define DCORE1_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC0_EML_QM_DCCM_SECTION 0x8000 + +#define mmDCORE1_TPC0_EML_QM_ARCAUX_BASE 0x1000007FF904A000ull +#define DCORE1_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_QM_ARCAUX_SECTION 0xE800 + +#define mmDCORE1_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x1000007FF904AE80ull +#define DCORE1_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE1_TPC0_EML_TPC_QM_BASE 0x1000007FF904C000ull +#define DCORE1_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_TPC_QM_SECTION 0x9000 + +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FF904C900ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FF904C908ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FF904C910ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FF904C918ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FF904C920ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FF904C928ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FF904C930ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FF904C938ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FF904C940ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FF904C948ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE \ +0x1000007FF904C950ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE \ +0x1000007FF904C958ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE \ +0x1000007FF904C960ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE \ +0x1000007FF904C968ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE \ +0x1000007FF904C970ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE \ +0x1000007FF904C978ull +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE1_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x1000007FF904CB00ull +#define DCORE1_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE1_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1000007FF904CB80ull +#define DCORE1_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE1_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x1000007FF904CC00ull +#define DCORE1_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x1000007FF904CC80ull +#define DCORE1_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE1_TPC0_EML_TPC_QM_CGM_BASE 0x1000007FF904CD80ull +#define DCORE1_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC0_EML_TPC_QM_CGM_SECTION 0x1000 + +#define mmDCORE1_TPC0_EML_TPC_QM_SPECIAL_BASE 0x1000007FF904CE80ull +#define DCORE1_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 + +#define mmDCORE1_TPC0_EML_CS_BASE 0x1000007FF91FF000ull +#define DCORE1_TPC0_EML_CS_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_EML_CS_SECTION 0x1000 + +#define mmDCORE1_TPC1_ROM_TABLE_BASE 0x1000007FF9200000ull +#define DCORE1_TPC1_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_ROM_TABLE_SECTION 0x1000 + +#define mmDCORE1_TPC1_EML_SPMU_BASE 0x1000007FF9201000ull +#define DCORE1_TPC1_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_SPMU_SECTION 0x1000 + +#define mmDCORE1_TPC1_EML_ETF_BASE 0x1000007FF9202000ull +#define DCORE1_TPC1_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_ETF_SECTION 0x1000 + +#define mmDCORE1_TPC1_EML_STM_BASE 0x1000007FF9203000ull +#define DCORE1_TPC1_EML_STM_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_STM_SECTION 0x2000 + +#define mmDCORE1_TPC1_EML_CTI_BASE 0x1000007FF9205000ull +#define DCORE1_TPC1_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_CTI_SECTION 0x1000 + +#define mmDCORE1_TPC1_EML_FUNNEL_BASE 0x1000007FF9206000ull +#define DCORE1_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_FUNNEL_SECTION 0x1000 + +#define mmDCORE1_TPC1_EML_BUSMON_0_BASE 0x1000007FF9207000ull +#define DCORE1_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_BUSMON_0_SECTION 0x1000 + +#define mmDCORE1_TPC1_EML_BUSMON_1_BASE 0x1000007FF9208000ull +#define DCORE1_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_BUSMON_1_SECTION 0x1000 + +#define mmDCORE1_TPC1_EML_BUSMON_2_BASE 0x1000007FF9209000ull +#define DCORE1_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_BUSMON_2_SECTION 0x1000 + +#define mmDCORE1_TPC1_EML_BUSMON_3_BASE 0x1000007FF920A000ull +#define DCORE1_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_BUSMON_3_SECTION 0x1000 + +#define mmDCORE1_TPC1_QM_ARC_RTT_BASE 0x1000007FF920B000ull +#define DCORE1_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_TPC1_QM_ARC_RTT_SECTION 0x35000 + +#define mmDCORE1_TPC1_EML_CFG_BASE 0x1000007FF9240000ull +#define DCORE1_TPC1_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_CFG_SECTION 0xE800 + +#define mmDCORE1_TPC1_EML_CFG_SPECIAL_BASE 0x1000007FF9240E80ull +#define DCORE1_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1000007FF9241000ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC1_EML_TPC_CFG_BASE 0x1000007FF9241000ull +#define DCORE1_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_TPC_CFG_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1000007FF9241050ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1000007FF92410A0ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1000007FF92410F0ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1000007FF9241140ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1000007FF9241190ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1000007FF92411E0ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1000007FF9241230ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1000007FF9241280ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1000007FF92412D0ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1000007FF9241320ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1000007FF9241370ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1000007FF92413C0ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1000007FF9241410ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1000007FF9241460ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1000007FF92414B0ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FF9241500ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_BASE 0x1000007FF9241508ull +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1000007FF92415DCull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1000007FF924162Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1000007FF924167Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1000007FF92416CCull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1000007FF924171Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1000007FF924176Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1000007FF92417BCull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1000007FF924180Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1000007FF924185Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1000007FF92418ACull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1000007FF92418FCull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1000007FF924194Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1000007FF924199Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1000007FF92419ECull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1000007FF9241A3Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1000007FF9241A8Cull +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1000007FF9241ADCull +#define DCORE1_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_QM_BASE 0x1000007FF9241AE4ull +#define DCORE1_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0 + +#define mmDCORE1_TPC1_EML_TPC_CFG_AXUSER_BASE 0x1000007FF9241E00ull +#define DCORE1_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE1_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x1000007FF9241E80ull +#define DCORE1_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC1_EML_QM_DCCM_BASE 0x1000007FF9242000ull +#define DCORE1_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC1_EML_QM_DCCM_SECTION 0x8000 + +#define mmDCORE1_TPC1_EML_QM_ARCAUX_BASE 0x1000007FF924A000ull +#define DCORE1_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_QM_ARCAUX_SECTION 0xE800 + +#define mmDCORE1_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x1000007FF924AE80ull +#define DCORE1_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE1_TPC1_EML_TPC_QM_BASE 0x1000007FF924C000ull +#define DCORE1_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_TPC_QM_SECTION 0x9000 + +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FF924C900ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FF924C908ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FF924C910ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FF924C918ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FF924C920ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FF924C928ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FF924C930ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FF924C938ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FF924C940ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FF924C948ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE \ +0x1000007FF924C950ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE \ +0x1000007FF924C958ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE \ +0x1000007FF924C960ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE \ +0x1000007FF924C968ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE \ +0x1000007FF924C970ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE \ +0x1000007FF924C978ull +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE1_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x1000007FF924CB00ull +#define DCORE1_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE1_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1000007FF924CB80ull +#define DCORE1_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE1_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x1000007FF924CC00ull +#define DCORE1_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x1000007FF924CC80ull +#define DCORE1_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE1_TPC1_EML_TPC_QM_CGM_BASE 0x1000007FF924CD80ull +#define DCORE1_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC1_EML_TPC_QM_CGM_SECTION 0x1000 + +#define mmDCORE1_TPC1_EML_TPC_QM_SPECIAL_BASE 0x1000007FF924CE80ull +#define DCORE1_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 + +#define mmDCORE1_TPC1_EML_CS_BASE 0x1000007FF93FF000ull +#define DCORE1_TPC1_EML_CS_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_EML_CS_SECTION 0x1000 + +#define mmDCORE1_TPC2_ROM_TABLE_BASE 0x1000007FF9400000ull +#define DCORE1_TPC2_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_ROM_TABLE_SECTION 0x1000 + +#define mmDCORE1_TPC2_EML_SPMU_BASE 0x1000007FF9401000ull +#define DCORE1_TPC2_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_SPMU_SECTION 0x1000 + +#define mmDCORE1_TPC2_EML_ETF_BASE 0x1000007FF9402000ull +#define DCORE1_TPC2_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_ETF_SECTION 0x1000 + +#define mmDCORE1_TPC2_EML_STM_BASE 0x1000007FF9403000ull +#define DCORE1_TPC2_EML_STM_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_STM_SECTION 0x2000 + +#define mmDCORE1_TPC2_EML_CTI_BASE 0x1000007FF9405000ull +#define DCORE1_TPC2_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_CTI_SECTION 0x1000 + +#define mmDCORE1_TPC2_EML_FUNNEL_BASE 0x1000007FF9406000ull +#define DCORE1_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_FUNNEL_SECTION 0x1000 + +#define mmDCORE1_TPC2_EML_BUSMON_0_BASE 0x1000007FF9407000ull +#define DCORE1_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_BUSMON_0_SECTION 0x1000 + +#define mmDCORE1_TPC2_EML_BUSMON_1_BASE 0x1000007FF9408000ull +#define DCORE1_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_BUSMON_1_SECTION 0x1000 + +#define mmDCORE1_TPC2_EML_BUSMON_2_BASE 0x1000007FF9409000ull +#define DCORE1_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_BUSMON_2_SECTION 0x1000 + +#define mmDCORE1_TPC2_EML_BUSMON_3_BASE 0x1000007FF940A000ull +#define DCORE1_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_BUSMON_3_SECTION 0x1000 + +#define mmDCORE1_TPC2_QM_ARC_RTT_BASE 0x1000007FF940B000ull +#define DCORE1_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_TPC2_QM_ARC_RTT_SECTION 0x35000 + +#define mmDCORE1_TPC2_EML_CFG_BASE 0x1000007FF9440000ull +#define DCORE1_TPC2_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_CFG_SECTION 0xE800 + +#define mmDCORE1_TPC2_EML_CFG_SPECIAL_BASE 0x1000007FF9440E80ull +#define DCORE1_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1000007FF9441000ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC2_EML_TPC_CFG_BASE 0x1000007FF9441000ull +#define DCORE1_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_TPC_CFG_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1000007FF9441050ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1000007FF94410A0ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1000007FF94410F0ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1000007FF9441140ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1000007FF9441190ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1000007FF94411E0ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1000007FF9441230ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1000007FF9441280ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1000007FF94412D0ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1000007FF9441320ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1000007FF9441370ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1000007FF94413C0ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1000007FF9441410ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1000007FF9441460ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1000007FF94414B0ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FF9441500ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_BASE 0x1000007FF9441508ull +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1000007FF94415DCull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1000007FF944162Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1000007FF944167Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1000007FF94416CCull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1000007FF944171Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1000007FF944176Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1000007FF94417BCull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1000007FF944180Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1000007FF944185Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1000007FF94418ACull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1000007FF94418FCull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1000007FF944194Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1000007FF944199Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1000007FF94419ECull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1000007FF9441A3Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1000007FF9441A8Cull +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1000007FF9441ADCull +#define DCORE1_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_QM_BASE 0x1000007FF9441AE4ull +#define DCORE1_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0 + +#define mmDCORE1_TPC2_EML_TPC_CFG_AXUSER_BASE 0x1000007FF9441E00ull +#define DCORE1_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE1_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x1000007FF9441E80ull +#define DCORE1_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC2_EML_QM_DCCM_BASE 0x1000007FF9442000ull +#define DCORE1_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC2_EML_QM_DCCM_SECTION 0x8000 + +#define mmDCORE1_TPC2_EML_QM_ARCAUX_BASE 0x1000007FF944A000ull +#define DCORE1_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_QM_ARCAUX_SECTION 0xE800 + +#define mmDCORE1_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x1000007FF944AE80ull +#define DCORE1_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE1_TPC2_EML_TPC_QM_BASE 0x1000007FF944C000ull +#define DCORE1_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_TPC_QM_SECTION 0x9000 + +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FF944C900ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FF944C908ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FF944C910ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FF944C918ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FF944C920ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FF944C928ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FF944C930ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FF944C938ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FF944C940ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FF944C948ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE \ +0x1000007FF944C950ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE \ +0x1000007FF944C958ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE \ +0x1000007FF944C960ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE \ +0x1000007FF944C968ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE \ +0x1000007FF944C970ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE \ +0x1000007FF944C978ull +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE1_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x1000007FF944CB00ull +#define DCORE1_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE1_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1000007FF944CB80ull +#define DCORE1_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE1_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x1000007FF944CC00ull +#define DCORE1_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x1000007FF944CC80ull +#define DCORE1_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE1_TPC2_EML_TPC_QM_CGM_BASE 0x1000007FF944CD80ull +#define DCORE1_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC2_EML_TPC_QM_CGM_SECTION 0x1000 + +#define mmDCORE1_TPC2_EML_TPC_QM_SPECIAL_BASE 0x1000007FF944CE80ull +#define DCORE1_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 + +#define mmDCORE1_TPC2_EML_CS_BASE 0x1000007FF95FF000ull +#define DCORE1_TPC2_EML_CS_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_EML_CS_SECTION 0x1000 + +#define mmDCORE1_TPC3_ROM_TABLE_BASE 0x1000007FF9600000ull +#define DCORE1_TPC3_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_ROM_TABLE_SECTION 0x1000 + +#define mmDCORE1_TPC3_EML_SPMU_BASE 0x1000007FF9601000ull +#define DCORE1_TPC3_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_SPMU_SECTION 0x1000 + +#define mmDCORE1_TPC3_EML_ETF_BASE 0x1000007FF9602000ull +#define DCORE1_TPC3_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_ETF_SECTION 0x1000 + +#define mmDCORE1_TPC3_EML_STM_BASE 0x1000007FF9603000ull +#define DCORE1_TPC3_EML_STM_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_STM_SECTION 0x2000 + +#define mmDCORE1_TPC3_EML_CTI_BASE 0x1000007FF9605000ull +#define DCORE1_TPC3_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_CTI_SECTION 0x1000 + +#define mmDCORE1_TPC3_EML_FUNNEL_BASE 0x1000007FF9606000ull +#define DCORE1_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_FUNNEL_SECTION 0x1000 + +#define mmDCORE1_TPC3_EML_BUSMON_0_BASE 0x1000007FF9607000ull +#define DCORE1_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_BUSMON_0_SECTION 0x1000 + +#define mmDCORE1_TPC3_EML_BUSMON_1_BASE 0x1000007FF9608000ull +#define DCORE1_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_BUSMON_1_SECTION 0x1000 + +#define mmDCORE1_TPC3_EML_BUSMON_2_BASE 0x1000007FF9609000ull +#define DCORE1_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_BUSMON_2_SECTION 0x1000 + +#define mmDCORE1_TPC3_EML_BUSMON_3_BASE 0x1000007FF960A000ull +#define DCORE1_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_BUSMON_3_SECTION 0x1000 + +#define mmDCORE1_TPC3_QM_ARC_RTT_BASE 0x1000007FF960B000ull +#define DCORE1_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_TPC3_QM_ARC_RTT_SECTION 0x35000 + +#define mmDCORE1_TPC3_EML_CFG_BASE 0x1000007FF9640000ull +#define DCORE1_TPC3_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_CFG_SECTION 0xE800 + +#define mmDCORE1_TPC3_EML_CFG_SPECIAL_BASE 0x1000007FF9640E80ull +#define DCORE1_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1000007FF9641000ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC3_EML_TPC_CFG_BASE 0x1000007FF9641000ull +#define DCORE1_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_TPC_CFG_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1000007FF9641050ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1000007FF96410A0ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1000007FF96410F0ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1000007FF9641140ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1000007FF9641190ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1000007FF96411E0ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1000007FF9641230ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1000007FF9641280ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1000007FF96412D0ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1000007FF9641320ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1000007FF9641370ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1000007FF96413C0ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1000007FF9641410ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1000007FF9641460ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1000007FF96414B0ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FF9641500ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_BASE 0x1000007FF9641508ull +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1000007FF96415DCull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1000007FF964162Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1000007FF964167Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1000007FF96416CCull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1000007FF964171Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1000007FF964176Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1000007FF96417BCull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1000007FF964180Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1000007FF964185Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1000007FF96418ACull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1000007FF96418FCull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1000007FF964194Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1000007FF964199Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1000007FF96419ECull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1000007FF9641A3Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1000007FF9641A8Cull +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1000007FF9641ADCull +#define DCORE1_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_QM_BASE 0x1000007FF9641AE4ull +#define DCORE1_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0 + +#define mmDCORE1_TPC3_EML_TPC_CFG_AXUSER_BASE 0x1000007FF9641E00ull +#define DCORE1_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE1_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x1000007FF9641E80ull +#define DCORE1_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC3_EML_QM_DCCM_BASE 0x1000007FF9642000ull +#define DCORE1_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC3_EML_QM_DCCM_SECTION 0x8000 + +#define mmDCORE1_TPC3_EML_QM_ARCAUX_BASE 0x1000007FF964A000ull +#define DCORE1_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_QM_ARCAUX_SECTION 0xE800 + +#define mmDCORE1_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x1000007FF964AE80ull +#define DCORE1_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE1_TPC3_EML_TPC_QM_BASE 0x1000007FF964C000ull +#define DCORE1_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_TPC_QM_SECTION 0x9000 + +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FF964C900ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FF964C908ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FF964C910ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FF964C918ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FF964C920ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FF964C928ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FF964C930ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FF964C938ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FF964C940ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FF964C948ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE \ +0x1000007FF964C950ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE \ +0x1000007FF964C958ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE \ +0x1000007FF964C960ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE \ +0x1000007FF964C968ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE \ +0x1000007FF964C970ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE \ +0x1000007FF964C978ull +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE1_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x1000007FF964CB00ull +#define DCORE1_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE1_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1000007FF964CB80ull +#define DCORE1_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE1_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x1000007FF964CC00ull +#define DCORE1_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x1000007FF964CC80ull +#define DCORE1_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE1_TPC3_EML_TPC_QM_CGM_BASE 0x1000007FF964CD80ull +#define DCORE1_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC3_EML_TPC_QM_CGM_SECTION 0x1000 + +#define mmDCORE1_TPC3_EML_TPC_QM_SPECIAL_BASE 0x1000007FF964CE80ull +#define DCORE1_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 + +#define mmDCORE1_TPC3_EML_CS_BASE 0x1000007FF97FF000ull +#define DCORE1_TPC3_EML_CS_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_EML_CS_SECTION 0x1000 + +#define mmDCORE1_TPC4_ROM_TABLE_BASE 0x1000007FF9800000ull +#define DCORE1_TPC4_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_ROM_TABLE_SECTION 0x1000 + +#define mmDCORE1_TPC4_EML_SPMU_BASE 0x1000007FF9801000ull +#define DCORE1_TPC4_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_SPMU_SECTION 0x1000 + +#define mmDCORE1_TPC4_EML_ETF_BASE 0x1000007FF9802000ull +#define DCORE1_TPC4_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_ETF_SECTION 0x1000 + +#define mmDCORE1_TPC4_EML_STM_BASE 0x1000007FF9803000ull +#define DCORE1_TPC4_EML_STM_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_STM_SECTION 0x2000 + +#define mmDCORE1_TPC4_EML_CTI_BASE 0x1000007FF9805000ull +#define DCORE1_TPC4_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_CTI_SECTION 0x1000 + +#define mmDCORE1_TPC4_EML_FUNNEL_BASE 0x1000007FF9806000ull +#define DCORE1_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_FUNNEL_SECTION 0x1000 + +#define mmDCORE1_TPC4_EML_BUSMON_0_BASE 0x1000007FF9807000ull +#define DCORE1_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_BUSMON_0_SECTION 0x1000 + +#define mmDCORE1_TPC4_EML_BUSMON_1_BASE 0x1000007FF9808000ull +#define DCORE1_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_BUSMON_1_SECTION 0x1000 + +#define mmDCORE1_TPC4_EML_BUSMON_2_BASE 0x1000007FF9809000ull +#define DCORE1_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_BUSMON_2_SECTION 0x1000 + +#define mmDCORE1_TPC4_EML_BUSMON_3_BASE 0x1000007FF980A000ull +#define DCORE1_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_BUSMON_3_SECTION 0x1000 + +#define mmDCORE1_TPC4_QM_ARC_RTT_BASE 0x1000007FF980B000ull +#define DCORE1_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_TPC4_QM_ARC_RTT_SECTION 0x35000 + +#define mmDCORE1_TPC4_EML_CFG_BASE 0x1000007FF9840000ull +#define DCORE1_TPC4_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_CFG_SECTION 0xE800 + +#define mmDCORE1_TPC4_EML_CFG_SPECIAL_BASE 0x1000007FF9840E80ull +#define DCORE1_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1000007FF9841000ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC4_EML_TPC_CFG_BASE 0x1000007FF9841000ull +#define DCORE1_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_TPC_CFG_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1000007FF9841050ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1000007FF98410A0ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1000007FF98410F0ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1000007FF9841140ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1000007FF9841190ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1000007FF98411E0ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1000007FF9841230ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1000007FF9841280ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1000007FF98412D0ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1000007FF9841320ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1000007FF9841370ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1000007FF98413C0ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1000007FF9841410ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1000007FF9841460ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1000007FF98414B0ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FF9841500ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_BASE 0x1000007FF9841508ull +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1000007FF98415DCull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1000007FF984162Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1000007FF984167Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1000007FF98416CCull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1000007FF984171Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1000007FF984176Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1000007FF98417BCull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1000007FF984180Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1000007FF984185Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1000007FF98418ACull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1000007FF98418FCull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1000007FF984194Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1000007FF984199Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1000007FF98419ECull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1000007FF9841A3Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1000007FF9841A8Cull +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1000007FF9841ADCull +#define DCORE1_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_QM_BASE 0x1000007FF9841AE4ull +#define DCORE1_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0 + +#define mmDCORE1_TPC4_EML_TPC_CFG_AXUSER_BASE 0x1000007FF9841E00ull +#define DCORE1_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE1_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x1000007FF9841E80ull +#define DCORE1_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC4_EML_QM_DCCM_BASE 0x1000007FF9842000ull +#define DCORE1_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC4_EML_QM_DCCM_SECTION 0x8000 + +#define mmDCORE1_TPC4_EML_QM_ARCAUX_BASE 0x1000007FF984A000ull +#define DCORE1_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_QM_ARCAUX_SECTION 0xE800 + +#define mmDCORE1_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x1000007FF984AE80ull +#define DCORE1_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE1_TPC4_EML_TPC_QM_BASE 0x1000007FF984C000ull +#define DCORE1_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_TPC_QM_SECTION 0x9000 + +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FF984C900ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FF984C908ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FF984C910ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FF984C918ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FF984C920ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FF984C928ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FF984C930ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FF984C938ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FF984C940ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FF984C948ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE \ +0x1000007FF984C950ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE \ +0x1000007FF984C958ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE \ +0x1000007FF984C960ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE \ +0x1000007FF984C968ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE \ +0x1000007FF984C970ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE \ +0x1000007FF984C978ull +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE1_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x1000007FF984CB00ull +#define DCORE1_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE1_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1000007FF984CB80ull +#define DCORE1_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE1_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x1000007FF984CC00ull +#define DCORE1_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x1000007FF984CC80ull +#define DCORE1_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE1_TPC4_EML_TPC_QM_CGM_BASE 0x1000007FF984CD80ull +#define DCORE1_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC4_EML_TPC_QM_CGM_SECTION 0x1000 + +#define mmDCORE1_TPC4_EML_TPC_QM_SPECIAL_BASE 0x1000007FF984CE80ull +#define DCORE1_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 + +#define mmDCORE1_TPC4_EML_CS_BASE 0x1000007FF99FF000ull +#define DCORE1_TPC4_EML_CS_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_EML_CS_SECTION 0x1000 + +#define mmDCORE1_TPC5_ROM_TABLE_BASE 0x1000007FF9A00000ull +#define DCORE1_TPC5_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_ROM_TABLE_SECTION 0x1000 + +#define mmDCORE1_TPC5_EML_SPMU_BASE 0x1000007FF9A01000ull +#define DCORE1_TPC5_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_SPMU_SECTION 0x1000 + +#define mmDCORE1_TPC5_EML_ETF_BASE 0x1000007FF9A02000ull +#define DCORE1_TPC5_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_ETF_SECTION 0x1000 + +#define mmDCORE1_TPC5_EML_STM_BASE 0x1000007FF9A03000ull +#define DCORE1_TPC5_EML_STM_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_STM_SECTION 0x2000 + +#define mmDCORE1_TPC5_EML_CTI_BASE 0x1000007FF9A05000ull +#define DCORE1_TPC5_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_CTI_SECTION 0x1000 + +#define mmDCORE1_TPC5_EML_FUNNEL_BASE 0x1000007FF9A06000ull +#define DCORE1_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_FUNNEL_SECTION 0x1000 + +#define mmDCORE1_TPC5_EML_BUSMON_0_BASE 0x1000007FF9A07000ull +#define DCORE1_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_BUSMON_0_SECTION 0x1000 + +#define mmDCORE1_TPC5_EML_BUSMON_1_BASE 0x1000007FF9A08000ull +#define DCORE1_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_BUSMON_1_SECTION 0x1000 + +#define mmDCORE1_TPC5_EML_BUSMON_2_BASE 0x1000007FF9A09000ull +#define DCORE1_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_BUSMON_2_SECTION 0x1000 + +#define mmDCORE1_TPC5_EML_BUSMON_3_BASE 0x1000007FF9A0A000ull +#define DCORE1_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_BUSMON_3_SECTION 0x1000 + +#define mmDCORE1_TPC5_QM_ARC_RTT_BASE 0x1000007FF9A0B000ull +#define DCORE1_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_TPC5_QM_ARC_RTT_SECTION 0x35000 + +#define mmDCORE1_TPC5_EML_CFG_BASE 0x1000007FF9A40000ull +#define DCORE1_TPC5_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_CFG_SECTION 0xE800 + +#define mmDCORE1_TPC5_EML_CFG_SPECIAL_BASE 0x1000007FF9A40E80ull +#define DCORE1_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1000007FF9A41000ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC5_EML_TPC_CFG_BASE 0x1000007FF9A41000ull +#define DCORE1_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_TPC_CFG_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1000007FF9A41050ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1000007FF9A410A0ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1000007FF9A410F0ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1000007FF9A41140ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1000007FF9A41190ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1000007FF9A411E0ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1000007FF9A41230ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1000007FF9A41280ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1000007FF9A412D0ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1000007FF9A41320ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1000007FF9A41370ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1000007FF9A413C0ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1000007FF9A41410ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1000007FF9A41460ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1000007FF9A414B0ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FF9A41500ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_BASE 0x1000007FF9A41508ull +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1000007FF9A415DCull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1000007FF9A4162Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1000007FF9A4167Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1000007FF9A416CCull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1000007FF9A4171Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1000007FF9A4176Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1000007FF9A417BCull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1000007FF9A4180Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1000007FF9A4185Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1000007FF9A418ACull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1000007FF9A418FCull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1000007FF9A4194Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1000007FF9A4199Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1000007FF9A419ECull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1000007FF9A41A3Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1000007FF9A41A8Cull +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1000007FF9A41ADCull +#define DCORE1_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_QM_BASE 0x1000007FF9A41AE4ull +#define DCORE1_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0 + +#define mmDCORE1_TPC5_EML_TPC_CFG_AXUSER_BASE 0x1000007FF9A41E00ull +#define DCORE1_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE1_TPC5_EML_TPC_CFG_SPECIAL_BASE 0x1000007FF9A41E80ull +#define DCORE1_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC5_EML_QM_DCCM_BASE 0x1000007FF9A42000ull +#define DCORE1_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC5_EML_QM_DCCM_SECTION 0x8000 + +#define mmDCORE1_TPC5_EML_QM_ARCAUX_BASE 0x1000007FF9A4A000ull +#define DCORE1_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_QM_ARCAUX_SECTION 0xE800 + +#define mmDCORE1_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0x1000007FF9A4AE80ull +#define DCORE1_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE1_TPC5_EML_TPC_QM_BASE 0x1000007FF9A4C000ull +#define DCORE1_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_TPC_QM_SECTION 0x9000 + +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FF9A4C900ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FF9A4C908ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FF9A4C910ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FF9A4C918ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FF9A4C920ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FF9A4C928ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FF9A4C930ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FF9A4C938ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FF9A4C940ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FF9A4C948ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE \ +0x1000007FF9A4C950ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE \ +0x1000007FF9A4C958ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE \ +0x1000007FF9A4C960ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE \ +0x1000007FF9A4C968ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE \ +0x1000007FF9A4C970ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE \ +0x1000007FF9A4C978ull +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE1_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0x1000007FF9A4CB00ull +#define DCORE1_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE1_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1000007FF9A4CB80ull +#define DCORE1_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE1_TPC5_EML_TPC_QM_DBG_HBW_BASE 0x1000007FF9A4CC00ull +#define DCORE1_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_TPC5_EML_TPC_QM_DBG_LBW_BASE 0x1000007FF9A4CC80ull +#define DCORE1_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE1_TPC5_EML_TPC_QM_CGM_BASE 0x1000007FF9A4CD80ull +#define DCORE1_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC5_EML_TPC_QM_CGM_SECTION 0x1000 + +#define mmDCORE1_TPC5_EML_TPC_QM_SPECIAL_BASE 0x1000007FF9A4CE80ull +#define DCORE1_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 + +#define mmDCORE1_TPC5_EML_CS_BASE 0x1000007FF9BFF000ull +#define DCORE1_TPC5_EML_CS_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_EML_CS_SECTION 0x401000 + +#define mmDCORE2_TPC0_ROM_TABLE_BASE 0x1000007FFA000000ull +#define DCORE2_TPC0_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_ROM_TABLE_SECTION 0x1000 + +#define mmDCORE2_TPC0_EML_SPMU_BASE 0x1000007FFA001000ull +#define DCORE2_TPC0_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_SPMU_SECTION 0x1000 + +#define mmDCORE2_TPC0_EML_ETF_BASE 0x1000007FFA002000ull +#define DCORE2_TPC0_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_ETF_SECTION 0x1000 + +#define mmDCORE2_TPC0_EML_STM_BASE 0x1000007FFA003000ull +#define DCORE2_TPC0_EML_STM_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_STM_SECTION 0x2000 + +#define mmDCORE2_TPC0_EML_CTI_BASE 0x1000007FFA005000ull +#define DCORE2_TPC0_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_CTI_SECTION 0x1000 + +#define mmDCORE2_TPC0_EML_FUNNEL_BASE 0x1000007FFA006000ull +#define DCORE2_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_FUNNEL_SECTION 0x1000 + +#define mmDCORE2_TPC0_EML_BUSMON_0_BASE 0x1000007FFA007000ull +#define DCORE2_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_BUSMON_0_SECTION 0x1000 + +#define mmDCORE2_TPC0_EML_BUSMON_1_BASE 0x1000007FFA008000ull +#define DCORE2_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_BUSMON_1_SECTION 0x1000 + +#define mmDCORE2_TPC0_EML_BUSMON_2_BASE 0x1000007FFA009000ull +#define DCORE2_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_BUSMON_2_SECTION 0x1000 + +#define mmDCORE2_TPC0_EML_BUSMON_3_BASE 0x1000007FFA00A000ull +#define DCORE2_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_BUSMON_3_SECTION 0x1000 + +#define mmDCORE2_TPC0_QM_ARC_RTT_BASE 0x1000007FFA00B000ull +#define DCORE2_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_TPC0_QM_ARC_RTT_SECTION 0x35000 + +#define mmDCORE2_TPC0_EML_CFG_BASE 0x1000007FFA040000ull +#define DCORE2_TPC0_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_CFG_SECTION 0xE800 + +#define mmDCORE2_TPC0_EML_CFG_SPECIAL_BASE 0x1000007FFA040E80ull +#define DCORE2_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFA041000ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC0_EML_TPC_CFG_BASE 0x1000007FFA041000ull +#define DCORE2_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_TPC_CFG_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFA041050ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFA0410A0ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFA0410F0ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFA041140ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFA041190ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFA0411E0ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFA041230ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFA041280ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFA0412D0ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFA041320ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFA041370ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFA0413C0ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFA041410ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFA041460ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFA0414B0ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFA041500ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_BASE 0x1000007FFA041508ull +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1000007FFA0415DCull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1000007FFA04162Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1000007FFA04167Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1000007FFA0416CCull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1000007FFA04171Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1000007FFA04176Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1000007FFA0417BCull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1000007FFA04180Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1000007FFA04185Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1000007FFA0418ACull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1000007FFA0418FCull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1000007FFA04194Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1000007FFA04199Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1000007FFA0419ECull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1000007FFA041A3Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1000007FFA041A8Cull +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFA041ADCull +#define DCORE2_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_QM_BASE 0x1000007FFA041AE4ull +#define DCORE2_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0 + +#define mmDCORE2_TPC0_EML_TPC_CFG_AXUSER_BASE 0x1000007FFA041E00ull +#define DCORE2_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE2_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x1000007FFA041E80ull +#define DCORE2_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC0_EML_QM_DCCM_BASE 0x1000007FFA042000ull +#define DCORE2_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC0_EML_QM_DCCM_SECTION 0x8000 + +#define mmDCORE2_TPC0_EML_QM_ARCAUX_BASE 0x1000007FFA04A000ull +#define DCORE2_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_QM_ARCAUX_SECTION 0xE800 + +#define mmDCORE2_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x1000007FFA04AE80ull +#define DCORE2_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE2_TPC0_EML_TPC_QM_BASE 0x1000007FFA04C000ull +#define DCORE2_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_TPC_QM_SECTION 0x9000 + +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFA04C900ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFA04C908ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFA04C910ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFA04C918ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFA04C920ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFA04C928ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFA04C930ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFA04C938ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFA04C940ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFA04C948ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE \ +0x1000007FFA04C950ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE \ +0x1000007FFA04C958ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE \ +0x1000007FFA04C960ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE \ +0x1000007FFA04C968ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE \ +0x1000007FFA04C970ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE \ +0x1000007FFA04C978ull +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE2_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x1000007FFA04CB00ull +#define DCORE2_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE2_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1000007FFA04CB80ull +#define DCORE2_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE2_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x1000007FFA04CC00ull +#define DCORE2_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x1000007FFA04CC80ull +#define DCORE2_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE2_TPC0_EML_TPC_QM_CGM_BASE 0x1000007FFA04CD80ull +#define DCORE2_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC0_EML_TPC_QM_CGM_SECTION 0x1000 + +#define mmDCORE2_TPC0_EML_TPC_QM_SPECIAL_BASE 0x1000007FFA04CE80ull +#define DCORE2_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 + +#define mmDCORE2_TPC0_EML_CS_BASE 0x1000007FFA1FF000ull +#define DCORE2_TPC0_EML_CS_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_EML_CS_SECTION 0x1000 + +#define mmDCORE2_TPC1_ROM_TABLE_BASE 0x1000007FFA200000ull +#define DCORE2_TPC1_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_ROM_TABLE_SECTION 0x1000 + +#define mmDCORE2_TPC1_EML_SPMU_BASE 0x1000007FFA201000ull +#define DCORE2_TPC1_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_SPMU_SECTION 0x1000 + +#define mmDCORE2_TPC1_EML_ETF_BASE 0x1000007FFA202000ull +#define DCORE2_TPC1_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_ETF_SECTION 0x1000 + +#define mmDCORE2_TPC1_EML_STM_BASE 0x1000007FFA203000ull +#define DCORE2_TPC1_EML_STM_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_STM_SECTION 0x2000 + +#define mmDCORE2_TPC1_EML_CTI_BASE 0x1000007FFA205000ull +#define DCORE2_TPC1_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_CTI_SECTION 0x1000 + +#define mmDCORE2_TPC1_EML_FUNNEL_BASE 0x1000007FFA206000ull +#define DCORE2_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_FUNNEL_SECTION 0x1000 + +#define mmDCORE2_TPC1_EML_BUSMON_0_BASE 0x1000007FFA207000ull +#define DCORE2_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_BUSMON_0_SECTION 0x1000 + +#define mmDCORE2_TPC1_EML_BUSMON_1_BASE 0x1000007FFA208000ull +#define DCORE2_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_BUSMON_1_SECTION 0x1000 + +#define mmDCORE2_TPC1_EML_BUSMON_2_BASE 0x1000007FFA209000ull +#define DCORE2_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_BUSMON_2_SECTION 0x1000 + +#define mmDCORE2_TPC1_EML_BUSMON_3_BASE 0x1000007FFA20A000ull +#define DCORE2_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_BUSMON_3_SECTION 0x1000 + +#define mmDCORE2_TPC1_QM_ARC_RTT_BASE 0x1000007FFA20B000ull +#define DCORE2_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_TPC1_QM_ARC_RTT_SECTION 0x35000 + +#define mmDCORE2_TPC1_EML_CFG_BASE 0x1000007FFA240000ull +#define DCORE2_TPC1_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_CFG_SECTION 0xE800 + +#define mmDCORE2_TPC1_EML_CFG_SPECIAL_BASE 0x1000007FFA240E80ull +#define DCORE2_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFA241000ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC1_EML_TPC_CFG_BASE 0x1000007FFA241000ull +#define DCORE2_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_TPC_CFG_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFA241050ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFA2410A0ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFA2410F0ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFA241140ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFA241190ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFA2411E0ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFA241230ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFA241280ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFA2412D0ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFA241320ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFA241370ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFA2413C0ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFA241410ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFA241460ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFA2414B0ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFA241500ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_BASE 0x1000007FFA241508ull +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1000007FFA2415DCull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1000007FFA24162Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1000007FFA24167Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1000007FFA2416CCull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1000007FFA24171Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1000007FFA24176Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1000007FFA2417BCull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1000007FFA24180Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1000007FFA24185Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1000007FFA2418ACull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1000007FFA2418FCull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1000007FFA24194Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1000007FFA24199Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1000007FFA2419ECull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1000007FFA241A3Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1000007FFA241A8Cull +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFA241ADCull +#define DCORE2_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_QM_BASE 0x1000007FFA241AE4ull +#define DCORE2_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0 + +#define mmDCORE2_TPC1_EML_TPC_CFG_AXUSER_BASE 0x1000007FFA241E00ull +#define DCORE2_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE2_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x1000007FFA241E80ull +#define DCORE2_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC1_EML_QM_DCCM_BASE 0x1000007FFA242000ull +#define DCORE2_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC1_EML_QM_DCCM_SECTION 0x8000 + +#define mmDCORE2_TPC1_EML_QM_ARCAUX_BASE 0x1000007FFA24A000ull +#define DCORE2_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_QM_ARCAUX_SECTION 0xE800 + +#define mmDCORE2_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x1000007FFA24AE80ull +#define DCORE2_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE2_TPC1_EML_TPC_QM_BASE 0x1000007FFA24C000ull +#define DCORE2_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_TPC_QM_SECTION 0x9000 + +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFA24C900ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFA24C908ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFA24C910ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFA24C918ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFA24C920ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFA24C928ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFA24C930ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFA24C938ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFA24C940ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFA24C948ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE \ +0x1000007FFA24C950ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE \ +0x1000007FFA24C958ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE \ +0x1000007FFA24C960ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE \ +0x1000007FFA24C968ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE \ +0x1000007FFA24C970ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE \ +0x1000007FFA24C978ull +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE2_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x1000007FFA24CB00ull +#define DCORE2_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE2_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1000007FFA24CB80ull +#define DCORE2_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE2_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x1000007FFA24CC00ull +#define DCORE2_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x1000007FFA24CC80ull +#define DCORE2_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE2_TPC1_EML_TPC_QM_CGM_BASE 0x1000007FFA24CD80ull +#define DCORE2_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC1_EML_TPC_QM_CGM_SECTION 0x1000 + +#define mmDCORE2_TPC1_EML_TPC_QM_SPECIAL_BASE 0x1000007FFA24CE80ull +#define DCORE2_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 + +#define mmDCORE2_TPC1_EML_CS_BASE 0x1000007FFA3FF000ull +#define DCORE2_TPC1_EML_CS_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_EML_CS_SECTION 0x1000 + +#define mmDCORE2_TPC2_ROM_TABLE_BASE 0x1000007FFA400000ull +#define DCORE2_TPC2_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_ROM_TABLE_SECTION 0x1000 + +#define mmDCORE2_TPC2_EML_SPMU_BASE 0x1000007FFA401000ull +#define DCORE2_TPC2_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_SPMU_SECTION 0x1000 + +#define mmDCORE2_TPC2_EML_ETF_BASE 0x1000007FFA402000ull +#define DCORE2_TPC2_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_ETF_SECTION 0x1000 + +#define mmDCORE2_TPC2_EML_STM_BASE 0x1000007FFA403000ull +#define DCORE2_TPC2_EML_STM_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_STM_SECTION 0x2000 + +#define mmDCORE2_TPC2_EML_CTI_BASE 0x1000007FFA405000ull +#define DCORE2_TPC2_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_CTI_SECTION 0x1000 + +#define mmDCORE2_TPC2_EML_FUNNEL_BASE 0x1000007FFA406000ull +#define DCORE2_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_FUNNEL_SECTION 0x1000 + +#define mmDCORE2_TPC2_EML_BUSMON_0_BASE 0x1000007FFA407000ull +#define DCORE2_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_BUSMON_0_SECTION 0x1000 + +#define mmDCORE2_TPC2_EML_BUSMON_1_BASE 0x1000007FFA408000ull +#define DCORE2_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_BUSMON_1_SECTION 0x1000 + +#define mmDCORE2_TPC2_EML_BUSMON_2_BASE 0x1000007FFA409000ull +#define DCORE2_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_BUSMON_2_SECTION 0x1000 + +#define mmDCORE2_TPC2_EML_BUSMON_3_BASE 0x1000007FFA40A000ull +#define DCORE2_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_BUSMON_3_SECTION 0x1000 + +#define mmDCORE2_TPC2_QM_ARC_RTT_BASE 0x1000007FFA40B000ull +#define DCORE2_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_TPC2_QM_ARC_RTT_SECTION 0x35000 + +#define mmDCORE2_TPC2_EML_CFG_BASE 0x1000007FFA440000ull +#define DCORE2_TPC2_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_CFG_SECTION 0xE800 + +#define mmDCORE2_TPC2_EML_CFG_SPECIAL_BASE 0x1000007FFA440E80ull +#define DCORE2_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFA441000ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC2_EML_TPC_CFG_BASE 0x1000007FFA441000ull +#define DCORE2_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_TPC_CFG_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFA441050ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFA4410A0ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFA4410F0ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFA441140ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFA441190ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFA4411E0ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFA441230ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFA441280ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFA4412D0ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFA441320ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFA441370ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFA4413C0ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFA441410ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFA441460ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFA4414B0ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFA441500ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_BASE 0x1000007FFA441508ull +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1000007FFA4415DCull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1000007FFA44162Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1000007FFA44167Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1000007FFA4416CCull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1000007FFA44171Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1000007FFA44176Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1000007FFA4417BCull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1000007FFA44180Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1000007FFA44185Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1000007FFA4418ACull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1000007FFA4418FCull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1000007FFA44194Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1000007FFA44199Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1000007FFA4419ECull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1000007FFA441A3Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1000007FFA441A8Cull +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFA441ADCull +#define DCORE2_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_QM_BASE 0x1000007FFA441AE4ull +#define DCORE2_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0 + +#define mmDCORE2_TPC2_EML_TPC_CFG_AXUSER_BASE 0x1000007FFA441E00ull +#define DCORE2_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE2_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x1000007FFA441E80ull +#define DCORE2_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC2_EML_QM_DCCM_BASE 0x1000007FFA442000ull +#define DCORE2_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC2_EML_QM_DCCM_SECTION 0x8000 + +#define mmDCORE2_TPC2_EML_QM_ARCAUX_BASE 0x1000007FFA44A000ull +#define DCORE2_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_QM_ARCAUX_SECTION 0xE800 + +#define mmDCORE2_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x1000007FFA44AE80ull +#define DCORE2_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE2_TPC2_EML_TPC_QM_BASE 0x1000007FFA44C000ull +#define DCORE2_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_TPC_QM_SECTION 0x9000 + +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFA44C900ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFA44C908ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFA44C910ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFA44C918ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFA44C920ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFA44C928ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFA44C930ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFA44C938ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFA44C940ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFA44C948ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE \ +0x1000007FFA44C950ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE \ +0x1000007FFA44C958ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE \ +0x1000007FFA44C960ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE \ +0x1000007FFA44C968ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE \ +0x1000007FFA44C970ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE \ +0x1000007FFA44C978ull +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE2_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x1000007FFA44CB00ull +#define DCORE2_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE2_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1000007FFA44CB80ull +#define DCORE2_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE2_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x1000007FFA44CC00ull +#define DCORE2_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x1000007FFA44CC80ull +#define DCORE2_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE2_TPC2_EML_TPC_QM_CGM_BASE 0x1000007FFA44CD80ull +#define DCORE2_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC2_EML_TPC_QM_CGM_SECTION 0x1000 + +#define mmDCORE2_TPC2_EML_TPC_QM_SPECIAL_BASE 0x1000007FFA44CE80ull +#define DCORE2_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 + +#define mmDCORE2_TPC2_EML_CS_BASE 0x1000007FFA5FF000ull +#define DCORE2_TPC2_EML_CS_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_EML_CS_SECTION 0x1000 + +#define mmDCORE2_TPC3_ROM_TABLE_BASE 0x1000007FFA600000ull +#define DCORE2_TPC3_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_ROM_TABLE_SECTION 0x1000 + +#define mmDCORE2_TPC3_EML_SPMU_BASE 0x1000007FFA601000ull +#define DCORE2_TPC3_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_SPMU_SECTION 0x1000 + +#define mmDCORE2_TPC3_EML_ETF_BASE 0x1000007FFA602000ull +#define DCORE2_TPC3_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_ETF_SECTION 0x1000 + +#define mmDCORE2_TPC3_EML_STM_BASE 0x1000007FFA603000ull +#define DCORE2_TPC3_EML_STM_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_STM_SECTION 0x2000 + +#define mmDCORE2_TPC3_EML_CTI_BASE 0x1000007FFA605000ull +#define DCORE2_TPC3_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_CTI_SECTION 0x1000 + +#define mmDCORE2_TPC3_EML_FUNNEL_BASE 0x1000007FFA606000ull +#define DCORE2_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_FUNNEL_SECTION 0x1000 + +#define mmDCORE2_TPC3_EML_BUSMON_0_BASE 0x1000007FFA607000ull +#define DCORE2_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_BUSMON_0_SECTION 0x1000 + +#define mmDCORE2_TPC3_EML_BUSMON_1_BASE 0x1000007FFA608000ull +#define DCORE2_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_BUSMON_1_SECTION 0x1000 + +#define mmDCORE2_TPC3_EML_BUSMON_2_BASE 0x1000007FFA609000ull +#define DCORE2_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_BUSMON_2_SECTION 0x1000 + +#define mmDCORE2_TPC3_EML_BUSMON_3_BASE 0x1000007FFA60A000ull +#define DCORE2_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_BUSMON_3_SECTION 0x1000 + +#define mmDCORE2_TPC3_QM_ARC_RTT_BASE 0x1000007FFA60B000ull +#define DCORE2_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_TPC3_QM_ARC_RTT_SECTION 0x35000 + +#define mmDCORE2_TPC3_EML_CFG_BASE 0x1000007FFA640000ull +#define DCORE2_TPC3_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_CFG_SECTION 0xE800 + +#define mmDCORE2_TPC3_EML_CFG_SPECIAL_BASE 0x1000007FFA640E80ull +#define DCORE2_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFA641000ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC3_EML_TPC_CFG_BASE 0x1000007FFA641000ull +#define DCORE2_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_TPC_CFG_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFA641050ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFA6410A0ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFA6410F0ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFA641140ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFA641190ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFA6411E0ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFA641230ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFA641280ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFA6412D0ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFA641320ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFA641370ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFA6413C0ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFA641410ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFA641460ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFA6414B0ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFA641500ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_BASE 0x1000007FFA641508ull +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1000007FFA6415DCull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1000007FFA64162Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1000007FFA64167Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1000007FFA6416CCull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1000007FFA64171Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1000007FFA64176Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1000007FFA6417BCull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1000007FFA64180Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1000007FFA64185Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1000007FFA6418ACull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1000007FFA6418FCull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1000007FFA64194Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1000007FFA64199Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1000007FFA6419ECull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1000007FFA641A3Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1000007FFA641A8Cull +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFA641ADCull +#define DCORE2_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_QM_BASE 0x1000007FFA641AE4ull +#define DCORE2_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0 + +#define mmDCORE2_TPC3_EML_TPC_CFG_AXUSER_BASE 0x1000007FFA641E00ull +#define DCORE2_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE2_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x1000007FFA641E80ull +#define DCORE2_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC3_EML_QM_DCCM_BASE 0x1000007FFA642000ull +#define DCORE2_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC3_EML_QM_DCCM_SECTION 0x8000 + +#define mmDCORE2_TPC3_EML_QM_ARCAUX_BASE 0x1000007FFA64A000ull +#define DCORE2_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_QM_ARCAUX_SECTION 0xE800 + +#define mmDCORE2_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x1000007FFA64AE80ull +#define DCORE2_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE2_TPC3_EML_TPC_QM_BASE 0x1000007FFA64C000ull +#define DCORE2_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_TPC_QM_SECTION 0x9000 + +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFA64C900ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFA64C908ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFA64C910ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFA64C918ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFA64C920ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFA64C928ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFA64C930ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFA64C938ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFA64C940ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFA64C948ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE \ +0x1000007FFA64C950ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE \ +0x1000007FFA64C958ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE \ +0x1000007FFA64C960ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE \ +0x1000007FFA64C968ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE \ +0x1000007FFA64C970ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE \ +0x1000007FFA64C978ull +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE2_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x1000007FFA64CB00ull +#define DCORE2_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE2_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1000007FFA64CB80ull +#define DCORE2_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE2_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x1000007FFA64CC00ull +#define DCORE2_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x1000007FFA64CC80ull +#define DCORE2_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE2_TPC3_EML_TPC_QM_CGM_BASE 0x1000007FFA64CD80ull +#define DCORE2_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC3_EML_TPC_QM_CGM_SECTION 0x1000 + +#define mmDCORE2_TPC3_EML_TPC_QM_SPECIAL_BASE 0x1000007FFA64CE80ull +#define DCORE2_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 + +#define mmDCORE2_TPC3_EML_CS_BASE 0x1000007FFA7FF000ull +#define DCORE2_TPC3_EML_CS_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_EML_CS_SECTION 0x1000 + +#define mmDCORE2_TPC4_ROM_TABLE_BASE 0x1000007FFA800000ull +#define DCORE2_TPC4_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_ROM_TABLE_SECTION 0x1000 + +#define mmDCORE2_TPC4_EML_SPMU_BASE 0x1000007FFA801000ull +#define DCORE2_TPC4_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_SPMU_SECTION 0x1000 + +#define mmDCORE2_TPC4_EML_ETF_BASE 0x1000007FFA802000ull +#define DCORE2_TPC4_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_ETF_SECTION 0x1000 + +#define mmDCORE2_TPC4_EML_STM_BASE 0x1000007FFA803000ull +#define DCORE2_TPC4_EML_STM_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_STM_SECTION 0x2000 + +#define mmDCORE2_TPC4_EML_CTI_BASE 0x1000007FFA805000ull +#define DCORE2_TPC4_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_CTI_SECTION 0x1000 + +#define mmDCORE2_TPC4_EML_FUNNEL_BASE 0x1000007FFA806000ull +#define DCORE2_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_FUNNEL_SECTION 0x1000 + +#define mmDCORE2_TPC4_EML_BUSMON_0_BASE 0x1000007FFA807000ull +#define DCORE2_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_BUSMON_0_SECTION 0x1000 + +#define mmDCORE2_TPC4_EML_BUSMON_1_BASE 0x1000007FFA808000ull +#define DCORE2_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_BUSMON_1_SECTION 0x1000 + +#define mmDCORE2_TPC4_EML_BUSMON_2_BASE 0x1000007FFA809000ull +#define DCORE2_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_BUSMON_2_SECTION 0x1000 + +#define mmDCORE2_TPC4_EML_BUSMON_3_BASE 0x1000007FFA80A000ull +#define DCORE2_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_BUSMON_3_SECTION 0x1000 + +#define mmDCORE2_TPC4_QM_ARC_RTT_BASE 0x1000007FFA80B000ull +#define DCORE2_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_TPC4_QM_ARC_RTT_SECTION 0x35000 + +#define mmDCORE2_TPC4_EML_CFG_BASE 0x1000007FFA840000ull +#define DCORE2_TPC4_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_CFG_SECTION 0xE800 + +#define mmDCORE2_TPC4_EML_CFG_SPECIAL_BASE 0x1000007FFA840E80ull +#define DCORE2_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFA841000ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC4_EML_TPC_CFG_BASE 0x1000007FFA841000ull +#define DCORE2_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_TPC_CFG_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFA841050ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFA8410A0ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFA8410F0ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFA841140ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFA841190ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFA8411E0ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFA841230ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFA841280ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFA8412D0ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFA841320ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFA841370ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFA8413C0ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFA841410ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFA841460ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFA8414B0ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFA841500ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_BASE 0x1000007FFA841508ull +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1000007FFA8415DCull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1000007FFA84162Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1000007FFA84167Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1000007FFA8416CCull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1000007FFA84171Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1000007FFA84176Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1000007FFA8417BCull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1000007FFA84180Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1000007FFA84185Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1000007FFA8418ACull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1000007FFA8418FCull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1000007FFA84194Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1000007FFA84199Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1000007FFA8419ECull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1000007FFA841A3Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1000007FFA841A8Cull +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFA841ADCull +#define DCORE2_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_QM_BASE 0x1000007FFA841AE4ull +#define DCORE2_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0 + +#define mmDCORE2_TPC4_EML_TPC_CFG_AXUSER_BASE 0x1000007FFA841E00ull +#define DCORE2_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE2_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x1000007FFA841E80ull +#define DCORE2_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC4_EML_QM_DCCM_BASE 0x1000007FFA842000ull +#define DCORE2_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC4_EML_QM_DCCM_SECTION 0x8000 + +#define mmDCORE2_TPC4_EML_QM_ARCAUX_BASE 0x1000007FFA84A000ull +#define DCORE2_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_QM_ARCAUX_SECTION 0xE800 + +#define mmDCORE2_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x1000007FFA84AE80ull +#define DCORE2_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE2_TPC4_EML_TPC_QM_BASE 0x1000007FFA84C000ull +#define DCORE2_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_TPC_QM_SECTION 0x9000 + +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFA84C900ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFA84C908ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFA84C910ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFA84C918ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFA84C920ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFA84C928ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFA84C930ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFA84C938ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFA84C940ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFA84C948ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE \ +0x1000007FFA84C950ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE \ +0x1000007FFA84C958ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE \ +0x1000007FFA84C960ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE \ +0x1000007FFA84C968ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE \ +0x1000007FFA84C970ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE \ +0x1000007FFA84C978ull +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE2_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x1000007FFA84CB00ull +#define DCORE2_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE2_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1000007FFA84CB80ull +#define DCORE2_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE2_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x1000007FFA84CC00ull +#define DCORE2_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x1000007FFA84CC80ull +#define DCORE2_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE2_TPC4_EML_TPC_QM_CGM_BASE 0x1000007FFA84CD80ull +#define DCORE2_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC4_EML_TPC_QM_CGM_SECTION 0x1000 + +#define mmDCORE2_TPC4_EML_TPC_QM_SPECIAL_BASE 0x1000007FFA84CE80ull +#define DCORE2_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 + +#define mmDCORE2_TPC4_EML_CS_BASE 0x1000007FFA9FF000ull +#define DCORE2_TPC4_EML_CS_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_EML_CS_SECTION 0x1000 + +#define mmDCORE2_TPC5_ROM_TABLE_BASE 0x1000007FFAA00000ull +#define DCORE2_TPC5_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_ROM_TABLE_SECTION 0x1000 + +#define mmDCORE2_TPC5_EML_SPMU_BASE 0x1000007FFAA01000ull +#define DCORE2_TPC5_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_SPMU_SECTION 0x1000 + +#define mmDCORE2_TPC5_EML_ETF_BASE 0x1000007FFAA02000ull +#define DCORE2_TPC5_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_ETF_SECTION 0x1000 + +#define mmDCORE2_TPC5_EML_STM_BASE 0x1000007FFAA03000ull +#define DCORE2_TPC5_EML_STM_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_STM_SECTION 0x2000 + +#define mmDCORE2_TPC5_EML_CTI_BASE 0x1000007FFAA05000ull +#define DCORE2_TPC5_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_CTI_SECTION 0x1000 + +#define mmDCORE2_TPC5_EML_FUNNEL_BASE 0x1000007FFAA06000ull +#define DCORE2_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_FUNNEL_SECTION 0x1000 + +#define mmDCORE2_TPC5_EML_BUSMON_0_BASE 0x1000007FFAA07000ull +#define DCORE2_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_BUSMON_0_SECTION 0x1000 + +#define mmDCORE2_TPC5_EML_BUSMON_1_BASE 0x1000007FFAA08000ull +#define DCORE2_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_BUSMON_1_SECTION 0x1000 + +#define mmDCORE2_TPC5_EML_BUSMON_2_BASE 0x1000007FFAA09000ull +#define DCORE2_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_BUSMON_2_SECTION 0x1000 + +#define mmDCORE2_TPC5_EML_BUSMON_3_BASE 0x1000007FFAA0A000ull +#define DCORE2_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_BUSMON_3_SECTION 0x1000 + +#define mmDCORE2_TPC5_QM_ARC_RTT_BASE 0x1000007FFAA0B000ull +#define DCORE2_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_TPC5_QM_ARC_RTT_SECTION 0x35000 + +#define mmDCORE2_TPC5_EML_CFG_BASE 0x1000007FFAA40000ull +#define DCORE2_TPC5_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_CFG_SECTION 0xE800 + +#define mmDCORE2_TPC5_EML_CFG_SPECIAL_BASE 0x1000007FFAA40E80ull +#define DCORE2_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFAA41000ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC5_EML_TPC_CFG_BASE 0x1000007FFAA41000ull +#define DCORE2_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_TPC_CFG_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFAA41050ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFAA410A0ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFAA410F0ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFAA41140ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFAA41190ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFAA411E0ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFAA41230ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFAA41280ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFAA412D0ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFAA41320ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFAA41370ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFAA413C0ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFAA41410ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFAA41460ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFAA414B0ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFAA41500ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_BASE 0x1000007FFAA41508ull +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1000007FFAA415DCull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1000007FFAA4162Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1000007FFAA4167Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1000007FFAA416CCull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1000007FFAA4171Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1000007FFAA4176Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1000007FFAA417BCull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1000007FFAA4180Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1000007FFAA4185Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1000007FFAA418ACull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1000007FFAA418FCull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1000007FFAA4194Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1000007FFAA4199Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1000007FFAA419ECull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1000007FFAA41A3Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1000007FFAA41A8Cull +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFAA41ADCull +#define DCORE2_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_QM_BASE 0x1000007FFAA41AE4ull +#define DCORE2_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0 + +#define mmDCORE2_TPC5_EML_TPC_CFG_AXUSER_BASE 0x1000007FFAA41E00ull +#define DCORE2_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE2_TPC5_EML_TPC_CFG_SPECIAL_BASE 0x1000007FFAA41E80ull +#define DCORE2_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC5_EML_QM_DCCM_BASE 0x1000007FFAA42000ull +#define DCORE2_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC5_EML_QM_DCCM_SECTION 0x8000 + +#define mmDCORE2_TPC5_EML_QM_ARCAUX_BASE 0x1000007FFAA4A000ull +#define DCORE2_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_QM_ARCAUX_SECTION 0xE800 + +#define mmDCORE2_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0x1000007FFAA4AE80ull +#define DCORE2_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE2_TPC5_EML_TPC_QM_BASE 0x1000007FFAA4C000ull +#define DCORE2_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_TPC_QM_SECTION 0x9000 + +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFAA4C900ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFAA4C908ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFAA4C910ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFAA4C918ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFAA4C920ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFAA4C928ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFAA4C930ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFAA4C938ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFAA4C940ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFAA4C948ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE \ +0x1000007FFAA4C950ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE \ +0x1000007FFAA4C958ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE \ +0x1000007FFAA4C960ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE \ +0x1000007FFAA4C968ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE \ +0x1000007FFAA4C970ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE \ +0x1000007FFAA4C978ull +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE2_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0x1000007FFAA4CB00ull +#define DCORE2_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE2_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1000007FFAA4CB80ull +#define DCORE2_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE2_TPC5_EML_TPC_QM_DBG_HBW_BASE 0x1000007FFAA4CC00ull +#define DCORE2_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_TPC5_EML_TPC_QM_DBG_LBW_BASE 0x1000007FFAA4CC80ull +#define DCORE2_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE2_TPC5_EML_TPC_QM_CGM_BASE 0x1000007FFAA4CD80ull +#define DCORE2_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC5_EML_TPC_QM_CGM_SECTION 0x1000 + +#define mmDCORE2_TPC5_EML_TPC_QM_SPECIAL_BASE 0x1000007FFAA4CE80ull +#define DCORE2_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 + +#define mmDCORE2_TPC5_EML_CS_BASE 0x1000007FFABFF000ull +#define DCORE2_TPC5_EML_CS_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_EML_CS_SECTION 0x401000 + +#define mmDCORE3_TPC0_ROM_TABLE_BASE 0x1000007FFB000000ull +#define DCORE3_TPC0_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_ROM_TABLE_SECTION 0x1000 + +#define mmDCORE3_TPC0_EML_SPMU_BASE 0x1000007FFB001000ull +#define DCORE3_TPC0_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_SPMU_SECTION 0x1000 + +#define mmDCORE3_TPC0_EML_ETF_BASE 0x1000007FFB002000ull +#define DCORE3_TPC0_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_ETF_SECTION 0x1000 + +#define mmDCORE3_TPC0_EML_STM_BASE 0x1000007FFB003000ull +#define DCORE3_TPC0_EML_STM_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_STM_SECTION 0x2000 + +#define mmDCORE3_TPC0_EML_CTI_BASE 0x1000007FFB005000ull +#define DCORE3_TPC0_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_CTI_SECTION 0x1000 + +#define mmDCORE3_TPC0_EML_FUNNEL_BASE 0x1000007FFB006000ull +#define DCORE3_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_FUNNEL_SECTION 0x1000 + +#define mmDCORE3_TPC0_EML_BUSMON_0_BASE 0x1000007FFB007000ull +#define DCORE3_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_BUSMON_0_SECTION 0x1000 + +#define mmDCORE3_TPC0_EML_BUSMON_1_BASE 0x1000007FFB008000ull +#define DCORE3_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_BUSMON_1_SECTION 0x1000 + +#define mmDCORE3_TPC0_EML_BUSMON_2_BASE 0x1000007FFB009000ull +#define DCORE3_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_BUSMON_2_SECTION 0x1000 + +#define mmDCORE3_TPC0_EML_BUSMON_3_BASE 0x1000007FFB00A000ull +#define DCORE3_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_BUSMON_3_SECTION 0x1000 + +#define mmDCORE3_TPC0_QM_ARC_RTT_BASE 0x1000007FFB00B000ull +#define DCORE3_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_TPC0_QM_ARC_RTT_SECTION 0x35000 + +#define mmDCORE3_TPC0_EML_CFG_BASE 0x1000007FFB040000ull +#define DCORE3_TPC0_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_CFG_SECTION 0xE800 + +#define mmDCORE3_TPC0_EML_CFG_SPECIAL_BASE 0x1000007FFB040E80ull +#define DCORE3_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFB041000ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC0_EML_TPC_CFG_BASE 0x1000007FFB041000ull +#define DCORE3_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_TPC_CFG_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFB041050ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFB0410A0ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFB0410F0ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFB041140ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFB041190ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFB0411E0ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFB041230ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFB041280ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFB0412D0ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFB041320ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFB041370ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFB0413C0ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFB041410ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFB041460ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFB0414B0ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFB041500ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_BASE 0x1000007FFB041508ull +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1000007FFB0415DCull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1000007FFB04162Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1000007FFB04167Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1000007FFB0416CCull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1000007FFB04171Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1000007FFB04176Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1000007FFB0417BCull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1000007FFB04180Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1000007FFB04185Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1000007FFB0418ACull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1000007FFB0418FCull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1000007FFB04194Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1000007FFB04199Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1000007FFB0419ECull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1000007FFB041A3Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1000007FFB041A8Cull +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFB041ADCull +#define DCORE3_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_QM_BASE 0x1000007FFB041AE4ull +#define DCORE3_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0 + +#define mmDCORE3_TPC0_EML_TPC_CFG_AXUSER_BASE 0x1000007FFB041E00ull +#define DCORE3_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE3_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x1000007FFB041E80ull +#define DCORE3_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC0_EML_QM_DCCM_BASE 0x1000007FFB042000ull +#define DCORE3_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC0_EML_QM_DCCM_SECTION 0x8000 + +#define mmDCORE3_TPC0_EML_QM_ARCAUX_BASE 0x1000007FFB04A000ull +#define DCORE3_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_QM_ARCAUX_SECTION 0xE800 + +#define mmDCORE3_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x1000007FFB04AE80ull +#define DCORE3_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE3_TPC0_EML_TPC_QM_BASE 0x1000007FFB04C000ull +#define DCORE3_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_TPC_QM_SECTION 0x9000 + +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFB04C900ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFB04C908ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFB04C910ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFB04C918ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFB04C920ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFB04C928ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFB04C930ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFB04C938ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFB04C940ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFB04C948ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE \ +0x1000007FFB04C950ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE \ +0x1000007FFB04C958ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE \ +0x1000007FFB04C960ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE \ +0x1000007FFB04C968ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE \ +0x1000007FFB04C970ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE \ +0x1000007FFB04C978ull +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE3_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x1000007FFB04CB00ull +#define DCORE3_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE3_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1000007FFB04CB80ull +#define DCORE3_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE3_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x1000007FFB04CC00ull +#define DCORE3_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x1000007FFB04CC80ull +#define DCORE3_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE3_TPC0_EML_TPC_QM_CGM_BASE 0x1000007FFB04CD80ull +#define DCORE3_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC0_EML_TPC_QM_CGM_SECTION 0x1000 + +#define mmDCORE3_TPC0_EML_TPC_QM_SPECIAL_BASE 0x1000007FFB04CE80ull +#define DCORE3_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 + +#define mmDCORE3_TPC0_EML_CS_BASE 0x1000007FFB1FF000ull +#define DCORE3_TPC0_EML_CS_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_EML_CS_SECTION 0x1000 + +#define mmDCORE3_TPC1_ROM_TABLE_BASE 0x1000007FFB200000ull +#define DCORE3_TPC1_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_ROM_TABLE_SECTION 0x1000 + +#define mmDCORE3_TPC1_EML_SPMU_BASE 0x1000007FFB201000ull +#define DCORE3_TPC1_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_SPMU_SECTION 0x1000 + +#define mmDCORE3_TPC1_EML_ETF_BASE 0x1000007FFB202000ull +#define DCORE3_TPC1_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_ETF_SECTION 0x1000 + +#define mmDCORE3_TPC1_EML_STM_BASE 0x1000007FFB203000ull +#define DCORE3_TPC1_EML_STM_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_STM_SECTION 0x2000 + +#define mmDCORE3_TPC1_EML_CTI_BASE 0x1000007FFB205000ull +#define DCORE3_TPC1_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_CTI_SECTION 0x1000 + +#define mmDCORE3_TPC1_EML_FUNNEL_BASE 0x1000007FFB206000ull +#define DCORE3_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_FUNNEL_SECTION 0x1000 + +#define mmDCORE3_TPC1_EML_BUSMON_0_BASE 0x1000007FFB207000ull +#define DCORE3_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_BUSMON_0_SECTION 0x1000 + +#define mmDCORE3_TPC1_EML_BUSMON_1_BASE 0x1000007FFB208000ull +#define DCORE3_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_BUSMON_1_SECTION 0x1000 + +#define mmDCORE3_TPC1_EML_BUSMON_2_BASE 0x1000007FFB209000ull +#define DCORE3_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_BUSMON_2_SECTION 0x1000 + +#define mmDCORE3_TPC1_EML_BUSMON_3_BASE 0x1000007FFB20A000ull +#define DCORE3_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_BUSMON_3_SECTION 0x1000 + +#define mmDCORE3_TPC1_QM_ARC_RTT_BASE 0x1000007FFB20B000ull +#define DCORE3_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_TPC1_QM_ARC_RTT_SECTION 0x35000 + +#define mmDCORE3_TPC1_EML_CFG_BASE 0x1000007FFB240000ull +#define DCORE3_TPC1_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_CFG_SECTION 0xE800 + +#define mmDCORE3_TPC1_EML_CFG_SPECIAL_BASE 0x1000007FFB240E80ull +#define DCORE3_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFB241000ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC1_EML_TPC_CFG_BASE 0x1000007FFB241000ull +#define DCORE3_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_TPC_CFG_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFB241050ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFB2410A0ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFB2410F0ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFB241140ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFB241190ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFB2411E0ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFB241230ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFB241280ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFB2412D0ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFB241320ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFB241370ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFB2413C0ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFB241410ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFB241460ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFB2414B0ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFB241500ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_BASE 0x1000007FFB241508ull +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1000007FFB2415DCull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1000007FFB24162Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1000007FFB24167Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1000007FFB2416CCull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1000007FFB24171Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1000007FFB24176Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1000007FFB2417BCull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1000007FFB24180Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1000007FFB24185Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1000007FFB2418ACull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1000007FFB2418FCull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1000007FFB24194Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1000007FFB24199Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1000007FFB2419ECull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1000007FFB241A3Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1000007FFB241A8Cull +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFB241ADCull +#define DCORE3_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_QM_BASE 0x1000007FFB241AE4ull +#define DCORE3_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0 + +#define mmDCORE3_TPC1_EML_TPC_CFG_AXUSER_BASE 0x1000007FFB241E00ull +#define DCORE3_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE3_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x1000007FFB241E80ull +#define DCORE3_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC1_EML_QM_DCCM_BASE 0x1000007FFB242000ull +#define DCORE3_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC1_EML_QM_DCCM_SECTION 0x8000 + +#define mmDCORE3_TPC1_EML_QM_ARCAUX_BASE 0x1000007FFB24A000ull +#define DCORE3_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_QM_ARCAUX_SECTION 0xE800 + +#define mmDCORE3_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x1000007FFB24AE80ull +#define DCORE3_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE3_TPC1_EML_TPC_QM_BASE 0x1000007FFB24C000ull +#define DCORE3_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_TPC_QM_SECTION 0x9000 + +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFB24C900ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFB24C908ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFB24C910ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFB24C918ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFB24C920ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFB24C928ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFB24C930ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFB24C938ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFB24C940ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFB24C948ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE \ +0x1000007FFB24C950ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE \ +0x1000007FFB24C958ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE \ +0x1000007FFB24C960ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE \ +0x1000007FFB24C968ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE \ +0x1000007FFB24C970ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE \ +0x1000007FFB24C978ull +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE3_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x1000007FFB24CB00ull +#define DCORE3_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE3_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1000007FFB24CB80ull +#define DCORE3_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE3_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x1000007FFB24CC00ull +#define DCORE3_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x1000007FFB24CC80ull +#define DCORE3_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE3_TPC1_EML_TPC_QM_CGM_BASE 0x1000007FFB24CD80ull +#define DCORE3_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC1_EML_TPC_QM_CGM_SECTION 0x1000 + +#define mmDCORE3_TPC1_EML_TPC_QM_SPECIAL_BASE 0x1000007FFB24CE80ull +#define DCORE3_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 + +#define mmDCORE3_TPC1_EML_CS_BASE 0x1000007FFB3FF000ull +#define DCORE3_TPC1_EML_CS_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_EML_CS_SECTION 0x1000 + +#define mmDCORE3_TPC2_ROM_TABLE_BASE 0x1000007FFB400000ull +#define DCORE3_TPC2_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_ROM_TABLE_SECTION 0x1000 + +#define mmDCORE3_TPC2_EML_SPMU_BASE 0x1000007FFB401000ull +#define DCORE3_TPC2_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_SPMU_SECTION 0x1000 + +#define mmDCORE3_TPC2_EML_ETF_BASE 0x1000007FFB402000ull +#define DCORE3_TPC2_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_ETF_SECTION 0x1000 + +#define mmDCORE3_TPC2_EML_STM_BASE 0x1000007FFB403000ull +#define DCORE3_TPC2_EML_STM_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_STM_SECTION 0x2000 + +#define mmDCORE3_TPC2_EML_CTI_BASE 0x1000007FFB405000ull +#define DCORE3_TPC2_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_CTI_SECTION 0x1000 + +#define mmDCORE3_TPC2_EML_FUNNEL_BASE 0x1000007FFB406000ull +#define DCORE3_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_FUNNEL_SECTION 0x1000 + +#define mmDCORE3_TPC2_EML_BUSMON_0_BASE 0x1000007FFB407000ull +#define DCORE3_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_BUSMON_0_SECTION 0x1000 + +#define mmDCORE3_TPC2_EML_BUSMON_1_BASE 0x1000007FFB408000ull +#define DCORE3_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_BUSMON_1_SECTION 0x1000 + +#define mmDCORE3_TPC2_EML_BUSMON_2_BASE 0x1000007FFB409000ull +#define DCORE3_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_BUSMON_2_SECTION 0x1000 + +#define mmDCORE3_TPC2_EML_BUSMON_3_BASE 0x1000007FFB40A000ull +#define DCORE3_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_BUSMON_3_SECTION 0x1000 + +#define mmDCORE3_TPC2_QM_ARC_RTT_BASE 0x1000007FFB40B000ull +#define DCORE3_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_TPC2_QM_ARC_RTT_SECTION 0x35000 + +#define mmDCORE3_TPC2_EML_CFG_BASE 0x1000007FFB440000ull +#define DCORE3_TPC2_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_CFG_SECTION 0xE800 + +#define mmDCORE3_TPC2_EML_CFG_SPECIAL_BASE 0x1000007FFB440E80ull +#define DCORE3_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFB441000ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC2_EML_TPC_CFG_BASE 0x1000007FFB441000ull +#define DCORE3_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_TPC_CFG_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFB441050ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFB4410A0ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFB4410F0ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFB441140ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFB441190ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFB4411E0ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFB441230ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFB441280ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFB4412D0ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFB441320ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFB441370ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFB4413C0ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFB441410ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFB441460ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFB4414B0ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFB441500ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_BASE 0x1000007FFB441508ull +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1000007FFB4415DCull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1000007FFB44162Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1000007FFB44167Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1000007FFB4416CCull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1000007FFB44171Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1000007FFB44176Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1000007FFB4417BCull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1000007FFB44180Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1000007FFB44185Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1000007FFB4418ACull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1000007FFB4418FCull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1000007FFB44194Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1000007FFB44199Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1000007FFB4419ECull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1000007FFB441A3Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1000007FFB441A8Cull +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFB441ADCull +#define DCORE3_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_QM_BASE 0x1000007FFB441AE4ull +#define DCORE3_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0 + +#define mmDCORE3_TPC2_EML_TPC_CFG_AXUSER_BASE 0x1000007FFB441E00ull +#define DCORE3_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE3_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x1000007FFB441E80ull +#define DCORE3_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC2_EML_QM_DCCM_BASE 0x1000007FFB442000ull +#define DCORE3_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC2_EML_QM_DCCM_SECTION 0x8000 + +#define mmDCORE3_TPC2_EML_QM_ARCAUX_BASE 0x1000007FFB44A000ull +#define DCORE3_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_QM_ARCAUX_SECTION 0xE800 + +#define mmDCORE3_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x1000007FFB44AE80ull +#define DCORE3_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE3_TPC2_EML_TPC_QM_BASE 0x1000007FFB44C000ull +#define DCORE3_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_TPC_QM_SECTION 0x9000 + +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFB44C900ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFB44C908ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFB44C910ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFB44C918ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFB44C920ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFB44C928ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFB44C930ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFB44C938ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFB44C940ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFB44C948ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE \ +0x1000007FFB44C950ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE \ +0x1000007FFB44C958ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE \ +0x1000007FFB44C960ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE \ +0x1000007FFB44C968ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE \ +0x1000007FFB44C970ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE \ +0x1000007FFB44C978ull +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE3_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x1000007FFB44CB00ull +#define DCORE3_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE3_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1000007FFB44CB80ull +#define DCORE3_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE3_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x1000007FFB44CC00ull +#define DCORE3_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x1000007FFB44CC80ull +#define DCORE3_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE3_TPC2_EML_TPC_QM_CGM_BASE 0x1000007FFB44CD80ull +#define DCORE3_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC2_EML_TPC_QM_CGM_SECTION 0x1000 + +#define mmDCORE3_TPC2_EML_TPC_QM_SPECIAL_BASE 0x1000007FFB44CE80ull +#define DCORE3_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 + +#define mmDCORE3_TPC2_EML_CS_BASE 0x1000007FFB5FF000ull +#define DCORE3_TPC2_EML_CS_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_EML_CS_SECTION 0x1000 + +#define mmDCORE3_TPC3_ROM_TABLE_BASE 0x1000007FFB600000ull +#define DCORE3_TPC3_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_ROM_TABLE_SECTION 0x1000 + +#define mmDCORE3_TPC3_EML_SPMU_BASE 0x1000007FFB601000ull +#define DCORE3_TPC3_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_SPMU_SECTION 0x1000 + +#define mmDCORE3_TPC3_EML_ETF_BASE 0x1000007FFB602000ull +#define DCORE3_TPC3_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_ETF_SECTION 0x1000 + +#define mmDCORE3_TPC3_EML_STM_BASE 0x1000007FFB603000ull +#define DCORE3_TPC3_EML_STM_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_STM_SECTION 0x2000 + +#define mmDCORE3_TPC3_EML_CTI_BASE 0x1000007FFB605000ull +#define DCORE3_TPC3_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_CTI_SECTION 0x1000 + +#define mmDCORE3_TPC3_EML_FUNNEL_BASE 0x1000007FFB606000ull +#define DCORE3_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_FUNNEL_SECTION 0x1000 + +#define mmDCORE3_TPC3_EML_BUSMON_0_BASE 0x1000007FFB607000ull +#define DCORE3_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_BUSMON_0_SECTION 0x1000 + +#define mmDCORE3_TPC3_EML_BUSMON_1_BASE 0x1000007FFB608000ull +#define DCORE3_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_BUSMON_1_SECTION 0x1000 + +#define mmDCORE3_TPC3_EML_BUSMON_2_BASE 0x1000007FFB609000ull +#define DCORE3_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_BUSMON_2_SECTION 0x1000 + +#define mmDCORE3_TPC3_EML_BUSMON_3_BASE 0x1000007FFB60A000ull +#define DCORE3_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_BUSMON_3_SECTION 0x1000 + +#define mmDCORE3_TPC3_QM_ARC_RTT_BASE 0x1000007FFB60B000ull +#define DCORE3_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_TPC3_QM_ARC_RTT_SECTION 0x35000 + +#define mmDCORE3_TPC3_EML_CFG_BASE 0x1000007FFB640000ull +#define DCORE3_TPC3_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_CFG_SECTION 0xE800 + +#define mmDCORE3_TPC3_EML_CFG_SPECIAL_BASE 0x1000007FFB640E80ull +#define DCORE3_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFB641000ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC3_EML_TPC_CFG_BASE 0x1000007FFB641000ull +#define DCORE3_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_TPC_CFG_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFB641050ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFB6410A0ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFB6410F0ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFB641140ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFB641190ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFB6411E0ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFB641230ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFB641280ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFB6412D0ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFB641320ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFB641370ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFB6413C0ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFB641410ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFB641460ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFB6414B0ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFB641500ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_BASE 0x1000007FFB641508ull +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1000007FFB6415DCull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1000007FFB64162Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1000007FFB64167Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1000007FFB6416CCull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1000007FFB64171Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1000007FFB64176Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1000007FFB6417BCull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1000007FFB64180Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1000007FFB64185Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1000007FFB6418ACull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1000007FFB6418FCull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1000007FFB64194Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1000007FFB64199Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1000007FFB6419ECull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1000007FFB641A3Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1000007FFB641A8Cull +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFB641ADCull +#define DCORE3_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_QM_BASE 0x1000007FFB641AE4ull +#define DCORE3_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0 + +#define mmDCORE3_TPC3_EML_TPC_CFG_AXUSER_BASE 0x1000007FFB641E00ull +#define DCORE3_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE3_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x1000007FFB641E80ull +#define DCORE3_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC3_EML_QM_DCCM_BASE 0x1000007FFB642000ull +#define DCORE3_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC3_EML_QM_DCCM_SECTION 0x8000 + +#define mmDCORE3_TPC3_EML_QM_ARCAUX_BASE 0x1000007FFB64A000ull +#define DCORE3_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_QM_ARCAUX_SECTION 0xE800 + +#define mmDCORE3_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x1000007FFB64AE80ull +#define DCORE3_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE3_TPC3_EML_TPC_QM_BASE 0x1000007FFB64C000ull +#define DCORE3_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_TPC_QM_SECTION 0x9000 + +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFB64C900ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFB64C908ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFB64C910ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFB64C918ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFB64C920ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFB64C928ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFB64C930ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFB64C938ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFB64C940ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFB64C948ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE \ +0x1000007FFB64C950ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE \ +0x1000007FFB64C958ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE \ +0x1000007FFB64C960ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE \ +0x1000007FFB64C968ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE \ +0x1000007FFB64C970ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE \ +0x1000007FFB64C978ull +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE3_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x1000007FFB64CB00ull +#define DCORE3_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE3_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1000007FFB64CB80ull +#define DCORE3_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE3_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x1000007FFB64CC00ull +#define DCORE3_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x1000007FFB64CC80ull +#define DCORE3_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE3_TPC3_EML_TPC_QM_CGM_BASE 0x1000007FFB64CD80ull +#define DCORE3_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC3_EML_TPC_QM_CGM_SECTION 0x1000 + +#define mmDCORE3_TPC3_EML_TPC_QM_SPECIAL_BASE 0x1000007FFB64CE80ull +#define DCORE3_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 + +#define mmDCORE3_TPC3_EML_CS_BASE 0x1000007FFB7FF000ull +#define DCORE3_TPC3_EML_CS_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_EML_CS_SECTION 0x1000 + +#define mmDCORE3_TPC4_ROM_TABLE_BASE 0x1000007FFB800000ull +#define DCORE3_TPC4_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_ROM_TABLE_SECTION 0x1000 + +#define mmDCORE3_TPC4_EML_SPMU_BASE 0x1000007FFB801000ull +#define DCORE3_TPC4_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_SPMU_SECTION 0x1000 + +#define mmDCORE3_TPC4_EML_ETF_BASE 0x1000007FFB802000ull +#define DCORE3_TPC4_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_ETF_SECTION 0x1000 + +#define mmDCORE3_TPC4_EML_STM_BASE 0x1000007FFB803000ull +#define DCORE3_TPC4_EML_STM_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_STM_SECTION 0x2000 + +#define mmDCORE3_TPC4_EML_CTI_BASE 0x1000007FFB805000ull +#define DCORE3_TPC4_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_CTI_SECTION 0x1000 + +#define mmDCORE3_TPC4_EML_FUNNEL_BASE 0x1000007FFB806000ull +#define DCORE3_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_FUNNEL_SECTION 0x1000 + +#define mmDCORE3_TPC4_EML_BUSMON_0_BASE 0x1000007FFB807000ull +#define DCORE3_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_BUSMON_0_SECTION 0x1000 + +#define mmDCORE3_TPC4_EML_BUSMON_1_BASE 0x1000007FFB808000ull +#define DCORE3_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_BUSMON_1_SECTION 0x1000 + +#define mmDCORE3_TPC4_EML_BUSMON_2_BASE 0x1000007FFB809000ull +#define DCORE3_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_BUSMON_2_SECTION 0x1000 + +#define mmDCORE3_TPC4_EML_BUSMON_3_BASE 0x1000007FFB80A000ull +#define DCORE3_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_BUSMON_3_SECTION 0x1000 + +#define mmDCORE3_TPC4_QM_ARC_RTT_BASE 0x1000007FFB80B000ull +#define DCORE3_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_TPC4_QM_ARC_RTT_SECTION 0x35000 + +#define mmDCORE3_TPC4_EML_CFG_BASE 0x1000007FFB840000ull +#define DCORE3_TPC4_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_CFG_SECTION 0xE800 + +#define mmDCORE3_TPC4_EML_CFG_SPECIAL_BASE 0x1000007FFB840E80ull +#define DCORE3_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFB841000ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC4_EML_TPC_CFG_BASE 0x1000007FFB841000ull +#define DCORE3_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_TPC_CFG_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFB841050ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFB8410A0ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFB8410F0ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFB841140ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFB841190ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFB8411E0ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFB841230ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFB841280ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFB8412D0ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFB841320ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFB841370ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFB8413C0ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFB841410ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFB841460ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFB8414B0ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFB841500ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_BASE 0x1000007FFB841508ull +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1000007FFB8415DCull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1000007FFB84162Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1000007FFB84167Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1000007FFB8416CCull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1000007FFB84171Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1000007FFB84176Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1000007FFB8417BCull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1000007FFB84180Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1000007FFB84185Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1000007FFB8418ACull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1000007FFB8418FCull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1000007FFB84194Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1000007FFB84199Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1000007FFB8419ECull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1000007FFB841A3Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1000007FFB841A8Cull +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFB841ADCull +#define DCORE3_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_QM_BASE 0x1000007FFB841AE4ull +#define DCORE3_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0 + +#define mmDCORE3_TPC4_EML_TPC_CFG_AXUSER_BASE 0x1000007FFB841E00ull +#define DCORE3_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE3_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x1000007FFB841E80ull +#define DCORE3_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC4_EML_QM_DCCM_BASE 0x1000007FFB842000ull +#define DCORE3_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC4_EML_QM_DCCM_SECTION 0x8000 + +#define mmDCORE3_TPC4_EML_QM_ARCAUX_BASE 0x1000007FFB84A000ull +#define DCORE3_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_QM_ARCAUX_SECTION 0xE800 + +#define mmDCORE3_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x1000007FFB84AE80ull +#define DCORE3_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE3_TPC4_EML_TPC_QM_BASE 0x1000007FFB84C000ull +#define DCORE3_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_TPC_QM_SECTION 0x9000 + +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFB84C900ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFB84C908ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFB84C910ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFB84C918ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFB84C920ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFB84C928ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFB84C930ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFB84C938ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFB84C940ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFB84C948ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE \ +0x1000007FFB84C950ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE \ +0x1000007FFB84C958ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE \ +0x1000007FFB84C960ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE \ +0x1000007FFB84C968ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE \ +0x1000007FFB84C970ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE \ +0x1000007FFB84C978ull +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE3_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x1000007FFB84CB00ull +#define DCORE3_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE3_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1000007FFB84CB80ull +#define DCORE3_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE3_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x1000007FFB84CC00ull +#define DCORE3_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x1000007FFB84CC80ull +#define DCORE3_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE3_TPC4_EML_TPC_QM_CGM_BASE 0x1000007FFB84CD80ull +#define DCORE3_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC4_EML_TPC_QM_CGM_SECTION 0x1000 + +#define mmDCORE3_TPC4_EML_TPC_QM_SPECIAL_BASE 0x1000007FFB84CE80ull +#define DCORE3_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 + +#define mmDCORE3_TPC4_EML_CS_BASE 0x1000007FFB9FF000ull +#define DCORE3_TPC4_EML_CS_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_EML_CS_SECTION 0x1000 + +#define mmDCORE3_TPC5_ROM_TABLE_BASE 0x1000007FFBA00000ull +#define DCORE3_TPC5_ROM_TABLE_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_ROM_TABLE_SECTION 0x1000 + +#define mmDCORE3_TPC5_EML_SPMU_BASE 0x1000007FFBA01000ull +#define DCORE3_TPC5_EML_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_SPMU_SECTION 0x1000 + +#define mmDCORE3_TPC5_EML_ETF_BASE 0x1000007FFBA02000ull +#define DCORE3_TPC5_EML_ETF_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_ETF_SECTION 0x1000 + +#define mmDCORE3_TPC5_EML_STM_BASE 0x1000007FFBA03000ull +#define DCORE3_TPC5_EML_STM_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_STM_SECTION 0x2000 + +#define mmDCORE3_TPC5_EML_CTI_BASE 0x1000007FFBA05000ull +#define DCORE3_TPC5_EML_CTI_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_CTI_SECTION 0x1000 + +#define mmDCORE3_TPC5_EML_FUNNEL_BASE 0x1000007FFBA06000ull +#define DCORE3_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_FUNNEL_SECTION 0x1000 + +#define mmDCORE3_TPC5_EML_BUSMON_0_BASE 0x1000007FFBA07000ull +#define DCORE3_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_BUSMON_0_SECTION 0x1000 + +#define mmDCORE3_TPC5_EML_BUSMON_1_BASE 0x1000007FFBA08000ull +#define DCORE3_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_BUSMON_1_SECTION 0x1000 + +#define mmDCORE3_TPC5_EML_BUSMON_2_BASE 0x1000007FFBA09000ull +#define DCORE3_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_BUSMON_2_SECTION 0x1000 + +#define mmDCORE3_TPC5_EML_BUSMON_3_BASE 0x1000007FFBA0A000ull +#define DCORE3_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_BUSMON_3_SECTION 0x1000 + +#define mmDCORE3_TPC5_QM_ARC_RTT_BASE 0x1000007FFBA0B000ull +#define DCORE3_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_TPC5_QM_ARC_RTT_SECTION 0x35000 + +#define mmDCORE3_TPC5_EML_CFG_BASE 0x1000007FFBA40000ull +#define DCORE3_TPC5_EML_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_CFG_SECTION 0xE800 + +#define mmDCORE3_TPC5_EML_CFG_SPECIAL_BASE 0x1000007FFBA40E80ull +#define DCORE3_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFBA41000ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC5_EML_TPC_CFG_BASE 0x1000007FFBA41000ull +#define DCORE3_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_TPC_CFG_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFBA41050ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFBA410A0ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFBA410F0ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFBA41140ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFBA41190ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFBA411E0ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFBA41230ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFBA41280ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFBA412D0ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFBA41320ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFBA41370ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFBA413C0ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFBA41410ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFBA41460ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFBA414B0ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFBA41500ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_BASE 0x1000007FFBA41508ull +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1000007FFBA415DCull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1000007FFBA4162Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1000007FFBA4167Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1000007FFBA416CCull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1000007FFBA4171Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1000007FFBA4176Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1000007FFBA417BCull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1000007FFBA4180Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1000007FFBA4185Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1000007FFBA418ACull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1000007FFBA418FCull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1000007FFBA4194Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1000007FFBA4199Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1000007FFBA419ECull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1000007FFBA41A3Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1000007FFBA41A8Cull +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFBA41ADCull +#define DCORE3_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_QM_BASE 0x1000007FFBA41AE4ull +#define DCORE3_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0 + +#define mmDCORE3_TPC5_EML_TPC_CFG_AXUSER_BASE 0x1000007FFBA41E00ull +#define DCORE3_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE3_TPC5_EML_TPC_CFG_SPECIAL_BASE 0x1000007FFBA41E80ull +#define DCORE3_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC5_EML_QM_DCCM_BASE 0x1000007FFBA42000ull +#define DCORE3_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC5_EML_QM_DCCM_SECTION 0x8000 + +#define mmDCORE3_TPC5_EML_QM_ARCAUX_BASE 0x1000007FFBA4A000ull +#define DCORE3_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_QM_ARCAUX_SECTION 0xE800 + +#define mmDCORE3_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0x1000007FFBA4AE80ull +#define DCORE3_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE3_TPC5_EML_TPC_QM_BASE 0x1000007FFBA4C000ull +#define DCORE3_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_TPC_QM_SECTION 0x9000 + +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFBA4C900ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFBA4C908ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFBA4C910ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFBA4C918ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFBA4C920ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFBA4C928ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFBA4C930ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFBA4C938ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFBA4C940ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFBA4C948ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE \ +0x1000007FFBA4C950ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE \ +0x1000007FFBA4C958ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE \ +0x1000007FFBA4C960ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE \ +0x1000007FFBA4C968ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE \ +0x1000007FFBA4C970ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE \ +0x1000007FFBA4C978ull +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE3_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0x1000007FFBA4CB00ull +#define DCORE3_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE3_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1000007FFBA4CB80ull +#define DCORE3_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE3_TPC5_EML_TPC_QM_DBG_HBW_BASE 0x1000007FFBA4CC00ull +#define DCORE3_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_TPC5_EML_TPC_QM_DBG_LBW_BASE 0x1000007FFBA4CC80ull +#define DCORE3_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE3_TPC5_EML_TPC_QM_CGM_BASE 0x1000007FFBA4CD80ull +#define DCORE3_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC5_EML_TPC_QM_CGM_SECTION 0x1000 + +#define mmDCORE3_TPC5_EML_TPC_QM_SPECIAL_BASE 0x1000007FFBA4CE80ull +#define DCORE3_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 + +#define mmDCORE3_TPC5_EML_CS_BASE 0x1000007FFBBFF000ull +#define DCORE3_TPC5_EML_CS_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_EML_CS_SECTION 0x401000 + +#define mmDCORE0_TPC0_QM_DCCM_BASE 0x1000007FFC000000ull +#define DCORE0_TPC0_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC0_QM_DCCM_SECTION 0x8000 + +#define mmDCORE0_TPC0_QM_ARC_AUX_BASE 0x1000007FFC008000ull +#define DCORE0_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE0_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC008E80ull +#define DCORE0_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE0_TPC0_QM_BASE 0x1000007FFC00A000ull +#define DCORE0_TPC0_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_QM_SECTION 0x9000 + +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC00A900ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC00A908ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC00A910ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC00A918ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC00A920ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC00A928ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC00A930ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC00A938ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC00A940ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC00A948ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC00A950ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC00A958ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC00A960ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC00A968ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC00A970ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC00A978ull +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE0_TPC0_QM_AXUSER_SECURED_BASE 0x1000007FFC00AB00ull +#define DCORE0_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_BASE 0x1000007FFC00AB80ull +#define DCORE0_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE0_TPC0_QM_DBG_HBW_BASE 0x1000007FFC00AC00ull +#define DCORE0_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC0_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_TPC0_QM_DBG_LBW_BASE 0x1000007FFC00AC80ull +#define DCORE0_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC0_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE0_TPC0_QM_CGM_BASE 0x1000007FFC00AD80ull +#define DCORE0_TPC0_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC0_QM_CGM_SECTION 0x1000 + +#define mmDCORE0_TPC0_QM_SPECIAL_BASE 0x1000007FFC00AE80ull +#define DCORE0_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC0_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFC00B000ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC0_CFG_BASE 0x1000007FFC00B000ull +#define DCORE0_TPC0_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC0_CFG_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFC00B050ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFC00B0A0ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFC00B0F0ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFC00B140ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFC00B190ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFC00B1E0ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFC00B230ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFC00B280ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFC00B2D0ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFC00B320ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFC00B370ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFC00B3C0ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFC00B410ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFC00B460ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFC00B4B0ull +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFC00B500ull +#define DCORE0_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC0_CFG_KERNEL_BASE 0x1000007FFC00B508ull +#define DCORE0_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC0_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE 0x1000007FFC00B5DCull +#define DCORE0_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_1_BASE 0x1000007FFC00B62Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_2_BASE 0x1000007FFC00B67Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_3_BASE 0x1000007FFC00B6CCull +#define DCORE0_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_4_BASE 0x1000007FFC00B71Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_5_BASE 0x1000007FFC00B76Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_6_BASE 0x1000007FFC00B7BCull +#define DCORE0_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_7_BASE 0x1000007FFC00B80Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_8_BASE 0x1000007FFC00B85Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_9_BASE 0x1000007FFC00B8ACull +#define DCORE0_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_10_BASE 0x1000007FFC00B8FCull +#define DCORE0_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_11_BASE 0x1000007FFC00B94Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_12_BASE 0x1000007FFC00B99Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_13_BASE 0x1000007FFC00B9ECull +#define DCORE0_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_14_BASE 0x1000007FFC00BA3Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_QM_TENSOR_15_BASE 0x1000007FFC00BA8Cull +#define DCORE0_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFC00BADCull +#define DCORE0_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC0_CFG_QM_BASE 0x1000007FFC00BAE4ull +#define DCORE0_TPC0_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC0_CFG_QM_SECTION 0x31C0 + +#define mmDCORE0_TPC0_CFG_AXUSER_BASE 0x1000007FFC00BE00ull +#define DCORE0_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE0_TPC0_CFG_SPECIAL_BASE 0x1000007FFC00BE80ull +#define DCORE0_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC0_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC00C000ull +#define DCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE0_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC00C200ull +#define DCORE0_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE0_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC00C400ull +#define DCORE0_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE0_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC00C600ull +#define DCORE0_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE0_TPC0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC00C800ull +#define DCORE0_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE0_TPC0_MSTR_IF_AXUSER_BASE 0x1000007FFC00CA80ull +#define DCORE0_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE0_TPC0_MSTR_IF_DBG_HBW_BASE 0x1000007FFC00CB00ull +#define DCORE0_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_TPC0_MSTR_IF_DBG_LBW_BASE 0x1000007FFC00CB80ull +#define DCORE0_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE0_TPC0_MSTR_IF_CORE_HBW_BASE 0x1000007FFC00CC00ull +#define DCORE0_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE0_TPC0_MSTR_IF_CORE_LBW_BASE 0x1000007FFC00CD80ull +#define DCORE0_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE0_TPC0_MSTR_IF_SPECIAL_BASE 0x1000007FFC00CE80ull +#define DCORE0_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE0_TPC1_QM_DCCM_BASE 0x1000007FFC010000ull +#define DCORE0_TPC1_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC1_QM_DCCM_SECTION 0x8000 + +#define mmDCORE0_TPC1_QM_ARC_AUX_BASE 0x1000007FFC018000ull +#define DCORE0_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE0_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC018E80ull +#define DCORE0_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE0_TPC1_QM_BASE 0x1000007FFC01A000ull +#define DCORE0_TPC1_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_QM_SECTION 0x9000 + +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC01A900ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC01A908ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC01A910ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC01A918ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC01A920ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC01A928ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC01A930ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC01A938ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC01A940ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC01A948ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC01A950ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC01A958ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC01A960ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC01A968ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC01A970ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC01A978ull +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE0_TPC1_QM_AXUSER_SECURED_BASE 0x1000007FFC01AB00ull +#define DCORE0_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE0_TPC1_QM_AXUSER_NONSECURED_BASE 0x1000007FFC01AB80ull +#define DCORE0_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE0_TPC1_QM_DBG_HBW_BASE 0x1000007FFC01AC00ull +#define DCORE0_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC1_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_TPC1_QM_DBG_LBW_BASE 0x1000007FFC01AC80ull +#define DCORE0_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC1_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE0_TPC1_QM_CGM_BASE 0x1000007FFC01AD80ull +#define DCORE0_TPC1_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC1_QM_CGM_SECTION 0x1000 + +#define mmDCORE0_TPC1_QM_SPECIAL_BASE 0x1000007FFC01AE80ull +#define DCORE0_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC1_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFC01B000ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC1_CFG_BASE 0x1000007FFC01B000ull +#define DCORE0_TPC1_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC1_CFG_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFC01B050ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFC01B0A0ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFC01B0F0ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFC01B140ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFC01B190ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFC01B1E0ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFC01B230ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFC01B280ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFC01B2D0ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFC01B320ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFC01B370ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFC01B3C0ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFC01B410ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFC01B460ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFC01B4B0ull +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFC01B500ull +#define DCORE0_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC1_CFG_KERNEL_BASE 0x1000007FFC01B508ull +#define DCORE0_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC1_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE0_TPC1_CFG_QM_TENSOR_0_BASE 0x1000007FFC01B5DCull +#define DCORE0_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_QM_TENSOR_1_BASE 0x1000007FFC01B62Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_QM_TENSOR_2_BASE 0x1000007FFC01B67Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_QM_TENSOR_3_BASE 0x1000007FFC01B6CCull +#define DCORE0_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_QM_TENSOR_4_BASE 0x1000007FFC01B71Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_QM_TENSOR_5_BASE 0x1000007FFC01B76Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_QM_TENSOR_6_BASE 0x1000007FFC01B7BCull +#define DCORE0_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_QM_TENSOR_7_BASE 0x1000007FFC01B80Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_QM_TENSOR_8_BASE 0x1000007FFC01B85Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_QM_TENSOR_9_BASE 0x1000007FFC01B8ACull +#define DCORE0_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_QM_TENSOR_10_BASE 0x1000007FFC01B8FCull +#define DCORE0_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_QM_TENSOR_11_BASE 0x1000007FFC01B94Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_QM_TENSOR_12_BASE 0x1000007FFC01B99Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_QM_TENSOR_13_BASE 0x1000007FFC01B9ECull +#define DCORE0_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_QM_TENSOR_14_BASE 0x1000007FFC01BA3Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_QM_TENSOR_15_BASE 0x1000007FFC01BA8Cull +#define DCORE0_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFC01BADCull +#define DCORE0_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC1_CFG_QM_BASE 0x1000007FFC01BAE4ull +#define DCORE0_TPC1_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC1_CFG_QM_SECTION 0x31C0 + +#define mmDCORE0_TPC1_CFG_AXUSER_BASE 0x1000007FFC01BE00ull +#define DCORE0_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE0_TPC1_CFG_SPECIAL_BASE 0x1000007FFC01BE80ull +#define DCORE0_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC1_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC01C000ull +#define DCORE0_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE0_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC01C200ull +#define DCORE0_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE0_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC01C400ull +#define DCORE0_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE0_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC01C600ull +#define DCORE0_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE0_TPC1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC01C800ull +#define DCORE0_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE0_TPC1_MSTR_IF_AXUSER_BASE 0x1000007FFC01CA80ull +#define DCORE0_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE0_TPC1_MSTR_IF_DBG_HBW_BASE 0x1000007FFC01CB00ull +#define DCORE0_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_TPC1_MSTR_IF_DBG_LBW_BASE 0x1000007FFC01CB80ull +#define DCORE0_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE0_TPC1_MSTR_IF_CORE_HBW_BASE 0x1000007FFC01CC00ull +#define DCORE0_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE0_TPC1_MSTR_IF_CORE_LBW_BASE 0x1000007FFC01CD80ull +#define DCORE0_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE0_TPC1_MSTR_IF_SPECIAL_BASE 0x1000007FFC01CE80ull +#define DCORE0_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE0_TPC2_QM_DCCM_BASE 0x1000007FFC020000ull +#define DCORE0_TPC2_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC2_QM_DCCM_SECTION 0x8000 + +#define mmDCORE0_TPC2_QM_ARC_AUX_BASE 0x1000007FFC028000ull +#define DCORE0_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE0_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC028E80ull +#define DCORE0_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE0_TPC2_QM_BASE 0x1000007FFC02A000ull +#define DCORE0_TPC2_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_QM_SECTION 0x9000 + +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC02A900ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC02A908ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC02A910ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC02A918ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC02A920ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC02A928ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC02A930ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC02A938ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC02A940ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC02A948ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC02A950ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC02A958ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC02A960ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC02A968ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC02A970ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC02A978ull +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE0_TPC2_QM_AXUSER_SECURED_BASE 0x1000007FFC02AB00ull +#define DCORE0_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE0_TPC2_QM_AXUSER_NONSECURED_BASE 0x1000007FFC02AB80ull +#define DCORE0_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE0_TPC2_QM_DBG_HBW_BASE 0x1000007FFC02AC00ull +#define DCORE0_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC2_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_TPC2_QM_DBG_LBW_BASE 0x1000007FFC02AC80ull +#define DCORE0_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC2_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE0_TPC2_QM_CGM_BASE 0x1000007FFC02AD80ull +#define DCORE0_TPC2_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC2_QM_CGM_SECTION 0x1000 + +#define mmDCORE0_TPC2_QM_SPECIAL_BASE 0x1000007FFC02AE80ull +#define DCORE0_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC2_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFC02B000ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC2_CFG_BASE 0x1000007FFC02B000ull +#define DCORE0_TPC2_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC2_CFG_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFC02B050ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFC02B0A0ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFC02B0F0ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFC02B140ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFC02B190ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFC02B1E0ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFC02B230ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFC02B280ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFC02B2D0ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFC02B320ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFC02B370ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFC02B3C0ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFC02B410ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFC02B460ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFC02B4B0ull +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFC02B500ull +#define DCORE0_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC2_CFG_KERNEL_BASE 0x1000007FFC02B508ull +#define DCORE0_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC2_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE0_TPC2_CFG_QM_TENSOR_0_BASE 0x1000007FFC02B5DCull +#define DCORE0_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_QM_TENSOR_1_BASE 0x1000007FFC02B62Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_QM_TENSOR_2_BASE 0x1000007FFC02B67Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_QM_TENSOR_3_BASE 0x1000007FFC02B6CCull +#define DCORE0_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_QM_TENSOR_4_BASE 0x1000007FFC02B71Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_QM_TENSOR_5_BASE 0x1000007FFC02B76Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_QM_TENSOR_6_BASE 0x1000007FFC02B7BCull +#define DCORE0_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_QM_TENSOR_7_BASE 0x1000007FFC02B80Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_QM_TENSOR_8_BASE 0x1000007FFC02B85Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_QM_TENSOR_9_BASE 0x1000007FFC02B8ACull +#define DCORE0_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_QM_TENSOR_10_BASE 0x1000007FFC02B8FCull +#define DCORE0_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_QM_TENSOR_11_BASE 0x1000007FFC02B94Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_QM_TENSOR_12_BASE 0x1000007FFC02B99Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_QM_TENSOR_13_BASE 0x1000007FFC02B9ECull +#define DCORE0_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_QM_TENSOR_14_BASE 0x1000007FFC02BA3Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_QM_TENSOR_15_BASE 0x1000007FFC02BA8Cull +#define DCORE0_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFC02BADCull +#define DCORE0_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC2_CFG_QM_BASE 0x1000007FFC02BAE4ull +#define DCORE0_TPC2_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC2_CFG_QM_SECTION 0x31C0 + +#define mmDCORE0_TPC2_CFG_AXUSER_BASE 0x1000007FFC02BE00ull +#define DCORE0_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE0_TPC2_CFG_SPECIAL_BASE 0x1000007FFC02BE80ull +#define DCORE0_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC2_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC02C000ull +#define DCORE0_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE0_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC02C200ull +#define DCORE0_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE0_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC02C400ull +#define DCORE0_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE0_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC02C600ull +#define DCORE0_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE0_TPC2_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC02C800ull +#define DCORE0_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE0_TPC2_MSTR_IF_AXUSER_BASE 0x1000007FFC02CA80ull +#define DCORE0_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC2_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE0_TPC2_MSTR_IF_DBG_HBW_BASE 0x1000007FFC02CB00ull +#define DCORE0_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_TPC2_MSTR_IF_DBG_LBW_BASE 0x1000007FFC02CB80ull +#define DCORE0_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE0_TPC2_MSTR_IF_CORE_HBW_BASE 0x1000007FFC02CC00ull +#define DCORE0_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE0_TPC2_MSTR_IF_CORE_LBW_BASE 0x1000007FFC02CD80ull +#define DCORE0_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE0_TPC2_MSTR_IF_SPECIAL_BASE 0x1000007FFC02CE80ull +#define DCORE0_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE0_TPC3_QM_DCCM_BASE 0x1000007FFC030000ull +#define DCORE0_TPC3_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC3_QM_DCCM_SECTION 0x8000 + +#define mmDCORE0_TPC3_QM_ARC_AUX_BASE 0x1000007FFC038000ull +#define DCORE0_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE0_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC038E80ull +#define DCORE0_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE0_TPC3_QM_BASE 0x1000007FFC03A000ull +#define DCORE0_TPC3_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_QM_SECTION 0x9000 + +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC03A900ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC03A908ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC03A910ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC03A918ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC03A920ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC03A928ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC03A930ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC03A938ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC03A940ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC03A948ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC03A950ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC03A958ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC03A960ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC03A968ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC03A970ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC03A978ull +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE0_TPC3_QM_AXUSER_SECURED_BASE 0x1000007FFC03AB00ull +#define DCORE0_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE0_TPC3_QM_AXUSER_NONSECURED_BASE 0x1000007FFC03AB80ull +#define DCORE0_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE0_TPC3_QM_DBG_HBW_BASE 0x1000007FFC03AC00ull +#define DCORE0_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC3_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_TPC3_QM_DBG_LBW_BASE 0x1000007FFC03AC80ull +#define DCORE0_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC3_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE0_TPC3_QM_CGM_BASE 0x1000007FFC03AD80ull +#define DCORE0_TPC3_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC3_QM_CGM_SECTION 0x1000 + +#define mmDCORE0_TPC3_QM_SPECIAL_BASE 0x1000007FFC03AE80ull +#define DCORE0_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC3_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFC03B000ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC3_CFG_BASE 0x1000007FFC03B000ull +#define DCORE0_TPC3_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC3_CFG_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFC03B050ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFC03B0A0ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFC03B0F0ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFC03B140ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFC03B190ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFC03B1E0ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFC03B230ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFC03B280ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFC03B2D0ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFC03B320ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFC03B370ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFC03B3C0ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFC03B410ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFC03B460ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFC03B4B0ull +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFC03B500ull +#define DCORE0_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC3_CFG_KERNEL_BASE 0x1000007FFC03B508ull +#define DCORE0_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC3_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE0_TPC3_CFG_QM_TENSOR_0_BASE 0x1000007FFC03B5DCull +#define DCORE0_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_QM_TENSOR_1_BASE 0x1000007FFC03B62Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_QM_TENSOR_2_BASE 0x1000007FFC03B67Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_QM_TENSOR_3_BASE 0x1000007FFC03B6CCull +#define DCORE0_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_QM_TENSOR_4_BASE 0x1000007FFC03B71Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_QM_TENSOR_5_BASE 0x1000007FFC03B76Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_QM_TENSOR_6_BASE 0x1000007FFC03B7BCull +#define DCORE0_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_QM_TENSOR_7_BASE 0x1000007FFC03B80Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_QM_TENSOR_8_BASE 0x1000007FFC03B85Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_QM_TENSOR_9_BASE 0x1000007FFC03B8ACull +#define DCORE0_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_QM_TENSOR_10_BASE 0x1000007FFC03B8FCull +#define DCORE0_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_QM_TENSOR_11_BASE 0x1000007FFC03B94Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_QM_TENSOR_12_BASE 0x1000007FFC03B99Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_QM_TENSOR_13_BASE 0x1000007FFC03B9ECull +#define DCORE0_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_QM_TENSOR_14_BASE 0x1000007FFC03BA3Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_QM_TENSOR_15_BASE 0x1000007FFC03BA8Cull +#define DCORE0_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFC03BADCull +#define DCORE0_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC3_CFG_QM_BASE 0x1000007FFC03BAE4ull +#define DCORE0_TPC3_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC3_CFG_QM_SECTION 0x31C0 + +#define mmDCORE0_TPC3_CFG_AXUSER_BASE 0x1000007FFC03BE00ull +#define DCORE0_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE0_TPC3_CFG_SPECIAL_BASE 0x1000007FFC03BE80ull +#define DCORE0_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC3_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC03C000ull +#define DCORE0_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE0_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC03C200ull +#define DCORE0_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE0_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC03C400ull +#define DCORE0_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE0_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC03C600ull +#define DCORE0_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE0_TPC3_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC03C800ull +#define DCORE0_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE0_TPC3_MSTR_IF_AXUSER_BASE 0x1000007FFC03CA80ull +#define DCORE0_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC3_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE0_TPC3_MSTR_IF_DBG_HBW_BASE 0x1000007FFC03CB00ull +#define DCORE0_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_TPC3_MSTR_IF_DBG_LBW_BASE 0x1000007FFC03CB80ull +#define DCORE0_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE0_TPC3_MSTR_IF_CORE_HBW_BASE 0x1000007FFC03CC00ull +#define DCORE0_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE0_TPC3_MSTR_IF_CORE_LBW_BASE 0x1000007FFC03CD80ull +#define DCORE0_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE0_TPC3_MSTR_IF_SPECIAL_BASE 0x1000007FFC03CE80ull +#define DCORE0_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE0_TPC4_QM_DCCM_BASE 0x1000007FFC040000ull +#define DCORE0_TPC4_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC4_QM_DCCM_SECTION 0x8000 + +#define mmDCORE0_TPC4_QM_ARC_AUX_BASE 0x1000007FFC048000ull +#define DCORE0_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE0_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC048E80ull +#define DCORE0_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE0_TPC4_QM_BASE 0x1000007FFC04A000ull +#define DCORE0_TPC4_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_QM_SECTION 0x9000 + +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC04A900ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC04A908ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC04A910ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC04A918ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC04A920ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC04A928ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC04A930ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC04A938ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC04A940ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC04A948ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC04A950ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC04A958ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC04A960ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC04A968ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC04A970ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC04A978ull +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE0_TPC4_QM_AXUSER_SECURED_BASE 0x1000007FFC04AB00ull +#define DCORE0_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE0_TPC4_QM_AXUSER_NONSECURED_BASE 0x1000007FFC04AB80ull +#define DCORE0_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE0_TPC4_QM_DBG_HBW_BASE 0x1000007FFC04AC00ull +#define DCORE0_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC4_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_TPC4_QM_DBG_LBW_BASE 0x1000007FFC04AC80ull +#define DCORE0_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC4_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE0_TPC4_QM_CGM_BASE 0x1000007FFC04AD80ull +#define DCORE0_TPC4_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC4_QM_CGM_SECTION 0x1000 + +#define mmDCORE0_TPC4_QM_SPECIAL_BASE 0x1000007FFC04AE80ull +#define DCORE0_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC4_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFC04B000ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC4_CFG_BASE 0x1000007FFC04B000ull +#define DCORE0_TPC4_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC4_CFG_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFC04B050ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFC04B0A0ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFC04B0F0ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFC04B140ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFC04B190ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFC04B1E0ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFC04B230ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFC04B280ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFC04B2D0ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFC04B320ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFC04B370ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFC04B3C0ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFC04B410ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFC04B460ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFC04B4B0ull +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFC04B500ull +#define DCORE0_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC4_CFG_KERNEL_BASE 0x1000007FFC04B508ull +#define DCORE0_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC4_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE0_TPC4_CFG_QM_TENSOR_0_BASE 0x1000007FFC04B5DCull +#define DCORE0_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_QM_TENSOR_1_BASE 0x1000007FFC04B62Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_QM_TENSOR_2_BASE 0x1000007FFC04B67Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_QM_TENSOR_3_BASE 0x1000007FFC04B6CCull +#define DCORE0_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_QM_TENSOR_4_BASE 0x1000007FFC04B71Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_QM_TENSOR_5_BASE 0x1000007FFC04B76Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_QM_TENSOR_6_BASE 0x1000007FFC04B7BCull +#define DCORE0_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_QM_TENSOR_7_BASE 0x1000007FFC04B80Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_QM_TENSOR_8_BASE 0x1000007FFC04B85Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_QM_TENSOR_9_BASE 0x1000007FFC04B8ACull +#define DCORE0_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_QM_TENSOR_10_BASE 0x1000007FFC04B8FCull +#define DCORE0_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_QM_TENSOR_11_BASE 0x1000007FFC04B94Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_QM_TENSOR_12_BASE 0x1000007FFC04B99Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_QM_TENSOR_13_BASE 0x1000007FFC04B9ECull +#define DCORE0_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_QM_TENSOR_14_BASE 0x1000007FFC04BA3Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_QM_TENSOR_15_BASE 0x1000007FFC04BA8Cull +#define DCORE0_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFC04BADCull +#define DCORE0_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC4_CFG_QM_BASE 0x1000007FFC04BAE4ull +#define DCORE0_TPC4_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC4_CFG_QM_SECTION 0x31C0 + +#define mmDCORE0_TPC4_CFG_AXUSER_BASE 0x1000007FFC04BE00ull +#define DCORE0_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE0_TPC4_CFG_SPECIAL_BASE 0x1000007FFC04BE80ull +#define DCORE0_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC4_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC04C000ull +#define DCORE0_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE0_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC04C200ull +#define DCORE0_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE0_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC04C400ull +#define DCORE0_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE0_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC04C600ull +#define DCORE0_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE0_TPC4_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC04C800ull +#define DCORE0_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE0_TPC4_MSTR_IF_AXUSER_BASE 0x1000007FFC04CA80ull +#define DCORE0_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC4_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE0_TPC4_MSTR_IF_DBG_HBW_BASE 0x1000007FFC04CB00ull +#define DCORE0_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_TPC4_MSTR_IF_DBG_LBW_BASE 0x1000007FFC04CB80ull +#define DCORE0_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE0_TPC4_MSTR_IF_CORE_HBW_BASE 0x1000007FFC04CC00ull +#define DCORE0_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE0_TPC4_MSTR_IF_CORE_LBW_BASE 0x1000007FFC04CD80ull +#define DCORE0_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE0_TPC4_MSTR_IF_SPECIAL_BASE 0x1000007FFC04CE80ull +#define DCORE0_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE0_TPC5_QM_DCCM_BASE 0x1000007FFC050000ull +#define DCORE0_TPC5_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC5_QM_DCCM_SECTION 0x8000 + +#define mmDCORE0_TPC5_QM_ARC_AUX_BASE 0x1000007FFC058000ull +#define DCORE0_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE0_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC058E80ull +#define DCORE0_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE0_TPC5_QM_BASE 0x1000007FFC05A000ull +#define DCORE0_TPC5_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_QM_SECTION 0x9000 + +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC05A900ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC05A908ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC05A910ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC05A918ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC05A920ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC05A928ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC05A930ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC05A938ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC05A940ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC05A948ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC05A950ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC05A958ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC05A960ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC05A968ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC05A970ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC05A978ull +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE0_TPC5_QM_AXUSER_SECURED_BASE 0x1000007FFC05AB00ull +#define DCORE0_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE0_TPC5_QM_AXUSER_NONSECURED_BASE 0x1000007FFC05AB80ull +#define DCORE0_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE0_TPC5_QM_DBG_HBW_BASE 0x1000007FFC05AC00ull +#define DCORE0_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC5_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_TPC5_QM_DBG_LBW_BASE 0x1000007FFC05AC80ull +#define DCORE0_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC5_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE0_TPC5_QM_CGM_BASE 0x1000007FFC05AD80ull +#define DCORE0_TPC5_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC5_QM_CGM_SECTION 0x1000 + +#define mmDCORE0_TPC5_QM_SPECIAL_BASE 0x1000007FFC05AE80ull +#define DCORE0_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC5_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFC05B000ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC5_CFG_BASE 0x1000007FFC05B000ull +#define DCORE0_TPC5_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC5_CFG_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFC05B050ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFC05B0A0ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFC05B0F0ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFC05B140ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFC05B190ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFC05B1E0ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFC05B230ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFC05B280ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFC05B2D0ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFC05B320ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFC05B370ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFC05B3C0ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFC05B410ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFC05B460ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFC05B4B0ull +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFC05B500ull +#define DCORE0_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC5_CFG_KERNEL_BASE 0x1000007FFC05B508ull +#define DCORE0_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC5_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE0_TPC5_CFG_QM_TENSOR_0_BASE 0x1000007FFC05B5DCull +#define DCORE0_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_QM_TENSOR_1_BASE 0x1000007FFC05B62Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_QM_TENSOR_2_BASE 0x1000007FFC05B67Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_QM_TENSOR_3_BASE 0x1000007FFC05B6CCull +#define DCORE0_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_QM_TENSOR_4_BASE 0x1000007FFC05B71Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_QM_TENSOR_5_BASE 0x1000007FFC05B76Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_QM_TENSOR_6_BASE 0x1000007FFC05B7BCull +#define DCORE0_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_QM_TENSOR_7_BASE 0x1000007FFC05B80Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_QM_TENSOR_8_BASE 0x1000007FFC05B85Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_QM_TENSOR_9_BASE 0x1000007FFC05B8ACull +#define DCORE0_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_QM_TENSOR_10_BASE 0x1000007FFC05B8FCull +#define DCORE0_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_QM_TENSOR_11_BASE 0x1000007FFC05B94Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_QM_TENSOR_12_BASE 0x1000007FFC05B99Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_QM_TENSOR_13_BASE 0x1000007FFC05B9ECull +#define DCORE0_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_QM_TENSOR_14_BASE 0x1000007FFC05BA3Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_QM_TENSOR_15_BASE 0x1000007FFC05BA8Cull +#define DCORE0_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFC05BADCull +#define DCORE0_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC5_CFG_QM_BASE 0x1000007FFC05BAE4ull +#define DCORE0_TPC5_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC5_CFG_QM_SECTION 0x31C0 + +#define mmDCORE0_TPC5_CFG_AXUSER_BASE 0x1000007FFC05BE00ull +#define DCORE0_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE0_TPC5_CFG_SPECIAL_BASE 0x1000007FFC05BE80ull +#define DCORE0_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC5_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC05C000ull +#define DCORE0_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE0_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC05C200ull +#define DCORE0_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE0_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC05C400ull +#define DCORE0_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE0_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC05C600ull +#define DCORE0_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE0_TPC5_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC05C800ull +#define DCORE0_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE0_TPC5_MSTR_IF_AXUSER_BASE 0x1000007FFC05CA80ull +#define DCORE0_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC5_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE0_TPC5_MSTR_IF_DBG_HBW_BASE 0x1000007FFC05CB00ull +#define DCORE0_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_TPC5_MSTR_IF_DBG_LBW_BASE 0x1000007FFC05CB80ull +#define DCORE0_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE0_TPC5_MSTR_IF_CORE_HBW_BASE 0x1000007FFC05CC00ull +#define DCORE0_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE0_TPC5_MSTR_IF_CORE_LBW_BASE 0x1000007FFC05CD80ull +#define DCORE0_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE0_TPC5_MSTR_IF_SPECIAL_BASE 0x1000007FFC05CE80ull +#define DCORE0_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC5_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE0_TPC6_QM_DCCM_BASE 0x1000007FFC060000ull +#define DCORE0_TPC6_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_TPC6_QM_DCCM_SECTION 0x8000 + +#define mmDCORE0_TPC6_QM_ARC_AUX_BASE 0x1000007FFC068000ull +#define DCORE0_TPC6_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE0_TPC6_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC068E80ull +#define DCORE0_TPC6_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC6_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE0_TPC6_QM_BASE 0x1000007FFC06A000ull +#define DCORE0_TPC6_QM_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_QM_SECTION 0x9000 + +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC06A900ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC06A908ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC06A910ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC06A918ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC06A920ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC06A928ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC06A930ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC06A938ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC06A940ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC06A948ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC06A950ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC06A958ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC06A960ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC06A968ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC06A970ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC06A978ull +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE0_TPC6_QM_AXUSER_SECURED_BASE 0x1000007FFC06AB00ull +#define DCORE0_TPC6_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE0_TPC6_QM_AXUSER_NONSECURED_BASE 0x1000007FFC06AB80ull +#define DCORE0_TPC6_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE0_TPC6_QM_DBG_HBW_BASE 0x1000007FFC06AC00ull +#define DCORE0_TPC6_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC6_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_TPC6_QM_DBG_LBW_BASE 0x1000007FFC06AC80ull +#define DCORE0_TPC6_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC6_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE0_TPC6_QM_CGM_BASE 0x1000007FFC06AD80ull +#define DCORE0_TPC6_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_TPC6_QM_CGM_SECTION 0x1000 + +#define mmDCORE0_TPC6_QM_SPECIAL_BASE 0x1000007FFC06AE80ull +#define DCORE0_TPC6_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC6_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFC06B000ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC6_CFG_BASE 0x1000007FFC06B000ull +#define DCORE0_TPC6_CFG_MAX_OFFSET 0x1000 +#define DCORE0_TPC6_CFG_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFC06B050ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFC06B0A0ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFC06B0F0ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFC06B140ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFC06B190ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFC06B1E0ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFC06B230ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFC06B280ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFC06B2D0ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFC06B320ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFC06B370ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFC06B3C0ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFC06B410ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFC06B460ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFC06B4B0ull +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFC06B500ull +#define DCORE0_TPC6_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC6_CFG_KERNEL_BASE 0x1000007FFC06B508ull +#define DCORE0_TPC6_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE0_TPC6_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE0_TPC6_CFG_QM_TENSOR_0_BASE 0x1000007FFC06B5DCull +#define DCORE0_TPC6_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_QM_TENSOR_1_BASE 0x1000007FFC06B62Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_QM_TENSOR_2_BASE 0x1000007FFC06B67Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_QM_TENSOR_3_BASE 0x1000007FFC06B6CCull +#define DCORE0_TPC6_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_QM_TENSOR_4_BASE 0x1000007FFC06B71Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_QM_TENSOR_5_BASE 0x1000007FFC06B76Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_QM_TENSOR_6_BASE 0x1000007FFC06B7BCull +#define DCORE0_TPC6_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_QM_TENSOR_7_BASE 0x1000007FFC06B80Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_QM_TENSOR_8_BASE 0x1000007FFC06B85Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_QM_TENSOR_9_BASE 0x1000007FFC06B8ACull +#define DCORE0_TPC6_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_QM_TENSOR_10_BASE 0x1000007FFC06B8FCull +#define DCORE0_TPC6_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_QM_TENSOR_11_BASE 0x1000007FFC06B94Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_QM_TENSOR_12_BASE 0x1000007FFC06B99Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_QM_TENSOR_13_BASE 0x1000007FFC06B9ECull +#define DCORE0_TPC6_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_QM_TENSOR_14_BASE 0x1000007FFC06BA3Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_QM_TENSOR_15_BASE 0x1000007FFC06BA8Cull +#define DCORE0_TPC6_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE0_TPC6_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFC06BADCull +#define DCORE0_TPC6_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE0_TPC6_CFG_QM_BASE 0x1000007FFC06BAE4ull +#define DCORE0_TPC6_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE0_TPC6_CFG_QM_SECTION 0x31C0 + +#define mmDCORE0_TPC6_CFG_AXUSER_BASE 0x1000007FFC06BE00ull +#define DCORE0_TPC6_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE0_TPC6_CFG_SPECIAL_BASE 0x1000007FFC06BE80ull +#define DCORE0_TPC6_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC6_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC6_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC06C000ull +#define DCORE0_TPC6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE0_TPC6_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC06C200ull +#define DCORE0_TPC6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_TPC6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE0_TPC6_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC06C400ull +#define DCORE0_TPC6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE0_TPC6_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC06C600ull +#define DCORE0_TPC6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_TPC6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE0_TPC6_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC06C800ull +#define DCORE0_TPC6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_TPC6_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE0_TPC6_MSTR_IF_AXUSER_BASE 0x1000007FFC06CA80ull +#define DCORE0_TPC6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_TPC6_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE0_TPC6_MSTR_IF_DBG_HBW_BASE 0x1000007FFC06CB00ull +#define DCORE0_TPC6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC6_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_TPC6_MSTR_IF_DBG_LBW_BASE 0x1000007FFC06CB80ull +#define DCORE0_TPC6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_TPC6_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE0_TPC6_MSTR_IF_CORE_HBW_BASE 0x1000007FFC06CC00ull +#define DCORE0_TPC6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_TPC6_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE0_TPC6_MSTR_IF_CORE_LBW_BASE 0x1000007FFC06CD80ull +#define DCORE0_TPC6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_TPC6_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE0_TPC6_MSTR_IF_SPECIAL_BASE 0x1000007FFC06CE80ull +#define DCORE0_TPC6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC6_MSTR_IF_SPECIAL_SECTION 0x13180 + +#define mmDCORE0_HMMU0_MMU_BASE 0x1000007FFC080000ull +#define DCORE0_HMMU0_MMU_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_MMU_SECTION 0xE800 + +#define mmDCORE0_HMMU0_MMU_SPECIAL_BASE 0x1000007FFC080E80ull +#define DCORE0_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU0_MMU_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_HMMU0_STLB_BASE 0x1000007FFC081000ull +#define DCORE0_HMMU0_STLB_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_STLB_SECTION 0xE800 + +#define mmDCORE0_HMMU0_STLB_SPECIAL_BASE 0x1000007FFC081E80ull +#define DCORE0_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU0_STLB_SPECIAL_SECTION 0x1180 + +#define mmDCORE0_HMMU0_SCRAMB_OUT_BASE 0x1000007FFC083000ull +#define DCORE0_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_SCRAMB_OUT_SECTION 0xE800 + +#define mmDCORE0_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x1000007FFC083E80ull +#define DCORE0_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC084000ull +#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE0_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC084200ull +#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE0_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC084400ull +#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE0_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC084600ull +#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE0_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC084800ull +#define DCORE0_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE0_HMMU0_MSTR_IF_AXUSER_BASE 0x1000007FFC084A80ull +#define DCORE0_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE0_HMMU0_MSTR_IF_DBG_HBW_BASE 0x1000007FFC084B00ull +#define DCORE0_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_HMMU0_MSTR_IF_DBG_LBW_BASE 0x1000007FFC084B80ull +#define DCORE0_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE0_HMMU0_MSTR_IF_CORE_HBW_BASE 0x1000007FFC084C00ull +#define DCORE0_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE0_HMMU0_MSTR_IF_CORE_LBW_BASE 0x1000007FFC084D80ull +#define DCORE0_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE0_HMMU0_MSTR_IF_SPECIAL_BASE 0x1000007FFC084E80ull +#define DCORE0_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180 + +#define mmDCORE0_HMMU1_MMU_BASE 0x1000007FFC090000ull +#define DCORE0_HMMU1_MMU_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_MMU_SECTION 0xE800 + +#define mmDCORE0_HMMU1_MMU_SPECIAL_BASE 0x1000007FFC090E80ull +#define DCORE0_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU1_MMU_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_HMMU1_STLB_BASE 0x1000007FFC091000ull +#define DCORE0_HMMU1_STLB_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_STLB_SECTION 0xE800 + +#define mmDCORE0_HMMU1_STLB_SPECIAL_BASE 0x1000007FFC091E80ull +#define DCORE0_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU1_STLB_SPECIAL_SECTION 0x1180 + +#define mmDCORE0_HMMU1_SCRAMB_OUT_BASE 0x1000007FFC093000ull +#define DCORE0_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_SCRAMB_OUT_SECTION 0xE800 + +#define mmDCORE0_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x1000007FFC093E80ull +#define DCORE0_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC094000ull +#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE0_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC094200ull +#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE0_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC094400ull +#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE0_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC094600ull +#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE0_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC094800ull +#define DCORE0_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE0_HMMU1_MSTR_IF_AXUSER_BASE 0x1000007FFC094A80ull +#define DCORE0_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE0_HMMU1_MSTR_IF_DBG_HBW_BASE 0x1000007FFC094B00ull +#define DCORE0_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_HMMU1_MSTR_IF_DBG_LBW_BASE 0x1000007FFC094B80ull +#define DCORE0_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE0_HMMU1_MSTR_IF_CORE_HBW_BASE 0x1000007FFC094C00ull +#define DCORE0_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE0_HMMU1_MSTR_IF_CORE_LBW_BASE 0x1000007FFC094D80ull +#define DCORE0_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE0_HMMU1_MSTR_IF_SPECIAL_BASE 0x1000007FFC094E80ull +#define DCORE0_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180 + +#define mmDCORE0_HMMU2_MMU_BASE 0x1000007FFC0A0000ull +#define DCORE0_HMMU2_MMU_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_MMU_SECTION 0xE800 + +#define mmDCORE0_HMMU2_MMU_SPECIAL_BASE 0x1000007FFC0A0E80ull +#define DCORE0_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU2_MMU_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_HMMU2_STLB_BASE 0x1000007FFC0A1000ull +#define DCORE0_HMMU2_STLB_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_STLB_SECTION 0xE800 + +#define mmDCORE0_HMMU2_STLB_SPECIAL_BASE 0x1000007FFC0A1E80ull +#define DCORE0_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU2_STLB_SPECIAL_SECTION 0x1180 + +#define mmDCORE0_HMMU2_SCRAMB_OUT_BASE 0x1000007FFC0A3000ull +#define DCORE0_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_SCRAMB_OUT_SECTION 0xE800 + +#define mmDCORE0_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x1000007FFC0A3E80ull +#define DCORE0_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC0A4000ull +#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE0_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC0A4200ull +#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE0_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC0A4400ull +#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE0_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC0A4600ull +#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE0_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC0A4800ull +#define DCORE0_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE0_HMMU2_MSTR_IF_AXUSER_BASE 0x1000007FFC0A4A80ull +#define DCORE0_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE0_HMMU2_MSTR_IF_DBG_HBW_BASE 0x1000007FFC0A4B00ull +#define DCORE0_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_HMMU2_MSTR_IF_DBG_LBW_BASE 0x1000007FFC0A4B80ull +#define DCORE0_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE0_HMMU2_MSTR_IF_CORE_HBW_BASE 0x1000007FFC0A4C00ull +#define DCORE0_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE0_HMMU2_MSTR_IF_CORE_LBW_BASE 0x1000007FFC0A4D80ull +#define DCORE0_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE0_HMMU2_MSTR_IF_SPECIAL_BASE 0x1000007FFC0A4E80ull +#define DCORE0_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180 + +#define mmDCORE0_HMMU3_MMU_BASE 0x1000007FFC0B0000ull +#define DCORE0_HMMU3_MMU_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_MMU_SECTION 0xE800 + +#define mmDCORE0_HMMU3_MMU_SPECIAL_BASE 0x1000007FFC0B0E80ull +#define DCORE0_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU3_MMU_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_HMMU3_STLB_BASE 0x1000007FFC0B1000ull +#define DCORE0_HMMU3_STLB_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_STLB_SECTION 0xE800 + +#define mmDCORE0_HMMU3_STLB_SPECIAL_BASE 0x1000007FFC0B1E80ull +#define DCORE0_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU3_STLB_SPECIAL_SECTION 0x1180 + +#define mmDCORE0_HMMU3_SCRAMB_OUT_BASE 0x1000007FFC0B3000ull +#define DCORE0_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_SCRAMB_OUT_SECTION 0xE800 + +#define mmDCORE0_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x1000007FFC0B3E80ull +#define DCORE0_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC0B4000ull +#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE0_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC0B4200ull +#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE0_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC0B4400ull +#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE0_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC0B4600ull +#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE0_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC0B4800ull +#define DCORE0_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE0_HMMU3_MSTR_IF_AXUSER_BASE 0x1000007FFC0B4A80ull +#define DCORE0_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE0_HMMU3_MSTR_IF_DBG_HBW_BASE 0x1000007FFC0B4B00ull +#define DCORE0_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_HMMU3_MSTR_IF_DBG_LBW_BASE 0x1000007FFC0B4B80ull +#define DCORE0_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE0_HMMU3_MSTR_IF_CORE_HBW_BASE 0x1000007FFC0B4C00ull +#define DCORE0_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE0_HMMU3_MSTR_IF_CORE_LBW_BASE 0x1000007FFC0B4D80ull +#define DCORE0_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE0_HMMU3_MSTR_IF_SPECIAL_BASE 0x1000007FFC0B4E80ull +#define DCORE0_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180 + +#define mmDCORE0_SYNC_MNGR_OBJS_BASE 0x1000007FFC100000ull +#define DCORE0_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00 +#define DCORE0_SYNC_MNGR_OBJS_SECTION 0x1E000 + +#define mmDCORE0_SYNC_MNGR_GLBL_BASE 0x1000007FFC11E000ull +#define DCORE0_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000 +#define DCORE0_SYNC_MNGR_GLBL_SECTION 0xE800 + +#define mmDCORE0_SYNC_MNGR_GLBL_SPECIAL_BASE 0x1000007FFC11EE80ull +#define DCORE0_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC11F000ull +#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC11F200ull +#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC11F400ull +#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC11F600ull +#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC11F800ull +#define DCORE0_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x1000007FFC11FA80ull +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x1000007FFC11FB00ull +#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x1000007FFC11FB80ull +#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x1000007FFC11FC00ull +#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x1000007FFC11FD80ull +#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE0_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x1000007FFC11FE80ull +#define DCORE0_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_HIF0_BASE 0x1000007FFC120000ull +#define DCORE0_HIF0_MAX_OFFSET 0x1000 +#define DCORE0_HIF0_SECTION 0xE800 + +#define mmDCORE0_HIF0_SPECIAL_BASE 0x1000007FFC120E80ull +#define DCORE0_HIF0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HIF0_SPECIAL_SECTION 0x3180 + +#define mmDCORE0_HIF1_BASE 0x1000007FFC124000ull +#define DCORE0_HIF1_MAX_OFFSET 0x1000 +#define DCORE0_HIF1_SECTION 0xE800 + +#define mmDCORE0_HIF1_SPECIAL_BASE 0x1000007FFC124E80ull +#define DCORE0_HIF1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HIF1_SPECIAL_SECTION 0x3180 + +#define mmDCORE0_HIF2_BASE 0x1000007FFC128000ull +#define DCORE0_HIF2_MAX_OFFSET 0x1000 +#define DCORE0_HIF2_SECTION 0xE800 + +#define mmDCORE0_HIF2_SPECIAL_BASE 0x1000007FFC128E80ull +#define DCORE0_HIF2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HIF2_SPECIAL_SECTION 0x3180 + +#define mmDCORE0_HIF3_BASE 0x1000007FFC12C000ull +#define DCORE0_HIF3_MAX_OFFSET 0x1000 +#define DCORE0_HIF3_SECTION 0xE800 + +#define mmDCORE0_HIF3_SPECIAL_BASE 0x1000007FFC12CE80ull +#define DCORE0_HIF3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HIF3_SPECIAL_SECTION 0x13180 + +#define mmDCORE0_RTR0_CTRL_BASE 0x1000007FFC140000ull +#define DCORE0_RTR0_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_RTR0_CTRL_SECTION 0xE800 + +#define mmDCORE0_RTR0_CTRL_SPECIAL_BASE 0x1000007FFC140E80ull +#define DCORE0_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR0_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR0_H3_BASE 0x1000007FFC141000ull +#define DCORE0_RTR0_H3_MAX_OFFSET 0x1000 +#define DCORE0_RTR0_H3_SECTION 0xE800 + +#define mmDCORE0_RTR0_H3_SPECIAL_BASE 0x1000007FFC141E80ull +#define DCORE0_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR0_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC142000ull +#define DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC142200ull +#define DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC142400ull +#define DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC142600ull +#define DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE0_RTR0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC142800ull +#define DCORE0_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE0_RTR0_MSTR_IF_AXUSER_BASE 0x1000007FFC142A80ull +#define DCORE0_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_RTR0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE0_RTR0_MSTR_IF_DBG_HBW_BASE 0x1000007FFC142B00ull +#define DCORE0_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_RTR0_MSTR_IF_DBG_LBW_BASE 0x1000007FFC142B80ull +#define DCORE0_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE0_RTR0_MSTR_IF_CORE_HBW_BASE 0x1000007FFC142C00ull +#define DCORE0_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE0_RTR0_MSTR_IF_CORE_LBW_BASE 0x1000007FFC142D80ull +#define DCORE0_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE0_RTR0_MSTR_IF_SPECIAL_BASE 0x1000007FFC142E80ull +#define DCORE0_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR0_ADD_DEC_HBW_BASE 0x1000007FFC143000ull +#define DCORE0_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE0_RTR0_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE0_RTR0_ADD_DEC_LBW_BASE 0x1000007FFC143400ull +#define DCORE0_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE0_RTR0_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE0_RTR0_ADD_DEC_SPECIAL_BASE 0x1000007FFC143E80ull +#define DCORE0_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR0_BASE 0x1000007FFC144000ull +#define DCORE0_RTR0_MAX_OFFSET 0x1000 +#define DCORE0_RTR0_SECTION 0x3000 + +#define mmDCORE0_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC144300ull +#define DCORE0_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR0_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC144340ull +#define DCORE0_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC144380ull +#define DCORE0_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR0_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC1443C0ull +#define DCORE0_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC144400ull +#define DCORE0_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR0_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC144440ull +#define DCORE0_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC144480ull +#define DCORE0_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR0_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC1444C0ull +#define DCORE0_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR0_HBW_MFIFO_BASE 0x1000007FFC144500ull +#define DCORE0_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE0_RTR0_E2E_RD_LL_STAT_BASE 0x1000007FFC144540ull +#define DCORE0_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR0_E2E_WR_LL_STAT_BASE 0x1000007FFC144580ull +#define DCORE0_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR0_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE0_RTR0_RTR_HBW_XACT_STAT_BASE 0x1000007FFC144600ull +#define DCORE0_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE0_RTR0_RTR_LBW_XACT_STAT_BASE 0x1000007FFC144680ull +#define DCORE0_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE0_RTR0_RTR_E2E_XACT_STAT_BASE 0x1000007FFC144700ull +#define DCORE0_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE0_RTR0_SPECIAL_BASE 0x1000007FFC144E80ull +#define DCORE0_RTR0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR0_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR0_DBG_ADDR_BASE 0x1000007FFC145000ull +#define DCORE0_RTR0_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE0_RTR0_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE0_RTR0_DBG_ADDR_SPECIAL_BASE 0x1000007FFC145E80ull +#define DCORE0_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE0_RTR1_CTRL_BASE 0x1000007FFC148000ull +#define DCORE0_RTR1_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_RTR1_CTRL_SECTION 0xE800 + +#define mmDCORE0_RTR1_CTRL_SPECIAL_BASE 0x1000007FFC148E80ull +#define DCORE0_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR1_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR1_H3_BASE 0x1000007FFC149000ull +#define DCORE0_RTR1_H3_MAX_OFFSET 0x1000 +#define DCORE0_RTR1_H3_SECTION 0xE800 + +#define mmDCORE0_RTR1_H3_SPECIAL_BASE 0x1000007FFC149E80ull +#define DCORE0_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR1_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC14A000ull +#define DCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE0_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC14A200ull +#define DCORE0_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE0_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC14A400ull +#define DCORE0_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE0_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC14A600ull +#define DCORE0_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE0_RTR1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC14A800ull +#define DCORE0_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE0_RTR1_MSTR_IF_AXUSER_BASE 0x1000007FFC14AA80ull +#define DCORE0_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_RTR1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE0_RTR1_MSTR_IF_DBG_HBW_BASE 0x1000007FFC14AB00ull +#define DCORE0_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_RTR1_MSTR_IF_DBG_LBW_BASE 0x1000007FFC14AB80ull +#define DCORE0_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE0_RTR1_MSTR_IF_CORE_HBW_BASE 0x1000007FFC14AC00ull +#define DCORE0_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE0_RTR1_MSTR_IF_CORE_LBW_BASE 0x1000007FFC14AD80ull +#define DCORE0_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE0_RTR1_MSTR_IF_SPECIAL_BASE 0x1000007FFC14AE80ull +#define DCORE0_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR1_ADD_DEC_HBW_BASE 0x1000007FFC14B000ull +#define DCORE0_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE0_RTR1_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE0_RTR1_ADD_DEC_LBW_BASE 0x1000007FFC14B400ull +#define DCORE0_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE0_RTR1_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE0_RTR1_ADD_DEC_SPECIAL_BASE 0x1000007FFC14BE80ull +#define DCORE0_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR1_BASE 0x1000007FFC14C000ull +#define DCORE0_RTR1_MAX_OFFSET 0x1000 +#define DCORE0_RTR1_SECTION 0x3000 + +#define mmDCORE0_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC14C300ull +#define DCORE0_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR1_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC14C340ull +#define DCORE0_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC14C380ull +#define DCORE0_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR1_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC14C3C0ull +#define DCORE0_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC14C400ull +#define DCORE0_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR1_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC14C440ull +#define DCORE0_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC14C480ull +#define DCORE0_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR1_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC14C4C0ull +#define DCORE0_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR1_HBW_MFIFO_BASE 0x1000007FFC14C500ull +#define DCORE0_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE0_RTR1_E2E_RD_LL_STAT_BASE 0x1000007FFC14C540ull +#define DCORE0_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR1_E2E_WR_LL_STAT_BASE 0x1000007FFC14C580ull +#define DCORE0_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR1_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE0_RTR1_RTR_HBW_XACT_STAT_BASE 0x1000007FFC14C600ull +#define DCORE0_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE0_RTR1_RTR_LBW_XACT_STAT_BASE 0x1000007FFC14C680ull +#define DCORE0_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE0_RTR1_RTR_E2E_XACT_STAT_BASE 0x1000007FFC14C700ull +#define DCORE0_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE0_RTR1_SPECIAL_BASE 0x1000007FFC14CE80ull +#define DCORE0_RTR1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR1_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR1_DBG_ADDR_BASE 0x1000007FFC14D000ull +#define DCORE0_RTR1_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE0_RTR1_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE0_RTR1_DBG_ADDR_SPECIAL_BASE 0x1000007FFC14DE80ull +#define DCORE0_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE0_RTR2_CTRL_BASE 0x1000007FFC150000ull +#define DCORE0_RTR2_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_RTR2_CTRL_SECTION 0xE800 + +#define mmDCORE0_RTR2_CTRL_SPECIAL_BASE 0x1000007FFC150E80ull +#define DCORE0_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR2_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR2_H3_BASE 0x1000007FFC151000ull +#define DCORE0_RTR2_H3_MAX_OFFSET 0x1000 +#define DCORE0_RTR2_H3_SECTION 0xE800 + +#define mmDCORE0_RTR2_H3_SPECIAL_BASE 0x1000007FFC151E80ull +#define DCORE0_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR2_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC152000ull +#define DCORE0_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE0_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC152200ull +#define DCORE0_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE0_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC152400ull +#define DCORE0_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE0_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC152600ull +#define DCORE0_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE0_RTR2_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC152800ull +#define DCORE0_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE0_RTR2_MSTR_IF_AXUSER_BASE 0x1000007FFC152A80ull +#define DCORE0_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_RTR2_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE0_RTR2_MSTR_IF_DBG_HBW_BASE 0x1000007FFC152B00ull +#define DCORE0_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_RTR2_MSTR_IF_DBG_LBW_BASE 0x1000007FFC152B80ull +#define DCORE0_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE0_RTR2_MSTR_IF_CORE_HBW_BASE 0x1000007FFC152C00ull +#define DCORE0_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE0_RTR2_MSTR_IF_CORE_LBW_BASE 0x1000007FFC152D80ull +#define DCORE0_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE0_RTR2_MSTR_IF_SPECIAL_BASE 0x1000007FFC152E80ull +#define DCORE0_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR2_ADD_DEC_HBW_BASE 0x1000007FFC153000ull +#define DCORE0_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE0_RTR2_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE0_RTR2_ADD_DEC_LBW_BASE 0x1000007FFC153400ull +#define DCORE0_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE0_RTR2_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE0_RTR2_ADD_DEC_SPECIAL_BASE 0x1000007FFC153E80ull +#define DCORE0_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR2_BASE 0x1000007FFC154000ull +#define DCORE0_RTR2_MAX_OFFSET 0x1000 +#define DCORE0_RTR2_SECTION 0x3000 + +#define mmDCORE0_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC154300ull +#define DCORE0_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR2_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC154340ull +#define DCORE0_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC154380ull +#define DCORE0_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR2_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC1543C0ull +#define DCORE0_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC154400ull +#define DCORE0_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR2_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC154440ull +#define DCORE0_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC154480ull +#define DCORE0_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR2_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC1544C0ull +#define DCORE0_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR2_HBW_MFIFO_BASE 0x1000007FFC154500ull +#define DCORE0_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE0_RTR2_E2E_RD_LL_STAT_BASE 0x1000007FFC154540ull +#define DCORE0_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR2_E2E_WR_LL_STAT_BASE 0x1000007FFC154580ull +#define DCORE0_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR2_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE0_RTR2_RTR_HBW_XACT_STAT_BASE 0x1000007FFC154600ull +#define DCORE0_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE0_RTR2_RTR_LBW_XACT_STAT_BASE 0x1000007FFC154680ull +#define DCORE0_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE0_RTR2_RTR_E2E_XACT_STAT_BASE 0x1000007FFC154700ull +#define DCORE0_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE0_RTR2_SPECIAL_BASE 0x1000007FFC154E80ull +#define DCORE0_RTR2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR2_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR2_DBG_ADDR_BASE 0x1000007FFC155000ull +#define DCORE0_RTR2_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE0_RTR2_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE0_RTR2_DBG_ADDR_SPECIAL_BASE 0x1000007FFC155E80ull +#define DCORE0_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE0_RTR3_CTRL_BASE 0x1000007FFC158000ull +#define DCORE0_RTR3_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_RTR3_CTRL_SECTION 0xE800 + +#define mmDCORE0_RTR3_CTRL_SPECIAL_BASE 0x1000007FFC158E80ull +#define DCORE0_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR3_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR3_H3_BASE 0x1000007FFC159000ull +#define DCORE0_RTR3_H3_MAX_OFFSET 0x1000 +#define DCORE0_RTR3_H3_SECTION 0xE800 + +#define mmDCORE0_RTR3_H3_SPECIAL_BASE 0x1000007FFC159E80ull +#define DCORE0_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR3_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC15A000ull +#define DCORE0_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE0_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC15A200ull +#define DCORE0_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE0_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC15A400ull +#define DCORE0_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE0_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC15A600ull +#define DCORE0_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE0_RTR3_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC15A800ull +#define DCORE0_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE0_RTR3_MSTR_IF_AXUSER_BASE 0x1000007FFC15AA80ull +#define DCORE0_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_RTR3_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE0_RTR3_MSTR_IF_DBG_HBW_BASE 0x1000007FFC15AB00ull +#define DCORE0_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_RTR3_MSTR_IF_DBG_LBW_BASE 0x1000007FFC15AB80ull +#define DCORE0_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE0_RTR3_MSTR_IF_CORE_HBW_BASE 0x1000007FFC15AC00ull +#define DCORE0_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE0_RTR3_MSTR_IF_CORE_LBW_BASE 0x1000007FFC15AD80ull +#define DCORE0_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE0_RTR3_MSTR_IF_SPECIAL_BASE 0x1000007FFC15AE80ull +#define DCORE0_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR3_ADD_DEC_HBW_BASE 0x1000007FFC15B000ull +#define DCORE0_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE0_RTR3_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE0_RTR3_ADD_DEC_LBW_BASE 0x1000007FFC15B400ull +#define DCORE0_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE0_RTR3_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE0_RTR3_ADD_DEC_SPECIAL_BASE 0x1000007FFC15BE80ull +#define DCORE0_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR3_BASE 0x1000007FFC15C000ull +#define DCORE0_RTR3_MAX_OFFSET 0x1000 +#define DCORE0_RTR3_SECTION 0x3000 + +#define mmDCORE0_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC15C300ull +#define DCORE0_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR3_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC15C340ull +#define DCORE0_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC15C380ull +#define DCORE0_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR3_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC15C3C0ull +#define DCORE0_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC15C400ull +#define DCORE0_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR3_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC15C440ull +#define DCORE0_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC15C480ull +#define DCORE0_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR3_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC15C4C0ull +#define DCORE0_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR3_HBW_MFIFO_BASE 0x1000007FFC15C500ull +#define DCORE0_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE0_RTR3_E2E_RD_LL_STAT_BASE 0x1000007FFC15C540ull +#define DCORE0_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR3_E2E_WR_LL_STAT_BASE 0x1000007FFC15C580ull +#define DCORE0_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR3_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE0_RTR3_RTR_HBW_XACT_STAT_BASE 0x1000007FFC15C600ull +#define DCORE0_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE0_RTR3_RTR_LBW_XACT_STAT_BASE 0x1000007FFC15C680ull +#define DCORE0_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE0_RTR3_RTR_E2E_XACT_STAT_BASE 0x1000007FFC15C700ull +#define DCORE0_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE0_RTR3_SPECIAL_BASE 0x1000007FFC15CE80ull +#define DCORE0_RTR3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR3_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR3_DBG_ADDR_BASE 0x1000007FFC15D000ull +#define DCORE0_RTR3_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE0_RTR3_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE0_RTR3_DBG_ADDR_SPECIAL_BASE 0x1000007FFC15DE80ull +#define DCORE0_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE0_RTR4_CTRL_BASE 0x1000007FFC160000ull +#define DCORE0_RTR4_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_RTR4_CTRL_SECTION 0xE800 + +#define mmDCORE0_RTR4_CTRL_SPECIAL_BASE 0x1000007FFC160E80ull +#define DCORE0_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR4_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR4_H3_BASE 0x1000007FFC161000ull +#define DCORE0_RTR4_H3_MAX_OFFSET 0x1000 +#define DCORE0_RTR4_H3_SECTION 0xE800 + +#define mmDCORE0_RTR4_H3_SPECIAL_BASE 0x1000007FFC161E80ull +#define DCORE0_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR4_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC162000ull +#define DCORE0_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE0_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC162200ull +#define DCORE0_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE0_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC162400ull +#define DCORE0_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE0_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC162600ull +#define DCORE0_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE0_RTR4_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC162800ull +#define DCORE0_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE0_RTR4_MSTR_IF_AXUSER_BASE 0x1000007FFC162A80ull +#define DCORE0_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_RTR4_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE0_RTR4_MSTR_IF_DBG_HBW_BASE 0x1000007FFC162B00ull +#define DCORE0_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_RTR4_MSTR_IF_DBG_LBW_BASE 0x1000007FFC162B80ull +#define DCORE0_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE0_RTR4_MSTR_IF_CORE_HBW_BASE 0x1000007FFC162C00ull +#define DCORE0_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE0_RTR4_MSTR_IF_CORE_LBW_BASE 0x1000007FFC162D80ull +#define DCORE0_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE0_RTR4_MSTR_IF_SPECIAL_BASE 0x1000007FFC162E80ull +#define DCORE0_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR4_ADD_DEC_HBW_BASE 0x1000007FFC163000ull +#define DCORE0_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE0_RTR4_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE0_RTR4_ADD_DEC_LBW_BASE 0x1000007FFC163400ull +#define DCORE0_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE0_RTR4_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE0_RTR4_ADD_DEC_SPECIAL_BASE 0x1000007FFC163E80ull +#define DCORE0_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR4_BASE 0x1000007FFC164000ull +#define DCORE0_RTR4_MAX_OFFSET 0x1000 +#define DCORE0_RTR4_SECTION 0x3000 + +#define mmDCORE0_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC164300ull +#define DCORE0_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR4_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC164340ull +#define DCORE0_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC164380ull +#define DCORE0_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR4_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC1643C0ull +#define DCORE0_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC164400ull +#define DCORE0_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR4_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC164440ull +#define DCORE0_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC164480ull +#define DCORE0_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR4_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC1644C0ull +#define DCORE0_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR4_HBW_MFIFO_BASE 0x1000007FFC164500ull +#define DCORE0_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE0_RTR4_E2E_RD_LL_STAT_BASE 0x1000007FFC164540ull +#define DCORE0_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR4_E2E_WR_LL_STAT_BASE 0x1000007FFC164580ull +#define DCORE0_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR4_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE0_RTR4_RTR_HBW_XACT_STAT_BASE 0x1000007FFC164600ull +#define DCORE0_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE0_RTR4_RTR_LBW_XACT_STAT_BASE 0x1000007FFC164680ull +#define DCORE0_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE0_RTR4_RTR_E2E_XACT_STAT_BASE 0x1000007FFC164700ull +#define DCORE0_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE0_RTR4_SPECIAL_BASE 0x1000007FFC164E80ull +#define DCORE0_RTR4_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR4_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR4_DBG_ADDR_BASE 0x1000007FFC165000ull +#define DCORE0_RTR4_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE0_RTR4_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE0_RTR4_DBG_ADDR_SPECIAL_BASE 0x1000007FFC165E80ull +#define DCORE0_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE0_RTR5_CTRL_BASE 0x1000007FFC168000ull +#define DCORE0_RTR5_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_RTR5_CTRL_SECTION 0xE800 + +#define mmDCORE0_RTR5_CTRL_SPECIAL_BASE 0x1000007FFC168E80ull +#define DCORE0_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR5_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR5_H3_BASE 0x1000007FFC169000ull +#define DCORE0_RTR5_H3_MAX_OFFSET 0x1000 +#define DCORE0_RTR5_H3_SECTION 0xE800 + +#define mmDCORE0_RTR5_H3_SPECIAL_BASE 0x1000007FFC169E80ull +#define DCORE0_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR5_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC16A000ull +#define DCORE0_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE0_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC16A200ull +#define DCORE0_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE0_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC16A400ull +#define DCORE0_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE0_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC16A600ull +#define DCORE0_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE0_RTR5_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC16A800ull +#define DCORE0_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE0_RTR5_MSTR_IF_AXUSER_BASE 0x1000007FFC16AA80ull +#define DCORE0_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_RTR5_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE0_RTR5_MSTR_IF_DBG_HBW_BASE 0x1000007FFC16AB00ull +#define DCORE0_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_RTR5_MSTR_IF_DBG_LBW_BASE 0x1000007FFC16AB80ull +#define DCORE0_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE0_RTR5_MSTR_IF_CORE_HBW_BASE 0x1000007FFC16AC00ull +#define DCORE0_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE0_RTR5_MSTR_IF_CORE_LBW_BASE 0x1000007FFC16AD80ull +#define DCORE0_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE0_RTR5_MSTR_IF_SPECIAL_BASE 0x1000007FFC16AE80ull +#define DCORE0_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR5_ADD_DEC_HBW_BASE 0x1000007FFC16B000ull +#define DCORE0_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE0_RTR5_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE0_RTR5_ADD_DEC_LBW_BASE 0x1000007FFC16B400ull +#define DCORE0_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE0_RTR5_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE0_RTR5_ADD_DEC_SPECIAL_BASE 0x1000007FFC16BE80ull +#define DCORE0_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR5_BASE 0x1000007FFC16C000ull +#define DCORE0_RTR5_MAX_OFFSET 0x1000 +#define DCORE0_RTR5_SECTION 0x3000 + +#define mmDCORE0_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC16C300ull +#define DCORE0_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR5_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC16C340ull +#define DCORE0_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC16C380ull +#define DCORE0_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR5_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC16C3C0ull +#define DCORE0_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC16C400ull +#define DCORE0_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR5_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC16C440ull +#define DCORE0_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC16C480ull +#define DCORE0_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR5_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC16C4C0ull +#define DCORE0_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR5_HBW_MFIFO_BASE 0x1000007FFC16C500ull +#define DCORE0_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE0_RTR5_E2E_RD_LL_STAT_BASE 0x1000007FFC16C540ull +#define DCORE0_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR5_E2E_WR_LL_STAT_BASE 0x1000007FFC16C580ull +#define DCORE0_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR5_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE0_RTR5_RTR_HBW_XACT_STAT_BASE 0x1000007FFC16C600ull +#define DCORE0_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE0_RTR5_RTR_LBW_XACT_STAT_BASE 0x1000007FFC16C680ull +#define DCORE0_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE0_RTR5_RTR_E2E_XACT_STAT_BASE 0x1000007FFC16C700ull +#define DCORE0_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE0_RTR5_SPECIAL_BASE 0x1000007FFC16CE80ull +#define DCORE0_RTR5_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR5_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR5_DBG_ADDR_BASE 0x1000007FFC16D000ull +#define DCORE0_RTR5_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE0_RTR5_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE0_RTR5_DBG_ADDR_SPECIAL_BASE 0x1000007FFC16DE80ull +#define DCORE0_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE0_RTR6_CTRL_BASE 0x1000007FFC170000ull +#define DCORE0_RTR6_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_RTR6_CTRL_SECTION 0xE800 + +#define mmDCORE0_RTR6_CTRL_SPECIAL_BASE 0x1000007FFC170E80ull +#define DCORE0_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR6_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR6_H3_BASE 0x1000007FFC171000ull +#define DCORE0_RTR6_H3_MAX_OFFSET 0x1000 +#define DCORE0_RTR6_H3_SECTION 0xE800 + +#define mmDCORE0_RTR6_H3_SPECIAL_BASE 0x1000007FFC171E80ull +#define DCORE0_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR6_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC172000ull +#define DCORE0_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE0_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC172200ull +#define DCORE0_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE0_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC172400ull +#define DCORE0_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE0_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC172600ull +#define DCORE0_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE0_RTR6_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC172800ull +#define DCORE0_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE0_RTR6_MSTR_IF_AXUSER_BASE 0x1000007FFC172A80ull +#define DCORE0_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_RTR6_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE0_RTR6_MSTR_IF_DBG_HBW_BASE 0x1000007FFC172B00ull +#define DCORE0_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_RTR6_MSTR_IF_DBG_LBW_BASE 0x1000007FFC172B80ull +#define DCORE0_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE0_RTR6_MSTR_IF_CORE_HBW_BASE 0x1000007FFC172C00ull +#define DCORE0_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE0_RTR6_MSTR_IF_CORE_LBW_BASE 0x1000007FFC172D80ull +#define DCORE0_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE0_RTR6_MSTR_IF_SPECIAL_BASE 0x1000007FFC172E80ull +#define DCORE0_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR6_ADD_DEC_HBW_BASE 0x1000007FFC173000ull +#define DCORE0_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE0_RTR6_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE0_RTR6_ADD_DEC_LBW_BASE 0x1000007FFC173400ull +#define DCORE0_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE0_RTR6_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE0_RTR6_ADD_DEC_SPECIAL_BASE 0x1000007FFC173E80ull +#define DCORE0_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR6_BASE 0x1000007FFC174000ull +#define DCORE0_RTR6_MAX_OFFSET 0x1000 +#define DCORE0_RTR6_SECTION 0x3000 + +#define mmDCORE0_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC174300ull +#define DCORE0_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR6_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC174340ull +#define DCORE0_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC174380ull +#define DCORE0_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR6_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC1743C0ull +#define DCORE0_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC174400ull +#define DCORE0_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR6_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC174440ull +#define DCORE0_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC174480ull +#define DCORE0_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR6_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC1744C0ull +#define DCORE0_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR6_HBW_MFIFO_BASE 0x1000007FFC174500ull +#define DCORE0_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE0_RTR6_E2E_RD_LL_STAT_BASE 0x1000007FFC174540ull +#define DCORE0_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR6_E2E_WR_LL_STAT_BASE 0x1000007FFC174580ull +#define DCORE0_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR6_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE0_RTR6_RTR_HBW_XACT_STAT_BASE 0x1000007FFC174600ull +#define DCORE0_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE0_RTR6_RTR_LBW_XACT_STAT_BASE 0x1000007FFC174680ull +#define DCORE0_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE0_RTR6_RTR_E2E_XACT_STAT_BASE 0x1000007FFC174700ull +#define DCORE0_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE0_RTR6_SPECIAL_BASE 0x1000007FFC174E80ull +#define DCORE0_RTR6_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR6_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR6_DBG_ADDR_BASE 0x1000007FFC175000ull +#define DCORE0_RTR6_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE0_RTR6_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE0_RTR6_DBG_ADDR_SPECIAL_BASE 0x1000007FFC175E80ull +#define DCORE0_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE0_RTR7_CTRL_BASE 0x1000007FFC178000ull +#define DCORE0_RTR7_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_RTR7_CTRL_SECTION 0xE800 + +#define mmDCORE0_RTR7_CTRL_SPECIAL_BASE 0x1000007FFC178E80ull +#define DCORE0_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR7_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR7_H3_BASE 0x1000007FFC179000ull +#define DCORE0_RTR7_H3_MAX_OFFSET 0x1000 +#define DCORE0_RTR7_H3_SECTION 0xE800 + +#define mmDCORE0_RTR7_H3_SPECIAL_BASE 0x1000007FFC179E80ull +#define DCORE0_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR7_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC17A000ull +#define DCORE0_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE0_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC17A200ull +#define DCORE0_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE0_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC17A400ull +#define DCORE0_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE0_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC17A600ull +#define DCORE0_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE0_RTR7_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC17A800ull +#define DCORE0_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE0_RTR7_MSTR_IF_AXUSER_BASE 0x1000007FFC17AA80ull +#define DCORE0_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_RTR7_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE0_RTR7_MSTR_IF_DBG_HBW_BASE 0x1000007FFC17AB00ull +#define DCORE0_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_RTR7_MSTR_IF_DBG_LBW_BASE 0x1000007FFC17AB80ull +#define DCORE0_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE0_RTR7_MSTR_IF_CORE_HBW_BASE 0x1000007FFC17AC00ull +#define DCORE0_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE0_RTR7_MSTR_IF_CORE_LBW_BASE 0x1000007FFC17AD80ull +#define DCORE0_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE0_RTR7_MSTR_IF_SPECIAL_BASE 0x1000007FFC17AE80ull +#define DCORE0_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR7_ADD_DEC_HBW_BASE 0x1000007FFC17B000ull +#define DCORE0_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE0_RTR7_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE0_RTR7_ADD_DEC_LBW_BASE 0x1000007FFC17B400ull +#define DCORE0_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE0_RTR7_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE0_RTR7_ADD_DEC_SPECIAL_BASE 0x1000007FFC17BE80ull +#define DCORE0_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR7_BASE 0x1000007FFC17C000ull +#define DCORE0_RTR7_MAX_OFFSET 0x1000 +#define DCORE0_RTR7_SECTION 0x3000 + +#define mmDCORE0_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC17C300ull +#define DCORE0_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR7_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC17C340ull +#define DCORE0_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC17C380ull +#define DCORE0_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR7_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC17C3C0ull +#define DCORE0_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC17C400ull +#define DCORE0_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR7_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC17C440ull +#define DCORE0_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC17C480ull +#define DCORE0_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR7_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC17C4C0ull +#define DCORE0_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR7_HBW_MFIFO_BASE 0x1000007FFC17C500ull +#define DCORE0_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE0_RTR7_E2E_RD_LL_STAT_BASE 0x1000007FFC17C540ull +#define DCORE0_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE0_RTR7_E2E_WR_LL_STAT_BASE 0x1000007FFC17C580ull +#define DCORE0_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE0_RTR7_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE0_RTR7_RTR_HBW_XACT_STAT_BASE 0x1000007FFC17C600ull +#define DCORE0_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE0_RTR7_RTR_LBW_XACT_STAT_BASE 0x1000007FFC17C680ull +#define DCORE0_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE0_RTR7_RTR_E2E_XACT_STAT_BASE 0x1000007FFC17C700ull +#define DCORE0_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE0_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE0_RTR7_SPECIAL_BASE 0x1000007FFC17CE80ull +#define DCORE0_RTR7_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR7_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_RTR7_DBG_ADDR_BASE 0x1000007FFC17D000ull +#define DCORE0_RTR7_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE0_RTR7_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE0_RTR7_DBG_ADDR_SPECIAL_BASE 0x1000007FFC17DE80ull +#define DCORE0_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE0_SRAM0_BANK_BASE 0x1000007FFC180000ull +#define DCORE0_SRAM0_BANK_MAX_OFFSET 0x1000 +#define DCORE0_SRAM0_BANK_SECTION 0xE800 + +#define mmDCORE0_SRAM0_BANK_SPECIAL_BASE 0x1000007FFC180E80ull +#define DCORE0_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM0_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_SRAM0_RTR_BASE 0x1000007FFC181000ull +#define DCORE0_SRAM0_RTR_MAX_OFFSET 0x1000 +#define DCORE0_SRAM0_RTR_SECTION 0xE800 + +#define mmDCORE0_SRAM0_RTR_SPECIAL_BASE 0x1000007FFC181E80ull +#define DCORE0_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM0_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC182000ull +#define DCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC182100ull +#define DCORE0_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC182200ull +#define DCORE0_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC182300ull +#define DCORE0_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC182400ull +#define DCORE0_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC182500ull +#define DCORE0_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC182600ull +#define DCORE0_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC182700ull +#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC182780ull +#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC182800ull +#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC182880ull +#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC182900ull +#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC182980ull +#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC182A00ull +#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC182A80ull +#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE0_SRAM0_DBG_CNT_SPECIAL_BASE 0x1000007FFC182E80ull +#define DCORE0_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE0_SRAM1_BANK_BASE 0x1000007FFC188000ull +#define DCORE0_SRAM1_BANK_MAX_OFFSET 0x1000 +#define DCORE0_SRAM1_BANK_SECTION 0xE800 + +#define mmDCORE0_SRAM1_BANK_SPECIAL_BASE 0x1000007FFC188E80ull +#define DCORE0_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM1_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_SRAM1_RTR_BASE 0x1000007FFC189000ull +#define DCORE0_SRAM1_RTR_MAX_OFFSET 0x1000 +#define DCORE0_SRAM1_RTR_SECTION 0xE800 + +#define mmDCORE0_SRAM1_RTR_SPECIAL_BASE 0x1000007FFC189E80ull +#define DCORE0_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM1_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC18A000ull +#define DCORE0_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC18A100ull +#define DCORE0_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC18A200ull +#define DCORE0_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC18A300ull +#define DCORE0_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC18A400ull +#define DCORE0_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC18A500ull +#define DCORE0_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC18A600ull +#define DCORE0_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC18A700ull +#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC18A780ull +#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC18A800ull +#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC18A880ull +#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC18A900ull +#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC18A980ull +#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC18AA00ull +#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC18AA80ull +#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE0_SRAM1_DBG_CNT_SPECIAL_BASE 0x1000007FFC18AE80ull +#define DCORE0_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE0_SRAM2_BANK_BASE 0x1000007FFC190000ull +#define DCORE0_SRAM2_BANK_MAX_OFFSET 0x1000 +#define DCORE0_SRAM2_BANK_SECTION 0xE800 + +#define mmDCORE0_SRAM2_BANK_SPECIAL_BASE 0x1000007FFC190E80ull +#define DCORE0_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM2_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_SRAM2_RTR_BASE 0x1000007FFC191000ull +#define DCORE0_SRAM2_RTR_MAX_OFFSET 0x1000 +#define DCORE0_SRAM2_RTR_SECTION 0xE800 + +#define mmDCORE0_SRAM2_RTR_SPECIAL_BASE 0x1000007FFC191E80ull +#define DCORE0_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM2_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC192000ull +#define DCORE0_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC192100ull +#define DCORE0_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC192200ull +#define DCORE0_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC192300ull +#define DCORE0_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC192400ull +#define DCORE0_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC192500ull +#define DCORE0_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC192600ull +#define DCORE0_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC192700ull +#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC192780ull +#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC192800ull +#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC192880ull +#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC192900ull +#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC192980ull +#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC192A00ull +#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC192A80ull +#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE0_SRAM2_DBG_CNT_SPECIAL_BASE 0x1000007FFC192E80ull +#define DCORE0_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE0_SRAM3_BANK_BASE 0x1000007FFC198000ull +#define DCORE0_SRAM3_BANK_MAX_OFFSET 0x1000 +#define DCORE0_SRAM3_BANK_SECTION 0xE800 + +#define mmDCORE0_SRAM3_BANK_SPECIAL_BASE 0x1000007FFC198E80ull +#define DCORE0_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM3_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_SRAM3_RTR_BASE 0x1000007FFC199000ull +#define DCORE0_SRAM3_RTR_MAX_OFFSET 0x1000 +#define DCORE0_SRAM3_RTR_SECTION 0xE800 + +#define mmDCORE0_SRAM3_RTR_SPECIAL_BASE 0x1000007FFC199E80ull +#define DCORE0_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM3_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC19A000ull +#define DCORE0_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC19A100ull +#define DCORE0_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC19A200ull +#define DCORE0_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC19A300ull +#define DCORE0_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC19A400ull +#define DCORE0_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC19A500ull +#define DCORE0_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC19A600ull +#define DCORE0_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC19A700ull +#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC19A780ull +#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC19A800ull +#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC19A880ull +#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC19A900ull +#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC19A980ull +#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC19AA00ull +#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC19AA80ull +#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE0_SRAM3_DBG_CNT_SPECIAL_BASE 0x1000007FFC19AE80ull +#define DCORE0_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE0_SRAM4_BANK_BASE 0x1000007FFC1A0000ull +#define DCORE0_SRAM4_BANK_MAX_OFFSET 0x1000 +#define DCORE0_SRAM4_BANK_SECTION 0xE800 + +#define mmDCORE0_SRAM4_BANK_SPECIAL_BASE 0x1000007FFC1A0E80ull +#define DCORE0_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM4_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_SRAM4_RTR_BASE 0x1000007FFC1A1000ull +#define DCORE0_SRAM4_RTR_MAX_OFFSET 0x1000 +#define DCORE0_SRAM4_RTR_SECTION 0xE800 + +#define mmDCORE0_SRAM4_RTR_SPECIAL_BASE 0x1000007FFC1A1E80ull +#define DCORE0_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM4_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC1A2000ull +#define DCORE0_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC1A2100ull +#define DCORE0_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC1A2200ull +#define DCORE0_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC1A2300ull +#define DCORE0_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC1A2400ull +#define DCORE0_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC1A2500ull +#define DCORE0_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC1A2600ull +#define DCORE0_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC1A2700ull +#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC1A2780ull +#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC1A2800ull +#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC1A2880ull +#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC1A2900ull +#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC1A2980ull +#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC1A2A00ull +#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC1A2A80ull +#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE0_SRAM4_DBG_CNT_SPECIAL_BASE 0x1000007FFC1A2E80ull +#define DCORE0_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE0_SRAM5_BANK_BASE 0x1000007FFC1A8000ull +#define DCORE0_SRAM5_BANK_MAX_OFFSET 0x1000 +#define DCORE0_SRAM5_BANK_SECTION 0xE800 + +#define mmDCORE0_SRAM5_BANK_SPECIAL_BASE 0x1000007FFC1A8E80ull +#define DCORE0_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM5_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_SRAM5_RTR_BASE 0x1000007FFC1A9000ull +#define DCORE0_SRAM5_RTR_MAX_OFFSET 0x1000 +#define DCORE0_SRAM5_RTR_SECTION 0xE800 + +#define mmDCORE0_SRAM5_RTR_SPECIAL_BASE 0x1000007FFC1A9E80ull +#define DCORE0_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM5_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC1AA000ull +#define DCORE0_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC1AA100ull +#define DCORE0_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC1AA200ull +#define DCORE0_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC1AA300ull +#define DCORE0_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC1AA400ull +#define DCORE0_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC1AA500ull +#define DCORE0_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC1AA600ull +#define DCORE0_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC1AA700ull +#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC1AA780ull +#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC1AA800ull +#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC1AA880ull +#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC1AA900ull +#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC1AA980ull +#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC1AAA00ull +#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC1AAA80ull +#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE0_SRAM5_DBG_CNT_SPECIAL_BASE 0x1000007FFC1AAE80ull +#define DCORE0_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE0_SRAM6_BANK_BASE 0x1000007FFC1B0000ull +#define DCORE0_SRAM6_BANK_MAX_OFFSET 0x1000 +#define DCORE0_SRAM6_BANK_SECTION 0xE800 + +#define mmDCORE0_SRAM6_BANK_SPECIAL_BASE 0x1000007FFC1B0E80ull +#define DCORE0_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM6_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_SRAM6_RTR_BASE 0x1000007FFC1B1000ull +#define DCORE0_SRAM6_RTR_MAX_OFFSET 0x1000 +#define DCORE0_SRAM6_RTR_SECTION 0xE800 + +#define mmDCORE0_SRAM6_RTR_SPECIAL_BASE 0x1000007FFC1B1E80ull +#define DCORE0_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM6_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC1B2000ull +#define DCORE0_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC1B2100ull +#define DCORE0_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC1B2200ull +#define DCORE0_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC1B2300ull +#define DCORE0_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC1B2400ull +#define DCORE0_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC1B2500ull +#define DCORE0_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC1B2600ull +#define DCORE0_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC1B2700ull +#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC1B2780ull +#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC1B2800ull +#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC1B2880ull +#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC1B2900ull +#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC1B2980ull +#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC1B2A00ull +#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC1B2A80ull +#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE0_SRAM6_DBG_CNT_SPECIAL_BASE 0x1000007FFC1B2E80ull +#define DCORE0_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE0_SRAM7_BANK_BASE 0x1000007FFC1B8000ull +#define DCORE0_SRAM7_BANK_MAX_OFFSET 0x1000 +#define DCORE0_SRAM7_BANK_SECTION 0xE800 + +#define mmDCORE0_SRAM7_BANK_SPECIAL_BASE 0x1000007FFC1B8E80ull +#define DCORE0_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM7_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_SRAM7_RTR_BASE 0x1000007FFC1B9000ull +#define DCORE0_SRAM7_RTR_MAX_OFFSET 0x1000 +#define DCORE0_SRAM7_RTR_SECTION 0xE800 + +#define mmDCORE0_SRAM7_RTR_SPECIAL_BASE 0x1000007FFC1B9E80ull +#define DCORE0_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM7_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC1BA000ull +#define DCORE0_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC1BA100ull +#define DCORE0_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC1BA200ull +#define DCORE0_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC1BA300ull +#define DCORE0_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC1BA400ull +#define DCORE0_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC1BA500ull +#define DCORE0_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC1BA600ull +#define DCORE0_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE0_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE0_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC1BA700ull +#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC1BA780ull +#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC1BA800ull +#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC1BA880ull +#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC1BA900ull +#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC1BA980ull +#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC1BAA00ull +#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE0_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC1BAA80ull +#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE0_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE0_SRAM7_DBG_CNT_SPECIAL_BASE 0x1000007FFC1BAE80ull +#define DCORE0_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE0_EDMA0_QM_DCCM_BASE 0x1000007FFC1C0000ull +#define DCORE0_EDMA0_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_EDMA0_QM_DCCM_SECTION 0x8000 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_BASE 0x1000007FFC1C8000ull +#define DCORE0_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE0_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC1C8E80ull +#define DCORE0_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE0_EDMA0_QM_BASE 0x1000007FFC1CA000ull +#define DCORE0_EDMA0_QM_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_QM_SECTION 0x9000 + +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC1CA900ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC1CA908ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC1CA910ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC1CA918ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC1CA920ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC1CA928ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC1CA930ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC1CA938ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC1CA940ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC1CA948ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC1CA950ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC1CA958ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC1CA960ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC1CA968ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC1CA970ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC1CA978ull +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE0_EDMA0_QM_AXUSER_SECURED_BASE 0x1000007FFC1CAB00ull +#define DCORE0_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_BASE 0x1000007FFC1CAB80ull +#define DCORE0_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE0_EDMA0_QM_DBG_HBW_BASE 0x1000007FFC1CAC00ull +#define DCORE0_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_EDMA0_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_EDMA0_QM_DBG_LBW_BASE 0x1000007FFC1CAC80ull +#define DCORE0_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_EDMA0_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE0_EDMA0_QM_CGM_BASE 0x1000007FFC1CAD80ull +#define DCORE0_EDMA0_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_EDMA0_QM_CGM_SECTION 0x1000 + +#define mmDCORE0_EDMA0_QM_SPECIAL_BASE 0x1000007FFC1CAE80ull +#define DCORE0_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_EDMA0_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_EDMA0_CORE_BASE 0x1000007FFC1CB000ull +#define DCORE0_EDMA0_CORE_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_CORE_SECTION 0x8000 + +#define mmDCORE0_EDMA0_CORE_CTX_AXUSER_BASE 0x1000007FFC1CB800ull +#define DCORE0_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000 + +#define mmDCORE0_EDMA0_CORE_CTX_BASE 0x1000007FFC1CB860ull +#define DCORE0_EDMA0_CORE_CTX_MAX_OFFSET 0x9000 +#define DCORE0_EDMA0_CORE_CTX_SECTION 0x5A00 + +#define mmDCORE0_EDMA0_CORE_KDMA_CGM_BASE 0x1000007FFC1CBE00ull +#define DCORE0_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define DCORE0_EDMA0_CORE_KDMA_CGM_SECTION 0x8000 + +#define mmDCORE0_EDMA0_CORE_SPECIAL_BASE 0x1000007FFC1CBE80ull +#define DCORE0_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_EDMA0_CORE_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC1CC000ull +#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE0_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC1CC200ull +#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE0_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC1CC400ull +#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE0_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC1CC600ull +#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE0_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC1CC800ull +#define DCORE0_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE0_EDMA0_MSTR_IF_AXUSER_BASE 0x1000007FFC1CCA80ull +#define DCORE0_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE0_EDMA0_MSTR_IF_DBG_HBW_BASE 0x1000007FFC1CCB00ull +#define DCORE0_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_EDMA0_MSTR_IF_DBG_LBW_BASE 0x1000007FFC1CCB80ull +#define DCORE0_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE0_EDMA0_MSTR_IF_CORE_HBW_BASE 0x1000007FFC1CCC00ull +#define DCORE0_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE0_EDMA0_MSTR_IF_CORE_LBW_BASE 0x1000007FFC1CCD80ull +#define DCORE0_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE0_EDMA0_MSTR_IF_SPECIAL_BASE 0x1000007FFC1CCE80ull +#define DCORE0_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE0_EDMA1_QM_DCCM_BASE 0x1000007FFC1D0000ull +#define DCORE0_EDMA1_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE0_EDMA1_QM_DCCM_SECTION 0x8000 + +#define mmDCORE0_EDMA1_QM_ARC_AUX_BASE 0x1000007FFC1D8000ull +#define DCORE0_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE0_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC1D8E80ull +#define DCORE0_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE0_EDMA1_QM_BASE 0x1000007FFC1DA000ull +#define DCORE0_EDMA1_QM_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_QM_SECTION 0x9000 + +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC1DA900ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC1DA908ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC1DA910ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC1DA918ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC1DA920ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC1DA928ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC1DA930ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC1DA938ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC1DA940ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC1DA948ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC1DA950ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC1DA958ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC1DA960ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC1DA968ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC1DA970ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC1DA978ull +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE0_EDMA1_QM_AXUSER_SECURED_BASE 0x1000007FFC1DAB00ull +#define DCORE0_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE0_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_BASE 0x1000007FFC1DAB80ull +#define DCORE0_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE0_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE0_EDMA1_QM_DBG_HBW_BASE 0x1000007FFC1DAC00ull +#define DCORE0_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_EDMA1_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_EDMA1_QM_DBG_LBW_BASE 0x1000007FFC1DAC80ull +#define DCORE0_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_EDMA1_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE0_EDMA1_QM_CGM_BASE 0x1000007FFC1DAD80ull +#define DCORE0_EDMA1_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE0_EDMA1_QM_CGM_SECTION 0x1000 + +#define mmDCORE0_EDMA1_QM_SPECIAL_BASE 0x1000007FFC1DAE80ull +#define DCORE0_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_EDMA1_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_EDMA1_CORE_BASE 0x1000007FFC1DB000ull +#define DCORE0_EDMA1_CORE_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_CORE_SECTION 0x8000 + +#define mmDCORE0_EDMA1_CORE_CTX_AXUSER_BASE 0x1000007FFC1DB800ull +#define DCORE0_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000 + +#define mmDCORE0_EDMA1_CORE_CTX_BASE 0x1000007FFC1DB860ull +#define DCORE0_EDMA1_CORE_CTX_MAX_OFFSET 0x9000 +#define DCORE0_EDMA1_CORE_CTX_SECTION 0x5A00 + +#define mmDCORE0_EDMA1_CORE_KDMA_CGM_BASE 0x1000007FFC1DBE00ull +#define DCORE0_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define DCORE0_EDMA1_CORE_KDMA_CGM_SECTION 0x8000 + +#define mmDCORE0_EDMA1_CORE_SPECIAL_BASE 0x1000007FFC1DBE80ull +#define DCORE0_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_EDMA1_CORE_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC1DC000ull +#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE0_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC1DC200ull +#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE0_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC1DC400ull +#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE0_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC1DC600ull +#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE0_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC1DC800ull +#define DCORE0_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE0_EDMA1_MSTR_IF_AXUSER_BASE 0x1000007FFC1DCA80ull +#define DCORE0_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE0_EDMA1_MSTR_IF_DBG_HBW_BASE 0x1000007FFC1DCB00ull +#define DCORE0_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_EDMA1_MSTR_IF_DBG_LBW_BASE 0x1000007FFC1DCB80ull +#define DCORE0_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE0_EDMA1_MSTR_IF_CORE_HBW_BASE 0x1000007FFC1DCC00ull +#define DCORE0_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE0_EDMA1_MSTR_IF_CORE_LBW_BASE 0x1000007FFC1DCD80ull +#define DCORE0_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE0_EDMA1_MSTR_IF_SPECIAL_BASE 0x1000007FFC1DCE80ull +#define DCORE0_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE0_DEC0_CMD_BASE 0x1000007FFC1E0000ull +#define DCORE0_DEC0_CMD_MAX_OFFSET 0x1100 +#define DCORE0_DEC0_CMD_SECTION 0x1000 + +#define mmDCORE0_DEC0_VSI_BASE 0x1000007FFC1E1000ull +#define DCORE0_DEC0_VSI_MAX_OFFSET 0x6FC0 +#define DCORE0_DEC0_VSI_SECTION 0x1000 + +#define mmDCORE0_DEC0_L2C_BASE 0x1000007FFC1E2000ull +#define DCORE0_DEC0_L2C_MAX_OFFSET 0x39C0 +#define DCORE0_DEC0_L2C_SECTION 0x1000 + +#define mmDCORE0_VDEC0_BRDG_CTRL_BASE 0x1000007FFC1E3000ull +#define DCORE0_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_BRDG_CTRL_SECTION 0x8000 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x1000007FFC1E3800ull +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x1000007FFC1E3900ull +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x1000007FFC1E3A00ull +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x1000007FFC1E3B00ull +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 + +#define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x1000007FFC1E3C00ull +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 + +#define mmDCORE0_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x1000007FFC1E3E80ull +#define DCORE0_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_VDEC0_CTRL_BASE 0x1000007FFC1E4000ull +#define DCORE0_VDEC0_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_CTRL_SECTION 0xE800 + +#define mmDCORE0_VDEC0_CTRL_SPECIAL_BASE 0x1000007FFC1E4E80ull +#define DCORE0_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_VDEC0_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC1E5000ull +#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE0_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC1E5200ull +#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE0_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC1E5400ull +#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE0_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC1E5600ull +#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE0_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC1E5800ull +#define DCORE0_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE0_VDEC0_MSTR_IF_AXUSER_BASE 0x1000007FFC1E5A80ull +#define DCORE0_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE0_VDEC0_MSTR_IF_DBG_HBW_BASE 0x1000007FFC1E5B00ull +#define DCORE0_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_VDEC0_MSTR_IF_DBG_LBW_BASE 0x1000007FFC1E5B80ull +#define DCORE0_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE0_VDEC0_MSTR_IF_CORE_HBW_BASE 0x1000007FFC1E5C00ull +#define DCORE0_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE0_VDEC0_MSTR_IF_CORE_LBW_BASE 0x1000007FFC1E5D80ull +#define DCORE0_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE0_VDEC0_MSTR_IF_SPECIAL_BASE 0x1000007FFC1E5E80ull +#define DCORE0_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180 + +#define mmDCORE0_DEC1_CMD_BASE 0x1000007FFC1F0000ull +#define DCORE0_DEC1_CMD_MAX_OFFSET 0x1100 +#define DCORE0_DEC1_CMD_SECTION 0x1000 + +#define mmDCORE0_DEC1_VSI_BASE 0x1000007FFC1F1000ull +#define DCORE0_DEC1_VSI_MAX_OFFSET 0x6FC0 +#define DCORE0_DEC1_VSI_SECTION 0x1000 + +#define mmDCORE0_DEC1_L2C_BASE 0x1000007FFC1F2000ull +#define DCORE0_DEC1_L2C_MAX_OFFSET 0x39C0 +#define DCORE0_DEC1_L2C_SECTION 0x1000 + +#define mmDCORE0_VDEC1_BRDG_CTRL_BASE 0x1000007FFC1F3000ull +#define DCORE0_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_BRDG_CTRL_SECTION 0x8000 + +#define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x1000007FFC1F3800ull +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 + +#define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x1000007FFC1F3900ull +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 + +#define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x1000007FFC1F3A00ull +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 + +#define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x1000007FFC1F3B00ull +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 + +#define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x1000007FFC1F3C00ull +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define DCORE0_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 + +#define mmDCORE0_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x1000007FFC1F3E80ull +#define DCORE0_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_VDEC1_CTRL_BASE 0x1000007FFC1F4000ull +#define DCORE0_VDEC1_CTRL_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_CTRL_SECTION 0xE800 + +#define mmDCORE0_VDEC1_CTRL_SPECIAL_BASE 0x1000007FFC1F4E80ull +#define DCORE0_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_VDEC1_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC1F5000ull +#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE0_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC1F5200ull +#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE0_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC1F5400ull +#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE0_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC1F5600ull +#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE0_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE0_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC1F5800ull +#define DCORE0_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE0_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE0_VDEC1_MSTR_IF_AXUSER_BASE 0x1000007FFC1F5A80ull +#define DCORE0_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE0_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE0_VDEC1_MSTR_IF_DBG_HBW_BASE 0x1000007FFC1F5B00ull +#define DCORE0_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE0_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE0_VDEC1_MSTR_IF_DBG_LBW_BASE 0x1000007FFC1F5B80ull +#define DCORE0_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE0_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE0_VDEC1_MSTR_IF_CORE_HBW_BASE 0x1000007FFC1F5C00ull +#define DCORE0_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE0_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE0_VDEC1_MSTR_IF_CORE_LBW_BASE 0x1000007FFC1F5D80ull +#define DCORE0_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE0_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE0_VDEC1_MSTR_IF_SPECIAL_BASE 0x1000007FFC1F5E80ull +#define DCORE0_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180 + +#define mmDCORE1_TPC0_QM_DCCM_BASE 0x1000007FFC200000ull +#define DCORE1_TPC0_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC0_QM_DCCM_SECTION 0x8000 + +#define mmDCORE1_TPC0_QM_ARC_AUX_BASE 0x1000007FFC208000ull +#define DCORE1_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE1_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC208E80ull +#define DCORE1_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE1_TPC0_QM_BASE 0x1000007FFC20A000ull +#define DCORE1_TPC0_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_QM_SECTION 0x9000 + +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC20A900ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC20A908ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC20A910ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC20A918ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC20A920ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC20A928ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC20A930ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC20A938ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC20A940ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC20A948ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC20A950ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC20A958ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC20A960ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC20A968ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC20A970ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC20A978ull +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE1_TPC0_QM_AXUSER_SECURED_BASE 0x1000007FFC20AB00ull +#define DCORE1_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE1_TPC0_QM_AXUSER_NONSECURED_BASE 0x1000007FFC20AB80ull +#define DCORE1_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE1_TPC0_QM_DBG_HBW_BASE 0x1000007FFC20AC00ull +#define DCORE1_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC0_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_TPC0_QM_DBG_LBW_BASE 0x1000007FFC20AC80ull +#define DCORE1_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC0_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE1_TPC0_QM_CGM_BASE 0x1000007FFC20AD80ull +#define DCORE1_TPC0_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC0_QM_CGM_SECTION 0x1000 + +#define mmDCORE1_TPC0_QM_SPECIAL_BASE 0x1000007FFC20AE80ull +#define DCORE1_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC0_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFC20B000ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC0_CFG_BASE 0x1000007FFC20B000ull +#define DCORE1_TPC0_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC0_CFG_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFC20B050ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFC20B0A0ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFC20B0F0ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFC20B140ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFC20B190ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFC20B1E0ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFC20B230ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFC20B280ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFC20B2D0ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFC20B320ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFC20B370ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFC20B3C0ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFC20B410ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFC20B460ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFC20B4B0ull +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFC20B500ull +#define DCORE1_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE1_TPC0_CFG_KERNEL_BASE 0x1000007FFC20B508ull +#define DCORE1_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC0_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE1_TPC0_CFG_QM_TENSOR_0_BASE 0x1000007FFC20B5DCull +#define DCORE1_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_QM_TENSOR_1_BASE 0x1000007FFC20B62Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_QM_TENSOR_2_BASE 0x1000007FFC20B67Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_QM_TENSOR_3_BASE 0x1000007FFC20B6CCull +#define DCORE1_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_QM_TENSOR_4_BASE 0x1000007FFC20B71Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_QM_TENSOR_5_BASE 0x1000007FFC20B76Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_QM_TENSOR_6_BASE 0x1000007FFC20B7BCull +#define DCORE1_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_QM_TENSOR_7_BASE 0x1000007FFC20B80Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_QM_TENSOR_8_BASE 0x1000007FFC20B85Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_QM_TENSOR_9_BASE 0x1000007FFC20B8ACull +#define DCORE1_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_QM_TENSOR_10_BASE 0x1000007FFC20B8FCull +#define DCORE1_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_QM_TENSOR_11_BASE 0x1000007FFC20B94Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_QM_TENSOR_12_BASE 0x1000007FFC20B99Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_QM_TENSOR_13_BASE 0x1000007FFC20B9ECull +#define DCORE1_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_QM_TENSOR_14_BASE 0x1000007FFC20BA3Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_QM_TENSOR_15_BASE 0x1000007FFC20BA8Cull +#define DCORE1_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE1_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFC20BADCull +#define DCORE1_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE1_TPC0_CFG_QM_BASE 0x1000007FFC20BAE4ull +#define DCORE1_TPC0_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC0_CFG_QM_SECTION 0x31C0 + +#define mmDCORE1_TPC0_CFG_AXUSER_BASE 0x1000007FFC20BE00ull +#define DCORE1_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE1_TPC0_CFG_SPECIAL_BASE 0x1000007FFC20BE80ull +#define DCORE1_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC0_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC20C000ull +#define DCORE1_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE1_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC20C200ull +#define DCORE1_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE1_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC20C400ull +#define DCORE1_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE1_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC20C600ull +#define DCORE1_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE1_TPC0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC20C800ull +#define DCORE1_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE1_TPC0_MSTR_IF_AXUSER_BASE 0x1000007FFC20CA80ull +#define DCORE1_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE1_TPC0_MSTR_IF_DBG_HBW_BASE 0x1000007FFC20CB00ull +#define DCORE1_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_TPC0_MSTR_IF_DBG_LBW_BASE 0x1000007FFC20CB80ull +#define DCORE1_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE1_TPC0_MSTR_IF_CORE_HBW_BASE 0x1000007FFC20CC00ull +#define DCORE1_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE1_TPC0_MSTR_IF_CORE_LBW_BASE 0x1000007FFC20CD80ull +#define DCORE1_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE1_TPC0_MSTR_IF_SPECIAL_BASE 0x1000007FFC20CE80ull +#define DCORE1_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE1_TPC1_QM_DCCM_BASE 0x1000007FFC210000ull +#define DCORE1_TPC1_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC1_QM_DCCM_SECTION 0x8000 + +#define mmDCORE1_TPC1_QM_ARC_AUX_BASE 0x1000007FFC218000ull +#define DCORE1_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE1_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC218E80ull +#define DCORE1_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE1_TPC1_QM_BASE 0x1000007FFC21A000ull +#define DCORE1_TPC1_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_QM_SECTION 0x9000 + +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC21A900ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC21A908ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC21A910ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC21A918ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC21A920ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC21A928ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC21A930ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC21A938ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC21A940ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC21A948ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC21A950ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC21A958ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC21A960ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC21A968ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC21A970ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC21A978ull +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE1_TPC1_QM_AXUSER_SECURED_BASE 0x1000007FFC21AB00ull +#define DCORE1_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE1_TPC1_QM_AXUSER_NONSECURED_BASE 0x1000007FFC21AB80ull +#define DCORE1_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE1_TPC1_QM_DBG_HBW_BASE 0x1000007FFC21AC00ull +#define DCORE1_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC1_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_TPC1_QM_DBG_LBW_BASE 0x1000007FFC21AC80ull +#define DCORE1_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC1_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE1_TPC1_QM_CGM_BASE 0x1000007FFC21AD80ull +#define DCORE1_TPC1_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC1_QM_CGM_SECTION 0x1000 + +#define mmDCORE1_TPC1_QM_SPECIAL_BASE 0x1000007FFC21AE80ull +#define DCORE1_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC1_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFC21B000ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC1_CFG_BASE 0x1000007FFC21B000ull +#define DCORE1_TPC1_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC1_CFG_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFC21B050ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFC21B0A0ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFC21B0F0ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFC21B140ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFC21B190ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFC21B1E0ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFC21B230ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFC21B280ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFC21B2D0ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFC21B320ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFC21B370ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFC21B3C0ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFC21B410ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFC21B460ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFC21B4B0ull +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFC21B500ull +#define DCORE1_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE1_TPC1_CFG_KERNEL_BASE 0x1000007FFC21B508ull +#define DCORE1_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC1_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE1_TPC1_CFG_QM_TENSOR_0_BASE 0x1000007FFC21B5DCull +#define DCORE1_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_QM_TENSOR_1_BASE 0x1000007FFC21B62Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_QM_TENSOR_2_BASE 0x1000007FFC21B67Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_QM_TENSOR_3_BASE 0x1000007FFC21B6CCull +#define DCORE1_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_QM_TENSOR_4_BASE 0x1000007FFC21B71Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_QM_TENSOR_5_BASE 0x1000007FFC21B76Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_QM_TENSOR_6_BASE 0x1000007FFC21B7BCull +#define DCORE1_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_QM_TENSOR_7_BASE 0x1000007FFC21B80Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_QM_TENSOR_8_BASE 0x1000007FFC21B85Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_QM_TENSOR_9_BASE 0x1000007FFC21B8ACull +#define DCORE1_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_QM_TENSOR_10_BASE 0x1000007FFC21B8FCull +#define DCORE1_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_QM_TENSOR_11_BASE 0x1000007FFC21B94Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_QM_TENSOR_12_BASE 0x1000007FFC21B99Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_QM_TENSOR_13_BASE 0x1000007FFC21B9ECull +#define DCORE1_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_QM_TENSOR_14_BASE 0x1000007FFC21BA3Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_QM_TENSOR_15_BASE 0x1000007FFC21BA8Cull +#define DCORE1_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE1_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFC21BADCull +#define DCORE1_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE1_TPC1_CFG_QM_BASE 0x1000007FFC21BAE4ull +#define DCORE1_TPC1_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC1_CFG_QM_SECTION 0x31C0 + +#define mmDCORE1_TPC1_CFG_AXUSER_BASE 0x1000007FFC21BE00ull +#define DCORE1_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE1_TPC1_CFG_SPECIAL_BASE 0x1000007FFC21BE80ull +#define DCORE1_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC1_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC21C000ull +#define DCORE1_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE1_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC21C200ull +#define DCORE1_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE1_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC21C400ull +#define DCORE1_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE1_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC21C600ull +#define DCORE1_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE1_TPC1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC21C800ull +#define DCORE1_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE1_TPC1_MSTR_IF_AXUSER_BASE 0x1000007FFC21CA80ull +#define DCORE1_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE1_TPC1_MSTR_IF_DBG_HBW_BASE 0x1000007FFC21CB00ull +#define DCORE1_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_TPC1_MSTR_IF_DBG_LBW_BASE 0x1000007FFC21CB80ull +#define DCORE1_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE1_TPC1_MSTR_IF_CORE_HBW_BASE 0x1000007FFC21CC00ull +#define DCORE1_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE1_TPC1_MSTR_IF_CORE_LBW_BASE 0x1000007FFC21CD80ull +#define DCORE1_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE1_TPC1_MSTR_IF_SPECIAL_BASE 0x1000007FFC21CE80ull +#define DCORE1_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE1_TPC2_QM_DCCM_BASE 0x1000007FFC220000ull +#define DCORE1_TPC2_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC2_QM_DCCM_SECTION 0x8000 + +#define mmDCORE1_TPC2_QM_ARC_AUX_BASE 0x1000007FFC228000ull +#define DCORE1_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE1_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC228E80ull +#define DCORE1_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE1_TPC2_QM_BASE 0x1000007FFC22A000ull +#define DCORE1_TPC2_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_QM_SECTION 0x9000 + +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC22A900ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC22A908ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC22A910ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC22A918ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC22A920ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC22A928ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC22A930ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC22A938ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC22A940ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC22A948ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC22A950ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC22A958ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC22A960ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC22A968ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC22A970ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC22A978ull +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE1_TPC2_QM_AXUSER_SECURED_BASE 0x1000007FFC22AB00ull +#define DCORE1_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE1_TPC2_QM_AXUSER_NONSECURED_BASE 0x1000007FFC22AB80ull +#define DCORE1_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE1_TPC2_QM_DBG_HBW_BASE 0x1000007FFC22AC00ull +#define DCORE1_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC2_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_TPC2_QM_DBG_LBW_BASE 0x1000007FFC22AC80ull +#define DCORE1_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC2_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE1_TPC2_QM_CGM_BASE 0x1000007FFC22AD80ull +#define DCORE1_TPC2_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC2_QM_CGM_SECTION 0x1000 + +#define mmDCORE1_TPC2_QM_SPECIAL_BASE 0x1000007FFC22AE80ull +#define DCORE1_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC2_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFC22B000ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC2_CFG_BASE 0x1000007FFC22B000ull +#define DCORE1_TPC2_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC2_CFG_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFC22B050ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFC22B0A0ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFC22B0F0ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFC22B140ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFC22B190ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFC22B1E0ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFC22B230ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFC22B280ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFC22B2D0ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFC22B320ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFC22B370ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFC22B3C0ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFC22B410ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFC22B460ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFC22B4B0ull +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFC22B500ull +#define DCORE1_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE1_TPC2_CFG_KERNEL_BASE 0x1000007FFC22B508ull +#define DCORE1_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC2_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE1_TPC2_CFG_QM_TENSOR_0_BASE 0x1000007FFC22B5DCull +#define DCORE1_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_QM_TENSOR_1_BASE 0x1000007FFC22B62Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_QM_TENSOR_2_BASE 0x1000007FFC22B67Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_QM_TENSOR_3_BASE 0x1000007FFC22B6CCull +#define DCORE1_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_QM_TENSOR_4_BASE 0x1000007FFC22B71Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_QM_TENSOR_5_BASE 0x1000007FFC22B76Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_QM_TENSOR_6_BASE 0x1000007FFC22B7BCull +#define DCORE1_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_QM_TENSOR_7_BASE 0x1000007FFC22B80Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_QM_TENSOR_8_BASE 0x1000007FFC22B85Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_QM_TENSOR_9_BASE 0x1000007FFC22B8ACull +#define DCORE1_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_QM_TENSOR_10_BASE 0x1000007FFC22B8FCull +#define DCORE1_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_QM_TENSOR_11_BASE 0x1000007FFC22B94Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_QM_TENSOR_12_BASE 0x1000007FFC22B99Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_QM_TENSOR_13_BASE 0x1000007FFC22B9ECull +#define DCORE1_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_QM_TENSOR_14_BASE 0x1000007FFC22BA3Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_QM_TENSOR_15_BASE 0x1000007FFC22BA8Cull +#define DCORE1_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE1_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFC22BADCull +#define DCORE1_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE1_TPC2_CFG_QM_BASE 0x1000007FFC22BAE4ull +#define DCORE1_TPC2_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC2_CFG_QM_SECTION 0x31C0 + +#define mmDCORE1_TPC2_CFG_AXUSER_BASE 0x1000007FFC22BE00ull +#define DCORE1_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE1_TPC2_CFG_SPECIAL_BASE 0x1000007FFC22BE80ull +#define DCORE1_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC2_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC22C000ull +#define DCORE1_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE1_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC22C200ull +#define DCORE1_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE1_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC22C400ull +#define DCORE1_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE1_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC22C600ull +#define DCORE1_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE1_TPC2_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC22C800ull +#define DCORE1_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE1_TPC2_MSTR_IF_AXUSER_BASE 0x1000007FFC22CA80ull +#define DCORE1_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC2_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE1_TPC2_MSTR_IF_DBG_HBW_BASE 0x1000007FFC22CB00ull +#define DCORE1_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_TPC2_MSTR_IF_DBG_LBW_BASE 0x1000007FFC22CB80ull +#define DCORE1_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE1_TPC2_MSTR_IF_CORE_HBW_BASE 0x1000007FFC22CC00ull +#define DCORE1_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE1_TPC2_MSTR_IF_CORE_LBW_BASE 0x1000007FFC22CD80ull +#define DCORE1_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE1_TPC2_MSTR_IF_SPECIAL_BASE 0x1000007FFC22CE80ull +#define DCORE1_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE1_TPC3_QM_DCCM_BASE 0x1000007FFC230000ull +#define DCORE1_TPC3_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC3_QM_DCCM_SECTION 0x8000 + +#define mmDCORE1_TPC3_QM_ARC_AUX_BASE 0x1000007FFC238000ull +#define DCORE1_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE1_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC238E80ull +#define DCORE1_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE1_TPC3_QM_BASE 0x1000007FFC23A000ull +#define DCORE1_TPC3_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_QM_SECTION 0x9000 + +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC23A900ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC23A908ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC23A910ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC23A918ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC23A920ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC23A928ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC23A930ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC23A938ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC23A940ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC23A948ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC23A950ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC23A958ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC23A960ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC23A968ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC23A970ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC23A978ull +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE1_TPC3_QM_AXUSER_SECURED_BASE 0x1000007FFC23AB00ull +#define DCORE1_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE1_TPC3_QM_AXUSER_NONSECURED_BASE 0x1000007FFC23AB80ull +#define DCORE1_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE1_TPC3_QM_DBG_HBW_BASE 0x1000007FFC23AC00ull +#define DCORE1_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC3_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_TPC3_QM_DBG_LBW_BASE 0x1000007FFC23AC80ull +#define DCORE1_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC3_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE1_TPC3_QM_CGM_BASE 0x1000007FFC23AD80ull +#define DCORE1_TPC3_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC3_QM_CGM_SECTION 0x1000 + +#define mmDCORE1_TPC3_QM_SPECIAL_BASE 0x1000007FFC23AE80ull +#define DCORE1_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC3_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFC23B000ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC3_CFG_BASE 0x1000007FFC23B000ull +#define DCORE1_TPC3_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC3_CFG_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFC23B050ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFC23B0A0ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFC23B0F0ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFC23B140ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFC23B190ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFC23B1E0ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFC23B230ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFC23B280ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFC23B2D0ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFC23B320ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFC23B370ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFC23B3C0ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFC23B410ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFC23B460ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFC23B4B0ull +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFC23B500ull +#define DCORE1_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE1_TPC3_CFG_KERNEL_BASE 0x1000007FFC23B508ull +#define DCORE1_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC3_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE1_TPC3_CFG_QM_TENSOR_0_BASE 0x1000007FFC23B5DCull +#define DCORE1_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_QM_TENSOR_1_BASE 0x1000007FFC23B62Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_QM_TENSOR_2_BASE 0x1000007FFC23B67Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_QM_TENSOR_3_BASE 0x1000007FFC23B6CCull +#define DCORE1_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_QM_TENSOR_4_BASE 0x1000007FFC23B71Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_QM_TENSOR_5_BASE 0x1000007FFC23B76Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_QM_TENSOR_6_BASE 0x1000007FFC23B7BCull +#define DCORE1_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_QM_TENSOR_7_BASE 0x1000007FFC23B80Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_QM_TENSOR_8_BASE 0x1000007FFC23B85Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_QM_TENSOR_9_BASE 0x1000007FFC23B8ACull +#define DCORE1_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_QM_TENSOR_10_BASE 0x1000007FFC23B8FCull +#define DCORE1_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_QM_TENSOR_11_BASE 0x1000007FFC23B94Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_QM_TENSOR_12_BASE 0x1000007FFC23B99Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_QM_TENSOR_13_BASE 0x1000007FFC23B9ECull +#define DCORE1_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_QM_TENSOR_14_BASE 0x1000007FFC23BA3Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_QM_TENSOR_15_BASE 0x1000007FFC23BA8Cull +#define DCORE1_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE1_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFC23BADCull +#define DCORE1_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE1_TPC3_CFG_QM_BASE 0x1000007FFC23BAE4ull +#define DCORE1_TPC3_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC3_CFG_QM_SECTION 0x31C0 + +#define mmDCORE1_TPC3_CFG_AXUSER_BASE 0x1000007FFC23BE00ull +#define DCORE1_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE1_TPC3_CFG_SPECIAL_BASE 0x1000007FFC23BE80ull +#define DCORE1_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC3_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC23C000ull +#define DCORE1_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE1_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC23C200ull +#define DCORE1_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE1_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC23C400ull +#define DCORE1_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE1_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC23C600ull +#define DCORE1_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE1_TPC3_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC23C800ull +#define DCORE1_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE1_TPC3_MSTR_IF_AXUSER_BASE 0x1000007FFC23CA80ull +#define DCORE1_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC3_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE1_TPC3_MSTR_IF_DBG_HBW_BASE 0x1000007FFC23CB00ull +#define DCORE1_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_TPC3_MSTR_IF_DBG_LBW_BASE 0x1000007FFC23CB80ull +#define DCORE1_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE1_TPC3_MSTR_IF_CORE_HBW_BASE 0x1000007FFC23CC00ull +#define DCORE1_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE1_TPC3_MSTR_IF_CORE_LBW_BASE 0x1000007FFC23CD80ull +#define DCORE1_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE1_TPC3_MSTR_IF_SPECIAL_BASE 0x1000007FFC23CE80ull +#define DCORE1_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE1_TPC4_QM_DCCM_BASE 0x1000007FFC240000ull +#define DCORE1_TPC4_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC4_QM_DCCM_SECTION 0x8000 + +#define mmDCORE1_TPC4_QM_ARC_AUX_BASE 0x1000007FFC248000ull +#define DCORE1_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE1_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC248E80ull +#define DCORE1_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE1_TPC4_QM_BASE 0x1000007FFC24A000ull +#define DCORE1_TPC4_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_QM_SECTION 0x9000 + +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC24A900ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC24A908ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC24A910ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC24A918ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC24A920ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC24A928ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC24A930ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC24A938ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC24A940ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC24A948ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC24A950ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC24A958ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC24A960ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC24A968ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC24A970ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC24A978ull +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE1_TPC4_QM_AXUSER_SECURED_BASE 0x1000007FFC24AB00ull +#define DCORE1_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE1_TPC4_QM_AXUSER_NONSECURED_BASE 0x1000007FFC24AB80ull +#define DCORE1_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE1_TPC4_QM_DBG_HBW_BASE 0x1000007FFC24AC00ull +#define DCORE1_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC4_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_TPC4_QM_DBG_LBW_BASE 0x1000007FFC24AC80ull +#define DCORE1_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC4_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE1_TPC4_QM_CGM_BASE 0x1000007FFC24AD80ull +#define DCORE1_TPC4_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC4_QM_CGM_SECTION 0x1000 + +#define mmDCORE1_TPC4_QM_SPECIAL_BASE 0x1000007FFC24AE80ull +#define DCORE1_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC4_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFC24B000ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC4_CFG_BASE 0x1000007FFC24B000ull +#define DCORE1_TPC4_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC4_CFG_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFC24B050ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFC24B0A0ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFC24B0F0ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFC24B140ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFC24B190ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFC24B1E0ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFC24B230ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFC24B280ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFC24B2D0ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFC24B320ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFC24B370ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFC24B3C0ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFC24B410ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFC24B460ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFC24B4B0ull +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFC24B500ull +#define DCORE1_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE1_TPC4_CFG_KERNEL_BASE 0x1000007FFC24B508ull +#define DCORE1_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC4_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE1_TPC4_CFG_QM_TENSOR_0_BASE 0x1000007FFC24B5DCull +#define DCORE1_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_QM_TENSOR_1_BASE 0x1000007FFC24B62Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_QM_TENSOR_2_BASE 0x1000007FFC24B67Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_QM_TENSOR_3_BASE 0x1000007FFC24B6CCull +#define DCORE1_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_QM_TENSOR_4_BASE 0x1000007FFC24B71Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_QM_TENSOR_5_BASE 0x1000007FFC24B76Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_QM_TENSOR_6_BASE 0x1000007FFC24B7BCull +#define DCORE1_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_QM_TENSOR_7_BASE 0x1000007FFC24B80Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_QM_TENSOR_8_BASE 0x1000007FFC24B85Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_QM_TENSOR_9_BASE 0x1000007FFC24B8ACull +#define DCORE1_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_QM_TENSOR_10_BASE 0x1000007FFC24B8FCull +#define DCORE1_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_QM_TENSOR_11_BASE 0x1000007FFC24B94Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_QM_TENSOR_12_BASE 0x1000007FFC24B99Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_QM_TENSOR_13_BASE 0x1000007FFC24B9ECull +#define DCORE1_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_QM_TENSOR_14_BASE 0x1000007FFC24BA3Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_QM_TENSOR_15_BASE 0x1000007FFC24BA8Cull +#define DCORE1_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE1_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFC24BADCull +#define DCORE1_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE1_TPC4_CFG_QM_BASE 0x1000007FFC24BAE4ull +#define DCORE1_TPC4_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC4_CFG_QM_SECTION 0x31C0 + +#define mmDCORE1_TPC4_CFG_AXUSER_BASE 0x1000007FFC24BE00ull +#define DCORE1_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE1_TPC4_CFG_SPECIAL_BASE 0x1000007FFC24BE80ull +#define DCORE1_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC4_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC24C000ull +#define DCORE1_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE1_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC24C200ull +#define DCORE1_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE1_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC24C400ull +#define DCORE1_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE1_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC24C600ull +#define DCORE1_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE1_TPC4_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC24C800ull +#define DCORE1_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE1_TPC4_MSTR_IF_AXUSER_BASE 0x1000007FFC24CA80ull +#define DCORE1_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC4_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE1_TPC4_MSTR_IF_DBG_HBW_BASE 0x1000007FFC24CB00ull +#define DCORE1_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_TPC4_MSTR_IF_DBG_LBW_BASE 0x1000007FFC24CB80ull +#define DCORE1_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE1_TPC4_MSTR_IF_CORE_HBW_BASE 0x1000007FFC24CC00ull +#define DCORE1_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE1_TPC4_MSTR_IF_CORE_LBW_BASE 0x1000007FFC24CD80ull +#define DCORE1_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE1_TPC4_MSTR_IF_SPECIAL_BASE 0x1000007FFC24CE80ull +#define DCORE1_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE1_TPC5_QM_DCCM_BASE 0x1000007FFC250000ull +#define DCORE1_TPC5_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_TPC5_QM_DCCM_SECTION 0x8000 + +#define mmDCORE1_TPC5_QM_ARC_AUX_BASE 0x1000007FFC258000ull +#define DCORE1_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE1_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC258E80ull +#define DCORE1_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE1_TPC5_QM_BASE 0x1000007FFC25A000ull +#define DCORE1_TPC5_QM_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_QM_SECTION 0x9000 + +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC25A900ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC25A908ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC25A910ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC25A918ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC25A920ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC25A928ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC25A930ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC25A938ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC25A940ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC25A948ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC25A950ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC25A958ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC25A960ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC25A968ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC25A970ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC25A978ull +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE1_TPC5_QM_AXUSER_SECURED_BASE 0x1000007FFC25AB00ull +#define DCORE1_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE1_TPC5_QM_AXUSER_NONSECURED_BASE 0x1000007FFC25AB80ull +#define DCORE1_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE1_TPC5_QM_DBG_HBW_BASE 0x1000007FFC25AC00ull +#define DCORE1_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC5_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_TPC5_QM_DBG_LBW_BASE 0x1000007FFC25AC80ull +#define DCORE1_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC5_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE1_TPC5_QM_CGM_BASE 0x1000007FFC25AD80ull +#define DCORE1_TPC5_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_TPC5_QM_CGM_SECTION 0x1000 + +#define mmDCORE1_TPC5_QM_SPECIAL_BASE 0x1000007FFC25AE80ull +#define DCORE1_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC5_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFC25B000ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC5_CFG_BASE 0x1000007FFC25B000ull +#define DCORE1_TPC5_CFG_MAX_OFFSET 0x1000 +#define DCORE1_TPC5_CFG_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFC25B050ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFC25B0A0ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFC25B0F0ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFC25B140ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFC25B190ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFC25B1E0ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFC25B230ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFC25B280ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFC25B2D0ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFC25B320ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFC25B370ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFC25B3C0ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFC25B410ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFC25B460ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFC25B4B0ull +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFC25B500ull +#define DCORE1_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE1_TPC5_CFG_KERNEL_BASE 0x1000007FFC25B508ull +#define DCORE1_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE1_TPC5_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE1_TPC5_CFG_QM_TENSOR_0_BASE 0x1000007FFC25B5DCull +#define DCORE1_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_QM_TENSOR_1_BASE 0x1000007FFC25B62Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_QM_TENSOR_2_BASE 0x1000007FFC25B67Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_QM_TENSOR_3_BASE 0x1000007FFC25B6CCull +#define DCORE1_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_QM_TENSOR_4_BASE 0x1000007FFC25B71Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_QM_TENSOR_5_BASE 0x1000007FFC25B76Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_QM_TENSOR_6_BASE 0x1000007FFC25B7BCull +#define DCORE1_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_QM_TENSOR_7_BASE 0x1000007FFC25B80Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_QM_TENSOR_8_BASE 0x1000007FFC25B85Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_QM_TENSOR_9_BASE 0x1000007FFC25B8ACull +#define DCORE1_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_QM_TENSOR_10_BASE 0x1000007FFC25B8FCull +#define DCORE1_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_QM_TENSOR_11_BASE 0x1000007FFC25B94Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_QM_TENSOR_12_BASE 0x1000007FFC25B99Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_QM_TENSOR_13_BASE 0x1000007FFC25B9ECull +#define DCORE1_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_QM_TENSOR_14_BASE 0x1000007FFC25BA3Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_QM_TENSOR_15_BASE 0x1000007FFC25BA8Cull +#define DCORE1_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE1_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFC25BADCull +#define DCORE1_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE1_TPC5_CFG_QM_BASE 0x1000007FFC25BAE4ull +#define DCORE1_TPC5_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE1_TPC5_CFG_QM_SECTION 0x31C0 + +#define mmDCORE1_TPC5_CFG_AXUSER_BASE 0x1000007FFC25BE00ull +#define DCORE1_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE1_TPC5_CFG_SPECIAL_BASE 0x1000007FFC25BE80ull +#define DCORE1_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC5_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC25C000ull +#define DCORE1_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE1_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC25C200ull +#define DCORE1_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE1_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC25C400ull +#define DCORE1_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE1_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC25C600ull +#define DCORE1_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE1_TPC5_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC25C800ull +#define DCORE1_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE1_TPC5_MSTR_IF_AXUSER_BASE 0x1000007FFC25CA80ull +#define DCORE1_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_TPC5_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE1_TPC5_MSTR_IF_DBG_HBW_BASE 0x1000007FFC25CB00ull +#define DCORE1_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_TPC5_MSTR_IF_DBG_LBW_BASE 0x1000007FFC25CB80ull +#define DCORE1_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE1_TPC5_MSTR_IF_CORE_HBW_BASE 0x1000007FFC25CC00ull +#define DCORE1_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE1_TPC5_MSTR_IF_CORE_LBW_BASE 0x1000007FFC25CD80ull +#define DCORE1_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE1_TPC5_MSTR_IF_SPECIAL_BASE 0x1000007FFC25CE80ull +#define DCORE1_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC5_MSTR_IF_SPECIAL_SECTION 0x23180 + +#define mmDCORE1_HMMU0_MMU_BASE 0x1000007FFC280000ull +#define DCORE1_HMMU0_MMU_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_MMU_SECTION 0xE800 + +#define mmDCORE1_HMMU0_MMU_SPECIAL_BASE 0x1000007FFC280E80ull +#define DCORE1_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU0_MMU_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_HMMU0_STLB_BASE 0x1000007FFC281000ull +#define DCORE1_HMMU0_STLB_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_STLB_SECTION 0xE800 + +#define mmDCORE1_HMMU0_STLB_SPECIAL_BASE 0x1000007FFC281E80ull +#define DCORE1_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU0_STLB_SPECIAL_SECTION 0x1180 + +#define mmDCORE1_HMMU0_SCRAMB_OUT_BASE 0x1000007FFC283000ull +#define DCORE1_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_SCRAMB_OUT_SECTION 0xE800 + +#define mmDCORE1_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x1000007FFC283E80ull +#define DCORE1_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC284000ull +#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE1_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC284200ull +#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE1_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC284400ull +#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE1_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC284600ull +#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE1_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC284800ull +#define DCORE1_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE1_HMMU0_MSTR_IF_AXUSER_BASE 0x1000007FFC284A80ull +#define DCORE1_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE1_HMMU0_MSTR_IF_DBG_HBW_BASE 0x1000007FFC284B00ull +#define DCORE1_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_HMMU0_MSTR_IF_DBG_LBW_BASE 0x1000007FFC284B80ull +#define DCORE1_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE1_HMMU0_MSTR_IF_CORE_HBW_BASE 0x1000007FFC284C00ull +#define DCORE1_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE1_HMMU0_MSTR_IF_CORE_LBW_BASE 0x1000007FFC284D80ull +#define DCORE1_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE1_HMMU0_MSTR_IF_SPECIAL_BASE 0x1000007FFC284E80ull +#define DCORE1_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180 + +#define mmDCORE1_HMMU1_MMU_BASE 0x1000007FFC290000ull +#define DCORE1_HMMU1_MMU_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_MMU_SECTION 0xE800 + +#define mmDCORE1_HMMU1_MMU_SPECIAL_BASE 0x1000007FFC290E80ull +#define DCORE1_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU1_MMU_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_HMMU1_STLB_BASE 0x1000007FFC291000ull +#define DCORE1_HMMU1_STLB_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_STLB_SECTION 0xE800 + +#define mmDCORE1_HMMU1_STLB_SPECIAL_BASE 0x1000007FFC291E80ull +#define DCORE1_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU1_STLB_SPECIAL_SECTION 0x1180 + +#define mmDCORE1_HMMU1_SCRAMB_OUT_BASE 0x1000007FFC293000ull +#define DCORE1_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_SCRAMB_OUT_SECTION 0xE800 + +#define mmDCORE1_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x1000007FFC293E80ull +#define DCORE1_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC294000ull +#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE1_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC294200ull +#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE1_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC294400ull +#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE1_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC294600ull +#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE1_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC294800ull +#define DCORE1_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE1_HMMU1_MSTR_IF_AXUSER_BASE 0x1000007FFC294A80ull +#define DCORE1_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE1_HMMU1_MSTR_IF_DBG_HBW_BASE 0x1000007FFC294B00ull +#define DCORE1_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_HMMU1_MSTR_IF_DBG_LBW_BASE 0x1000007FFC294B80ull +#define DCORE1_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE1_HMMU1_MSTR_IF_CORE_HBW_BASE 0x1000007FFC294C00ull +#define DCORE1_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE1_HMMU1_MSTR_IF_CORE_LBW_BASE 0x1000007FFC294D80ull +#define DCORE1_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE1_HMMU1_MSTR_IF_SPECIAL_BASE 0x1000007FFC294E80ull +#define DCORE1_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180 + +#define mmDCORE1_HMMU2_MMU_BASE 0x1000007FFC2A0000ull +#define DCORE1_HMMU2_MMU_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_MMU_SECTION 0xE800 + +#define mmDCORE1_HMMU2_MMU_SPECIAL_BASE 0x1000007FFC2A0E80ull +#define DCORE1_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU2_MMU_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_HMMU2_STLB_BASE 0x1000007FFC2A1000ull +#define DCORE1_HMMU2_STLB_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_STLB_SECTION 0xE800 + +#define mmDCORE1_HMMU2_STLB_SPECIAL_BASE 0x1000007FFC2A1E80ull +#define DCORE1_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU2_STLB_SPECIAL_SECTION 0x1180 + +#define mmDCORE1_HMMU2_SCRAMB_OUT_BASE 0x1000007FFC2A3000ull +#define DCORE1_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_SCRAMB_OUT_SECTION 0xE800 + +#define mmDCORE1_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x1000007FFC2A3E80ull +#define DCORE1_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC2A4000ull +#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE1_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC2A4200ull +#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE1_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC2A4400ull +#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE1_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC2A4600ull +#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE1_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC2A4800ull +#define DCORE1_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE1_HMMU2_MSTR_IF_AXUSER_BASE 0x1000007FFC2A4A80ull +#define DCORE1_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE1_HMMU2_MSTR_IF_DBG_HBW_BASE 0x1000007FFC2A4B00ull +#define DCORE1_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_HMMU2_MSTR_IF_DBG_LBW_BASE 0x1000007FFC2A4B80ull +#define DCORE1_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE1_HMMU2_MSTR_IF_CORE_HBW_BASE 0x1000007FFC2A4C00ull +#define DCORE1_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE1_HMMU2_MSTR_IF_CORE_LBW_BASE 0x1000007FFC2A4D80ull +#define DCORE1_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE1_HMMU2_MSTR_IF_SPECIAL_BASE 0x1000007FFC2A4E80ull +#define DCORE1_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180 + +#define mmDCORE1_HMMU3_MMU_BASE 0x1000007FFC2B0000ull +#define DCORE1_HMMU3_MMU_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_MMU_SECTION 0xE800 + +#define mmDCORE1_HMMU3_MMU_SPECIAL_BASE 0x1000007FFC2B0E80ull +#define DCORE1_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU3_MMU_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_HMMU3_STLB_BASE 0x1000007FFC2B1000ull +#define DCORE1_HMMU3_STLB_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_STLB_SECTION 0xE800 + +#define mmDCORE1_HMMU3_STLB_SPECIAL_BASE 0x1000007FFC2B1E80ull +#define DCORE1_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU3_STLB_SPECIAL_SECTION 0x1180 + +#define mmDCORE1_HMMU3_SCRAMB_OUT_BASE 0x1000007FFC2B3000ull +#define DCORE1_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_SCRAMB_OUT_SECTION 0xE800 + +#define mmDCORE1_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x1000007FFC2B3E80ull +#define DCORE1_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC2B4000ull +#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE1_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC2B4200ull +#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE1_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC2B4400ull +#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE1_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC2B4600ull +#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE1_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC2B4800ull +#define DCORE1_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE1_HMMU3_MSTR_IF_AXUSER_BASE 0x1000007FFC2B4A80ull +#define DCORE1_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE1_HMMU3_MSTR_IF_DBG_HBW_BASE 0x1000007FFC2B4B00ull +#define DCORE1_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_HMMU3_MSTR_IF_DBG_LBW_BASE 0x1000007FFC2B4B80ull +#define DCORE1_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE1_HMMU3_MSTR_IF_CORE_HBW_BASE 0x1000007FFC2B4C00ull +#define DCORE1_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE1_HMMU3_MSTR_IF_CORE_LBW_BASE 0x1000007FFC2B4D80ull +#define DCORE1_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE1_HMMU3_MSTR_IF_SPECIAL_BASE 0x1000007FFC2B4E80ull +#define DCORE1_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180 + +#define mmDCORE1_SYNC_MNGR_OBJS_BASE 0x1000007FFC300000ull +#define DCORE1_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00 +#define DCORE1_SYNC_MNGR_OBJS_SECTION 0x1E000 + +#define mmDCORE1_SYNC_MNGR_GLBL_BASE 0x1000007FFC31E000ull +#define DCORE1_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000 +#define DCORE1_SYNC_MNGR_GLBL_SECTION 0xE800 + +#define mmDCORE1_SYNC_MNGR_GLBL_SPECIAL_BASE 0x1000007FFC31EE80ull +#define DCORE1_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC31F000ull +#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC31F200ull +#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC31F400ull +#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC31F600ull +#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE1_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC31F800ull +#define DCORE1_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE1_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x1000007FFC31FA80ull +#define DCORE1_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE1_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x1000007FFC31FB00ull +#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x1000007FFC31FB80ull +#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE1_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x1000007FFC31FC00ull +#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE1_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x1000007FFC31FD80ull +#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE1_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x1000007FFC31FE80ull +#define DCORE1_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_HIF0_BASE 0x1000007FFC320000ull +#define DCORE1_HIF0_MAX_OFFSET 0x1000 +#define DCORE1_HIF0_SECTION 0xE800 + +#define mmDCORE1_HIF0_SPECIAL_BASE 0x1000007FFC320E80ull +#define DCORE1_HIF0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HIF0_SPECIAL_SECTION 0x3180 + +#define mmDCORE1_HIF1_BASE 0x1000007FFC324000ull +#define DCORE1_HIF1_MAX_OFFSET 0x1000 +#define DCORE1_HIF1_SECTION 0xE800 + +#define mmDCORE1_HIF1_SPECIAL_BASE 0x1000007FFC324E80ull +#define DCORE1_HIF1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HIF1_SPECIAL_SECTION 0x3180 + +#define mmDCORE1_HIF2_BASE 0x1000007FFC328000ull +#define DCORE1_HIF2_MAX_OFFSET 0x1000 +#define DCORE1_HIF2_SECTION 0xE800 + +#define mmDCORE1_HIF2_SPECIAL_BASE 0x1000007FFC328E80ull +#define DCORE1_HIF2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HIF2_SPECIAL_SECTION 0x3180 + +#define mmDCORE1_HIF3_BASE 0x1000007FFC32C000ull +#define DCORE1_HIF3_MAX_OFFSET 0x1000 +#define DCORE1_HIF3_SECTION 0xE800 + +#define mmDCORE1_HIF3_SPECIAL_BASE 0x1000007FFC32CE80ull +#define DCORE1_HIF3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HIF3_SPECIAL_SECTION 0x13180 + +#define mmDCORE1_RTR0_CTRL_BASE 0x1000007FFC340000ull +#define DCORE1_RTR0_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_RTR0_CTRL_SECTION 0xE800 + +#define mmDCORE1_RTR0_CTRL_SPECIAL_BASE 0x1000007FFC340E80ull +#define DCORE1_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR0_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR0_H3_BASE 0x1000007FFC341000ull +#define DCORE1_RTR0_H3_MAX_OFFSET 0x1000 +#define DCORE1_RTR0_H3_SECTION 0xE800 + +#define mmDCORE1_RTR0_H3_SPECIAL_BASE 0x1000007FFC341E80ull +#define DCORE1_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR0_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC342000ull +#define DCORE1_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE1_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC342200ull +#define DCORE1_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE1_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC342400ull +#define DCORE1_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE1_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC342600ull +#define DCORE1_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE1_RTR0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC342800ull +#define DCORE1_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE1_RTR0_MSTR_IF_AXUSER_BASE 0x1000007FFC342A80ull +#define DCORE1_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_RTR0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE1_RTR0_MSTR_IF_DBG_HBW_BASE 0x1000007FFC342B00ull +#define DCORE1_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_RTR0_MSTR_IF_DBG_LBW_BASE 0x1000007FFC342B80ull +#define DCORE1_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE1_RTR0_MSTR_IF_CORE_HBW_BASE 0x1000007FFC342C00ull +#define DCORE1_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE1_RTR0_MSTR_IF_CORE_LBW_BASE 0x1000007FFC342D80ull +#define DCORE1_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE1_RTR0_MSTR_IF_SPECIAL_BASE 0x1000007FFC342E80ull +#define DCORE1_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR0_ADD_DEC_HBW_BASE 0x1000007FFC343000ull +#define DCORE1_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE1_RTR0_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE1_RTR0_ADD_DEC_LBW_BASE 0x1000007FFC343400ull +#define DCORE1_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE1_RTR0_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE1_RTR0_ADD_DEC_SPECIAL_BASE 0x1000007FFC343E80ull +#define DCORE1_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR0_BASE 0x1000007FFC344000ull +#define DCORE1_RTR0_MAX_OFFSET 0x1000 +#define DCORE1_RTR0_SECTION 0x3000 + +#define mmDCORE1_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC344300ull +#define DCORE1_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR0_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC344340ull +#define DCORE1_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC344380ull +#define DCORE1_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR0_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC3443C0ull +#define DCORE1_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC344400ull +#define DCORE1_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR0_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC344440ull +#define DCORE1_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC344480ull +#define DCORE1_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR0_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC3444C0ull +#define DCORE1_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR0_HBW_MFIFO_BASE 0x1000007FFC344500ull +#define DCORE1_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE1_RTR0_E2E_RD_LL_STAT_BASE 0x1000007FFC344540ull +#define DCORE1_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR0_E2E_WR_LL_STAT_BASE 0x1000007FFC344580ull +#define DCORE1_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR0_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE1_RTR0_RTR_HBW_XACT_STAT_BASE 0x1000007FFC344600ull +#define DCORE1_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE1_RTR0_RTR_LBW_XACT_STAT_BASE 0x1000007FFC344680ull +#define DCORE1_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE1_RTR0_RTR_E2E_XACT_STAT_BASE 0x1000007FFC344700ull +#define DCORE1_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE1_RTR0_SPECIAL_BASE 0x1000007FFC344E80ull +#define DCORE1_RTR0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR0_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR0_DBG_ADDR_BASE 0x1000007FFC345000ull +#define DCORE1_RTR0_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE1_RTR0_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE1_RTR0_DBG_ADDR_SPECIAL_BASE 0x1000007FFC345E80ull +#define DCORE1_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE1_RTR1_CTRL_BASE 0x1000007FFC348000ull +#define DCORE1_RTR1_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_RTR1_CTRL_SECTION 0xE800 + +#define mmDCORE1_RTR1_CTRL_SPECIAL_BASE 0x1000007FFC348E80ull +#define DCORE1_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR1_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR1_H3_BASE 0x1000007FFC349000ull +#define DCORE1_RTR1_H3_MAX_OFFSET 0x1000 +#define DCORE1_RTR1_H3_SECTION 0xE800 + +#define mmDCORE1_RTR1_H3_SPECIAL_BASE 0x1000007FFC349E80ull +#define DCORE1_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR1_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC34A000ull +#define DCORE1_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE1_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC34A200ull +#define DCORE1_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE1_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC34A400ull +#define DCORE1_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE1_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC34A600ull +#define DCORE1_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE1_RTR1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC34A800ull +#define DCORE1_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE1_RTR1_MSTR_IF_AXUSER_BASE 0x1000007FFC34AA80ull +#define DCORE1_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_RTR1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE1_RTR1_MSTR_IF_DBG_HBW_BASE 0x1000007FFC34AB00ull +#define DCORE1_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_RTR1_MSTR_IF_DBG_LBW_BASE 0x1000007FFC34AB80ull +#define DCORE1_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE1_RTR1_MSTR_IF_CORE_HBW_BASE 0x1000007FFC34AC00ull +#define DCORE1_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE1_RTR1_MSTR_IF_CORE_LBW_BASE 0x1000007FFC34AD80ull +#define DCORE1_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE1_RTR1_MSTR_IF_SPECIAL_BASE 0x1000007FFC34AE80ull +#define DCORE1_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR1_ADD_DEC_HBW_BASE 0x1000007FFC34B000ull +#define DCORE1_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE1_RTR1_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE1_RTR1_ADD_DEC_LBW_BASE 0x1000007FFC34B400ull +#define DCORE1_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE1_RTR1_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE1_RTR1_ADD_DEC_SPECIAL_BASE 0x1000007FFC34BE80ull +#define DCORE1_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR1_BASE 0x1000007FFC34C000ull +#define DCORE1_RTR1_MAX_OFFSET 0x1000 +#define DCORE1_RTR1_SECTION 0x3000 + +#define mmDCORE1_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC34C300ull +#define DCORE1_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR1_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC34C340ull +#define DCORE1_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC34C380ull +#define DCORE1_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR1_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC34C3C0ull +#define DCORE1_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC34C400ull +#define DCORE1_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR1_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC34C440ull +#define DCORE1_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC34C480ull +#define DCORE1_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR1_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC34C4C0ull +#define DCORE1_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR1_HBW_MFIFO_BASE 0x1000007FFC34C500ull +#define DCORE1_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE1_RTR1_E2E_RD_LL_STAT_BASE 0x1000007FFC34C540ull +#define DCORE1_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR1_E2E_WR_LL_STAT_BASE 0x1000007FFC34C580ull +#define DCORE1_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR1_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE1_RTR1_RTR_HBW_XACT_STAT_BASE 0x1000007FFC34C600ull +#define DCORE1_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE1_RTR1_RTR_LBW_XACT_STAT_BASE 0x1000007FFC34C680ull +#define DCORE1_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE1_RTR1_RTR_E2E_XACT_STAT_BASE 0x1000007FFC34C700ull +#define DCORE1_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE1_RTR1_SPECIAL_BASE 0x1000007FFC34CE80ull +#define DCORE1_RTR1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR1_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR1_DBG_ADDR_BASE 0x1000007FFC34D000ull +#define DCORE1_RTR1_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE1_RTR1_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE1_RTR1_DBG_ADDR_SPECIAL_BASE 0x1000007FFC34DE80ull +#define DCORE1_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE1_RTR2_CTRL_BASE 0x1000007FFC350000ull +#define DCORE1_RTR2_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_RTR2_CTRL_SECTION 0xE800 + +#define mmDCORE1_RTR2_CTRL_SPECIAL_BASE 0x1000007FFC350E80ull +#define DCORE1_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR2_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR2_H3_BASE 0x1000007FFC351000ull +#define DCORE1_RTR2_H3_MAX_OFFSET 0x1000 +#define DCORE1_RTR2_H3_SECTION 0xE800 + +#define mmDCORE1_RTR2_H3_SPECIAL_BASE 0x1000007FFC351E80ull +#define DCORE1_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR2_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC352000ull +#define DCORE1_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE1_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC352200ull +#define DCORE1_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE1_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC352400ull +#define DCORE1_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE1_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC352600ull +#define DCORE1_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE1_RTR2_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC352800ull +#define DCORE1_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE1_RTR2_MSTR_IF_AXUSER_BASE 0x1000007FFC352A80ull +#define DCORE1_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_RTR2_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE1_RTR2_MSTR_IF_DBG_HBW_BASE 0x1000007FFC352B00ull +#define DCORE1_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_RTR2_MSTR_IF_DBG_LBW_BASE 0x1000007FFC352B80ull +#define DCORE1_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE1_RTR2_MSTR_IF_CORE_HBW_BASE 0x1000007FFC352C00ull +#define DCORE1_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE1_RTR2_MSTR_IF_CORE_LBW_BASE 0x1000007FFC352D80ull +#define DCORE1_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE1_RTR2_MSTR_IF_SPECIAL_BASE 0x1000007FFC352E80ull +#define DCORE1_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR2_ADD_DEC_HBW_BASE 0x1000007FFC353000ull +#define DCORE1_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE1_RTR2_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE1_RTR2_ADD_DEC_LBW_BASE 0x1000007FFC353400ull +#define DCORE1_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE1_RTR2_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE1_RTR2_ADD_DEC_SPECIAL_BASE 0x1000007FFC353E80ull +#define DCORE1_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR2_BASE 0x1000007FFC354000ull +#define DCORE1_RTR2_MAX_OFFSET 0x1000 +#define DCORE1_RTR2_SECTION 0x3000 + +#define mmDCORE1_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC354300ull +#define DCORE1_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR2_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC354340ull +#define DCORE1_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC354380ull +#define DCORE1_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR2_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC3543C0ull +#define DCORE1_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC354400ull +#define DCORE1_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR2_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC354440ull +#define DCORE1_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC354480ull +#define DCORE1_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR2_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC3544C0ull +#define DCORE1_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR2_HBW_MFIFO_BASE 0x1000007FFC354500ull +#define DCORE1_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE1_RTR2_E2E_RD_LL_STAT_BASE 0x1000007FFC354540ull +#define DCORE1_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR2_E2E_WR_LL_STAT_BASE 0x1000007FFC354580ull +#define DCORE1_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR2_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE1_RTR2_RTR_HBW_XACT_STAT_BASE 0x1000007FFC354600ull +#define DCORE1_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE1_RTR2_RTR_LBW_XACT_STAT_BASE 0x1000007FFC354680ull +#define DCORE1_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE1_RTR2_RTR_E2E_XACT_STAT_BASE 0x1000007FFC354700ull +#define DCORE1_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE1_RTR2_SPECIAL_BASE 0x1000007FFC354E80ull +#define DCORE1_RTR2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR2_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR2_DBG_ADDR_BASE 0x1000007FFC355000ull +#define DCORE1_RTR2_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE1_RTR2_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE1_RTR2_DBG_ADDR_SPECIAL_BASE 0x1000007FFC355E80ull +#define DCORE1_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE1_RTR3_CTRL_BASE 0x1000007FFC358000ull +#define DCORE1_RTR3_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_RTR3_CTRL_SECTION 0xE800 + +#define mmDCORE1_RTR3_CTRL_SPECIAL_BASE 0x1000007FFC358E80ull +#define DCORE1_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR3_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR3_H3_BASE 0x1000007FFC359000ull +#define DCORE1_RTR3_H3_MAX_OFFSET 0x1000 +#define DCORE1_RTR3_H3_SECTION 0xE800 + +#define mmDCORE1_RTR3_H3_SPECIAL_BASE 0x1000007FFC359E80ull +#define DCORE1_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR3_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC35A000ull +#define DCORE1_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE1_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC35A200ull +#define DCORE1_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE1_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC35A400ull +#define DCORE1_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE1_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC35A600ull +#define DCORE1_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE1_RTR3_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC35A800ull +#define DCORE1_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE1_RTR3_MSTR_IF_AXUSER_BASE 0x1000007FFC35AA80ull +#define DCORE1_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_RTR3_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE1_RTR3_MSTR_IF_DBG_HBW_BASE 0x1000007FFC35AB00ull +#define DCORE1_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_RTR3_MSTR_IF_DBG_LBW_BASE 0x1000007FFC35AB80ull +#define DCORE1_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE1_RTR3_MSTR_IF_CORE_HBW_BASE 0x1000007FFC35AC00ull +#define DCORE1_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE1_RTR3_MSTR_IF_CORE_LBW_BASE 0x1000007FFC35AD80ull +#define DCORE1_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE1_RTR3_MSTR_IF_SPECIAL_BASE 0x1000007FFC35AE80ull +#define DCORE1_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR3_ADD_DEC_HBW_BASE 0x1000007FFC35B000ull +#define DCORE1_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE1_RTR3_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE1_RTR3_ADD_DEC_LBW_BASE 0x1000007FFC35B400ull +#define DCORE1_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE1_RTR3_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE1_RTR3_ADD_DEC_SPECIAL_BASE 0x1000007FFC35BE80ull +#define DCORE1_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR3_BASE 0x1000007FFC35C000ull +#define DCORE1_RTR3_MAX_OFFSET 0x1000 +#define DCORE1_RTR3_SECTION 0x3000 + +#define mmDCORE1_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC35C300ull +#define DCORE1_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR3_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC35C340ull +#define DCORE1_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC35C380ull +#define DCORE1_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR3_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC35C3C0ull +#define DCORE1_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC35C400ull +#define DCORE1_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR3_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC35C440ull +#define DCORE1_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC35C480ull +#define DCORE1_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR3_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC35C4C0ull +#define DCORE1_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR3_HBW_MFIFO_BASE 0x1000007FFC35C500ull +#define DCORE1_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE1_RTR3_E2E_RD_LL_STAT_BASE 0x1000007FFC35C540ull +#define DCORE1_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR3_E2E_WR_LL_STAT_BASE 0x1000007FFC35C580ull +#define DCORE1_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR3_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE1_RTR3_RTR_HBW_XACT_STAT_BASE 0x1000007FFC35C600ull +#define DCORE1_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE1_RTR3_RTR_LBW_XACT_STAT_BASE 0x1000007FFC35C680ull +#define DCORE1_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE1_RTR3_RTR_E2E_XACT_STAT_BASE 0x1000007FFC35C700ull +#define DCORE1_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE1_RTR3_SPECIAL_BASE 0x1000007FFC35CE80ull +#define DCORE1_RTR3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR3_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR3_DBG_ADDR_BASE 0x1000007FFC35D000ull +#define DCORE1_RTR3_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE1_RTR3_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE1_RTR3_DBG_ADDR_SPECIAL_BASE 0x1000007FFC35DE80ull +#define DCORE1_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE1_RTR4_CTRL_BASE 0x1000007FFC360000ull +#define DCORE1_RTR4_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_RTR4_CTRL_SECTION 0xE800 + +#define mmDCORE1_RTR4_CTRL_SPECIAL_BASE 0x1000007FFC360E80ull +#define DCORE1_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR4_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR4_H3_BASE 0x1000007FFC361000ull +#define DCORE1_RTR4_H3_MAX_OFFSET 0x1000 +#define DCORE1_RTR4_H3_SECTION 0xE800 + +#define mmDCORE1_RTR4_H3_SPECIAL_BASE 0x1000007FFC361E80ull +#define DCORE1_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR4_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC362000ull +#define DCORE1_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE1_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC362200ull +#define DCORE1_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE1_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC362400ull +#define DCORE1_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE1_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC362600ull +#define DCORE1_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE1_RTR4_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC362800ull +#define DCORE1_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE1_RTR4_MSTR_IF_AXUSER_BASE 0x1000007FFC362A80ull +#define DCORE1_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_RTR4_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE1_RTR4_MSTR_IF_DBG_HBW_BASE 0x1000007FFC362B00ull +#define DCORE1_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_RTR4_MSTR_IF_DBG_LBW_BASE 0x1000007FFC362B80ull +#define DCORE1_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE1_RTR4_MSTR_IF_CORE_HBW_BASE 0x1000007FFC362C00ull +#define DCORE1_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE1_RTR4_MSTR_IF_CORE_LBW_BASE 0x1000007FFC362D80ull +#define DCORE1_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE1_RTR4_MSTR_IF_SPECIAL_BASE 0x1000007FFC362E80ull +#define DCORE1_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR4_ADD_DEC_HBW_BASE 0x1000007FFC363000ull +#define DCORE1_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE1_RTR4_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE1_RTR4_ADD_DEC_LBW_BASE 0x1000007FFC363400ull +#define DCORE1_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE1_RTR4_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE1_RTR4_ADD_DEC_SPECIAL_BASE 0x1000007FFC363E80ull +#define DCORE1_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR4_BASE 0x1000007FFC364000ull +#define DCORE1_RTR4_MAX_OFFSET 0x1000 +#define DCORE1_RTR4_SECTION 0x3000 + +#define mmDCORE1_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC364300ull +#define DCORE1_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR4_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC364340ull +#define DCORE1_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC364380ull +#define DCORE1_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR4_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC3643C0ull +#define DCORE1_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC364400ull +#define DCORE1_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR4_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC364440ull +#define DCORE1_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC364480ull +#define DCORE1_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR4_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC3644C0ull +#define DCORE1_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR4_HBW_MFIFO_BASE 0x1000007FFC364500ull +#define DCORE1_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE1_RTR4_E2E_RD_LL_STAT_BASE 0x1000007FFC364540ull +#define DCORE1_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR4_E2E_WR_LL_STAT_BASE 0x1000007FFC364580ull +#define DCORE1_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR4_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE1_RTR4_RTR_HBW_XACT_STAT_BASE 0x1000007FFC364600ull +#define DCORE1_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE1_RTR4_RTR_LBW_XACT_STAT_BASE 0x1000007FFC364680ull +#define DCORE1_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE1_RTR4_RTR_E2E_XACT_STAT_BASE 0x1000007FFC364700ull +#define DCORE1_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE1_RTR4_SPECIAL_BASE 0x1000007FFC364E80ull +#define DCORE1_RTR4_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR4_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR4_DBG_ADDR_BASE 0x1000007FFC365000ull +#define DCORE1_RTR4_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE1_RTR4_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE1_RTR4_DBG_ADDR_SPECIAL_BASE 0x1000007FFC365E80ull +#define DCORE1_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE1_RTR5_CTRL_BASE 0x1000007FFC368000ull +#define DCORE1_RTR5_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_RTR5_CTRL_SECTION 0xE800 + +#define mmDCORE1_RTR5_CTRL_SPECIAL_BASE 0x1000007FFC368E80ull +#define DCORE1_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR5_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR5_H3_BASE 0x1000007FFC369000ull +#define DCORE1_RTR5_H3_MAX_OFFSET 0x1000 +#define DCORE1_RTR5_H3_SECTION 0xE800 + +#define mmDCORE1_RTR5_H3_SPECIAL_BASE 0x1000007FFC369E80ull +#define DCORE1_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR5_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC36A000ull +#define DCORE1_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE1_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC36A200ull +#define DCORE1_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE1_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC36A400ull +#define DCORE1_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE1_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC36A600ull +#define DCORE1_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE1_RTR5_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC36A800ull +#define DCORE1_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE1_RTR5_MSTR_IF_AXUSER_BASE 0x1000007FFC36AA80ull +#define DCORE1_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_RTR5_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE1_RTR5_MSTR_IF_DBG_HBW_BASE 0x1000007FFC36AB00ull +#define DCORE1_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_RTR5_MSTR_IF_DBG_LBW_BASE 0x1000007FFC36AB80ull +#define DCORE1_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE1_RTR5_MSTR_IF_CORE_HBW_BASE 0x1000007FFC36AC00ull +#define DCORE1_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE1_RTR5_MSTR_IF_CORE_LBW_BASE 0x1000007FFC36AD80ull +#define DCORE1_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE1_RTR5_MSTR_IF_SPECIAL_BASE 0x1000007FFC36AE80ull +#define DCORE1_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR5_ADD_DEC_HBW_BASE 0x1000007FFC36B000ull +#define DCORE1_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE1_RTR5_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE1_RTR5_ADD_DEC_LBW_BASE 0x1000007FFC36B400ull +#define DCORE1_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE1_RTR5_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE1_RTR5_ADD_DEC_SPECIAL_BASE 0x1000007FFC36BE80ull +#define DCORE1_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR5_BASE 0x1000007FFC36C000ull +#define DCORE1_RTR5_MAX_OFFSET 0x1000 +#define DCORE1_RTR5_SECTION 0x3000 + +#define mmDCORE1_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC36C300ull +#define DCORE1_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR5_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC36C340ull +#define DCORE1_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC36C380ull +#define DCORE1_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR5_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC36C3C0ull +#define DCORE1_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC36C400ull +#define DCORE1_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR5_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC36C440ull +#define DCORE1_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC36C480ull +#define DCORE1_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR5_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC36C4C0ull +#define DCORE1_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR5_HBW_MFIFO_BASE 0x1000007FFC36C500ull +#define DCORE1_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE1_RTR5_E2E_RD_LL_STAT_BASE 0x1000007FFC36C540ull +#define DCORE1_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR5_E2E_WR_LL_STAT_BASE 0x1000007FFC36C580ull +#define DCORE1_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR5_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE1_RTR5_RTR_HBW_XACT_STAT_BASE 0x1000007FFC36C600ull +#define DCORE1_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE1_RTR5_RTR_LBW_XACT_STAT_BASE 0x1000007FFC36C680ull +#define DCORE1_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE1_RTR5_RTR_E2E_XACT_STAT_BASE 0x1000007FFC36C700ull +#define DCORE1_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE1_RTR5_SPECIAL_BASE 0x1000007FFC36CE80ull +#define DCORE1_RTR5_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR5_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR5_DBG_ADDR_BASE 0x1000007FFC36D000ull +#define DCORE1_RTR5_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE1_RTR5_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE1_RTR5_DBG_ADDR_SPECIAL_BASE 0x1000007FFC36DE80ull +#define DCORE1_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE1_RTR6_CTRL_BASE 0x1000007FFC370000ull +#define DCORE1_RTR6_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_RTR6_CTRL_SECTION 0xE800 + +#define mmDCORE1_RTR6_CTRL_SPECIAL_BASE 0x1000007FFC370E80ull +#define DCORE1_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR6_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR6_H3_BASE 0x1000007FFC371000ull +#define DCORE1_RTR6_H3_MAX_OFFSET 0x1000 +#define DCORE1_RTR6_H3_SECTION 0xE800 + +#define mmDCORE1_RTR6_H3_SPECIAL_BASE 0x1000007FFC371E80ull +#define DCORE1_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR6_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC372000ull +#define DCORE1_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE1_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC372200ull +#define DCORE1_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE1_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC372400ull +#define DCORE1_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE1_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC372600ull +#define DCORE1_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE1_RTR6_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC372800ull +#define DCORE1_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE1_RTR6_MSTR_IF_AXUSER_BASE 0x1000007FFC372A80ull +#define DCORE1_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_RTR6_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE1_RTR6_MSTR_IF_DBG_HBW_BASE 0x1000007FFC372B00ull +#define DCORE1_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_RTR6_MSTR_IF_DBG_LBW_BASE 0x1000007FFC372B80ull +#define DCORE1_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE1_RTR6_MSTR_IF_CORE_HBW_BASE 0x1000007FFC372C00ull +#define DCORE1_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE1_RTR6_MSTR_IF_CORE_LBW_BASE 0x1000007FFC372D80ull +#define DCORE1_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE1_RTR6_MSTR_IF_SPECIAL_BASE 0x1000007FFC372E80ull +#define DCORE1_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR6_ADD_DEC_HBW_BASE 0x1000007FFC373000ull +#define DCORE1_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE1_RTR6_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE1_RTR6_ADD_DEC_LBW_BASE 0x1000007FFC373400ull +#define DCORE1_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE1_RTR6_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE1_RTR6_ADD_DEC_SPECIAL_BASE 0x1000007FFC373E80ull +#define DCORE1_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR6_BASE 0x1000007FFC374000ull +#define DCORE1_RTR6_MAX_OFFSET 0x1000 +#define DCORE1_RTR6_SECTION 0x3000 + +#define mmDCORE1_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC374300ull +#define DCORE1_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR6_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC374340ull +#define DCORE1_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC374380ull +#define DCORE1_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR6_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC3743C0ull +#define DCORE1_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC374400ull +#define DCORE1_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR6_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC374440ull +#define DCORE1_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC374480ull +#define DCORE1_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR6_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC3744C0ull +#define DCORE1_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR6_HBW_MFIFO_BASE 0x1000007FFC374500ull +#define DCORE1_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE1_RTR6_E2E_RD_LL_STAT_BASE 0x1000007FFC374540ull +#define DCORE1_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR6_E2E_WR_LL_STAT_BASE 0x1000007FFC374580ull +#define DCORE1_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR6_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE1_RTR6_RTR_HBW_XACT_STAT_BASE 0x1000007FFC374600ull +#define DCORE1_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE1_RTR6_RTR_LBW_XACT_STAT_BASE 0x1000007FFC374680ull +#define DCORE1_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE1_RTR6_RTR_E2E_XACT_STAT_BASE 0x1000007FFC374700ull +#define DCORE1_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE1_RTR6_SPECIAL_BASE 0x1000007FFC374E80ull +#define DCORE1_RTR6_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR6_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR6_DBG_ADDR_BASE 0x1000007FFC375000ull +#define DCORE1_RTR6_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE1_RTR6_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE1_RTR6_DBG_ADDR_SPECIAL_BASE 0x1000007FFC375E80ull +#define DCORE1_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE1_RTR7_CTRL_BASE 0x1000007FFC378000ull +#define DCORE1_RTR7_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_RTR7_CTRL_SECTION 0xE800 + +#define mmDCORE1_RTR7_CTRL_SPECIAL_BASE 0x1000007FFC378E80ull +#define DCORE1_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR7_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR7_H3_BASE 0x1000007FFC379000ull +#define DCORE1_RTR7_H3_MAX_OFFSET 0x1000 +#define DCORE1_RTR7_H3_SECTION 0xE800 + +#define mmDCORE1_RTR7_H3_SPECIAL_BASE 0x1000007FFC379E80ull +#define DCORE1_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR7_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC37A000ull +#define DCORE1_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE1_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC37A200ull +#define DCORE1_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE1_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC37A400ull +#define DCORE1_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE1_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC37A600ull +#define DCORE1_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE1_RTR7_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC37A800ull +#define DCORE1_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE1_RTR7_MSTR_IF_AXUSER_BASE 0x1000007FFC37AA80ull +#define DCORE1_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_RTR7_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE1_RTR7_MSTR_IF_DBG_HBW_BASE 0x1000007FFC37AB00ull +#define DCORE1_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_RTR7_MSTR_IF_DBG_LBW_BASE 0x1000007FFC37AB80ull +#define DCORE1_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE1_RTR7_MSTR_IF_CORE_HBW_BASE 0x1000007FFC37AC00ull +#define DCORE1_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE1_RTR7_MSTR_IF_CORE_LBW_BASE 0x1000007FFC37AD80ull +#define DCORE1_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE1_RTR7_MSTR_IF_SPECIAL_BASE 0x1000007FFC37AE80ull +#define DCORE1_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR7_ADD_DEC_HBW_BASE 0x1000007FFC37B000ull +#define DCORE1_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE1_RTR7_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE1_RTR7_ADD_DEC_LBW_BASE 0x1000007FFC37B400ull +#define DCORE1_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE1_RTR7_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE1_RTR7_ADD_DEC_SPECIAL_BASE 0x1000007FFC37BE80ull +#define DCORE1_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR7_BASE 0x1000007FFC37C000ull +#define DCORE1_RTR7_MAX_OFFSET 0x1000 +#define DCORE1_RTR7_SECTION 0x3000 + +#define mmDCORE1_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC37C300ull +#define DCORE1_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR7_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC37C340ull +#define DCORE1_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC37C380ull +#define DCORE1_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR7_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC37C3C0ull +#define DCORE1_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC37C400ull +#define DCORE1_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR7_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC37C440ull +#define DCORE1_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC37C480ull +#define DCORE1_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR7_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC37C4C0ull +#define DCORE1_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR7_HBW_MFIFO_BASE 0x1000007FFC37C500ull +#define DCORE1_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE1_RTR7_E2E_RD_LL_STAT_BASE 0x1000007FFC37C540ull +#define DCORE1_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE1_RTR7_E2E_WR_LL_STAT_BASE 0x1000007FFC37C580ull +#define DCORE1_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE1_RTR7_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE1_RTR7_RTR_HBW_XACT_STAT_BASE 0x1000007FFC37C600ull +#define DCORE1_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE1_RTR7_RTR_LBW_XACT_STAT_BASE 0x1000007FFC37C680ull +#define DCORE1_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE1_RTR7_RTR_E2E_XACT_STAT_BASE 0x1000007FFC37C700ull +#define DCORE1_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE1_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE1_RTR7_SPECIAL_BASE 0x1000007FFC37CE80ull +#define DCORE1_RTR7_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR7_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_RTR7_DBG_ADDR_BASE 0x1000007FFC37D000ull +#define DCORE1_RTR7_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE1_RTR7_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE1_RTR7_DBG_ADDR_SPECIAL_BASE 0x1000007FFC37DE80ull +#define DCORE1_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE1_SRAM0_BANK_BASE 0x1000007FFC380000ull +#define DCORE1_SRAM0_BANK_MAX_OFFSET 0x1000 +#define DCORE1_SRAM0_BANK_SECTION 0xE800 + +#define mmDCORE1_SRAM0_BANK_SPECIAL_BASE 0x1000007FFC380E80ull +#define DCORE1_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM0_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_SRAM0_RTR_BASE 0x1000007FFC381000ull +#define DCORE1_SRAM0_RTR_MAX_OFFSET 0x1000 +#define DCORE1_SRAM0_RTR_SECTION 0xE800 + +#define mmDCORE1_SRAM0_RTR_SPECIAL_BASE 0x1000007FFC381E80ull +#define DCORE1_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM0_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC382000ull +#define DCORE1_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC382100ull +#define DCORE1_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC382200ull +#define DCORE1_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC382300ull +#define DCORE1_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC382400ull +#define DCORE1_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC382500ull +#define DCORE1_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC382600ull +#define DCORE1_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC382700ull +#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC382780ull +#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC382800ull +#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC382880ull +#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC382900ull +#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC382980ull +#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC382A00ull +#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC382A80ull +#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE1_SRAM0_DBG_CNT_SPECIAL_BASE 0x1000007FFC382E80ull +#define DCORE1_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE1_SRAM1_BANK_BASE 0x1000007FFC388000ull +#define DCORE1_SRAM1_BANK_MAX_OFFSET 0x1000 +#define DCORE1_SRAM1_BANK_SECTION 0xE800 + +#define mmDCORE1_SRAM1_BANK_SPECIAL_BASE 0x1000007FFC388E80ull +#define DCORE1_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM1_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_SRAM1_RTR_BASE 0x1000007FFC389000ull +#define DCORE1_SRAM1_RTR_MAX_OFFSET 0x1000 +#define DCORE1_SRAM1_RTR_SECTION 0xE800 + +#define mmDCORE1_SRAM1_RTR_SPECIAL_BASE 0x1000007FFC389E80ull +#define DCORE1_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM1_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC38A000ull +#define DCORE1_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC38A100ull +#define DCORE1_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC38A200ull +#define DCORE1_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC38A300ull +#define DCORE1_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC38A400ull +#define DCORE1_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC38A500ull +#define DCORE1_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC38A600ull +#define DCORE1_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC38A700ull +#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC38A780ull +#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC38A800ull +#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC38A880ull +#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC38A900ull +#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC38A980ull +#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC38AA00ull +#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC38AA80ull +#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE1_SRAM1_DBG_CNT_SPECIAL_BASE 0x1000007FFC38AE80ull +#define DCORE1_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE1_SRAM2_BANK_BASE 0x1000007FFC390000ull +#define DCORE1_SRAM2_BANK_MAX_OFFSET 0x1000 +#define DCORE1_SRAM2_BANK_SECTION 0xE800 + +#define mmDCORE1_SRAM2_BANK_SPECIAL_BASE 0x1000007FFC390E80ull +#define DCORE1_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM2_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_SRAM2_RTR_BASE 0x1000007FFC391000ull +#define DCORE1_SRAM2_RTR_MAX_OFFSET 0x1000 +#define DCORE1_SRAM2_RTR_SECTION 0xE800 + +#define mmDCORE1_SRAM2_RTR_SPECIAL_BASE 0x1000007FFC391E80ull +#define DCORE1_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM2_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC392000ull +#define DCORE1_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC392100ull +#define DCORE1_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC392200ull +#define DCORE1_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC392300ull +#define DCORE1_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC392400ull +#define DCORE1_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC392500ull +#define DCORE1_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC392600ull +#define DCORE1_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC392700ull +#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC392780ull +#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC392800ull +#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC392880ull +#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC392900ull +#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC392980ull +#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC392A00ull +#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC392A80ull +#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE1_SRAM2_DBG_CNT_SPECIAL_BASE 0x1000007FFC392E80ull +#define DCORE1_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE1_SRAM3_BANK_BASE 0x1000007FFC398000ull +#define DCORE1_SRAM3_BANK_MAX_OFFSET 0x1000 +#define DCORE1_SRAM3_BANK_SECTION 0xE800 + +#define mmDCORE1_SRAM3_BANK_SPECIAL_BASE 0x1000007FFC398E80ull +#define DCORE1_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM3_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_SRAM3_RTR_BASE 0x1000007FFC399000ull +#define DCORE1_SRAM3_RTR_MAX_OFFSET 0x1000 +#define DCORE1_SRAM3_RTR_SECTION 0xE800 + +#define mmDCORE1_SRAM3_RTR_SPECIAL_BASE 0x1000007FFC399E80ull +#define DCORE1_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM3_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC39A000ull +#define DCORE1_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC39A100ull +#define DCORE1_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC39A200ull +#define DCORE1_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC39A300ull +#define DCORE1_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC39A400ull +#define DCORE1_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC39A500ull +#define DCORE1_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC39A600ull +#define DCORE1_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC39A700ull +#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC39A780ull +#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC39A800ull +#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC39A880ull +#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC39A900ull +#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC39A980ull +#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC39AA00ull +#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC39AA80ull +#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE1_SRAM3_DBG_CNT_SPECIAL_BASE 0x1000007FFC39AE80ull +#define DCORE1_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE1_SRAM4_BANK_BASE 0x1000007FFC3A0000ull +#define DCORE1_SRAM4_BANK_MAX_OFFSET 0x1000 +#define DCORE1_SRAM4_BANK_SECTION 0xE800 + +#define mmDCORE1_SRAM4_BANK_SPECIAL_BASE 0x1000007FFC3A0E80ull +#define DCORE1_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM4_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_SRAM4_RTR_BASE 0x1000007FFC3A1000ull +#define DCORE1_SRAM4_RTR_MAX_OFFSET 0x1000 +#define DCORE1_SRAM4_RTR_SECTION 0xE800 + +#define mmDCORE1_SRAM4_RTR_SPECIAL_BASE 0x1000007FFC3A1E80ull +#define DCORE1_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM4_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC3A2000ull +#define DCORE1_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC3A2100ull +#define DCORE1_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC3A2200ull +#define DCORE1_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC3A2300ull +#define DCORE1_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC3A2400ull +#define DCORE1_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC3A2500ull +#define DCORE1_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC3A2600ull +#define DCORE1_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC3A2700ull +#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC3A2780ull +#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC3A2800ull +#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC3A2880ull +#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC3A2900ull +#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC3A2980ull +#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC3A2A00ull +#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC3A2A80ull +#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE1_SRAM4_DBG_CNT_SPECIAL_BASE 0x1000007FFC3A2E80ull +#define DCORE1_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE1_SRAM5_BANK_BASE 0x1000007FFC3A8000ull +#define DCORE1_SRAM5_BANK_MAX_OFFSET 0x1000 +#define DCORE1_SRAM5_BANK_SECTION 0xE800 + +#define mmDCORE1_SRAM5_BANK_SPECIAL_BASE 0x1000007FFC3A8E80ull +#define DCORE1_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM5_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_SRAM5_RTR_BASE 0x1000007FFC3A9000ull +#define DCORE1_SRAM5_RTR_MAX_OFFSET 0x1000 +#define DCORE1_SRAM5_RTR_SECTION 0xE800 + +#define mmDCORE1_SRAM5_RTR_SPECIAL_BASE 0x1000007FFC3A9E80ull +#define DCORE1_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM5_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC3AA000ull +#define DCORE1_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC3AA100ull +#define DCORE1_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC3AA200ull +#define DCORE1_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC3AA300ull +#define DCORE1_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC3AA400ull +#define DCORE1_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC3AA500ull +#define DCORE1_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC3AA600ull +#define DCORE1_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC3AA700ull +#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC3AA780ull +#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC3AA800ull +#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC3AA880ull +#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC3AA900ull +#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC3AA980ull +#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC3AAA00ull +#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC3AAA80ull +#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE1_SRAM5_DBG_CNT_SPECIAL_BASE 0x1000007FFC3AAE80ull +#define DCORE1_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE1_SRAM6_BANK_BASE 0x1000007FFC3B0000ull +#define DCORE1_SRAM6_BANK_MAX_OFFSET 0x1000 +#define DCORE1_SRAM6_BANK_SECTION 0xE800 + +#define mmDCORE1_SRAM6_BANK_SPECIAL_BASE 0x1000007FFC3B0E80ull +#define DCORE1_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM6_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_SRAM6_RTR_BASE 0x1000007FFC3B1000ull +#define DCORE1_SRAM6_RTR_MAX_OFFSET 0x1000 +#define DCORE1_SRAM6_RTR_SECTION 0xE800 + +#define mmDCORE1_SRAM6_RTR_SPECIAL_BASE 0x1000007FFC3B1E80ull +#define DCORE1_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM6_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC3B2000ull +#define DCORE1_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC3B2100ull +#define DCORE1_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC3B2200ull +#define DCORE1_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC3B2300ull +#define DCORE1_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC3B2400ull +#define DCORE1_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC3B2500ull +#define DCORE1_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC3B2600ull +#define DCORE1_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC3B2700ull +#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC3B2780ull +#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC3B2800ull +#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC3B2880ull +#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC3B2900ull +#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC3B2980ull +#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC3B2A00ull +#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC3B2A80ull +#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE1_SRAM6_DBG_CNT_SPECIAL_BASE 0x1000007FFC3B2E80ull +#define DCORE1_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE1_SRAM7_BANK_BASE 0x1000007FFC3B8000ull +#define DCORE1_SRAM7_BANK_MAX_OFFSET 0x1000 +#define DCORE1_SRAM7_BANK_SECTION 0xE800 + +#define mmDCORE1_SRAM7_BANK_SPECIAL_BASE 0x1000007FFC3B8E80ull +#define DCORE1_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM7_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_SRAM7_RTR_BASE 0x1000007FFC3B9000ull +#define DCORE1_SRAM7_RTR_MAX_OFFSET 0x1000 +#define DCORE1_SRAM7_RTR_SECTION 0xE800 + +#define mmDCORE1_SRAM7_RTR_SPECIAL_BASE 0x1000007FFC3B9E80ull +#define DCORE1_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM7_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC3BA000ull +#define DCORE1_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC3BA100ull +#define DCORE1_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC3BA200ull +#define DCORE1_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC3BA300ull +#define DCORE1_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC3BA400ull +#define DCORE1_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC3BA500ull +#define DCORE1_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC3BA600ull +#define DCORE1_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE1_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE1_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC3BA700ull +#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC3BA780ull +#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC3BA800ull +#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC3BA880ull +#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC3BA900ull +#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC3BA980ull +#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC3BAA00ull +#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE1_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC3BAA80ull +#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE1_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE1_SRAM7_DBG_CNT_SPECIAL_BASE 0x1000007FFC3BAE80ull +#define DCORE1_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE1_EDMA0_QM_DCCM_BASE 0x1000007FFC3C0000ull +#define DCORE1_EDMA0_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_EDMA0_QM_DCCM_SECTION 0x8000 + +#define mmDCORE1_EDMA0_QM_ARC_AUX_BASE 0x1000007FFC3C8000ull +#define DCORE1_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE1_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC3C8E80ull +#define DCORE1_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE1_EDMA0_QM_BASE 0x1000007FFC3CA000ull +#define DCORE1_EDMA0_QM_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_QM_SECTION 0x9000 + +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC3CA900ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC3CA908ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC3CA910ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC3CA918ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC3CA920ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC3CA928ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC3CA930ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC3CA938ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC3CA940ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC3CA948ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC3CA950ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC3CA958ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC3CA960ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC3CA968ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC3CA970ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC3CA978ull +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE1_EDMA0_QM_AXUSER_SECURED_BASE 0x1000007FFC3CAB00ull +#define DCORE1_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE1_EDMA0_QM_AXUSER_NONSECURED_BASE 0x1000007FFC3CAB80ull +#define DCORE1_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE1_EDMA0_QM_DBG_HBW_BASE 0x1000007FFC3CAC00ull +#define DCORE1_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_EDMA0_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_EDMA0_QM_DBG_LBW_BASE 0x1000007FFC3CAC80ull +#define DCORE1_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_EDMA0_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE1_EDMA0_QM_CGM_BASE 0x1000007FFC3CAD80ull +#define DCORE1_EDMA0_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_EDMA0_QM_CGM_SECTION 0x1000 + +#define mmDCORE1_EDMA0_QM_SPECIAL_BASE 0x1000007FFC3CAE80ull +#define DCORE1_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_EDMA0_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_EDMA0_CORE_BASE 0x1000007FFC3CB000ull +#define DCORE1_EDMA0_CORE_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_CORE_SECTION 0x8000 + +#define mmDCORE1_EDMA0_CORE_CTX_AXUSER_BASE 0x1000007FFC3CB800ull +#define DCORE1_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000 + +#define mmDCORE1_EDMA0_CORE_CTX_BASE 0x1000007FFC3CB860ull +#define DCORE1_EDMA0_CORE_CTX_MAX_OFFSET 0x9000 +#define DCORE1_EDMA0_CORE_CTX_SECTION 0x5A00 + +#define mmDCORE1_EDMA0_CORE_KDMA_CGM_BASE 0x1000007FFC3CBE00ull +#define DCORE1_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define DCORE1_EDMA0_CORE_KDMA_CGM_SECTION 0x8000 + +#define mmDCORE1_EDMA0_CORE_SPECIAL_BASE 0x1000007FFC3CBE80ull +#define DCORE1_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_EDMA0_CORE_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC3CC000ull +#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE1_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC3CC200ull +#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE1_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC3CC400ull +#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE1_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC3CC600ull +#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE1_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC3CC800ull +#define DCORE1_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE1_EDMA0_MSTR_IF_AXUSER_BASE 0x1000007FFC3CCA80ull +#define DCORE1_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE1_EDMA0_MSTR_IF_DBG_HBW_BASE 0x1000007FFC3CCB00ull +#define DCORE1_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_EDMA0_MSTR_IF_DBG_LBW_BASE 0x1000007FFC3CCB80ull +#define DCORE1_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE1_EDMA0_MSTR_IF_CORE_HBW_BASE 0x1000007FFC3CCC00ull +#define DCORE1_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE1_EDMA0_MSTR_IF_CORE_LBW_BASE 0x1000007FFC3CCD80ull +#define DCORE1_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE1_EDMA0_MSTR_IF_SPECIAL_BASE 0x1000007FFC3CCE80ull +#define DCORE1_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE1_EDMA1_QM_DCCM_BASE 0x1000007FFC3D0000ull +#define DCORE1_EDMA1_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE1_EDMA1_QM_DCCM_SECTION 0x8000 + +#define mmDCORE1_EDMA1_QM_ARC_AUX_BASE 0x1000007FFC3D8000ull +#define DCORE1_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE1_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC3D8E80ull +#define DCORE1_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE1_EDMA1_QM_BASE 0x1000007FFC3DA000ull +#define DCORE1_EDMA1_QM_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_QM_SECTION 0x9000 + +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC3DA900ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC3DA908ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC3DA910ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC3DA918ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC3DA920ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC3DA928ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC3DA930ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC3DA938ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC3DA940ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC3DA948ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC3DA950ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC3DA958ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC3DA960ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC3DA968ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC3DA970ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC3DA978ull +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE1_EDMA1_QM_AXUSER_SECURED_BASE 0x1000007FFC3DAB00ull +#define DCORE1_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE1_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE1_EDMA1_QM_AXUSER_NONSECURED_BASE 0x1000007FFC3DAB80ull +#define DCORE1_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE1_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE1_EDMA1_QM_DBG_HBW_BASE 0x1000007FFC3DAC00ull +#define DCORE1_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_EDMA1_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_EDMA1_QM_DBG_LBW_BASE 0x1000007FFC3DAC80ull +#define DCORE1_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_EDMA1_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE1_EDMA1_QM_CGM_BASE 0x1000007FFC3DAD80ull +#define DCORE1_EDMA1_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE1_EDMA1_QM_CGM_SECTION 0x1000 + +#define mmDCORE1_EDMA1_QM_SPECIAL_BASE 0x1000007FFC3DAE80ull +#define DCORE1_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_EDMA1_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_EDMA1_CORE_BASE 0x1000007FFC3DB000ull +#define DCORE1_EDMA1_CORE_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_CORE_SECTION 0x8000 + +#define mmDCORE1_EDMA1_CORE_CTX_AXUSER_BASE 0x1000007FFC3DB800ull +#define DCORE1_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000 + +#define mmDCORE1_EDMA1_CORE_CTX_BASE 0x1000007FFC3DB860ull +#define DCORE1_EDMA1_CORE_CTX_MAX_OFFSET 0x9000 +#define DCORE1_EDMA1_CORE_CTX_SECTION 0x5A00 + +#define mmDCORE1_EDMA1_CORE_KDMA_CGM_BASE 0x1000007FFC3DBE00ull +#define DCORE1_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define DCORE1_EDMA1_CORE_KDMA_CGM_SECTION 0x8000 + +#define mmDCORE1_EDMA1_CORE_SPECIAL_BASE 0x1000007FFC3DBE80ull +#define DCORE1_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_EDMA1_CORE_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC3DC000ull +#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE1_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC3DC200ull +#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE1_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC3DC400ull +#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE1_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC3DC600ull +#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE1_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC3DC800ull +#define DCORE1_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE1_EDMA1_MSTR_IF_AXUSER_BASE 0x1000007FFC3DCA80ull +#define DCORE1_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE1_EDMA1_MSTR_IF_DBG_HBW_BASE 0x1000007FFC3DCB00ull +#define DCORE1_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_EDMA1_MSTR_IF_DBG_LBW_BASE 0x1000007FFC3DCB80ull +#define DCORE1_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE1_EDMA1_MSTR_IF_CORE_HBW_BASE 0x1000007FFC3DCC00ull +#define DCORE1_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE1_EDMA1_MSTR_IF_CORE_LBW_BASE 0x1000007FFC3DCD80ull +#define DCORE1_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE1_EDMA1_MSTR_IF_SPECIAL_BASE 0x1000007FFC3DCE80ull +#define DCORE1_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE1_DEC0_CMD_BASE 0x1000007FFC3E0000ull +#define DCORE1_DEC0_CMD_MAX_OFFSET 0x1100 +#define DCORE1_DEC0_CMD_SECTION 0x1000 + +#define mmDCORE1_DEC0_VSI_BASE 0x1000007FFC3E1000ull +#define DCORE1_DEC0_VSI_MAX_OFFSET 0x6FC0 +#define DCORE1_DEC0_VSI_SECTION 0x1000 + +#define mmDCORE1_DEC0_L2C_BASE 0x1000007FFC3E2000ull +#define DCORE1_DEC0_L2C_MAX_OFFSET 0x39C0 +#define DCORE1_DEC0_L2C_SECTION 0x1000 + +#define mmDCORE1_VDEC0_BRDG_CTRL_BASE 0x1000007FFC3E3000ull +#define DCORE1_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_BRDG_CTRL_SECTION 0x8000 + +#define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x1000007FFC3E3800ull +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 + +#define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x1000007FFC3E3900ull +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 + +#define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x1000007FFC3E3A00ull +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 + +#define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x1000007FFC3E3B00ull +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 + +#define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x1000007FFC3E3C00ull +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define DCORE1_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 + +#define mmDCORE1_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x1000007FFC3E3E80ull +#define DCORE1_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_VDEC0_CTRL_BASE 0x1000007FFC3E4000ull +#define DCORE1_VDEC0_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_CTRL_SECTION 0xE800 + +#define mmDCORE1_VDEC0_CTRL_SPECIAL_BASE 0x1000007FFC3E4E80ull +#define DCORE1_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_VDEC0_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC3E5000ull +#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE1_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC3E5200ull +#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE1_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC3E5400ull +#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE1_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC3E5600ull +#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE1_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC3E5800ull +#define DCORE1_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE1_VDEC0_MSTR_IF_AXUSER_BASE 0x1000007FFC3E5A80ull +#define DCORE1_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE1_VDEC0_MSTR_IF_DBG_HBW_BASE 0x1000007FFC3E5B00ull +#define DCORE1_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_VDEC0_MSTR_IF_DBG_LBW_BASE 0x1000007FFC3E5B80ull +#define DCORE1_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE1_VDEC0_MSTR_IF_CORE_HBW_BASE 0x1000007FFC3E5C00ull +#define DCORE1_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE1_VDEC0_MSTR_IF_CORE_LBW_BASE 0x1000007FFC3E5D80ull +#define DCORE1_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE1_VDEC0_MSTR_IF_SPECIAL_BASE 0x1000007FFC3E5E80ull +#define DCORE1_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180 + +#define mmDCORE1_DEC1_CMD_BASE 0x1000007FFC3F0000ull +#define DCORE1_DEC1_CMD_MAX_OFFSET 0x1100 +#define DCORE1_DEC1_CMD_SECTION 0x1000 + +#define mmDCORE1_DEC1_VSI_BASE 0x1000007FFC3F1000ull +#define DCORE1_DEC1_VSI_MAX_OFFSET 0x6FC0 +#define DCORE1_DEC1_VSI_SECTION 0x1000 + +#define mmDCORE1_DEC1_L2C_BASE 0x1000007FFC3F2000ull +#define DCORE1_DEC1_L2C_MAX_OFFSET 0x39C0 +#define DCORE1_DEC1_L2C_SECTION 0x1000 + +#define mmDCORE1_VDEC1_BRDG_CTRL_BASE 0x1000007FFC3F3000ull +#define DCORE1_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_BRDG_CTRL_SECTION 0x8000 + +#define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x1000007FFC3F3800ull +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 + +#define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x1000007FFC3F3900ull +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 + +#define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x1000007FFC3F3A00ull +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 + +#define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x1000007FFC3F3B00ull +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 + +#define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x1000007FFC3F3C00ull +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define DCORE1_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 + +#define mmDCORE1_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x1000007FFC3F3E80ull +#define DCORE1_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_VDEC1_CTRL_BASE 0x1000007FFC3F4000ull +#define DCORE1_VDEC1_CTRL_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_CTRL_SECTION 0xE800 + +#define mmDCORE1_VDEC1_CTRL_SPECIAL_BASE 0x1000007FFC3F4E80ull +#define DCORE1_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_VDEC1_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC3F5000ull +#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE1_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC3F5200ull +#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE1_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC3F5400ull +#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE1_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC3F5600ull +#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE1_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE1_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC3F5800ull +#define DCORE1_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE1_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE1_VDEC1_MSTR_IF_AXUSER_BASE 0x1000007FFC3F5A80ull +#define DCORE1_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE1_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE1_VDEC1_MSTR_IF_DBG_HBW_BASE 0x1000007FFC3F5B00ull +#define DCORE1_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE1_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE1_VDEC1_MSTR_IF_DBG_LBW_BASE 0x1000007FFC3F5B80ull +#define DCORE1_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE1_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE1_VDEC1_MSTR_IF_CORE_HBW_BASE 0x1000007FFC3F5C00ull +#define DCORE1_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE1_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE1_VDEC1_MSTR_IF_CORE_LBW_BASE 0x1000007FFC3F5D80ull +#define DCORE1_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE1_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE1_VDEC1_MSTR_IF_SPECIAL_BASE 0x1000007FFC3F5E80ull +#define DCORE1_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180 + +#define mmDCORE2_TPC0_QM_DCCM_BASE 0x1000007FFC400000ull +#define DCORE2_TPC0_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC0_QM_DCCM_SECTION 0x8000 + +#define mmDCORE2_TPC0_QM_ARC_AUX_BASE 0x1000007FFC408000ull +#define DCORE2_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE2_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC408E80ull +#define DCORE2_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE2_TPC0_QM_BASE 0x1000007FFC40A000ull +#define DCORE2_TPC0_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_QM_SECTION 0x9000 + +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC40A900ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC40A908ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC40A910ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC40A918ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC40A920ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC40A928ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC40A930ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC40A938ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC40A940ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC40A948ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC40A950ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC40A958ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC40A960ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC40A968ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC40A970ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC40A978ull +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE2_TPC0_QM_AXUSER_SECURED_BASE 0x1000007FFC40AB00ull +#define DCORE2_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE2_TPC0_QM_AXUSER_NONSECURED_BASE 0x1000007FFC40AB80ull +#define DCORE2_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE2_TPC0_QM_DBG_HBW_BASE 0x1000007FFC40AC00ull +#define DCORE2_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC0_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_TPC0_QM_DBG_LBW_BASE 0x1000007FFC40AC80ull +#define DCORE2_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC0_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE2_TPC0_QM_CGM_BASE 0x1000007FFC40AD80ull +#define DCORE2_TPC0_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC0_QM_CGM_SECTION 0x1000 + +#define mmDCORE2_TPC0_QM_SPECIAL_BASE 0x1000007FFC40AE80ull +#define DCORE2_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC0_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFC40B000ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC0_CFG_BASE 0x1000007FFC40B000ull +#define DCORE2_TPC0_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC0_CFG_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFC40B050ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFC40B0A0ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFC40B0F0ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFC40B140ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFC40B190ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFC40B1E0ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFC40B230ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFC40B280ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFC40B2D0ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFC40B320ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFC40B370ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFC40B3C0ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFC40B410ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFC40B460ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFC40B4B0ull +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFC40B500ull +#define DCORE2_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE2_TPC0_CFG_KERNEL_BASE 0x1000007FFC40B508ull +#define DCORE2_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC0_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE2_TPC0_CFG_QM_TENSOR_0_BASE 0x1000007FFC40B5DCull +#define DCORE2_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_QM_TENSOR_1_BASE 0x1000007FFC40B62Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_QM_TENSOR_2_BASE 0x1000007FFC40B67Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_QM_TENSOR_3_BASE 0x1000007FFC40B6CCull +#define DCORE2_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_QM_TENSOR_4_BASE 0x1000007FFC40B71Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_QM_TENSOR_5_BASE 0x1000007FFC40B76Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_QM_TENSOR_6_BASE 0x1000007FFC40B7BCull +#define DCORE2_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_QM_TENSOR_7_BASE 0x1000007FFC40B80Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_QM_TENSOR_8_BASE 0x1000007FFC40B85Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_QM_TENSOR_9_BASE 0x1000007FFC40B8ACull +#define DCORE2_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_QM_TENSOR_10_BASE 0x1000007FFC40B8FCull +#define DCORE2_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_QM_TENSOR_11_BASE 0x1000007FFC40B94Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_QM_TENSOR_12_BASE 0x1000007FFC40B99Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_QM_TENSOR_13_BASE 0x1000007FFC40B9ECull +#define DCORE2_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_QM_TENSOR_14_BASE 0x1000007FFC40BA3Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_QM_TENSOR_15_BASE 0x1000007FFC40BA8Cull +#define DCORE2_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE2_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFC40BADCull +#define DCORE2_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE2_TPC0_CFG_QM_BASE 0x1000007FFC40BAE4ull +#define DCORE2_TPC0_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC0_CFG_QM_SECTION 0x31C0 + +#define mmDCORE2_TPC0_CFG_AXUSER_BASE 0x1000007FFC40BE00ull +#define DCORE2_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE2_TPC0_CFG_SPECIAL_BASE 0x1000007FFC40BE80ull +#define DCORE2_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC0_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC40C000ull +#define DCORE2_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE2_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC40C200ull +#define DCORE2_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE2_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC40C400ull +#define DCORE2_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE2_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC40C600ull +#define DCORE2_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE2_TPC0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC40C800ull +#define DCORE2_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE2_TPC0_MSTR_IF_AXUSER_BASE 0x1000007FFC40CA80ull +#define DCORE2_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE2_TPC0_MSTR_IF_DBG_HBW_BASE 0x1000007FFC40CB00ull +#define DCORE2_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_TPC0_MSTR_IF_DBG_LBW_BASE 0x1000007FFC40CB80ull +#define DCORE2_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE2_TPC0_MSTR_IF_CORE_HBW_BASE 0x1000007FFC40CC00ull +#define DCORE2_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE2_TPC0_MSTR_IF_CORE_LBW_BASE 0x1000007FFC40CD80ull +#define DCORE2_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE2_TPC0_MSTR_IF_SPECIAL_BASE 0x1000007FFC40CE80ull +#define DCORE2_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE2_TPC1_QM_DCCM_BASE 0x1000007FFC410000ull +#define DCORE2_TPC1_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC1_QM_DCCM_SECTION 0x8000 + +#define mmDCORE2_TPC1_QM_ARC_AUX_BASE 0x1000007FFC418000ull +#define DCORE2_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE2_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC418E80ull +#define DCORE2_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE2_TPC1_QM_BASE 0x1000007FFC41A000ull +#define DCORE2_TPC1_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_QM_SECTION 0x9000 + +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC41A900ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC41A908ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC41A910ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC41A918ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC41A920ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC41A928ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC41A930ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC41A938ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC41A940ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC41A948ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC41A950ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC41A958ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC41A960ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC41A968ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC41A970ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC41A978ull +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE2_TPC1_QM_AXUSER_SECURED_BASE 0x1000007FFC41AB00ull +#define DCORE2_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE2_TPC1_QM_AXUSER_NONSECURED_BASE 0x1000007FFC41AB80ull +#define DCORE2_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE2_TPC1_QM_DBG_HBW_BASE 0x1000007FFC41AC00ull +#define DCORE2_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC1_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_TPC1_QM_DBG_LBW_BASE 0x1000007FFC41AC80ull +#define DCORE2_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC1_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE2_TPC1_QM_CGM_BASE 0x1000007FFC41AD80ull +#define DCORE2_TPC1_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC1_QM_CGM_SECTION 0x1000 + +#define mmDCORE2_TPC1_QM_SPECIAL_BASE 0x1000007FFC41AE80ull +#define DCORE2_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC1_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFC41B000ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC1_CFG_BASE 0x1000007FFC41B000ull +#define DCORE2_TPC1_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC1_CFG_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFC41B050ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFC41B0A0ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFC41B0F0ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFC41B140ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFC41B190ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFC41B1E0ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFC41B230ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFC41B280ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFC41B2D0ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFC41B320ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFC41B370ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFC41B3C0ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFC41B410ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFC41B460ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFC41B4B0ull +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFC41B500ull +#define DCORE2_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE2_TPC1_CFG_KERNEL_BASE 0x1000007FFC41B508ull +#define DCORE2_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC1_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE2_TPC1_CFG_QM_TENSOR_0_BASE 0x1000007FFC41B5DCull +#define DCORE2_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_QM_TENSOR_1_BASE 0x1000007FFC41B62Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_QM_TENSOR_2_BASE 0x1000007FFC41B67Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_QM_TENSOR_3_BASE 0x1000007FFC41B6CCull +#define DCORE2_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_QM_TENSOR_4_BASE 0x1000007FFC41B71Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_QM_TENSOR_5_BASE 0x1000007FFC41B76Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_QM_TENSOR_6_BASE 0x1000007FFC41B7BCull +#define DCORE2_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_QM_TENSOR_7_BASE 0x1000007FFC41B80Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_QM_TENSOR_8_BASE 0x1000007FFC41B85Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_QM_TENSOR_9_BASE 0x1000007FFC41B8ACull +#define DCORE2_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_QM_TENSOR_10_BASE 0x1000007FFC41B8FCull +#define DCORE2_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_QM_TENSOR_11_BASE 0x1000007FFC41B94Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_QM_TENSOR_12_BASE 0x1000007FFC41B99Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_QM_TENSOR_13_BASE 0x1000007FFC41B9ECull +#define DCORE2_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_QM_TENSOR_14_BASE 0x1000007FFC41BA3Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_QM_TENSOR_15_BASE 0x1000007FFC41BA8Cull +#define DCORE2_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE2_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFC41BADCull +#define DCORE2_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE2_TPC1_CFG_QM_BASE 0x1000007FFC41BAE4ull +#define DCORE2_TPC1_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC1_CFG_QM_SECTION 0x31C0 + +#define mmDCORE2_TPC1_CFG_AXUSER_BASE 0x1000007FFC41BE00ull +#define DCORE2_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE2_TPC1_CFG_SPECIAL_BASE 0x1000007FFC41BE80ull +#define DCORE2_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC1_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC41C000ull +#define DCORE2_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE2_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC41C200ull +#define DCORE2_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE2_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC41C400ull +#define DCORE2_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE2_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC41C600ull +#define DCORE2_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE2_TPC1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC41C800ull +#define DCORE2_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE2_TPC1_MSTR_IF_AXUSER_BASE 0x1000007FFC41CA80ull +#define DCORE2_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE2_TPC1_MSTR_IF_DBG_HBW_BASE 0x1000007FFC41CB00ull +#define DCORE2_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_TPC1_MSTR_IF_DBG_LBW_BASE 0x1000007FFC41CB80ull +#define DCORE2_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE2_TPC1_MSTR_IF_CORE_HBW_BASE 0x1000007FFC41CC00ull +#define DCORE2_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE2_TPC1_MSTR_IF_CORE_LBW_BASE 0x1000007FFC41CD80ull +#define DCORE2_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE2_TPC1_MSTR_IF_SPECIAL_BASE 0x1000007FFC41CE80ull +#define DCORE2_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE2_TPC2_QM_DCCM_BASE 0x1000007FFC420000ull +#define DCORE2_TPC2_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC2_QM_DCCM_SECTION 0x8000 + +#define mmDCORE2_TPC2_QM_ARC_AUX_BASE 0x1000007FFC428000ull +#define DCORE2_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE2_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC428E80ull +#define DCORE2_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE2_TPC2_QM_BASE 0x1000007FFC42A000ull +#define DCORE2_TPC2_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_QM_SECTION 0x9000 + +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC42A900ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC42A908ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC42A910ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC42A918ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC42A920ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC42A928ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC42A930ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC42A938ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC42A940ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC42A948ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC42A950ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC42A958ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC42A960ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC42A968ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC42A970ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC42A978ull +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE2_TPC2_QM_AXUSER_SECURED_BASE 0x1000007FFC42AB00ull +#define DCORE2_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE2_TPC2_QM_AXUSER_NONSECURED_BASE 0x1000007FFC42AB80ull +#define DCORE2_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE2_TPC2_QM_DBG_HBW_BASE 0x1000007FFC42AC00ull +#define DCORE2_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC2_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_TPC2_QM_DBG_LBW_BASE 0x1000007FFC42AC80ull +#define DCORE2_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC2_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE2_TPC2_QM_CGM_BASE 0x1000007FFC42AD80ull +#define DCORE2_TPC2_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC2_QM_CGM_SECTION 0x1000 + +#define mmDCORE2_TPC2_QM_SPECIAL_BASE 0x1000007FFC42AE80ull +#define DCORE2_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC2_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFC42B000ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC2_CFG_BASE 0x1000007FFC42B000ull +#define DCORE2_TPC2_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC2_CFG_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFC42B050ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFC42B0A0ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFC42B0F0ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFC42B140ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFC42B190ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFC42B1E0ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFC42B230ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFC42B280ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFC42B2D0ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFC42B320ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFC42B370ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFC42B3C0ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFC42B410ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFC42B460ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFC42B4B0ull +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFC42B500ull +#define DCORE2_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE2_TPC2_CFG_KERNEL_BASE 0x1000007FFC42B508ull +#define DCORE2_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC2_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE2_TPC2_CFG_QM_TENSOR_0_BASE 0x1000007FFC42B5DCull +#define DCORE2_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_QM_TENSOR_1_BASE 0x1000007FFC42B62Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_QM_TENSOR_2_BASE 0x1000007FFC42B67Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_QM_TENSOR_3_BASE 0x1000007FFC42B6CCull +#define DCORE2_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_QM_TENSOR_4_BASE 0x1000007FFC42B71Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_QM_TENSOR_5_BASE 0x1000007FFC42B76Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_QM_TENSOR_6_BASE 0x1000007FFC42B7BCull +#define DCORE2_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_QM_TENSOR_7_BASE 0x1000007FFC42B80Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_QM_TENSOR_8_BASE 0x1000007FFC42B85Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_QM_TENSOR_9_BASE 0x1000007FFC42B8ACull +#define DCORE2_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_QM_TENSOR_10_BASE 0x1000007FFC42B8FCull +#define DCORE2_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_QM_TENSOR_11_BASE 0x1000007FFC42B94Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_QM_TENSOR_12_BASE 0x1000007FFC42B99Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_QM_TENSOR_13_BASE 0x1000007FFC42B9ECull +#define DCORE2_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_QM_TENSOR_14_BASE 0x1000007FFC42BA3Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_QM_TENSOR_15_BASE 0x1000007FFC42BA8Cull +#define DCORE2_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE2_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFC42BADCull +#define DCORE2_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE2_TPC2_CFG_QM_BASE 0x1000007FFC42BAE4ull +#define DCORE2_TPC2_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC2_CFG_QM_SECTION 0x31C0 + +#define mmDCORE2_TPC2_CFG_AXUSER_BASE 0x1000007FFC42BE00ull +#define DCORE2_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE2_TPC2_CFG_SPECIAL_BASE 0x1000007FFC42BE80ull +#define DCORE2_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC2_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC42C000ull +#define DCORE2_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE2_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC42C200ull +#define DCORE2_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE2_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC42C400ull +#define DCORE2_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE2_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC42C600ull +#define DCORE2_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE2_TPC2_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC42C800ull +#define DCORE2_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE2_TPC2_MSTR_IF_AXUSER_BASE 0x1000007FFC42CA80ull +#define DCORE2_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC2_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE2_TPC2_MSTR_IF_DBG_HBW_BASE 0x1000007FFC42CB00ull +#define DCORE2_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_TPC2_MSTR_IF_DBG_LBW_BASE 0x1000007FFC42CB80ull +#define DCORE2_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE2_TPC2_MSTR_IF_CORE_HBW_BASE 0x1000007FFC42CC00ull +#define DCORE2_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE2_TPC2_MSTR_IF_CORE_LBW_BASE 0x1000007FFC42CD80ull +#define DCORE2_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE2_TPC2_MSTR_IF_SPECIAL_BASE 0x1000007FFC42CE80ull +#define DCORE2_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE2_TPC3_QM_DCCM_BASE 0x1000007FFC430000ull +#define DCORE2_TPC3_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC3_QM_DCCM_SECTION 0x8000 + +#define mmDCORE2_TPC3_QM_ARC_AUX_BASE 0x1000007FFC438000ull +#define DCORE2_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE2_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC438E80ull +#define DCORE2_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE2_TPC3_QM_BASE 0x1000007FFC43A000ull +#define DCORE2_TPC3_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_QM_SECTION 0x9000 + +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC43A900ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC43A908ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC43A910ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC43A918ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC43A920ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC43A928ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC43A930ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC43A938ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC43A940ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC43A948ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC43A950ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC43A958ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC43A960ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC43A968ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC43A970ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC43A978ull +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE2_TPC3_QM_AXUSER_SECURED_BASE 0x1000007FFC43AB00ull +#define DCORE2_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE2_TPC3_QM_AXUSER_NONSECURED_BASE 0x1000007FFC43AB80ull +#define DCORE2_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE2_TPC3_QM_DBG_HBW_BASE 0x1000007FFC43AC00ull +#define DCORE2_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC3_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_TPC3_QM_DBG_LBW_BASE 0x1000007FFC43AC80ull +#define DCORE2_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC3_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE2_TPC3_QM_CGM_BASE 0x1000007FFC43AD80ull +#define DCORE2_TPC3_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC3_QM_CGM_SECTION 0x1000 + +#define mmDCORE2_TPC3_QM_SPECIAL_BASE 0x1000007FFC43AE80ull +#define DCORE2_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC3_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFC43B000ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC3_CFG_BASE 0x1000007FFC43B000ull +#define DCORE2_TPC3_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC3_CFG_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFC43B050ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFC43B0A0ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFC43B0F0ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFC43B140ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFC43B190ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFC43B1E0ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFC43B230ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFC43B280ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFC43B2D0ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFC43B320ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFC43B370ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFC43B3C0ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFC43B410ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFC43B460ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFC43B4B0ull +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFC43B500ull +#define DCORE2_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE2_TPC3_CFG_KERNEL_BASE 0x1000007FFC43B508ull +#define DCORE2_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC3_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE2_TPC3_CFG_QM_TENSOR_0_BASE 0x1000007FFC43B5DCull +#define DCORE2_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_QM_TENSOR_1_BASE 0x1000007FFC43B62Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_QM_TENSOR_2_BASE 0x1000007FFC43B67Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_QM_TENSOR_3_BASE 0x1000007FFC43B6CCull +#define DCORE2_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_QM_TENSOR_4_BASE 0x1000007FFC43B71Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_QM_TENSOR_5_BASE 0x1000007FFC43B76Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_QM_TENSOR_6_BASE 0x1000007FFC43B7BCull +#define DCORE2_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_QM_TENSOR_7_BASE 0x1000007FFC43B80Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_QM_TENSOR_8_BASE 0x1000007FFC43B85Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_QM_TENSOR_9_BASE 0x1000007FFC43B8ACull +#define DCORE2_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_QM_TENSOR_10_BASE 0x1000007FFC43B8FCull +#define DCORE2_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_QM_TENSOR_11_BASE 0x1000007FFC43B94Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_QM_TENSOR_12_BASE 0x1000007FFC43B99Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_QM_TENSOR_13_BASE 0x1000007FFC43B9ECull +#define DCORE2_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_QM_TENSOR_14_BASE 0x1000007FFC43BA3Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_QM_TENSOR_15_BASE 0x1000007FFC43BA8Cull +#define DCORE2_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE2_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFC43BADCull +#define DCORE2_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE2_TPC3_CFG_QM_BASE 0x1000007FFC43BAE4ull +#define DCORE2_TPC3_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC3_CFG_QM_SECTION 0x31C0 + +#define mmDCORE2_TPC3_CFG_AXUSER_BASE 0x1000007FFC43BE00ull +#define DCORE2_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE2_TPC3_CFG_SPECIAL_BASE 0x1000007FFC43BE80ull +#define DCORE2_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC3_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC43C000ull +#define DCORE2_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE2_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC43C200ull +#define DCORE2_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE2_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC43C400ull +#define DCORE2_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE2_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC43C600ull +#define DCORE2_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE2_TPC3_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC43C800ull +#define DCORE2_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE2_TPC3_MSTR_IF_AXUSER_BASE 0x1000007FFC43CA80ull +#define DCORE2_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC3_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE2_TPC3_MSTR_IF_DBG_HBW_BASE 0x1000007FFC43CB00ull +#define DCORE2_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_TPC3_MSTR_IF_DBG_LBW_BASE 0x1000007FFC43CB80ull +#define DCORE2_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE2_TPC3_MSTR_IF_CORE_HBW_BASE 0x1000007FFC43CC00ull +#define DCORE2_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE2_TPC3_MSTR_IF_CORE_LBW_BASE 0x1000007FFC43CD80ull +#define DCORE2_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE2_TPC3_MSTR_IF_SPECIAL_BASE 0x1000007FFC43CE80ull +#define DCORE2_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE2_TPC4_QM_DCCM_BASE 0x1000007FFC440000ull +#define DCORE2_TPC4_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC4_QM_DCCM_SECTION 0x8000 + +#define mmDCORE2_TPC4_QM_ARC_AUX_BASE 0x1000007FFC448000ull +#define DCORE2_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE2_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC448E80ull +#define DCORE2_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE2_TPC4_QM_BASE 0x1000007FFC44A000ull +#define DCORE2_TPC4_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_QM_SECTION 0x9000 + +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC44A900ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC44A908ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC44A910ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC44A918ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC44A920ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC44A928ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC44A930ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC44A938ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC44A940ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC44A948ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC44A950ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC44A958ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC44A960ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC44A968ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC44A970ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC44A978ull +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE2_TPC4_QM_AXUSER_SECURED_BASE 0x1000007FFC44AB00ull +#define DCORE2_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE2_TPC4_QM_AXUSER_NONSECURED_BASE 0x1000007FFC44AB80ull +#define DCORE2_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE2_TPC4_QM_DBG_HBW_BASE 0x1000007FFC44AC00ull +#define DCORE2_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC4_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_TPC4_QM_DBG_LBW_BASE 0x1000007FFC44AC80ull +#define DCORE2_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC4_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE2_TPC4_QM_CGM_BASE 0x1000007FFC44AD80ull +#define DCORE2_TPC4_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC4_QM_CGM_SECTION 0x1000 + +#define mmDCORE2_TPC4_QM_SPECIAL_BASE 0x1000007FFC44AE80ull +#define DCORE2_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC4_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFC44B000ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC4_CFG_BASE 0x1000007FFC44B000ull +#define DCORE2_TPC4_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC4_CFG_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFC44B050ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFC44B0A0ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFC44B0F0ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFC44B140ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFC44B190ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFC44B1E0ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFC44B230ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFC44B280ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFC44B2D0ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFC44B320ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFC44B370ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFC44B3C0ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFC44B410ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFC44B460ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFC44B4B0ull +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFC44B500ull +#define DCORE2_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE2_TPC4_CFG_KERNEL_BASE 0x1000007FFC44B508ull +#define DCORE2_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC4_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE2_TPC4_CFG_QM_TENSOR_0_BASE 0x1000007FFC44B5DCull +#define DCORE2_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_QM_TENSOR_1_BASE 0x1000007FFC44B62Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_QM_TENSOR_2_BASE 0x1000007FFC44B67Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_QM_TENSOR_3_BASE 0x1000007FFC44B6CCull +#define DCORE2_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_QM_TENSOR_4_BASE 0x1000007FFC44B71Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_QM_TENSOR_5_BASE 0x1000007FFC44B76Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_QM_TENSOR_6_BASE 0x1000007FFC44B7BCull +#define DCORE2_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_QM_TENSOR_7_BASE 0x1000007FFC44B80Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_QM_TENSOR_8_BASE 0x1000007FFC44B85Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_QM_TENSOR_9_BASE 0x1000007FFC44B8ACull +#define DCORE2_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_QM_TENSOR_10_BASE 0x1000007FFC44B8FCull +#define DCORE2_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_QM_TENSOR_11_BASE 0x1000007FFC44B94Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_QM_TENSOR_12_BASE 0x1000007FFC44B99Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_QM_TENSOR_13_BASE 0x1000007FFC44B9ECull +#define DCORE2_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_QM_TENSOR_14_BASE 0x1000007FFC44BA3Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_QM_TENSOR_15_BASE 0x1000007FFC44BA8Cull +#define DCORE2_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE2_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFC44BADCull +#define DCORE2_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE2_TPC4_CFG_QM_BASE 0x1000007FFC44BAE4ull +#define DCORE2_TPC4_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC4_CFG_QM_SECTION 0x31C0 + +#define mmDCORE2_TPC4_CFG_AXUSER_BASE 0x1000007FFC44BE00ull +#define DCORE2_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE2_TPC4_CFG_SPECIAL_BASE 0x1000007FFC44BE80ull +#define DCORE2_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC4_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC44C000ull +#define DCORE2_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE2_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC44C200ull +#define DCORE2_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE2_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC44C400ull +#define DCORE2_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE2_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC44C600ull +#define DCORE2_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE2_TPC4_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC44C800ull +#define DCORE2_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE2_TPC4_MSTR_IF_AXUSER_BASE 0x1000007FFC44CA80ull +#define DCORE2_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC4_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE2_TPC4_MSTR_IF_DBG_HBW_BASE 0x1000007FFC44CB00ull +#define DCORE2_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_TPC4_MSTR_IF_DBG_LBW_BASE 0x1000007FFC44CB80ull +#define DCORE2_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE2_TPC4_MSTR_IF_CORE_HBW_BASE 0x1000007FFC44CC00ull +#define DCORE2_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE2_TPC4_MSTR_IF_CORE_LBW_BASE 0x1000007FFC44CD80ull +#define DCORE2_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE2_TPC4_MSTR_IF_SPECIAL_BASE 0x1000007FFC44CE80ull +#define DCORE2_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE2_TPC5_QM_DCCM_BASE 0x1000007FFC450000ull +#define DCORE2_TPC5_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_TPC5_QM_DCCM_SECTION 0x8000 + +#define mmDCORE2_TPC5_QM_ARC_AUX_BASE 0x1000007FFC458000ull +#define DCORE2_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE2_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC458E80ull +#define DCORE2_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE2_TPC5_QM_BASE 0x1000007FFC45A000ull +#define DCORE2_TPC5_QM_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_QM_SECTION 0x9000 + +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC45A900ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC45A908ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC45A910ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC45A918ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC45A920ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC45A928ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC45A930ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC45A938ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC45A940ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC45A948ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC45A950ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC45A958ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC45A960ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC45A968ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC45A970ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC45A978ull +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE2_TPC5_QM_AXUSER_SECURED_BASE 0x1000007FFC45AB00ull +#define DCORE2_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE2_TPC5_QM_AXUSER_NONSECURED_BASE 0x1000007FFC45AB80ull +#define DCORE2_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE2_TPC5_QM_DBG_HBW_BASE 0x1000007FFC45AC00ull +#define DCORE2_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC5_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_TPC5_QM_DBG_LBW_BASE 0x1000007FFC45AC80ull +#define DCORE2_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC5_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE2_TPC5_QM_CGM_BASE 0x1000007FFC45AD80ull +#define DCORE2_TPC5_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_TPC5_QM_CGM_SECTION 0x1000 + +#define mmDCORE2_TPC5_QM_SPECIAL_BASE 0x1000007FFC45AE80ull +#define DCORE2_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC5_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFC45B000ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC5_CFG_BASE 0x1000007FFC45B000ull +#define DCORE2_TPC5_CFG_MAX_OFFSET 0x1000 +#define DCORE2_TPC5_CFG_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFC45B050ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFC45B0A0ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFC45B0F0ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFC45B140ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFC45B190ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFC45B1E0ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFC45B230ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFC45B280ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFC45B2D0ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFC45B320ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFC45B370ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFC45B3C0ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFC45B410ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFC45B460ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFC45B4B0ull +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFC45B500ull +#define DCORE2_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE2_TPC5_CFG_KERNEL_BASE 0x1000007FFC45B508ull +#define DCORE2_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE2_TPC5_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE2_TPC5_CFG_QM_TENSOR_0_BASE 0x1000007FFC45B5DCull +#define DCORE2_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_QM_TENSOR_1_BASE 0x1000007FFC45B62Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_QM_TENSOR_2_BASE 0x1000007FFC45B67Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_QM_TENSOR_3_BASE 0x1000007FFC45B6CCull +#define DCORE2_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_QM_TENSOR_4_BASE 0x1000007FFC45B71Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_QM_TENSOR_5_BASE 0x1000007FFC45B76Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_QM_TENSOR_6_BASE 0x1000007FFC45B7BCull +#define DCORE2_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_QM_TENSOR_7_BASE 0x1000007FFC45B80Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_QM_TENSOR_8_BASE 0x1000007FFC45B85Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_QM_TENSOR_9_BASE 0x1000007FFC45B8ACull +#define DCORE2_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_QM_TENSOR_10_BASE 0x1000007FFC45B8FCull +#define DCORE2_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_QM_TENSOR_11_BASE 0x1000007FFC45B94Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_QM_TENSOR_12_BASE 0x1000007FFC45B99Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_QM_TENSOR_13_BASE 0x1000007FFC45B9ECull +#define DCORE2_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_QM_TENSOR_14_BASE 0x1000007FFC45BA3Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_QM_TENSOR_15_BASE 0x1000007FFC45BA8Cull +#define DCORE2_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE2_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFC45BADCull +#define DCORE2_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE2_TPC5_CFG_QM_BASE 0x1000007FFC45BAE4ull +#define DCORE2_TPC5_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE2_TPC5_CFG_QM_SECTION 0x31C0 + +#define mmDCORE2_TPC5_CFG_AXUSER_BASE 0x1000007FFC45BE00ull +#define DCORE2_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE2_TPC5_CFG_SPECIAL_BASE 0x1000007FFC45BE80ull +#define DCORE2_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC5_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC45C000ull +#define DCORE2_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE2_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC45C200ull +#define DCORE2_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE2_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC45C400ull +#define DCORE2_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE2_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC45C600ull +#define DCORE2_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE2_TPC5_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC45C800ull +#define DCORE2_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE2_TPC5_MSTR_IF_AXUSER_BASE 0x1000007FFC45CA80ull +#define DCORE2_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_TPC5_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE2_TPC5_MSTR_IF_DBG_HBW_BASE 0x1000007FFC45CB00ull +#define DCORE2_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_TPC5_MSTR_IF_DBG_LBW_BASE 0x1000007FFC45CB80ull +#define DCORE2_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE2_TPC5_MSTR_IF_CORE_HBW_BASE 0x1000007FFC45CC00ull +#define DCORE2_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE2_TPC5_MSTR_IF_CORE_LBW_BASE 0x1000007FFC45CD80ull +#define DCORE2_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE2_TPC5_MSTR_IF_SPECIAL_BASE 0x1000007FFC45CE80ull +#define DCORE2_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC5_MSTR_IF_SPECIAL_SECTION 0x23180 + +#define mmDCORE2_HMMU0_MMU_BASE 0x1000007FFC480000ull +#define DCORE2_HMMU0_MMU_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_MMU_SECTION 0xE800 + +#define mmDCORE2_HMMU0_MMU_SPECIAL_BASE 0x1000007FFC480E80ull +#define DCORE2_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU0_MMU_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_HMMU0_STLB_BASE 0x1000007FFC481000ull +#define DCORE2_HMMU0_STLB_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_STLB_SECTION 0xE800 + +#define mmDCORE2_HMMU0_STLB_SPECIAL_BASE 0x1000007FFC481E80ull +#define DCORE2_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU0_STLB_SPECIAL_SECTION 0x1180 + +#define mmDCORE2_HMMU0_SCRAMB_OUT_BASE 0x1000007FFC483000ull +#define DCORE2_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_SCRAMB_OUT_SECTION 0xE800 + +#define mmDCORE2_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x1000007FFC483E80ull +#define DCORE2_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC484000ull +#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE2_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC484200ull +#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE2_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC484400ull +#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE2_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC484600ull +#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE2_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC484800ull +#define DCORE2_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE2_HMMU0_MSTR_IF_AXUSER_BASE 0x1000007FFC484A80ull +#define DCORE2_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE2_HMMU0_MSTR_IF_DBG_HBW_BASE 0x1000007FFC484B00ull +#define DCORE2_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_HMMU0_MSTR_IF_DBG_LBW_BASE 0x1000007FFC484B80ull +#define DCORE2_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE2_HMMU0_MSTR_IF_CORE_HBW_BASE 0x1000007FFC484C00ull +#define DCORE2_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE2_HMMU0_MSTR_IF_CORE_LBW_BASE 0x1000007FFC484D80ull +#define DCORE2_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE2_HMMU0_MSTR_IF_SPECIAL_BASE 0x1000007FFC484E80ull +#define DCORE2_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180 + +#define mmDCORE2_HMMU1_MMU_BASE 0x1000007FFC490000ull +#define DCORE2_HMMU1_MMU_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_MMU_SECTION 0xE800 + +#define mmDCORE2_HMMU1_MMU_SPECIAL_BASE 0x1000007FFC490E80ull +#define DCORE2_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU1_MMU_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_HMMU1_STLB_BASE 0x1000007FFC491000ull +#define DCORE2_HMMU1_STLB_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_STLB_SECTION 0xE800 + +#define mmDCORE2_HMMU1_STLB_SPECIAL_BASE 0x1000007FFC491E80ull +#define DCORE2_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU1_STLB_SPECIAL_SECTION 0x1180 + +#define mmDCORE2_HMMU1_SCRAMB_OUT_BASE 0x1000007FFC493000ull +#define DCORE2_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_SCRAMB_OUT_SECTION 0xE800 + +#define mmDCORE2_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x1000007FFC493E80ull +#define DCORE2_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC494000ull +#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE2_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC494200ull +#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE2_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC494400ull +#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE2_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC494600ull +#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE2_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC494800ull +#define DCORE2_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE2_HMMU1_MSTR_IF_AXUSER_BASE 0x1000007FFC494A80ull +#define DCORE2_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE2_HMMU1_MSTR_IF_DBG_HBW_BASE 0x1000007FFC494B00ull +#define DCORE2_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_HMMU1_MSTR_IF_DBG_LBW_BASE 0x1000007FFC494B80ull +#define DCORE2_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE2_HMMU1_MSTR_IF_CORE_HBW_BASE 0x1000007FFC494C00ull +#define DCORE2_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE2_HMMU1_MSTR_IF_CORE_LBW_BASE 0x1000007FFC494D80ull +#define DCORE2_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE2_HMMU1_MSTR_IF_SPECIAL_BASE 0x1000007FFC494E80ull +#define DCORE2_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180 + +#define mmDCORE2_HMMU2_MMU_BASE 0x1000007FFC4A0000ull +#define DCORE2_HMMU2_MMU_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_MMU_SECTION 0xE800 + +#define mmDCORE2_HMMU2_MMU_SPECIAL_BASE 0x1000007FFC4A0E80ull +#define DCORE2_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU2_MMU_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_HMMU2_STLB_BASE 0x1000007FFC4A1000ull +#define DCORE2_HMMU2_STLB_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_STLB_SECTION 0xE800 + +#define mmDCORE2_HMMU2_STLB_SPECIAL_BASE 0x1000007FFC4A1E80ull +#define DCORE2_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU2_STLB_SPECIAL_SECTION 0x1180 + +#define mmDCORE2_HMMU2_SCRAMB_OUT_BASE 0x1000007FFC4A3000ull +#define DCORE2_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_SCRAMB_OUT_SECTION 0xE800 + +#define mmDCORE2_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x1000007FFC4A3E80ull +#define DCORE2_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC4A4000ull +#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE2_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC4A4200ull +#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE2_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC4A4400ull +#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE2_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC4A4600ull +#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE2_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC4A4800ull +#define DCORE2_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE2_HMMU2_MSTR_IF_AXUSER_BASE 0x1000007FFC4A4A80ull +#define DCORE2_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE2_HMMU2_MSTR_IF_DBG_HBW_BASE 0x1000007FFC4A4B00ull +#define DCORE2_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_HMMU2_MSTR_IF_DBG_LBW_BASE 0x1000007FFC4A4B80ull +#define DCORE2_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE2_HMMU2_MSTR_IF_CORE_HBW_BASE 0x1000007FFC4A4C00ull +#define DCORE2_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE2_HMMU2_MSTR_IF_CORE_LBW_BASE 0x1000007FFC4A4D80ull +#define DCORE2_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE2_HMMU2_MSTR_IF_SPECIAL_BASE 0x1000007FFC4A4E80ull +#define DCORE2_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180 + +#define mmDCORE2_HMMU3_MMU_BASE 0x1000007FFC4B0000ull +#define DCORE2_HMMU3_MMU_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_MMU_SECTION 0xE800 + +#define mmDCORE2_HMMU3_MMU_SPECIAL_BASE 0x1000007FFC4B0E80ull +#define DCORE2_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU3_MMU_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_HMMU3_STLB_BASE 0x1000007FFC4B1000ull +#define DCORE2_HMMU3_STLB_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_STLB_SECTION 0xE800 + +#define mmDCORE2_HMMU3_STLB_SPECIAL_BASE 0x1000007FFC4B1E80ull +#define DCORE2_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU3_STLB_SPECIAL_SECTION 0x1180 + +#define mmDCORE2_HMMU3_SCRAMB_OUT_BASE 0x1000007FFC4B3000ull +#define DCORE2_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_SCRAMB_OUT_SECTION 0xE800 + +#define mmDCORE2_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x1000007FFC4B3E80ull +#define DCORE2_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC4B4000ull +#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE2_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC4B4200ull +#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE2_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC4B4400ull +#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE2_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC4B4600ull +#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE2_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC4B4800ull +#define DCORE2_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE2_HMMU3_MSTR_IF_AXUSER_BASE 0x1000007FFC4B4A80ull +#define DCORE2_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE2_HMMU3_MSTR_IF_DBG_HBW_BASE 0x1000007FFC4B4B00ull +#define DCORE2_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_HMMU3_MSTR_IF_DBG_LBW_BASE 0x1000007FFC4B4B80ull +#define DCORE2_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE2_HMMU3_MSTR_IF_CORE_HBW_BASE 0x1000007FFC4B4C00ull +#define DCORE2_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE2_HMMU3_MSTR_IF_CORE_LBW_BASE 0x1000007FFC4B4D80ull +#define DCORE2_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE2_HMMU3_MSTR_IF_SPECIAL_BASE 0x1000007FFC4B4E80ull +#define DCORE2_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180 + +#define mmDCORE2_SYNC_MNGR_OBJS_BASE 0x1000007FFC500000ull +#define DCORE2_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00 +#define DCORE2_SYNC_MNGR_OBJS_SECTION 0x1E000 + +#define mmDCORE2_SYNC_MNGR_GLBL_BASE 0x1000007FFC51E000ull +#define DCORE2_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000 +#define DCORE2_SYNC_MNGR_GLBL_SECTION 0xE800 + +#define mmDCORE2_SYNC_MNGR_GLBL_SPECIAL_BASE 0x1000007FFC51EE80ull +#define DCORE2_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC51F000ull +#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC51F200ull +#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC51F400ull +#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC51F600ull +#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE2_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC51F800ull +#define DCORE2_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE2_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x1000007FFC51FA80ull +#define DCORE2_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE2_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x1000007FFC51FB00ull +#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x1000007FFC51FB80ull +#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE2_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x1000007FFC51FC00ull +#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE2_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x1000007FFC51FD80ull +#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE2_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x1000007FFC51FE80ull +#define DCORE2_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_HIF0_BASE 0x1000007FFC520000ull +#define DCORE2_HIF0_MAX_OFFSET 0x1000 +#define DCORE2_HIF0_SECTION 0xE800 + +#define mmDCORE2_HIF0_SPECIAL_BASE 0x1000007FFC520E80ull +#define DCORE2_HIF0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HIF0_SPECIAL_SECTION 0x3180 + +#define mmDCORE2_HIF1_BASE 0x1000007FFC524000ull +#define DCORE2_HIF1_MAX_OFFSET 0x1000 +#define DCORE2_HIF1_SECTION 0xE800 + +#define mmDCORE2_HIF1_SPECIAL_BASE 0x1000007FFC524E80ull +#define DCORE2_HIF1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HIF1_SPECIAL_SECTION 0x3180 + +#define mmDCORE2_HIF2_BASE 0x1000007FFC528000ull +#define DCORE2_HIF2_MAX_OFFSET 0x1000 +#define DCORE2_HIF2_SECTION 0xE800 + +#define mmDCORE2_HIF2_SPECIAL_BASE 0x1000007FFC528E80ull +#define DCORE2_HIF2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HIF2_SPECIAL_SECTION 0x3180 + +#define mmDCORE2_HIF3_BASE 0x1000007FFC52C000ull +#define DCORE2_HIF3_MAX_OFFSET 0x1000 +#define DCORE2_HIF3_SECTION 0xE800 + +#define mmDCORE2_HIF3_SPECIAL_BASE 0x1000007FFC52CE80ull +#define DCORE2_HIF3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HIF3_SPECIAL_SECTION 0x13180 + +#define mmDCORE2_RTR0_CTRL_BASE 0x1000007FFC540000ull +#define DCORE2_RTR0_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_RTR0_CTRL_SECTION 0xE800 + +#define mmDCORE2_RTR0_CTRL_SPECIAL_BASE 0x1000007FFC540E80ull +#define DCORE2_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR0_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR0_H3_BASE 0x1000007FFC541000ull +#define DCORE2_RTR0_H3_MAX_OFFSET 0x1000 +#define DCORE2_RTR0_H3_SECTION 0xE800 + +#define mmDCORE2_RTR0_H3_SPECIAL_BASE 0x1000007FFC541E80ull +#define DCORE2_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR0_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC542000ull +#define DCORE2_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE2_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC542200ull +#define DCORE2_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE2_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC542400ull +#define DCORE2_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE2_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC542600ull +#define DCORE2_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE2_RTR0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC542800ull +#define DCORE2_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE2_RTR0_MSTR_IF_AXUSER_BASE 0x1000007FFC542A80ull +#define DCORE2_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_RTR0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE2_RTR0_MSTR_IF_DBG_HBW_BASE 0x1000007FFC542B00ull +#define DCORE2_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_RTR0_MSTR_IF_DBG_LBW_BASE 0x1000007FFC542B80ull +#define DCORE2_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE2_RTR0_MSTR_IF_CORE_HBW_BASE 0x1000007FFC542C00ull +#define DCORE2_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE2_RTR0_MSTR_IF_CORE_LBW_BASE 0x1000007FFC542D80ull +#define DCORE2_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE2_RTR0_MSTR_IF_SPECIAL_BASE 0x1000007FFC542E80ull +#define DCORE2_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR0_ADD_DEC_HBW_BASE 0x1000007FFC543000ull +#define DCORE2_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE2_RTR0_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE2_RTR0_ADD_DEC_LBW_BASE 0x1000007FFC543400ull +#define DCORE2_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE2_RTR0_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE2_RTR0_ADD_DEC_SPECIAL_BASE 0x1000007FFC543E80ull +#define DCORE2_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR0_BASE 0x1000007FFC544000ull +#define DCORE2_RTR0_MAX_OFFSET 0x1000 +#define DCORE2_RTR0_SECTION 0x3000 + +#define mmDCORE2_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC544300ull +#define DCORE2_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR0_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC544340ull +#define DCORE2_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC544380ull +#define DCORE2_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR0_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC5443C0ull +#define DCORE2_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC544400ull +#define DCORE2_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR0_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC544440ull +#define DCORE2_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC544480ull +#define DCORE2_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR0_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC5444C0ull +#define DCORE2_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR0_HBW_MFIFO_BASE 0x1000007FFC544500ull +#define DCORE2_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE2_RTR0_E2E_RD_LL_STAT_BASE 0x1000007FFC544540ull +#define DCORE2_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR0_E2E_WR_LL_STAT_BASE 0x1000007FFC544580ull +#define DCORE2_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR0_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE2_RTR0_RTR_HBW_XACT_STAT_BASE 0x1000007FFC544600ull +#define DCORE2_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE2_RTR0_RTR_LBW_XACT_STAT_BASE 0x1000007FFC544680ull +#define DCORE2_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE2_RTR0_RTR_E2E_XACT_STAT_BASE 0x1000007FFC544700ull +#define DCORE2_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE2_RTR0_SPECIAL_BASE 0x1000007FFC544E80ull +#define DCORE2_RTR0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR0_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR0_DBG_ADDR_BASE 0x1000007FFC545000ull +#define DCORE2_RTR0_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE2_RTR0_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE2_RTR0_DBG_ADDR_SPECIAL_BASE 0x1000007FFC545E80ull +#define DCORE2_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE2_RTR1_CTRL_BASE 0x1000007FFC548000ull +#define DCORE2_RTR1_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_RTR1_CTRL_SECTION 0xE800 + +#define mmDCORE2_RTR1_CTRL_SPECIAL_BASE 0x1000007FFC548E80ull +#define DCORE2_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR1_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR1_H3_BASE 0x1000007FFC549000ull +#define DCORE2_RTR1_H3_MAX_OFFSET 0x1000 +#define DCORE2_RTR1_H3_SECTION 0xE800 + +#define mmDCORE2_RTR1_H3_SPECIAL_BASE 0x1000007FFC549E80ull +#define DCORE2_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR1_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC54A000ull +#define DCORE2_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE2_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC54A200ull +#define DCORE2_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE2_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC54A400ull +#define DCORE2_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE2_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC54A600ull +#define DCORE2_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE2_RTR1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC54A800ull +#define DCORE2_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE2_RTR1_MSTR_IF_AXUSER_BASE 0x1000007FFC54AA80ull +#define DCORE2_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_RTR1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE2_RTR1_MSTR_IF_DBG_HBW_BASE 0x1000007FFC54AB00ull +#define DCORE2_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_RTR1_MSTR_IF_DBG_LBW_BASE 0x1000007FFC54AB80ull +#define DCORE2_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE2_RTR1_MSTR_IF_CORE_HBW_BASE 0x1000007FFC54AC00ull +#define DCORE2_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE2_RTR1_MSTR_IF_CORE_LBW_BASE 0x1000007FFC54AD80ull +#define DCORE2_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE2_RTR1_MSTR_IF_SPECIAL_BASE 0x1000007FFC54AE80ull +#define DCORE2_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR1_ADD_DEC_HBW_BASE 0x1000007FFC54B000ull +#define DCORE2_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE2_RTR1_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE2_RTR1_ADD_DEC_LBW_BASE 0x1000007FFC54B400ull +#define DCORE2_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE2_RTR1_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE2_RTR1_ADD_DEC_SPECIAL_BASE 0x1000007FFC54BE80ull +#define DCORE2_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR1_BASE 0x1000007FFC54C000ull +#define DCORE2_RTR1_MAX_OFFSET 0x1000 +#define DCORE2_RTR1_SECTION 0x3000 + +#define mmDCORE2_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC54C300ull +#define DCORE2_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR1_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC54C340ull +#define DCORE2_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC54C380ull +#define DCORE2_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR1_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC54C3C0ull +#define DCORE2_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC54C400ull +#define DCORE2_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR1_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC54C440ull +#define DCORE2_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC54C480ull +#define DCORE2_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR1_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC54C4C0ull +#define DCORE2_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR1_HBW_MFIFO_BASE 0x1000007FFC54C500ull +#define DCORE2_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE2_RTR1_E2E_RD_LL_STAT_BASE 0x1000007FFC54C540ull +#define DCORE2_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR1_E2E_WR_LL_STAT_BASE 0x1000007FFC54C580ull +#define DCORE2_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR1_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE2_RTR1_RTR_HBW_XACT_STAT_BASE 0x1000007FFC54C600ull +#define DCORE2_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE2_RTR1_RTR_LBW_XACT_STAT_BASE 0x1000007FFC54C680ull +#define DCORE2_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE2_RTR1_RTR_E2E_XACT_STAT_BASE 0x1000007FFC54C700ull +#define DCORE2_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE2_RTR1_SPECIAL_BASE 0x1000007FFC54CE80ull +#define DCORE2_RTR1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR1_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR1_DBG_ADDR_BASE 0x1000007FFC54D000ull +#define DCORE2_RTR1_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE2_RTR1_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE2_RTR1_DBG_ADDR_SPECIAL_BASE 0x1000007FFC54DE80ull +#define DCORE2_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE2_RTR2_CTRL_BASE 0x1000007FFC550000ull +#define DCORE2_RTR2_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_RTR2_CTRL_SECTION 0xE800 + +#define mmDCORE2_RTR2_CTRL_SPECIAL_BASE 0x1000007FFC550E80ull +#define DCORE2_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR2_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR2_H3_BASE 0x1000007FFC551000ull +#define DCORE2_RTR2_H3_MAX_OFFSET 0x1000 +#define DCORE2_RTR2_H3_SECTION 0xE800 + +#define mmDCORE2_RTR2_H3_SPECIAL_BASE 0x1000007FFC551E80ull +#define DCORE2_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR2_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC552000ull +#define DCORE2_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE2_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC552200ull +#define DCORE2_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE2_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC552400ull +#define DCORE2_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE2_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC552600ull +#define DCORE2_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE2_RTR2_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC552800ull +#define DCORE2_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE2_RTR2_MSTR_IF_AXUSER_BASE 0x1000007FFC552A80ull +#define DCORE2_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_RTR2_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE2_RTR2_MSTR_IF_DBG_HBW_BASE 0x1000007FFC552B00ull +#define DCORE2_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_RTR2_MSTR_IF_DBG_LBW_BASE 0x1000007FFC552B80ull +#define DCORE2_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE2_RTR2_MSTR_IF_CORE_HBW_BASE 0x1000007FFC552C00ull +#define DCORE2_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE2_RTR2_MSTR_IF_CORE_LBW_BASE 0x1000007FFC552D80ull +#define DCORE2_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE2_RTR2_MSTR_IF_SPECIAL_BASE 0x1000007FFC552E80ull +#define DCORE2_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR2_ADD_DEC_HBW_BASE 0x1000007FFC553000ull +#define DCORE2_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE2_RTR2_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE2_RTR2_ADD_DEC_LBW_BASE 0x1000007FFC553400ull +#define DCORE2_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE2_RTR2_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE2_RTR2_ADD_DEC_SPECIAL_BASE 0x1000007FFC553E80ull +#define DCORE2_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR2_BASE 0x1000007FFC554000ull +#define DCORE2_RTR2_MAX_OFFSET 0x1000 +#define DCORE2_RTR2_SECTION 0x3000 + +#define mmDCORE2_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC554300ull +#define DCORE2_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR2_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC554340ull +#define DCORE2_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC554380ull +#define DCORE2_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR2_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC5543C0ull +#define DCORE2_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC554400ull +#define DCORE2_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR2_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC554440ull +#define DCORE2_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC554480ull +#define DCORE2_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR2_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC5544C0ull +#define DCORE2_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR2_HBW_MFIFO_BASE 0x1000007FFC554500ull +#define DCORE2_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE2_RTR2_E2E_RD_LL_STAT_BASE 0x1000007FFC554540ull +#define DCORE2_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR2_E2E_WR_LL_STAT_BASE 0x1000007FFC554580ull +#define DCORE2_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR2_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE2_RTR2_RTR_HBW_XACT_STAT_BASE 0x1000007FFC554600ull +#define DCORE2_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE2_RTR2_RTR_LBW_XACT_STAT_BASE 0x1000007FFC554680ull +#define DCORE2_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE2_RTR2_RTR_E2E_XACT_STAT_BASE 0x1000007FFC554700ull +#define DCORE2_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE2_RTR2_SPECIAL_BASE 0x1000007FFC554E80ull +#define DCORE2_RTR2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR2_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR2_DBG_ADDR_BASE 0x1000007FFC555000ull +#define DCORE2_RTR2_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE2_RTR2_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE2_RTR2_DBG_ADDR_SPECIAL_BASE 0x1000007FFC555E80ull +#define DCORE2_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE2_RTR3_CTRL_BASE 0x1000007FFC558000ull +#define DCORE2_RTR3_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_RTR3_CTRL_SECTION 0xE800 + +#define mmDCORE2_RTR3_CTRL_SPECIAL_BASE 0x1000007FFC558E80ull +#define DCORE2_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR3_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR3_H3_BASE 0x1000007FFC559000ull +#define DCORE2_RTR3_H3_MAX_OFFSET 0x1000 +#define DCORE2_RTR3_H3_SECTION 0xE800 + +#define mmDCORE2_RTR3_H3_SPECIAL_BASE 0x1000007FFC559E80ull +#define DCORE2_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR3_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC55A000ull +#define DCORE2_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE2_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC55A200ull +#define DCORE2_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE2_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC55A400ull +#define DCORE2_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE2_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC55A600ull +#define DCORE2_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE2_RTR3_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC55A800ull +#define DCORE2_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE2_RTR3_MSTR_IF_AXUSER_BASE 0x1000007FFC55AA80ull +#define DCORE2_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_RTR3_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE2_RTR3_MSTR_IF_DBG_HBW_BASE 0x1000007FFC55AB00ull +#define DCORE2_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_RTR3_MSTR_IF_DBG_LBW_BASE 0x1000007FFC55AB80ull +#define DCORE2_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE2_RTR3_MSTR_IF_CORE_HBW_BASE 0x1000007FFC55AC00ull +#define DCORE2_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE2_RTR3_MSTR_IF_CORE_LBW_BASE 0x1000007FFC55AD80ull +#define DCORE2_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE2_RTR3_MSTR_IF_SPECIAL_BASE 0x1000007FFC55AE80ull +#define DCORE2_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR3_ADD_DEC_HBW_BASE 0x1000007FFC55B000ull +#define DCORE2_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE2_RTR3_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE2_RTR3_ADD_DEC_LBW_BASE 0x1000007FFC55B400ull +#define DCORE2_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE2_RTR3_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE2_RTR3_ADD_DEC_SPECIAL_BASE 0x1000007FFC55BE80ull +#define DCORE2_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR3_BASE 0x1000007FFC55C000ull +#define DCORE2_RTR3_MAX_OFFSET 0x1000 +#define DCORE2_RTR3_SECTION 0x3000 + +#define mmDCORE2_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC55C300ull +#define DCORE2_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR3_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC55C340ull +#define DCORE2_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC55C380ull +#define DCORE2_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR3_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC55C3C0ull +#define DCORE2_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC55C400ull +#define DCORE2_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR3_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC55C440ull +#define DCORE2_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC55C480ull +#define DCORE2_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR3_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC55C4C0ull +#define DCORE2_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR3_HBW_MFIFO_BASE 0x1000007FFC55C500ull +#define DCORE2_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE2_RTR3_E2E_RD_LL_STAT_BASE 0x1000007FFC55C540ull +#define DCORE2_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR3_E2E_WR_LL_STAT_BASE 0x1000007FFC55C580ull +#define DCORE2_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR3_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE2_RTR3_RTR_HBW_XACT_STAT_BASE 0x1000007FFC55C600ull +#define DCORE2_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE2_RTR3_RTR_LBW_XACT_STAT_BASE 0x1000007FFC55C680ull +#define DCORE2_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE2_RTR3_RTR_E2E_XACT_STAT_BASE 0x1000007FFC55C700ull +#define DCORE2_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE2_RTR3_SPECIAL_BASE 0x1000007FFC55CE80ull +#define DCORE2_RTR3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR3_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR3_DBG_ADDR_BASE 0x1000007FFC55D000ull +#define DCORE2_RTR3_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE2_RTR3_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE2_RTR3_DBG_ADDR_SPECIAL_BASE 0x1000007FFC55DE80ull +#define DCORE2_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE2_RTR4_CTRL_BASE 0x1000007FFC560000ull +#define DCORE2_RTR4_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_RTR4_CTRL_SECTION 0xE800 + +#define mmDCORE2_RTR4_CTRL_SPECIAL_BASE 0x1000007FFC560E80ull +#define DCORE2_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR4_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR4_H3_BASE 0x1000007FFC561000ull +#define DCORE2_RTR4_H3_MAX_OFFSET 0x1000 +#define DCORE2_RTR4_H3_SECTION 0xE800 + +#define mmDCORE2_RTR4_H3_SPECIAL_BASE 0x1000007FFC561E80ull +#define DCORE2_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR4_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC562000ull +#define DCORE2_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE2_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC562200ull +#define DCORE2_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE2_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC562400ull +#define DCORE2_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE2_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC562600ull +#define DCORE2_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE2_RTR4_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC562800ull +#define DCORE2_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE2_RTR4_MSTR_IF_AXUSER_BASE 0x1000007FFC562A80ull +#define DCORE2_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_RTR4_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE2_RTR4_MSTR_IF_DBG_HBW_BASE 0x1000007FFC562B00ull +#define DCORE2_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_RTR4_MSTR_IF_DBG_LBW_BASE 0x1000007FFC562B80ull +#define DCORE2_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE2_RTR4_MSTR_IF_CORE_HBW_BASE 0x1000007FFC562C00ull +#define DCORE2_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE2_RTR4_MSTR_IF_CORE_LBW_BASE 0x1000007FFC562D80ull +#define DCORE2_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE2_RTR4_MSTR_IF_SPECIAL_BASE 0x1000007FFC562E80ull +#define DCORE2_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR4_ADD_DEC_HBW_BASE 0x1000007FFC563000ull +#define DCORE2_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE2_RTR4_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE2_RTR4_ADD_DEC_LBW_BASE 0x1000007FFC563400ull +#define DCORE2_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE2_RTR4_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE2_RTR4_ADD_DEC_SPECIAL_BASE 0x1000007FFC563E80ull +#define DCORE2_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR4_BASE 0x1000007FFC564000ull +#define DCORE2_RTR4_MAX_OFFSET 0x1000 +#define DCORE2_RTR4_SECTION 0x3000 + +#define mmDCORE2_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC564300ull +#define DCORE2_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR4_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC564340ull +#define DCORE2_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC564380ull +#define DCORE2_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR4_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC5643C0ull +#define DCORE2_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC564400ull +#define DCORE2_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR4_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC564440ull +#define DCORE2_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC564480ull +#define DCORE2_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR4_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC5644C0ull +#define DCORE2_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR4_HBW_MFIFO_BASE 0x1000007FFC564500ull +#define DCORE2_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE2_RTR4_E2E_RD_LL_STAT_BASE 0x1000007FFC564540ull +#define DCORE2_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR4_E2E_WR_LL_STAT_BASE 0x1000007FFC564580ull +#define DCORE2_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR4_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE2_RTR4_RTR_HBW_XACT_STAT_BASE 0x1000007FFC564600ull +#define DCORE2_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE2_RTR4_RTR_LBW_XACT_STAT_BASE 0x1000007FFC564680ull +#define DCORE2_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE2_RTR4_RTR_E2E_XACT_STAT_BASE 0x1000007FFC564700ull +#define DCORE2_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE2_RTR4_SPECIAL_BASE 0x1000007FFC564E80ull +#define DCORE2_RTR4_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR4_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR4_DBG_ADDR_BASE 0x1000007FFC565000ull +#define DCORE2_RTR4_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE2_RTR4_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE2_RTR4_DBG_ADDR_SPECIAL_BASE 0x1000007FFC565E80ull +#define DCORE2_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE2_RTR5_CTRL_BASE 0x1000007FFC568000ull +#define DCORE2_RTR5_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_RTR5_CTRL_SECTION 0xE800 + +#define mmDCORE2_RTR5_CTRL_SPECIAL_BASE 0x1000007FFC568E80ull +#define DCORE2_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR5_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR5_H3_BASE 0x1000007FFC569000ull +#define DCORE2_RTR5_H3_MAX_OFFSET 0x1000 +#define DCORE2_RTR5_H3_SECTION 0xE800 + +#define mmDCORE2_RTR5_H3_SPECIAL_BASE 0x1000007FFC569E80ull +#define DCORE2_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR5_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC56A000ull +#define DCORE2_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE2_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC56A200ull +#define DCORE2_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE2_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC56A400ull +#define DCORE2_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE2_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC56A600ull +#define DCORE2_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE2_RTR5_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC56A800ull +#define DCORE2_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE2_RTR5_MSTR_IF_AXUSER_BASE 0x1000007FFC56AA80ull +#define DCORE2_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_RTR5_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE2_RTR5_MSTR_IF_DBG_HBW_BASE 0x1000007FFC56AB00ull +#define DCORE2_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_RTR5_MSTR_IF_DBG_LBW_BASE 0x1000007FFC56AB80ull +#define DCORE2_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE2_RTR5_MSTR_IF_CORE_HBW_BASE 0x1000007FFC56AC00ull +#define DCORE2_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE2_RTR5_MSTR_IF_CORE_LBW_BASE 0x1000007FFC56AD80ull +#define DCORE2_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE2_RTR5_MSTR_IF_SPECIAL_BASE 0x1000007FFC56AE80ull +#define DCORE2_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR5_ADD_DEC_HBW_BASE 0x1000007FFC56B000ull +#define DCORE2_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE2_RTR5_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE2_RTR5_ADD_DEC_LBW_BASE 0x1000007FFC56B400ull +#define DCORE2_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE2_RTR5_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE2_RTR5_ADD_DEC_SPECIAL_BASE 0x1000007FFC56BE80ull +#define DCORE2_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR5_BASE 0x1000007FFC56C000ull +#define DCORE2_RTR5_MAX_OFFSET 0x1000 +#define DCORE2_RTR5_SECTION 0x3000 + +#define mmDCORE2_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC56C300ull +#define DCORE2_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR5_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC56C340ull +#define DCORE2_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC56C380ull +#define DCORE2_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR5_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC56C3C0ull +#define DCORE2_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC56C400ull +#define DCORE2_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR5_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC56C440ull +#define DCORE2_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC56C480ull +#define DCORE2_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR5_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC56C4C0ull +#define DCORE2_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR5_HBW_MFIFO_BASE 0x1000007FFC56C500ull +#define DCORE2_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE2_RTR5_E2E_RD_LL_STAT_BASE 0x1000007FFC56C540ull +#define DCORE2_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR5_E2E_WR_LL_STAT_BASE 0x1000007FFC56C580ull +#define DCORE2_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR5_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE2_RTR5_RTR_HBW_XACT_STAT_BASE 0x1000007FFC56C600ull +#define DCORE2_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE2_RTR5_RTR_LBW_XACT_STAT_BASE 0x1000007FFC56C680ull +#define DCORE2_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE2_RTR5_RTR_E2E_XACT_STAT_BASE 0x1000007FFC56C700ull +#define DCORE2_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE2_RTR5_SPECIAL_BASE 0x1000007FFC56CE80ull +#define DCORE2_RTR5_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR5_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR5_DBG_ADDR_BASE 0x1000007FFC56D000ull +#define DCORE2_RTR5_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE2_RTR5_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE2_RTR5_DBG_ADDR_SPECIAL_BASE 0x1000007FFC56DE80ull +#define DCORE2_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE2_RTR6_CTRL_BASE 0x1000007FFC570000ull +#define DCORE2_RTR6_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_RTR6_CTRL_SECTION 0xE800 + +#define mmDCORE2_RTR6_CTRL_SPECIAL_BASE 0x1000007FFC570E80ull +#define DCORE2_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR6_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR6_H3_BASE 0x1000007FFC571000ull +#define DCORE2_RTR6_H3_MAX_OFFSET 0x1000 +#define DCORE2_RTR6_H3_SECTION 0xE800 + +#define mmDCORE2_RTR6_H3_SPECIAL_BASE 0x1000007FFC571E80ull +#define DCORE2_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR6_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC572000ull +#define DCORE2_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE2_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC572200ull +#define DCORE2_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE2_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC572400ull +#define DCORE2_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE2_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC572600ull +#define DCORE2_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE2_RTR6_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC572800ull +#define DCORE2_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE2_RTR6_MSTR_IF_AXUSER_BASE 0x1000007FFC572A80ull +#define DCORE2_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_RTR6_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE2_RTR6_MSTR_IF_DBG_HBW_BASE 0x1000007FFC572B00ull +#define DCORE2_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_RTR6_MSTR_IF_DBG_LBW_BASE 0x1000007FFC572B80ull +#define DCORE2_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE2_RTR6_MSTR_IF_CORE_HBW_BASE 0x1000007FFC572C00ull +#define DCORE2_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE2_RTR6_MSTR_IF_CORE_LBW_BASE 0x1000007FFC572D80ull +#define DCORE2_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE2_RTR6_MSTR_IF_SPECIAL_BASE 0x1000007FFC572E80ull +#define DCORE2_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR6_ADD_DEC_HBW_BASE 0x1000007FFC573000ull +#define DCORE2_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE2_RTR6_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE2_RTR6_ADD_DEC_LBW_BASE 0x1000007FFC573400ull +#define DCORE2_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE2_RTR6_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE2_RTR6_ADD_DEC_SPECIAL_BASE 0x1000007FFC573E80ull +#define DCORE2_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR6_BASE 0x1000007FFC574000ull +#define DCORE2_RTR6_MAX_OFFSET 0x1000 +#define DCORE2_RTR6_SECTION 0x3000 + +#define mmDCORE2_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC574300ull +#define DCORE2_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR6_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC574340ull +#define DCORE2_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC574380ull +#define DCORE2_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR6_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC5743C0ull +#define DCORE2_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC574400ull +#define DCORE2_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR6_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC574440ull +#define DCORE2_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC574480ull +#define DCORE2_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR6_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC5744C0ull +#define DCORE2_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR6_HBW_MFIFO_BASE 0x1000007FFC574500ull +#define DCORE2_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE2_RTR6_E2E_RD_LL_STAT_BASE 0x1000007FFC574540ull +#define DCORE2_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR6_E2E_WR_LL_STAT_BASE 0x1000007FFC574580ull +#define DCORE2_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR6_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE2_RTR6_RTR_HBW_XACT_STAT_BASE 0x1000007FFC574600ull +#define DCORE2_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE2_RTR6_RTR_LBW_XACT_STAT_BASE 0x1000007FFC574680ull +#define DCORE2_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE2_RTR6_RTR_E2E_XACT_STAT_BASE 0x1000007FFC574700ull +#define DCORE2_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE2_RTR6_SPECIAL_BASE 0x1000007FFC574E80ull +#define DCORE2_RTR6_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR6_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR6_DBG_ADDR_BASE 0x1000007FFC575000ull +#define DCORE2_RTR6_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE2_RTR6_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE2_RTR6_DBG_ADDR_SPECIAL_BASE 0x1000007FFC575E80ull +#define DCORE2_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE2_RTR7_CTRL_BASE 0x1000007FFC578000ull +#define DCORE2_RTR7_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_RTR7_CTRL_SECTION 0xE800 + +#define mmDCORE2_RTR7_CTRL_SPECIAL_BASE 0x1000007FFC578E80ull +#define DCORE2_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR7_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR7_H3_BASE 0x1000007FFC579000ull +#define DCORE2_RTR7_H3_MAX_OFFSET 0x1000 +#define DCORE2_RTR7_H3_SECTION 0xE800 + +#define mmDCORE2_RTR7_H3_SPECIAL_BASE 0x1000007FFC579E80ull +#define DCORE2_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR7_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC57A000ull +#define DCORE2_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE2_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC57A200ull +#define DCORE2_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE2_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC57A400ull +#define DCORE2_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE2_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC57A600ull +#define DCORE2_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE2_RTR7_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC57A800ull +#define DCORE2_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE2_RTR7_MSTR_IF_AXUSER_BASE 0x1000007FFC57AA80ull +#define DCORE2_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_RTR7_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE2_RTR7_MSTR_IF_DBG_HBW_BASE 0x1000007FFC57AB00ull +#define DCORE2_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_RTR7_MSTR_IF_DBG_LBW_BASE 0x1000007FFC57AB80ull +#define DCORE2_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE2_RTR7_MSTR_IF_CORE_HBW_BASE 0x1000007FFC57AC00ull +#define DCORE2_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE2_RTR7_MSTR_IF_CORE_LBW_BASE 0x1000007FFC57AD80ull +#define DCORE2_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE2_RTR7_MSTR_IF_SPECIAL_BASE 0x1000007FFC57AE80ull +#define DCORE2_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR7_ADD_DEC_HBW_BASE 0x1000007FFC57B000ull +#define DCORE2_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE2_RTR7_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE2_RTR7_ADD_DEC_LBW_BASE 0x1000007FFC57B400ull +#define DCORE2_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE2_RTR7_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE2_RTR7_ADD_DEC_SPECIAL_BASE 0x1000007FFC57BE80ull +#define DCORE2_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR7_BASE 0x1000007FFC57C000ull +#define DCORE2_RTR7_MAX_OFFSET 0x1000 +#define DCORE2_RTR7_SECTION 0x3000 + +#define mmDCORE2_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC57C300ull +#define DCORE2_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR7_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC57C340ull +#define DCORE2_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC57C380ull +#define DCORE2_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR7_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC57C3C0ull +#define DCORE2_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC57C400ull +#define DCORE2_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR7_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC57C440ull +#define DCORE2_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC57C480ull +#define DCORE2_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR7_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC57C4C0ull +#define DCORE2_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR7_HBW_MFIFO_BASE 0x1000007FFC57C500ull +#define DCORE2_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE2_RTR7_E2E_RD_LL_STAT_BASE 0x1000007FFC57C540ull +#define DCORE2_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE2_RTR7_E2E_WR_LL_STAT_BASE 0x1000007FFC57C580ull +#define DCORE2_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE2_RTR7_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE2_RTR7_RTR_HBW_XACT_STAT_BASE 0x1000007FFC57C600ull +#define DCORE2_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE2_RTR7_RTR_LBW_XACT_STAT_BASE 0x1000007FFC57C680ull +#define DCORE2_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE2_RTR7_RTR_E2E_XACT_STAT_BASE 0x1000007FFC57C700ull +#define DCORE2_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE2_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE2_RTR7_SPECIAL_BASE 0x1000007FFC57CE80ull +#define DCORE2_RTR7_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR7_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_RTR7_DBG_ADDR_BASE 0x1000007FFC57D000ull +#define DCORE2_RTR7_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE2_RTR7_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE2_RTR7_DBG_ADDR_SPECIAL_BASE 0x1000007FFC57DE80ull +#define DCORE2_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE2_SRAM0_BANK_BASE 0x1000007FFC580000ull +#define DCORE2_SRAM0_BANK_MAX_OFFSET 0x1000 +#define DCORE2_SRAM0_BANK_SECTION 0xE800 + +#define mmDCORE2_SRAM0_BANK_SPECIAL_BASE 0x1000007FFC580E80ull +#define DCORE2_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM0_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_SRAM0_RTR_BASE 0x1000007FFC581000ull +#define DCORE2_SRAM0_RTR_MAX_OFFSET 0x1000 +#define DCORE2_SRAM0_RTR_SECTION 0xE800 + +#define mmDCORE2_SRAM0_RTR_SPECIAL_BASE 0x1000007FFC581E80ull +#define DCORE2_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM0_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC582000ull +#define DCORE2_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC582100ull +#define DCORE2_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC582200ull +#define DCORE2_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC582300ull +#define DCORE2_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC582400ull +#define DCORE2_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC582500ull +#define DCORE2_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC582600ull +#define DCORE2_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC582700ull +#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC582780ull +#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC582800ull +#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC582880ull +#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC582900ull +#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC582980ull +#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC582A00ull +#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC582A80ull +#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE2_SRAM0_DBG_CNT_SPECIAL_BASE 0x1000007FFC582E80ull +#define DCORE2_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE2_SRAM1_BANK_BASE 0x1000007FFC588000ull +#define DCORE2_SRAM1_BANK_MAX_OFFSET 0x1000 +#define DCORE2_SRAM1_BANK_SECTION 0xE800 + +#define mmDCORE2_SRAM1_BANK_SPECIAL_BASE 0x1000007FFC588E80ull +#define DCORE2_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM1_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_SRAM1_RTR_BASE 0x1000007FFC589000ull +#define DCORE2_SRAM1_RTR_MAX_OFFSET 0x1000 +#define DCORE2_SRAM1_RTR_SECTION 0xE800 + +#define mmDCORE2_SRAM1_RTR_SPECIAL_BASE 0x1000007FFC589E80ull +#define DCORE2_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM1_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC58A000ull +#define DCORE2_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC58A100ull +#define DCORE2_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC58A200ull +#define DCORE2_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC58A300ull +#define DCORE2_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC58A400ull +#define DCORE2_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC58A500ull +#define DCORE2_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC58A600ull +#define DCORE2_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC58A700ull +#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC58A780ull +#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC58A800ull +#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC58A880ull +#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC58A900ull +#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC58A980ull +#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC58AA00ull +#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC58AA80ull +#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE2_SRAM1_DBG_CNT_SPECIAL_BASE 0x1000007FFC58AE80ull +#define DCORE2_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE2_SRAM2_BANK_BASE 0x1000007FFC590000ull +#define DCORE2_SRAM2_BANK_MAX_OFFSET 0x1000 +#define DCORE2_SRAM2_BANK_SECTION 0xE800 + +#define mmDCORE2_SRAM2_BANK_SPECIAL_BASE 0x1000007FFC590E80ull +#define DCORE2_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM2_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_SRAM2_RTR_BASE 0x1000007FFC591000ull +#define DCORE2_SRAM2_RTR_MAX_OFFSET 0x1000 +#define DCORE2_SRAM2_RTR_SECTION 0xE800 + +#define mmDCORE2_SRAM2_RTR_SPECIAL_BASE 0x1000007FFC591E80ull +#define DCORE2_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM2_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC592000ull +#define DCORE2_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC592100ull +#define DCORE2_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC592200ull +#define DCORE2_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC592300ull +#define DCORE2_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC592400ull +#define DCORE2_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC592500ull +#define DCORE2_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC592600ull +#define DCORE2_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC592700ull +#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC592780ull +#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC592800ull +#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC592880ull +#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC592900ull +#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC592980ull +#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC592A00ull +#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC592A80ull +#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE2_SRAM2_DBG_CNT_SPECIAL_BASE 0x1000007FFC592E80ull +#define DCORE2_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE2_SRAM3_BANK_BASE 0x1000007FFC598000ull +#define DCORE2_SRAM3_BANK_MAX_OFFSET 0x1000 +#define DCORE2_SRAM3_BANK_SECTION 0xE800 + +#define mmDCORE2_SRAM3_BANK_SPECIAL_BASE 0x1000007FFC598E80ull +#define DCORE2_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM3_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_SRAM3_RTR_BASE 0x1000007FFC599000ull +#define DCORE2_SRAM3_RTR_MAX_OFFSET 0x1000 +#define DCORE2_SRAM3_RTR_SECTION 0xE800 + +#define mmDCORE2_SRAM3_RTR_SPECIAL_BASE 0x1000007FFC599E80ull +#define DCORE2_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM3_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC59A000ull +#define DCORE2_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC59A100ull +#define DCORE2_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC59A200ull +#define DCORE2_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC59A300ull +#define DCORE2_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC59A400ull +#define DCORE2_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC59A500ull +#define DCORE2_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC59A600ull +#define DCORE2_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC59A700ull +#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC59A780ull +#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC59A800ull +#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC59A880ull +#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC59A900ull +#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC59A980ull +#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC59AA00ull +#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC59AA80ull +#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE2_SRAM3_DBG_CNT_SPECIAL_BASE 0x1000007FFC59AE80ull +#define DCORE2_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE2_SRAM4_BANK_BASE 0x1000007FFC5A0000ull +#define DCORE2_SRAM4_BANK_MAX_OFFSET 0x1000 +#define DCORE2_SRAM4_BANK_SECTION 0xE800 + +#define mmDCORE2_SRAM4_BANK_SPECIAL_BASE 0x1000007FFC5A0E80ull +#define DCORE2_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM4_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_SRAM4_RTR_BASE 0x1000007FFC5A1000ull +#define DCORE2_SRAM4_RTR_MAX_OFFSET 0x1000 +#define DCORE2_SRAM4_RTR_SECTION 0xE800 + +#define mmDCORE2_SRAM4_RTR_SPECIAL_BASE 0x1000007FFC5A1E80ull +#define DCORE2_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM4_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC5A2000ull +#define DCORE2_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC5A2100ull +#define DCORE2_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC5A2200ull +#define DCORE2_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC5A2300ull +#define DCORE2_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC5A2400ull +#define DCORE2_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC5A2500ull +#define DCORE2_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC5A2600ull +#define DCORE2_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC5A2700ull +#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC5A2780ull +#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC5A2800ull +#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC5A2880ull +#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC5A2900ull +#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC5A2980ull +#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC5A2A00ull +#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC5A2A80ull +#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE2_SRAM4_DBG_CNT_SPECIAL_BASE 0x1000007FFC5A2E80ull +#define DCORE2_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE2_SRAM5_BANK_BASE 0x1000007FFC5A8000ull +#define DCORE2_SRAM5_BANK_MAX_OFFSET 0x1000 +#define DCORE2_SRAM5_BANK_SECTION 0xE800 + +#define mmDCORE2_SRAM5_BANK_SPECIAL_BASE 0x1000007FFC5A8E80ull +#define DCORE2_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM5_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_SRAM5_RTR_BASE 0x1000007FFC5A9000ull +#define DCORE2_SRAM5_RTR_MAX_OFFSET 0x1000 +#define DCORE2_SRAM5_RTR_SECTION 0xE800 + +#define mmDCORE2_SRAM5_RTR_SPECIAL_BASE 0x1000007FFC5A9E80ull +#define DCORE2_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM5_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC5AA000ull +#define DCORE2_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC5AA100ull +#define DCORE2_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC5AA200ull +#define DCORE2_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC5AA300ull +#define DCORE2_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC5AA400ull +#define DCORE2_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC5AA500ull +#define DCORE2_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC5AA600ull +#define DCORE2_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC5AA700ull +#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC5AA780ull +#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC5AA800ull +#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC5AA880ull +#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC5AA900ull +#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC5AA980ull +#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC5AAA00ull +#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC5AAA80ull +#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE2_SRAM5_DBG_CNT_SPECIAL_BASE 0x1000007FFC5AAE80ull +#define DCORE2_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE2_SRAM6_BANK_BASE 0x1000007FFC5B0000ull +#define DCORE2_SRAM6_BANK_MAX_OFFSET 0x1000 +#define DCORE2_SRAM6_BANK_SECTION 0xE800 + +#define mmDCORE2_SRAM6_BANK_SPECIAL_BASE 0x1000007FFC5B0E80ull +#define DCORE2_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM6_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_SRAM6_RTR_BASE 0x1000007FFC5B1000ull +#define DCORE2_SRAM6_RTR_MAX_OFFSET 0x1000 +#define DCORE2_SRAM6_RTR_SECTION 0xE800 + +#define mmDCORE2_SRAM6_RTR_SPECIAL_BASE 0x1000007FFC5B1E80ull +#define DCORE2_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM6_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC5B2000ull +#define DCORE2_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC5B2100ull +#define DCORE2_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC5B2200ull +#define DCORE2_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC5B2300ull +#define DCORE2_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC5B2400ull +#define DCORE2_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC5B2500ull +#define DCORE2_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC5B2600ull +#define DCORE2_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC5B2700ull +#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC5B2780ull +#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC5B2800ull +#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC5B2880ull +#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC5B2900ull +#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC5B2980ull +#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC5B2A00ull +#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC5B2A80ull +#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE2_SRAM6_DBG_CNT_SPECIAL_BASE 0x1000007FFC5B2E80ull +#define DCORE2_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE2_SRAM7_BANK_BASE 0x1000007FFC5B8000ull +#define DCORE2_SRAM7_BANK_MAX_OFFSET 0x1000 +#define DCORE2_SRAM7_BANK_SECTION 0xE800 + +#define mmDCORE2_SRAM7_BANK_SPECIAL_BASE 0x1000007FFC5B8E80ull +#define DCORE2_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM7_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_SRAM7_RTR_BASE 0x1000007FFC5B9000ull +#define DCORE2_SRAM7_RTR_MAX_OFFSET 0x1000 +#define DCORE2_SRAM7_RTR_SECTION 0xE800 + +#define mmDCORE2_SRAM7_RTR_SPECIAL_BASE 0x1000007FFC5B9E80ull +#define DCORE2_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM7_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC5BA000ull +#define DCORE2_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC5BA100ull +#define DCORE2_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC5BA200ull +#define DCORE2_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC5BA300ull +#define DCORE2_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC5BA400ull +#define DCORE2_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC5BA500ull +#define DCORE2_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC5BA600ull +#define DCORE2_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE2_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE2_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC5BA700ull +#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC5BA780ull +#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC5BA800ull +#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC5BA880ull +#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC5BA900ull +#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC5BA980ull +#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC5BAA00ull +#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE2_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC5BAA80ull +#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE2_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE2_SRAM7_DBG_CNT_SPECIAL_BASE 0x1000007FFC5BAE80ull +#define DCORE2_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE2_EDMA0_QM_DCCM_BASE 0x1000007FFC5C0000ull +#define DCORE2_EDMA0_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_EDMA0_QM_DCCM_SECTION 0x8000 + +#define mmDCORE2_EDMA0_QM_ARC_AUX_BASE 0x1000007FFC5C8000ull +#define DCORE2_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE2_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC5C8E80ull +#define DCORE2_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE2_EDMA0_QM_BASE 0x1000007FFC5CA000ull +#define DCORE2_EDMA0_QM_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_QM_SECTION 0x9000 + +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC5CA900ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC5CA908ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC5CA910ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC5CA918ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC5CA920ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC5CA928ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC5CA930ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC5CA938ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC5CA940ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC5CA948ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC5CA950ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC5CA958ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC5CA960ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC5CA968ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC5CA970ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC5CA978ull +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE2_EDMA0_QM_AXUSER_SECURED_BASE 0x1000007FFC5CAB00ull +#define DCORE2_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE2_EDMA0_QM_AXUSER_NONSECURED_BASE 0x1000007FFC5CAB80ull +#define DCORE2_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE2_EDMA0_QM_DBG_HBW_BASE 0x1000007FFC5CAC00ull +#define DCORE2_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_EDMA0_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_EDMA0_QM_DBG_LBW_BASE 0x1000007FFC5CAC80ull +#define DCORE2_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_EDMA0_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE2_EDMA0_QM_CGM_BASE 0x1000007FFC5CAD80ull +#define DCORE2_EDMA0_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_EDMA0_QM_CGM_SECTION 0x1000 + +#define mmDCORE2_EDMA0_QM_SPECIAL_BASE 0x1000007FFC5CAE80ull +#define DCORE2_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_EDMA0_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_EDMA0_CORE_BASE 0x1000007FFC5CB000ull +#define DCORE2_EDMA0_CORE_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_CORE_SECTION 0x8000 + +#define mmDCORE2_EDMA0_CORE_CTX_AXUSER_BASE 0x1000007FFC5CB800ull +#define DCORE2_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000 + +#define mmDCORE2_EDMA0_CORE_CTX_BASE 0x1000007FFC5CB860ull +#define DCORE2_EDMA0_CORE_CTX_MAX_OFFSET 0x9000 +#define DCORE2_EDMA0_CORE_CTX_SECTION 0x5A00 + +#define mmDCORE2_EDMA0_CORE_KDMA_CGM_BASE 0x1000007FFC5CBE00ull +#define DCORE2_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define DCORE2_EDMA0_CORE_KDMA_CGM_SECTION 0x8000 + +#define mmDCORE2_EDMA0_CORE_SPECIAL_BASE 0x1000007FFC5CBE80ull +#define DCORE2_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_EDMA0_CORE_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC5CC000ull +#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE2_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC5CC200ull +#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE2_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC5CC400ull +#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE2_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC5CC600ull +#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE2_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC5CC800ull +#define DCORE2_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE2_EDMA0_MSTR_IF_AXUSER_BASE 0x1000007FFC5CCA80ull +#define DCORE2_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE2_EDMA0_MSTR_IF_DBG_HBW_BASE 0x1000007FFC5CCB00ull +#define DCORE2_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_EDMA0_MSTR_IF_DBG_LBW_BASE 0x1000007FFC5CCB80ull +#define DCORE2_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE2_EDMA0_MSTR_IF_CORE_HBW_BASE 0x1000007FFC5CCC00ull +#define DCORE2_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE2_EDMA0_MSTR_IF_CORE_LBW_BASE 0x1000007FFC5CCD80ull +#define DCORE2_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE2_EDMA0_MSTR_IF_SPECIAL_BASE 0x1000007FFC5CCE80ull +#define DCORE2_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE2_EDMA1_QM_DCCM_BASE 0x1000007FFC5D0000ull +#define DCORE2_EDMA1_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE2_EDMA1_QM_DCCM_SECTION 0x8000 + +#define mmDCORE2_EDMA1_QM_ARC_AUX_BASE 0x1000007FFC5D8000ull +#define DCORE2_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE2_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC5D8E80ull +#define DCORE2_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE2_EDMA1_QM_BASE 0x1000007FFC5DA000ull +#define DCORE2_EDMA1_QM_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_QM_SECTION 0x9000 + +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC5DA900ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC5DA908ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC5DA910ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC5DA918ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC5DA920ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC5DA928ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC5DA930ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC5DA938ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC5DA940ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC5DA948ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC5DA950ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC5DA958ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC5DA960ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC5DA968ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC5DA970ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC5DA978ull +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE2_EDMA1_QM_AXUSER_SECURED_BASE 0x1000007FFC5DAB00ull +#define DCORE2_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE2_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE2_EDMA1_QM_AXUSER_NONSECURED_BASE 0x1000007FFC5DAB80ull +#define DCORE2_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE2_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE2_EDMA1_QM_DBG_HBW_BASE 0x1000007FFC5DAC00ull +#define DCORE2_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_EDMA1_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_EDMA1_QM_DBG_LBW_BASE 0x1000007FFC5DAC80ull +#define DCORE2_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_EDMA1_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE2_EDMA1_QM_CGM_BASE 0x1000007FFC5DAD80ull +#define DCORE2_EDMA1_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE2_EDMA1_QM_CGM_SECTION 0x1000 + +#define mmDCORE2_EDMA1_QM_SPECIAL_BASE 0x1000007FFC5DAE80ull +#define DCORE2_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_EDMA1_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_EDMA1_CORE_BASE 0x1000007FFC5DB000ull +#define DCORE2_EDMA1_CORE_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_CORE_SECTION 0x8000 + +#define mmDCORE2_EDMA1_CORE_CTX_AXUSER_BASE 0x1000007FFC5DB800ull +#define DCORE2_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000 + +#define mmDCORE2_EDMA1_CORE_CTX_BASE 0x1000007FFC5DB860ull +#define DCORE2_EDMA1_CORE_CTX_MAX_OFFSET 0x9000 +#define DCORE2_EDMA1_CORE_CTX_SECTION 0x5A00 + +#define mmDCORE2_EDMA1_CORE_KDMA_CGM_BASE 0x1000007FFC5DBE00ull +#define DCORE2_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define DCORE2_EDMA1_CORE_KDMA_CGM_SECTION 0x8000 + +#define mmDCORE2_EDMA1_CORE_SPECIAL_BASE 0x1000007FFC5DBE80ull +#define DCORE2_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_EDMA1_CORE_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC5DC000ull +#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE2_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC5DC200ull +#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE2_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC5DC400ull +#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE2_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC5DC600ull +#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE2_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC5DC800ull +#define DCORE2_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE2_EDMA1_MSTR_IF_AXUSER_BASE 0x1000007FFC5DCA80ull +#define DCORE2_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE2_EDMA1_MSTR_IF_DBG_HBW_BASE 0x1000007FFC5DCB00ull +#define DCORE2_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_EDMA1_MSTR_IF_DBG_LBW_BASE 0x1000007FFC5DCB80ull +#define DCORE2_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE2_EDMA1_MSTR_IF_CORE_HBW_BASE 0x1000007FFC5DCC00ull +#define DCORE2_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE2_EDMA1_MSTR_IF_CORE_LBW_BASE 0x1000007FFC5DCD80ull +#define DCORE2_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE2_EDMA1_MSTR_IF_SPECIAL_BASE 0x1000007FFC5DCE80ull +#define DCORE2_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE2_DEC0_CMD_BASE 0x1000007FFC5E0000ull +#define DCORE2_DEC0_CMD_MAX_OFFSET 0x1100 +#define DCORE2_DEC0_CMD_SECTION 0x1000 + +#define mmDCORE2_DEC0_VSI_BASE 0x1000007FFC5E1000ull +#define DCORE2_DEC0_VSI_MAX_OFFSET 0x6FC0 +#define DCORE2_DEC0_VSI_SECTION 0x1000 + +#define mmDCORE2_DEC0_L2C_BASE 0x1000007FFC5E2000ull +#define DCORE2_DEC0_L2C_MAX_OFFSET 0x39C0 +#define DCORE2_DEC0_L2C_SECTION 0x1000 + +#define mmDCORE2_VDEC0_BRDG_CTRL_BASE 0x1000007FFC5E3000ull +#define DCORE2_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_BRDG_CTRL_SECTION 0x8000 + +#define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x1000007FFC5E3800ull +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 + +#define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x1000007FFC5E3900ull +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 + +#define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x1000007FFC5E3A00ull +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 + +#define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x1000007FFC5E3B00ull +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 + +#define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x1000007FFC5E3C00ull +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define DCORE2_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 + +#define mmDCORE2_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x1000007FFC5E3E80ull +#define DCORE2_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_VDEC0_CTRL_BASE 0x1000007FFC5E4000ull +#define DCORE2_VDEC0_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_CTRL_SECTION 0xE800 + +#define mmDCORE2_VDEC0_CTRL_SPECIAL_BASE 0x1000007FFC5E4E80ull +#define DCORE2_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_VDEC0_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC5E5000ull +#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE2_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC5E5200ull +#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE2_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC5E5400ull +#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE2_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC5E5600ull +#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE2_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC5E5800ull +#define DCORE2_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE2_VDEC0_MSTR_IF_AXUSER_BASE 0x1000007FFC5E5A80ull +#define DCORE2_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE2_VDEC0_MSTR_IF_DBG_HBW_BASE 0x1000007FFC5E5B00ull +#define DCORE2_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_VDEC0_MSTR_IF_DBG_LBW_BASE 0x1000007FFC5E5B80ull +#define DCORE2_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE2_VDEC0_MSTR_IF_CORE_HBW_BASE 0x1000007FFC5E5C00ull +#define DCORE2_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE2_VDEC0_MSTR_IF_CORE_LBW_BASE 0x1000007FFC5E5D80ull +#define DCORE2_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE2_VDEC0_MSTR_IF_SPECIAL_BASE 0x1000007FFC5E5E80ull +#define DCORE2_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180 + +#define mmDCORE2_DEC1_CMD_BASE 0x1000007FFC5F0000ull +#define DCORE2_DEC1_CMD_MAX_OFFSET 0x1100 +#define DCORE2_DEC1_CMD_SECTION 0x1000 + +#define mmDCORE2_DEC1_VSI_BASE 0x1000007FFC5F1000ull +#define DCORE2_DEC1_VSI_MAX_OFFSET 0x6FC0 +#define DCORE2_DEC1_VSI_SECTION 0x1000 + +#define mmDCORE2_DEC1_L2C_BASE 0x1000007FFC5F2000ull +#define DCORE2_DEC1_L2C_MAX_OFFSET 0x39C0 +#define DCORE2_DEC1_L2C_SECTION 0x1000 + +#define mmDCORE2_VDEC1_BRDG_CTRL_BASE 0x1000007FFC5F3000ull +#define DCORE2_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_BRDG_CTRL_SECTION 0x8000 + +#define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x1000007FFC5F3800ull +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 + +#define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x1000007FFC5F3900ull +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 + +#define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x1000007FFC5F3A00ull +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 + +#define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x1000007FFC5F3B00ull +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 + +#define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x1000007FFC5F3C00ull +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define DCORE2_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 + +#define mmDCORE2_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x1000007FFC5F3E80ull +#define DCORE2_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_VDEC1_CTRL_BASE 0x1000007FFC5F4000ull +#define DCORE2_VDEC1_CTRL_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_CTRL_SECTION 0xE800 + +#define mmDCORE2_VDEC1_CTRL_SPECIAL_BASE 0x1000007FFC5F4E80ull +#define DCORE2_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_VDEC1_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC5F5000ull +#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE2_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC5F5200ull +#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE2_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC5F5400ull +#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE2_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC5F5600ull +#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE2_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE2_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC5F5800ull +#define DCORE2_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE2_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE2_VDEC1_MSTR_IF_AXUSER_BASE 0x1000007FFC5F5A80ull +#define DCORE2_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE2_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE2_VDEC1_MSTR_IF_DBG_HBW_BASE 0x1000007FFC5F5B00ull +#define DCORE2_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE2_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE2_VDEC1_MSTR_IF_DBG_LBW_BASE 0x1000007FFC5F5B80ull +#define DCORE2_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE2_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE2_VDEC1_MSTR_IF_CORE_HBW_BASE 0x1000007FFC5F5C00ull +#define DCORE2_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE2_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE2_VDEC1_MSTR_IF_CORE_LBW_BASE 0x1000007FFC5F5D80ull +#define DCORE2_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE2_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE2_VDEC1_MSTR_IF_SPECIAL_BASE 0x1000007FFC5F5E80ull +#define DCORE2_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180 + +#define mmDCORE3_TPC0_QM_DCCM_BASE 0x1000007FFC600000ull +#define DCORE3_TPC0_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC0_QM_DCCM_SECTION 0x8000 + +#define mmDCORE3_TPC0_QM_ARC_AUX_BASE 0x1000007FFC608000ull +#define DCORE3_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE3_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC608E80ull +#define DCORE3_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE3_TPC0_QM_BASE 0x1000007FFC60A000ull +#define DCORE3_TPC0_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_QM_SECTION 0x9000 + +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC60A900ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC60A908ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC60A910ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC60A918ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC60A920ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC60A928ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC60A930ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC60A938ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC60A940ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC60A948ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC60A950ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC60A958ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC60A960ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC60A968ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC60A970ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC60A978ull +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE3_TPC0_QM_AXUSER_SECURED_BASE 0x1000007FFC60AB00ull +#define DCORE3_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE3_TPC0_QM_AXUSER_NONSECURED_BASE 0x1000007FFC60AB80ull +#define DCORE3_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE3_TPC0_QM_DBG_HBW_BASE 0x1000007FFC60AC00ull +#define DCORE3_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC0_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_TPC0_QM_DBG_LBW_BASE 0x1000007FFC60AC80ull +#define DCORE3_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC0_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE3_TPC0_QM_CGM_BASE 0x1000007FFC60AD80ull +#define DCORE3_TPC0_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC0_QM_CGM_SECTION 0x1000 + +#define mmDCORE3_TPC0_QM_SPECIAL_BASE 0x1000007FFC60AE80ull +#define DCORE3_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC0_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFC60B000ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC0_CFG_BASE 0x1000007FFC60B000ull +#define DCORE3_TPC0_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC0_CFG_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFC60B050ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFC60B0A0ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFC60B0F0ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFC60B140ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFC60B190ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFC60B1E0ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFC60B230ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFC60B280ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFC60B2D0ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFC60B320ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFC60B370ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFC60B3C0ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFC60B410ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFC60B460ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFC60B4B0ull +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFC60B500ull +#define DCORE3_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE3_TPC0_CFG_KERNEL_BASE 0x1000007FFC60B508ull +#define DCORE3_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC0_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE3_TPC0_CFG_QM_TENSOR_0_BASE 0x1000007FFC60B5DCull +#define DCORE3_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_QM_TENSOR_1_BASE 0x1000007FFC60B62Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_QM_TENSOR_2_BASE 0x1000007FFC60B67Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_QM_TENSOR_3_BASE 0x1000007FFC60B6CCull +#define DCORE3_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_QM_TENSOR_4_BASE 0x1000007FFC60B71Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_QM_TENSOR_5_BASE 0x1000007FFC60B76Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_QM_TENSOR_6_BASE 0x1000007FFC60B7BCull +#define DCORE3_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_QM_TENSOR_7_BASE 0x1000007FFC60B80Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_QM_TENSOR_8_BASE 0x1000007FFC60B85Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_QM_TENSOR_9_BASE 0x1000007FFC60B8ACull +#define DCORE3_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_QM_TENSOR_10_BASE 0x1000007FFC60B8FCull +#define DCORE3_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_QM_TENSOR_11_BASE 0x1000007FFC60B94Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_QM_TENSOR_12_BASE 0x1000007FFC60B99Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_QM_TENSOR_13_BASE 0x1000007FFC60B9ECull +#define DCORE3_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_QM_TENSOR_14_BASE 0x1000007FFC60BA3Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_QM_TENSOR_15_BASE 0x1000007FFC60BA8Cull +#define DCORE3_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE3_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFC60BADCull +#define DCORE3_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE3_TPC0_CFG_QM_BASE 0x1000007FFC60BAE4ull +#define DCORE3_TPC0_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC0_CFG_QM_SECTION 0x31C0 + +#define mmDCORE3_TPC0_CFG_AXUSER_BASE 0x1000007FFC60BE00ull +#define DCORE3_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE3_TPC0_CFG_SPECIAL_BASE 0x1000007FFC60BE80ull +#define DCORE3_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC0_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC60C000ull +#define DCORE3_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE3_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC60C200ull +#define DCORE3_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE3_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC60C400ull +#define DCORE3_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE3_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC60C600ull +#define DCORE3_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE3_TPC0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC60C800ull +#define DCORE3_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE3_TPC0_MSTR_IF_AXUSER_BASE 0x1000007FFC60CA80ull +#define DCORE3_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE3_TPC0_MSTR_IF_DBG_HBW_BASE 0x1000007FFC60CB00ull +#define DCORE3_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_TPC0_MSTR_IF_DBG_LBW_BASE 0x1000007FFC60CB80ull +#define DCORE3_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE3_TPC0_MSTR_IF_CORE_HBW_BASE 0x1000007FFC60CC00ull +#define DCORE3_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE3_TPC0_MSTR_IF_CORE_LBW_BASE 0x1000007FFC60CD80ull +#define DCORE3_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE3_TPC0_MSTR_IF_SPECIAL_BASE 0x1000007FFC60CE80ull +#define DCORE3_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE3_TPC1_QM_DCCM_BASE 0x1000007FFC610000ull +#define DCORE3_TPC1_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC1_QM_DCCM_SECTION 0x8000 + +#define mmDCORE3_TPC1_QM_ARC_AUX_BASE 0x1000007FFC618000ull +#define DCORE3_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE3_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC618E80ull +#define DCORE3_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE3_TPC1_QM_BASE 0x1000007FFC61A000ull +#define DCORE3_TPC1_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_QM_SECTION 0x9000 + +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC61A900ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC61A908ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC61A910ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC61A918ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC61A920ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC61A928ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC61A930ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC61A938ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC61A940ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC61A948ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC61A950ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC61A958ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC61A960ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC61A968ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC61A970ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC61A978ull +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE3_TPC1_QM_AXUSER_SECURED_BASE 0x1000007FFC61AB00ull +#define DCORE3_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE3_TPC1_QM_AXUSER_NONSECURED_BASE 0x1000007FFC61AB80ull +#define DCORE3_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE3_TPC1_QM_DBG_HBW_BASE 0x1000007FFC61AC00ull +#define DCORE3_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC1_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_TPC1_QM_DBG_LBW_BASE 0x1000007FFC61AC80ull +#define DCORE3_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC1_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE3_TPC1_QM_CGM_BASE 0x1000007FFC61AD80ull +#define DCORE3_TPC1_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC1_QM_CGM_SECTION 0x1000 + +#define mmDCORE3_TPC1_QM_SPECIAL_BASE 0x1000007FFC61AE80ull +#define DCORE3_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC1_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFC61B000ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC1_CFG_BASE 0x1000007FFC61B000ull +#define DCORE3_TPC1_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC1_CFG_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFC61B050ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFC61B0A0ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFC61B0F0ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFC61B140ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFC61B190ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFC61B1E0ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFC61B230ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFC61B280ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFC61B2D0ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFC61B320ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFC61B370ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFC61B3C0ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFC61B410ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFC61B460ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFC61B4B0ull +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFC61B500ull +#define DCORE3_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE3_TPC1_CFG_KERNEL_BASE 0x1000007FFC61B508ull +#define DCORE3_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC1_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE3_TPC1_CFG_QM_TENSOR_0_BASE 0x1000007FFC61B5DCull +#define DCORE3_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_QM_TENSOR_1_BASE 0x1000007FFC61B62Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_QM_TENSOR_2_BASE 0x1000007FFC61B67Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_QM_TENSOR_3_BASE 0x1000007FFC61B6CCull +#define DCORE3_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_QM_TENSOR_4_BASE 0x1000007FFC61B71Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_QM_TENSOR_5_BASE 0x1000007FFC61B76Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_QM_TENSOR_6_BASE 0x1000007FFC61B7BCull +#define DCORE3_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_QM_TENSOR_7_BASE 0x1000007FFC61B80Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_QM_TENSOR_8_BASE 0x1000007FFC61B85Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_QM_TENSOR_9_BASE 0x1000007FFC61B8ACull +#define DCORE3_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_QM_TENSOR_10_BASE 0x1000007FFC61B8FCull +#define DCORE3_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_QM_TENSOR_11_BASE 0x1000007FFC61B94Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_QM_TENSOR_12_BASE 0x1000007FFC61B99Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_QM_TENSOR_13_BASE 0x1000007FFC61B9ECull +#define DCORE3_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_QM_TENSOR_14_BASE 0x1000007FFC61BA3Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_QM_TENSOR_15_BASE 0x1000007FFC61BA8Cull +#define DCORE3_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE3_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFC61BADCull +#define DCORE3_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE3_TPC1_CFG_QM_BASE 0x1000007FFC61BAE4ull +#define DCORE3_TPC1_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC1_CFG_QM_SECTION 0x31C0 + +#define mmDCORE3_TPC1_CFG_AXUSER_BASE 0x1000007FFC61BE00ull +#define DCORE3_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE3_TPC1_CFG_SPECIAL_BASE 0x1000007FFC61BE80ull +#define DCORE3_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC1_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC61C000ull +#define DCORE3_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE3_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC61C200ull +#define DCORE3_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE3_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC61C400ull +#define DCORE3_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE3_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC61C600ull +#define DCORE3_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE3_TPC1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC61C800ull +#define DCORE3_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE3_TPC1_MSTR_IF_AXUSER_BASE 0x1000007FFC61CA80ull +#define DCORE3_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE3_TPC1_MSTR_IF_DBG_HBW_BASE 0x1000007FFC61CB00ull +#define DCORE3_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_TPC1_MSTR_IF_DBG_LBW_BASE 0x1000007FFC61CB80ull +#define DCORE3_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE3_TPC1_MSTR_IF_CORE_HBW_BASE 0x1000007FFC61CC00ull +#define DCORE3_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE3_TPC1_MSTR_IF_CORE_LBW_BASE 0x1000007FFC61CD80ull +#define DCORE3_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE3_TPC1_MSTR_IF_SPECIAL_BASE 0x1000007FFC61CE80ull +#define DCORE3_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE3_TPC2_QM_DCCM_BASE 0x1000007FFC620000ull +#define DCORE3_TPC2_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC2_QM_DCCM_SECTION 0x8000 + +#define mmDCORE3_TPC2_QM_ARC_AUX_BASE 0x1000007FFC628000ull +#define DCORE3_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE3_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC628E80ull +#define DCORE3_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE3_TPC2_QM_BASE 0x1000007FFC62A000ull +#define DCORE3_TPC2_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_QM_SECTION 0x9000 + +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC62A900ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC62A908ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC62A910ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC62A918ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC62A920ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC62A928ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC62A930ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC62A938ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC62A940ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC62A948ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC62A950ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC62A958ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC62A960ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC62A968ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC62A970ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC62A978ull +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE3_TPC2_QM_AXUSER_SECURED_BASE 0x1000007FFC62AB00ull +#define DCORE3_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE3_TPC2_QM_AXUSER_NONSECURED_BASE 0x1000007FFC62AB80ull +#define DCORE3_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE3_TPC2_QM_DBG_HBW_BASE 0x1000007FFC62AC00ull +#define DCORE3_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC2_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_TPC2_QM_DBG_LBW_BASE 0x1000007FFC62AC80ull +#define DCORE3_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC2_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE3_TPC2_QM_CGM_BASE 0x1000007FFC62AD80ull +#define DCORE3_TPC2_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC2_QM_CGM_SECTION 0x1000 + +#define mmDCORE3_TPC2_QM_SPECIAL_BASE 0x1000007FFC62AE80ull +#define DCORE3_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC2_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFC62B000ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC2_CFG_BASE 0x1000007FFC62B000ull +#define DCORE3_TPC2_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC2_CFG_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFC62B050ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFC62B0A0ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFC62B0F0ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFC62B140ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFC62B190ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFC62B1E0ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFC62B230ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFC62B280ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFC62B2D0ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFC62B320ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFC62B370ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFC62B3C0ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFC62B410ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFC62B460ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFC62B4B0ull +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFC62B500ull +#define DCORE3_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE3_TPC2_CFG_KERNEL_BASE 0x1000007FFC62B508ull +#define DCORE3_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC2_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE3_TPC2_CFG_QM_TENSOR_0_BASE 0x1000007FFC62B5DCull +#define DCORE3_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_QM_TENSOR_1_BASE 0x1000007FFC62B62Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_QM_TENSOR_2_BASE 0x1000007FFC62B67Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_QM_TENSOR_3_BASE 0x1000007FFC62B6CCull +#define DCORE3_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_QM_TENSOR_4_BASE 0x1000007FFC62B71Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_QM_TENSOR_5_BASE 0x1000007FFC62B76Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_QM_TENSOR_6_BASE 0x1000007FFC62B7BCull +#define DCORE3_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_QM_TENSOR_7_BASE 0x1000007FFC62B80Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_QM_TENSOR_8_BASE 0x1000007FFC62B85Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_QM_TENSOR_9_BASE 0x1000007FFC62B8ACull +#define DCORE3_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_QM_TENSOR_10_BASE 0x1000007FFC62B8FCull +#define DCORE3_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_QM_TENSOR_11_BASE 0x1000007FFC62B94Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_QM_TENSOR_12_BASE 0x1000007FFC62B99Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_QM_TENSOR_13_BASE 0x1000007FFC62B9ECull +#define DCORE3_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_QM_TENSOR_14_BASE 0x1000007FFC62BA3Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_QM_TENSOR_15_BASE 0x1000007FFC62BA8Cull +#define DCORE3_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE3_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFC62BADCull +#define DCORE3_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE3_TPC2_CFG_QM_BASE 0x1000007FFC62BAE4ull +#define DCORE3_TPC2_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC2_CFG_QM_SECTION 0x31C0 + +#define mmDCORE3_TPC2_CFG_AXUSER_BASE 0x1000007FFC62BE00ull +#define DCORE3_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE3_TPC2_CFG_SPECIAL_BASE 0x1000007FFC62BE80ull +#define DCORE3_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC2_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC62C000ull +#define DCORE3_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE3_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC62C200ull +#define DCORE3_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE3_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC62C400ull +#define DCORE3_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE3_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC62C600ull +#define DCORE3_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE3_TPC2_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC62C800ull +#define DCORE3_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE3_TPC2_MSTR_IF_AXUSER_BASE 0x1000007FFC62CA80ull +#define DCORE3_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC2_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE3_TPC2_MSTR_IF_DBG_HBW_BASE 0x1000007FFC62CB00ull +#define DCORE3_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_TPC2_MSTR_IF_DBG_LBW_BASE 0x1000007FFC62CB80ull +#define DCORE3_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE3_TPC2_MSTR_IF_CORE_HBW_BASE 0x1000007FFC62CC00ull +#define DCORE3_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE3_TPC2_MSTR_IF_CORE_LBW_BASE 0x1000007FFC62CD80ull +#define DCORE3_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE3_TPC2_MSTR_IF_SPECIAL_BASE 0x1000007FFC62CE80ull +#define DCORE3_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE3_TPC3_QM_DCCM_BASE 0x1000007FFC630000ull +#define DCORE3_TPC3_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC3_QM_DCCM_SECTION 0x8000 + +#define mmDCORE3_TPC3_QM_ARC_AUX_BASE 0x1000007FFC638000ull +#define DCORE3_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE3_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC638E80ull +#define DCORE3_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE3_TPC3_QM_BASE 0x1000007FFC63A000ull +#define DCORE3_TPC3_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_QM_SECTION 0x9000 + +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC63A900ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC63A908ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC63A910ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC63A918ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC63A920ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC63A928ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC63A930ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC63A938ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC63A940ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC63A948ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC63A950ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC63A958ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC63A960ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC63A968ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC63A970ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC63A978ull +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE3_TPC3_QM_AXUSER_SECURED_BASE 0x1000007FFC63AB00ull +#define DCORE3_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE3_TPC3_QM_AXUSER_NONSECURED_BASE 0x1000007FFC63AB80ull +#define DCORE3_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE3_TPC3_QM_DBG_HBW_BASE 0x1000007FFC63AC00ull +#define DCORE3_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC3_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_TPC3_QM_DBG_LBW_BASE 0x1000007FFC63AC80ull +#define DCORE3_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC3_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE3_TPC3_QM_CGM_BASE 0x1000007FFC63AD80ull +#define DCORE3_TPC3_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC3_QM_CGM_SECTION 0x1000 + +#define mmDCORE3_TPC3_QM_SPECIAL_BASE 0x1000007FFC63AE80ull +#define DCORE3_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC3_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFC63B000ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC3_CFG_BASE 0x1000007FFC63B000ull +#define DCORE3_TPC3_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC3_CFG_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFC63B050ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFC63B0A0ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFC63B0F0ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFC63B140ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFC63B190ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFC63B1E0ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFC63B230ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFC63B280ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFC63B2D0ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFC63B320ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFC63B370ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFC63B3C0ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFC63B410ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFC63B460ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFC63B4B0ull +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFC63B500ull +#define DCORE3_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE3_TPC3_CFG_KERNEL_BASE 0x1000007FFC63B508ull +#define DCORE3_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC3_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE3_TPC3_CFG_QM_TENSOR_0_BASE 0x1000007FFC63B5DCull +#define DCORE3_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_QM_TENSOR_1_BASE 0x1000007FFC63B62Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_QM_TENSOR_2_BASE 0x1000007FFC63B67Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_QM_TENSOR_3_BASE 0x1000007FFC63B6CCull +#define DCORE3_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_QM_TENSOR_4_BASE 0x1000007FFC63B71Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_QM_TENSOR_5_BASE 0x1000007FFC63B76Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_QM_TENSOR_6_BASE 0x1000007FFC63B7BCull +#define DCORE3_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_QM_TENSOR_7_BASE 0x1000007FFC63B80Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_QM_TENSOR_8_BASE 0x1000007FFC63B85Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_QM_TENSOR_9_BASE 0x1000007FFC63B8ACull +#define DCORE3_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_QM_TENSOR_10_BASE 0x1000007FFC63B8FCull +#define DCORE3_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_QM_TENSOR_11_BASE 0x1000007FFC63B94Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_QM_TENSOR_12_BASE 0x1000007FFC63B99Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_QM_TENSOR_13_BASE 0x1000007FFC63B9ECull +#define DCORE3_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_QM_TENSOR_14_BASE 0x1000007FFC63BA3Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_QM_TENSOR_15_BASE 0x1000007FFC63BA8Cull +#define DCORE3_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE3_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFC63BADCull +#define DCORE3_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE3_TPC3_CFG_QM_BASE 0x1000007FFC63BAE4ull +#define DCORE3_TPC3_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC3_CFG_QM_SECTION 0x31C0 + +#define mmDCORE3_TPC3_CFG_AXUSER_BASE 0x1000007FFC63BE00ull +#define DCORE3_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE3_TPC3_CFG_SPECIAL_BASE 0x1000007FFC63BE80ull +#define DCORE3_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC3_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC63C000ull +#define DCORE3_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE3_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC63C200ull +#define DCORE3_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE3_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC63C400ull +#define DCORE3_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE3_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC63C600ull +#define DCORE3_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE3_TPC3_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC63C800ull +#define DCORE3_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE3_TPC3_MSTR_IF_AXUSER_BASE 0x1000007FFC63CA80ull +#define DCORE3_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC3_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE3_TPC3_MSTR_IF_DBG_HBW_BASE 0x1000007FFC63CB00ull +#define DCORE3_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_TPC3_MSTR_IF_DBG_LBW_BASE 0x1000007FFC63CB80ull +#define DCORE3_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE3_TPC3_MSTR_IF_CORE_HBW_BASE 0x1000007FFC63CC00ull +#define DCORE3_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE3_TPC3_MSTR_IF_CORE_LBW_BASE 0x1000007FFC63CD80ull +#define DCORE3_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE3_TPC3_MSTR_IF_SPECIAL_BASE 0x1000007FFC63CE80ull +#define DCORE3_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE3_TPC4_QM_DCCM_BASE 0x1000007FFC640000ull +#define DCORE3_TPC4_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC4_QM_DCCM_SECTION 0x8000 + +#define mmDCORE3_TPC4_QM_ARC_AUX_BASE 0x1000007FFC648000ull +#define DCORE3_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE3_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC648E80ull +#define DCORE3_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE3_TPC4_QM_BASE 0x1000007FFC64A000ull +#define DCORE3_TPC4_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_QM_SECTION 0x9000 + +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC64A900ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC64A908ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC64A910ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC64A918ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC64A920ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC64A928ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC64A930ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC64A938ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC64A940ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC64A948ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC64A950ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC64A958ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC64A960ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC64A968ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC64A970ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC64A978ull +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE3_TPC4_QM_AXUSER_SECURED_BASE 0x1000007FFC64AB00ull +#define DCORE3_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE3_TPC4_QM_AXUSER_NONSECURED_BASE 0x1000007FFC64AB80ull +#define DCORE3_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE3_TPC4_QM_DBG_HBW_BASE 0x1000007FFC64AC00ull +#define DCORE3_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC4_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_TPC4_QM_DBG_LBW_BASE 0x1000007FFC64AC80ull +#define DCORE3_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC4_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE3_TPC4_QM_CGM_BASE 0x1000007FFC64AD80ull +#define DCORE3_TPC4_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC4_QM_CGM_SECTION 0x1000 + +#define mmDCORE3_TPC4_QM_SPECIAL_BASE 0x1000007FFC64AE80ull +#define DCORE3_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC4_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFC64B000ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC4_CFG_BASE 0x1000007FFC64B000ull +#define DCORE3_TPC4_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC4_CFG_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFC64B050ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFC64B0A0ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFC64B0F0ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFC64B140ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFC64B190ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFC64B1E0ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFC64B230ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFC64B280ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFC64B2D0ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFC64B320ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFC64B370ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFC64B3C0ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFC64B410ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFC64B460ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFC64B4B0ull +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFC64B500ull +#define DCORE3_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE3_TPC4_CFG_KERNEL_BASE 0x1000007FFC64B508ull +#define DCORE3_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC4_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE3_TPC4_CFG_QM_TENSOR_0_BASE 0x1000007FFC64B5DCull +#define DCORE3_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_QM_TENSOR_1_BASE 0x1000007FFC64B62Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_QM_TENSOR_2_BASE 0x1000007FFC64B67Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_QM_TENSOR_3_BASE 0x1000007FFC64B6CCull +#define DCORE3_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_QM_TENSOR_4_BASE 0x1000007FFC64B71Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_QM_TENSOR_5_BASE 0x1000007FFC64B76Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_QM_TENSOR_6_BASE 0x1000007FFC64B7BCull +#define DCORE3_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_QM_TENSOR_7_BASE 0x1000007FFC64B80Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_QM_TENSOR_8_BASE 0x1000007FFC64B85Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_QM_TENSOR_9_BASE 0x1000007FFC64B8ACull +#define DCORE3_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_QM_TENSOR_10_BASE 0x1000007FFC64B8FCull +#define DCORE3_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_QM_TENSOR_11_BASE 0x1000007FFC64B94Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_QM_TENSOR_12_BASE 0x1000007FFC64B99Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_QM_TENSOR_13_BASE 0x1000007FFC64B9ECull +#define DCORE3_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_QM_TENSOR_14_BASE 0x1000007FFC64BA3Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_QM_TENSOR_15_BASE 0x1000007FFC64BA8Cull +#define DCORE3_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE3_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFC64BADCull +#define DCORE3_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE3_TPC4_CFG_QM_BASE 0x1000007FFC64BAE4ull +#define DCORE3_TPC4_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC4_CFG_QM_SECTION 0x31C0 + +#define mmDCORE3_TPC4_CFG_AXUSER_BASE 0x1000007FFC64BE00ull +#define DCORE3_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE3_TPC4_CFG_SPECIAL_BASE 0x1000007FFC64BE80ull +#define DCORE3_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC4_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC64C000ull +#define DCORE3_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE3_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC64C200ull +#define DCORE3_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE3_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC64C400ull +#define DCORE3_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE3_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC64C600ull +#define DCORE3_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE3_TPC4_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC64C800ull +#define DCORE3_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE3_TPC4_MSTR_IF_AXUSER_BASE 0x1000007FFC64CA80ull +#define DCORE3_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC4_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE3_TPC4_MSTR_IF_DBG_HBW_BASE 0x1000007FFC64CB00ull +#define DCORE3_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_TPC4_MSTR_IF_DBG_LBW_BASE 0x1000007FFC64CB80ull +#define DCORE3_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE3_TPC4_MSTR_IF_CORE_HBW_BASE 0x1000007FFC64CC00ull +#define DCORE3_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE3_TPC4_MSTR_IF_CORE_LBW_BASE 0x1000007FFC64CD80ull +#define DCORE3_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE3_TPC4_MSTR_IF_SPECIAL_BASE 0x1000007FFC64CE80ull +#define DCORE3_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE3_TPC5_QM_DCCM_BASE 0x1000007FFC650000ull +#define DCORE3_TPC5_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_TPC5_QM_DCCM_SECTION 0x8000 + +#define mmDCORE3_TPC5_QM_ARC_AUX_BASE 0x1000007FFC658000ull +#define DCORE3_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE3_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC658E80ull +#define DCORE3_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE3_TPC5_QM_BASE 0x1000007FFC65A000ull +#define DCORE3_TPC5_QM_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_QM_SECTION 0x9000 + +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC65A900ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC65A908ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC65A910ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC65A918ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC65A920ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC65A928ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC65A930ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC65A938ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC65A940ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC65A948ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC65A950ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC65A958ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC65A960ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC65A968ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC65A970ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC65A978ull +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE3_TPC5_QM_AXUSER_SECURED_BASE 0x1000007FFC65AB00ull +#define DCORE3_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE3_TPC5_QM_AXUSER_NONSECURED_BASE 0x1000007FFC65AB80ull +#define DCORE3_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE3_TPC5_QM_DBG_HBW_BASE 0x1000007FFC65AC00ull +#define DCORE3_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC5_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_TPC5_QM_DBG_LBW_BASE 0x1000007FFC65AC80ull +#define DCORE3_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC5_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE3_TPC5_QM_CGM_BASE 0x1000007FFC65AD80ull +#define DCORE3_TPC5_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_TPC5_QM_CGM_SECTION 0x1000 + +#define mmDCORE3_TPC5_QM_SPECIAL_BASE 0x1000007FFC65AE80ull +#define DCORE3_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC5_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x1000007FFC65B000ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC5_CFG_BASE 0x1000007FFC65B000ull +#define DCORE3_TPC5_CFG_MAX_OFFSET 0x1000 +#define DCORE3_TPC5_CFG_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x1000007FFC65B050ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x1000007FFC65B0A0ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x1000007FFC65B0F0ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x1000007FFC65B140ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x1000007FFC65B190ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x1000007FFC65B1E0ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x1000007FFC65B230ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x1000007FFC65B280ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x1000007FFC65B2D0ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x1000007FFC65B320ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x1000007FFC65B370ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x1000007FFC65B3C0ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x1000007FFC65B410ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x1000007FFC65B460ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x1000007FFC65B4B0ull +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x1000007FFC65B500ull +#define DCORE3_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE3_TPC5_CFG_KERNEL_BASE 0x1000007FFC65B508ull +#define DCORE3_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400 +#define DCORE3_TPC5_CFG_KERNEL_SECTION 0xD400 + +#define mmDCORE3_TPC5_CFG_QM_TENSOR_0_BASE 0x1000007FFC65B5DCull +#define DCORE3_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_QM_TENSOR_1_BASE 0x1000007FFC65B62Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_QM_TENSOR_2_BASE 0x1000007FFC65B67Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_QM_TENSOR_3_BASE 0x1000007FFC65B6CCull +#define DCORE3_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_QM_TENSOR_4_BASE 0x1000007FFC65B71Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_QM_TENSOR_5_BASE 0x1000007FFC65B76Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_QM_TENSOR_6_BASE 0x1000007FFC65B7BCull +#define DCORE3_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_QM_TENSOR_7_BASE 0x1000007FFC65B80Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_QM_TENSOR_8_BASE 0x1000007FFC65B85Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_QM_TENSOR_9_BASE 0x1000007FFC65B8ACull +#define DCORE3_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_QM_TENSOR_10_BASE 0x1000007FFC65B8FCull +#define DCORE3_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_QM_TENSOR_11_BASE 0x1000007FFC65B94Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_QM_TENSOR_12_BASE 0x1000007FFC65B99Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_QM_TENSOR_13_BASE 0x1000007FFC65B9ECull +#define DCORE3_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_QM_TENSOR_14_BASE 0x1000007FFC65BA3Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_QM_TENSOR_15_BASE 0x1000007FFC65BA8Cull +#define DCORE3_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000 + +#define mmDCORE3_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x1000007FFC65BADCull +#define DCORE3_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000 + +#define mmDCORE3_TPC5_CFG_QM_BASE 0x1000007FFC65BAE4ull +#define DCORE3_TPC5_CFG_QM_MAX_OFFSET 0xD400 +#define DCORE3_TPC5_CFG_QM_SECTION 0x31C0 + +#define mmDCORE3_TPC5_CFG_AXUSER_BASE 0x1000007FFC65BE00ull +#define DCORE3_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_CFG_AXUSER_SECTION 0x8000 + +#define mmDCORE3_TPC5_CFG_SPECIAL_BASE 0x1000007FFC65BE80ull +#define DCORE3_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC5_CFG_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC65C000ull +#define DCORE3_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE3_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC65C200ull +#define DCORE3_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE3_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC65C400ull +#define DCORE3_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE3_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC65C600ull +#define DCORE3_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE3_TPC5_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC65C800ull +#define DCORE3_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE3_TPC5_MSTR_IF_AXUSER_BASE 0x1000007FFC65CA80ull +#define DCORE3_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_TPC5_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE3_TPC5_MSTR_IF_DBG_HBW_BASE 0x1000007FFC65CB00ull +#define DCORE3_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_TPC5_MSTR_IF_DBG_LBW_BASE 0x1000007FFC65CB80ull +#define DCORE3_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE3_TPC5_MSTR_IF_CORE_HBW_BASE 0x1000007FFC65CC00ull +#define DCORE3_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE3_TPC5_MSTR_IF_CORE_LBW_BASE 0x1000007FFC65CD80ull +#define DCORE3_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE3_TPC5_MSTR_IF_SPECIAL_BASE 0x1000007FFC65CE80ull +#define DCORE3_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC5_MSTR_IF_SPECIAL_SECTION 0x23180 + +#define mmDCORE3_HMMU0_MMU_BASE 0x1000007FFC680000ull +#define DCORE3_HMMU0_MMU_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_MMU_SECTION 0xE800 + +#define mmDCORE3_HMMU0_MMU_SPECIAL_BASE 0x1000007FFC680E80ull +#define DCORE3_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU0_MMU_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_HMMU0_STLB_BASE 0x1000007FFC681000ull +#define DCORE3_HMMU0_STLB_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_STLB_SECTION 0xE800 + +#define mmDCORE3_HMMU0_STLB_SPECIAL_BASE 0x1000007FFC681E80ull +#define DCORE3_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU0_STLB_SPECIAL_SECTION 0x1180 + +#define mmDCORE3_HMMU0_SCRAMB_OUT_BASE 0x1000007FFC683000ull +#define DCORE3_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_SCRAMB_OUT_SECTION 0xE800 + +#define mmDCORE3_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x1000007FFC683E80ull +#define DCORE3_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC684000ull +#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE3_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC684200ull +#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE3_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC684400ull +#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE3_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC684600ull +#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE3_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC684800ull +#define DCORE3_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE3_HMMU0_MSTR_IF_AXUSER_BASE 0x1000007FFC684A80ull +#define DCORE3_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE3_HMMU0_MSTR_IF_DBG_HBW_BASE 0x1000007FFC684B00ull +#define DCORE3_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_HMMU0_MSTR_IF_DBG_LBW_BASE 0x1000007FFC684B80ull +#define DCORE3_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE3_HMMU0_MSTR_IF_CORE_HBW_BASE 0x1000007FFC684C00ull +#define DCORE3_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE3_HMMU0_MSTR_IF_CORE_LBW_BASE 0x1000007FFC684D80ull +#define DCORE3_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE3_HMMU0_MSTR_IF_SPECIAL_BASE 0x1000007FFC684E80ull +#define DCORE3_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180 + +#define mmDCORE3_HMMU1_MMU_BASE 0x1000007FFC690000ull +#define DCORE3_HMMU1_MMU_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_MMU_SECTION 0xE800 + +#define mmDCORE3_HMMU1_MMU_SPECIAL_BASE 0x1000007FFC690E80ull +#define DCORE3_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU1_MMU_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_HMMU1_STLB_BASE 0x1000007FFC691000ull +#define DCORE3_HMMU1_STLB_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_STLB_SECTION 0xE800 + +#define mmDCORE3_HMMU1_STLB_SPECIAL_BASE 0x1000007FFC691E80ull +#define DCORE3_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU1_STLB_SPECIAL_SECTION 0x1180 + +#define mmDCORE3_HMMU1_SCRAMB_OUT_BASE 0x1000007FFC693000ull +#define DCORE3_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_SCRAMB_OUT_SECTION 0xE800 + +#define mmDCORE3_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x1000007FFC693E80ull +#define DCORE3_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC694000ull +#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE3_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC694200ull +#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE3_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC694400ull +#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE3_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC694600ull +#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE3_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC694800ull +#define DCORE3_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE3_HMMU1_MSTR_IF_AXUSER_BASE 0x1000007FFC694A80ull +#define DCORE3_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE3_HMMU1_MSTR_IF_DBG_HBW_BASE 0x1000007FFC694B00ull +#define DCORE3_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_HMMU1_MSTR_IF_DBG_LBW_BASE 0x1000007FFC694B80ull +#define DCORE3_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE3_HMMU1_MSTR_IF_CORE_HBW_BASE 0x1000007FFC694C00ull +#define DCORE3_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE3_HMMU1_MSTR_IF_CORE_LBW_BASE 0x1000007FFC694D80ull +#define DCORE3_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE3_HMMU1_MSTR_IF_SPECIAL_BASE 0x1000007FFC694E80ull +#define DCORE3_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180 + +#define mmDCORE3_HMMU2_MMU_BASE 0x1000007FFC6A0000ull +#define DCORE3_HMMU2_MMU_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_MMU_SECTION 0xE800 + +#define mmDCORE3_HMMU2_MMU_SPECIAL_BASE 0x1000007FFC6A0E80ull +#define DCORE3_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU2_MMU_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_HMMU2_STLB_BASE 0x1000007FFC6A1000ull +#define DCORE3_HMMU2_STLB_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_STLB_SECTION 0xE800 + +#define mmDCORE3_HMMU2_STLB_SPECIAL_BASE 0x1000007FFC6A1E80ull +#define DCORE3_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU2_STLB_SPECIAL_SECTION 0x1180 + +#define mmDCORE3_HMMU2_SCRAMB_OUT_BASE 0x1000007FFC6A3000ull +#define DCORE3_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_SCRAMB_OUT_SECTION 0xE800 + +#define mmDCORE3_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x1000007FFC6A3E80ull +#define DCORE3_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC6A4000ull +#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE3_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC6A4200ull +#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE3_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC6A4400ull +#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE3_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC6A4600ull +#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE3_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC6A4800ull +#define DCORE3_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE3_HMMU2_MSTR_IF_AXUSER_BASE 0x1000007FFC6A4A80ull +#define DCORE3_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE3_HMMU2_MSTR_IF_DBG_HBW_BASE 0x1000007FFC6A4B00ull +#define DCORE3_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_HMMU2_MSTR_IF_DBG_LBW_BASE 0x1000007FFC6A4B80ull +#define DCORE3_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE3_HMMU2_MSTR_IF_CORE_HBW_BASE 0x1000007FFC6A4C00ull +#define DCORE3_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE3_HMMU2_MSTR_IF_CORE_LBW_BASE 0x1000007FFC6A4D80ull +#define DCORE3_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE3_HMMU2_MSTR_IF_SPECIAL_BASE 0x1000007FFC6A4E80ull +#define DCORE3_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180 + +#define mmDCORE3_HMMU3_MMU_BASE 0x1000007FFC6B0000ull +#define DCORE3_HMMU3_MMU_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_MMU_SECTION 0xE800 + +#define mmDCORE3_HMMU3_MMU_SPECIAL_BASE 0x1000007FFC6B0E80ull +#define DCORE3_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU3_MMU_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_HMMU3_STLB_BASE 0x1000007FFC6B1000ull +#define DCORE3_HMMU3_STLB_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_STLB_SECTION 0xE800 + +#define mmDCORE3_HMMU3_STLB_SPECIAL_BASE 0x1000007FFC6B1E80ull +#define DCORE3_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU3_STLB_SPECIAL_SECTION 0x1180 + +#define mmDCORE3_HMMU3_SCRAMB_OUT_BASE 0x1000007FFC6B3000ull +#define DCORE3_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_SCRAMB_OUT_SECTION 0xE800 + +#define mmDCORE3_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x1000007FFC6B3E80ull +#define DCORE3_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC6B4000ull +#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE3_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC6B4200ull +#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE3_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC6B4400ull +#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE3_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC6B4600ull +#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE3_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC6B4800ull +#define DCORE3_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE3_HMMU3_MSTR_IF_AXUSER_BASE 0x1000007FFC6B4A80ull +#define DCORE3_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE3_HMMU3_MSTR_IF_DBG_HBW_BASE 0x1000007FFC6B4B00ull +#define DCORE3_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_HMMU3_MSTR_IF_DBG_LBW_BASE 0x1000007FFC6B4B80ull +#define DCORE3_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE3_HMMU3_MSTR_IF_CORE_HBW_BASE 0x1000007FFC6B4C00ull +#define DCORE3_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE3_HMMU3_MSTR_IF_CORE_LBW_BASE 0x1000007FFC6B4D80ull +#define DCORE3_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE3_HMMU3_MSTR_IF_SPECIAL_BASE 0x1000007FFC6B4E80ull +#define DCORE3_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180 + +#define mmDCORE3_SYNC_MNGR_OBJS_BASE 0x1000007FFC700000ull +#define DCORE3_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00 +#define DCORE3_SYNC_MNGR_OBJS_SECTION 0x1E000 + +#define mmDCORE3_SYNC_MNGR_GLBL_BASE 0x1000007FFC71E000ull +#define DCORE3_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000 +#define DCORE3_SYNC_MNGR_GLBL_SECTION 0xE800 + +#define mmDCORE3_SYNC_MNGR_GLBL_SPECIAL_BASE 0x1000007FFC71EE80ull +#define DCORE3_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC71F000ull +#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC71F200ull +#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC71F400ull +#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC71F600ull +#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE3_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC71F800ull +#define DCORE3_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE3_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x1000007FFC71FA80ull +#define DCORE3_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE3_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x1000007FFC71FB00ull +#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x1000007FFC71FB80ull +#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE3_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x1000007FFC71FC00ull +#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE3_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x1000007FFC71FD80ull +#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE3_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x1000007FFC71FE80ull +#define DCORE3_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_HIF0_BASE 0x1000007FFC720000ull +#define DCORE3_HIF0_MAX_OFFSET 0x1000 +#define DCORE3_HIF0_SECTION 0xE800 + +#define mmDCORE3_HIF0_SPECIAL_BASE 0x1000007FFC720E80ull +#define DCORE3_HIF0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HIF0_SPECIAL_SECTION 0x3180 + +#define mmDCORE3_HIF1_BASE 0x1000007FFC724000ull +#define DCORE3_HIF1_MAX_OFFSET 0x1000 +#define DCORE3_HIF1_SECTION 0xE800 + +#define mmDCORE3_HIF1_SPECIAL_BASE 0x1000007FFC724E80ull +#define DCORE3_HIF1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HIF1_SPECIAL_SECTION 0x3180 + +#define mmDCORE3_HIF2_BASE 0x1000007FFC728000ull +#define DCORE3_HIF2_MAX_OFFSET 0x1000 +#define DCORE3_HIF2_SECTION 0xE800 + +#define mmDCORE3_HIF2_SPECIAL_BASE 0x1000007FFC728E80ull +#define DCORE3_HIF2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HIF2_SPECIAL_SECTION 0x3180 + +#define mmDCORE3_HIF3_BASE 0x1000007FFC72C000ull +#define DCORE3_HIF3_MAX_OFFSET 0x1000 +#define DCORE3_HIF3_SECTION 0xE800 + +#define mmDCORE3_HIF3_SPECIAL_BASE 0x1000007FFC72CE80ull +#define DCORE3_HIF3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HIF3_SPECIAL_SECTION 0x13180 + +#define mmDCORE3_RTR0_CTRL_BASE 0x1000007FFC740000ull +#define DCORE3_RTR0_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_RTR0_CTRL_SECTION 0xE800 + +#define mmDCORE3_RTR0_CTRL_SPECIAL_BASE 0x1000007FFC740E80ull +#define DCORE3_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR0_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR0_H3_BASE 0x1000007FFC741000ull +#define DCORE3_RTR0_H3_MAX_OFFSET 0x1000 +#define DCORE3_RTR0_H3_SECTION 0xE800 + +#define mmDCORE3_RTR0_H3_SPECIAL_BASE 0x1000007FFC741E80ull +#define DCORE3_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR0_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC742000ull +#define DCORE3_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE3_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC742200ull +#define DCORE3_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE3_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC742400ull +#define DCORE3_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE3_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC742600ull +#define DCORE3_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE3_RTR0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC742800ull +#define DCORE3_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE3_RTR0_MSTR_IF_AXUSER_BASE 0x1000007FFC742A80ull +#define DCORE3_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_RTR0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE3_RTR0_MSTR_IF_DBG_HBW_BASE 0x1000007FFC742B00ull +#define DCORE3_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_RTR0_MSTR_IF_DBG_LBW_BASE 0x1000007FFC742B80ull +#define DCORE3_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE3_RTR0_MSTR_IF_CORE_HBW_BASE 0x1000007FFC742C00ull +#define DCORE3_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE3_RTR0_MSTR_IF_CORE_LBW_BASE 0x1000007FFC742D80ull +#define DCORE3_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE3_RTR0_MSTR_IF_SPECIAL_BASE 0x1000007FFC742E80ull +#define DCORE3_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR0_ADD_DEC_HBW_BASE 0x1000007FFC743000ull +#define DCORE3_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE3_RTR0_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE3_RTR0_ADD_DEC_LBW_BASE 0x1000007FFC743400ull +#define DCORE3_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE3_RTR0_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE3_RTR0_ADD_DEC_SPECIAL_BASE 0x1000007FFC743E80ull +#define DCORE3_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR0_BASE 0x1000007FFC744000ull +#define DCORE3_RTR0_MAX_OFFSET 0x1000 +#define DCORE3_RTR0_SECTION 0x3000 + +#define mmDCORE3_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC744300ull +#define DCORE3_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR0_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC744340ull +#define DCORE3_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC744380ull +#define DCORE3_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR0_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC7443C0ull +#define DCORE3_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC744400ull +#define DCORE3_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR0_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC744440ull +#define DCORE3_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC744480ull +#define DCORE3_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR0_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC7444C0ull +#define DCORE3_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR0_HBW_MFIFO_BASE 0x1000007FFC744500ull +#define DCORE3_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE3_RTR0_E2E_RD_LL_STAT_BASE 0x1000007FFC744540ull +#define DCORE3_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR0_E2E_WR_LL_STAT_BASE 0x1000007FFC744580ull +#define DCORE3_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR0_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE3_RTR0_RTR_HBW_XACT_STAT_BASE 0x1000007FFC744600ull +#define DCORE3_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE3_RTR0_RTR_LBW_XACT_STAT_BASE 0x1000007FFC744680ull +#define DCORE3_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE3_RTR0_RTR_E2E_XACT_STAT_BASE 0x1000007FFC744700ull +#define DCORE3_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE3_RTR0_SPECIAL_BASE 0x1000007FFC744E80ull +#define DCORE3_RTR0_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR0_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR0_DBG_ADDR_BASE 0x1000007FFC745000ull +#define DCORE3_RTR0_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE3_RTR0_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE3_RTR0_DBG_ADDR_SPECIAL_BASE 0x1000007FFC745E80ull +#define DCORE3_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE3_RTR1_CTRL_BASE 0x1000007FFC748000ull +#define DCORE3_RTR1_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_RTR1_CTRL_SECTION 0xE800 + +#define mmDCORE3_RTR1_CTRL_SPECIAL_BASE 0x1000007FFC748E80ull +#define DCORE3_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR1_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR1_H3_BASE 0x1000007FFC749000ull +#define DCORE3_RTR1_H3_MAX_OFFSET 0x1000 +#define DCORE3_RTR1_H3_SECTION 0xE800 + +#define mmDCORE3_RTR1_H3_SPECIAL_BASE 0x1000007FFC749E80ull +#define DCORE3_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR1_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC74A000ull +#define DCORE3_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE3_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC74A200ull +#define DCORE3_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE3_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC74A400ull +#define DCORE3_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE3_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC74A600ull +#define DCORE3_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE3_RTR1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC74A800ull +#define DCORE3_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE3_RTR1_MSTR_IF_AXUSER_BASE 0x1000007FFC74AA80ull +#define DCORE3_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_RTR1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE3_RTR1_MSTR_IF_DBG_HBW_BASE 0x1000007FFC74AB00ull +#define DCORE3_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_RTR1_MSTR_IF_DBG_LBW_BASE 0x1000007FFC74AB80ull +#define DCORE3_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE3_RTR1_MSTR_IF_CORE_HBW_BASE 0x1000007FFC74AC00ull +#define DCORE3_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE3_RTR1_MSTR_IF_CORE_LBW_BASE 0x1000007FFC74AD80ull +#define DCORE3_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE3_RTR1_MSTR_IF_SPECIAL_BASE 0x1000007FFC74AE80ull +#define DCORE3_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR1_ADD_DEC_HBW_BASE 0x1000007FFC74B000ull +#define DCORE3_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE3_RTR1_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE3_RTR1_ADD_DEC_LBW_BASE 0x1000007FFC74B400ull +#define DCORE3_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE3_RTR1_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE3_RTR1_ADD_DEC_SPECIAL_BASE 0x1000007FFC74BE80ull +#define DCORE3_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR1_BASE 0x1000007FFC74C000ull +#define DCORE3_RTR1_MAX_OFFSET 0x1000 +#define DCORE3_RTR1_SECTION 0x3000 + +#define mmDCORE3_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC74C300ull +#define DCORE3_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR1_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC74C340ull +#define DCORE3_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC74C380ull +#define DCORE3_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR1_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC74C3C0ull +#define DCORE3_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC74C400ull +#define DCORE3_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR1_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC74C440ull +#define DCORE3_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC74C480ull +#define DCORE3_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR1_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC74C4C0ull +#define DCORE3_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR1_HBW_MFIFO_BASE 0x1000007FFC74C500ull +#define DCORE3_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE3_RTR1_E2E_RD_LL_STAT_BASE 0x1000007FFC74C540ull +#define DCORE3_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR1_E2E_WR_LL_STAT_BASE 0x1000007FFC74C580ull +#define DCORE3_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR1_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE3_RTR1_RTR_HBW_XACT_STAT_BASE 0x1000007FFC74C600ull +#define DCORE3_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE3_RTR1_RTR_LBW_XACT_STAT_BASE 0x1000007FFC74C680ull +#define DCORE3_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE3_RTR1_RTR_E2E_XACT_STAT_BASE 0x1000007FFC74C700ull +#define DCORE3_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE3_RTR1_SPECIAL_BASE 0x1000007FFC74CE80ull +#define DCORE3_RTR1_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR1_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR1_DBG_ADDR_BASE 0x1000007FFC74D000ull +#define DCORE3_RTR1_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE3_RTR1_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE3_RTR1_DBG_ADDR_SPECIAL_BASE 0x1000007FFC74DE80ull +#define DCORE3_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE3_RTR2_CTRL_BASE 0x1000007FFC750000ull +#define DCORE3_RTR2_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_RTR2_CTRL_SECTION 0xE800 + +#define mmDCORE3_RTR2_CTRL_SPECIAL_BASE 0x1000007FFC750E80ull +#define DCORE3_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR2_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR2_H3_BASE 0x1000007FFC751000ull +#define DCORE3_RTR2_H3_MAX_OFFSET 0x1000 +#define DCORE3_RTR2_H3_SECTION 0xE800 + +#define mmDCORE3_RTR2_H3_SPECIAL_BASE 0x1000007FFC751E80ull +#define DCORE3_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR2_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC752000ull +#define DCORE3_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE3_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC752200ull +#define DCORE3_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE3_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC752400ull +#define DCORE3_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE3_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC752600ull +#define DCORE3_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE3_RTR2_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC752800ull +#define DCORE3_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE3_RTR2_MSTR_IF_AXUSER_BASE 0x1000007FFC752A80ull +#define DCORE3_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_RTR2_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE3_RTR2_MSTR_IF_DBG_HBW_BASE 0x1000007FFC752B00ull +#define DCORE3_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_RTR2_MSTR_IF_DBG_LBW_BASE 0x1000007FFC752B80ull +#define DCORE3_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE3_RTR2_MSTR_IF_CORE_HBW_BASE 0x1000007FFC752C00ull +#define DCORE3_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE3_RTR2_MSTR_IF_CORE_LBW_BASE 0x1000007FFC752D80ull +#define DCORE3_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE3_RTR2_MSTR_IF_SPECIAL_BASE 0x1000007FFC752E80ull +#define DCORE3_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR2_ADD_DEC_HBW_BASE 0x1000007FFC753000ull +#define DCORE3_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE3_RTR2_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE3_RTR2_ADD_DEC_LBW_BASE 0x1000007FFC753400ull +#define DCORE3_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE3_RTR2_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE3_RTR2_ADD_DEC_SPECIAL_BASE 0x1000007FFC753E80ull +#define DCORE3_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR2_BASE 0x1000007FFC754000ull +#define DCORE3_RTR2_MAX_OFFSET 0x1000 +#define DCORE3_RTR2_SECTION 0x3000 + +#define mmDCORE3_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC754300ull +#define DCORE3_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR2_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC754340ull +#define DCORE3_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC754380ull +#define DCORE3_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR2_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC7543C0ull +#define DCORE3_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC754400ull +#define DCORE3_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR2_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC754440ull +#define DCORE3_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC754480ull +#define DCORE3_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR2_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC7544C0ull +#define DCORE3_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR2_HBW_MFIFO_BASE 0x1000007FFC754500ull +#define DCORE3_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE3_RTR2_E2E_RD_LL_STAT_BASE 0x1000007FFC754540ull +#define DCORE3_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR2_E2E_WR_LL_STAT_BASE 0x1000007FFC754580ull +#define DCORE3_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR2_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE3_RTR2_RTR_HBW_XACT_STAT_BASE 0x1000007FFC754600ull +#define DCORE3_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE3_RTR2_RTR_LBW_XACT_STAT_BASE 0x1000007FFC754680ull +#define DCORE3_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE3_RTR2_RTR_E2E_XACT_STAT_BASE 0x1000007FFC754700ull +#define DCORE3_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE3_RTR2_SPECIAL_BASE 0x1000007FFC754E80ull +#define DCORE3_RTR2_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR2_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR2_DBG_ADDR_BASE 0x1000007FFC755000ull +#define DCORE3_RTR2_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE3_RTR2_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE3_RTR2_DBG_ADDR_SPECIAL_BASE 0x1000007FFC755E80ull +#define DCORE3_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE3_RTR3_CTRL_BASE 0x1000007FFC758000ull +#define DCORE3_RTR3_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_RTR3_CTRL_SECTION 0xE800 + +#define mmDCORE3_RTR3_CTRL_SPECIAL_BASE 0x1000007FFC758E80ull +#define DCORE3_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR3_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR3_H3_BASE 0x1000007FFC759000ull +#define DCORE3_RTR3_H3_MAX_OFFSET 0x1000 +#define DCORE3_RTR3_H3_SECTION 0xE800 + +#define mmDCORE3_RTR3_H3_SPECIAL_BASE 0x1000007FFC759E80ull +#define DCORE3_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR3_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC75A000ull +#define DCORE3_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE3_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC75A200ull +#define DCORE3_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE3_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC75A400ull +#define DCORE3_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE3_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC75A600ull +#define DCORE3_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE3_RTR3_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC75A800ull +#define DCORE3_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE3_RTR3_MSTR_IF_AXUSER_BASE 0x1000007FFC75AA80ull +#define DCORE3_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_RTR3_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE3_RTR3_MSTR_IF_DBG_HBW_BASE 0x1000007FFC75AB00ull +#define DCORE3_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_RTR3_MSTR_IF_DBG_LBW_BASE 0x1000007FFC75AB80ull +#define DCORE3_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE3_RTR3_MSTR_IF_CORE_HBW_BASE 0x1000007FFC75AC00ull +#define DCORE3_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE3_RTR3_MSTR_IF_CORE_LBW_BASE 0x1000007FFC75AD80ull +#define DCORE3_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE3_RTR3_MSTR_IF_SPECIAL_BASE 0x1000007FFC75AE80ull +#define DCORE3_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR3_ADD_DEC_HBW_BASE 0x1000007FFC75B000ull +#define DCORE3_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE3_RTR3_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE3_RTR3_ADD_DEC_LBW_BASE 0x1000007FFC75B400ull +#define DCORE3_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE3_RTR3_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE3_RTR3_ADD_DEC_SPECIAL_BASE 0x1000007FFC75BE80ull +#define DCORE3_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR3_BASE 0x1000007FFC75C000ull +#define DCORE3_RTR3_MAX_OFFSET 0x1000 +#define DCORE3_RTR3_SECTION 0x3000 + +#define mmDCORE3_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC75C300ull +#define DCORE3_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR3_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC75C340ull +#define DCORE3_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC75C380ull +#define DCORE3_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR3_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC75C3C0ull +#define DCORE3_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC75C400ull +#define DCORE3_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR3_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC75C440ull +#define DCORE3_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC75C480ull +#define DCORE3_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR3_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC75C4C0ull +#define DCORE3_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR3_HBW_MFIFO_BASE 0x1000007FFC75C500ull +#define DCORE3_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE3_RTR3_E2E_RD_LL_STAT_BASE 0x1000007FFC75C540ull +#define DCORE3_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR3_E2E_WR_LL_STAT_BASE 0x1000007FFC75C580ull +#define DCORE3_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR3_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE3_RTR3_RTR_HBW_XACT_STAT_BASE 0x1000007FFC75C600ull +#define DCORE3_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE3_RTR3_RTR_LBW_XACT_STAT_BASE 0x1000007FFC75C680ull +#define DCORE3_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE3_RTR3_RTR_E2E_XACT_STAT_BASE 0x1000007FFC75C700ull +#define DCORE3_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE3_RTR3_SPECIAL_BASE 0x1000007FFC75CE80ull +#define DCORE3_RTR3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR3_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR3_DBG_ADDR_BASE 0x1000007FFC75D000ull +#define DCORE3_RTR3_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE3_RTR3_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE3_RTR3_DBG_ADDR_SPECIAL_BASE 0x1000007FFC75DE80ull +#define DCORE3_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE3_RTR4_CTRL_BASE 0x1000007FFC760000ull +#define DCORE3_RTR4_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_RTR4_CTRL_SECTION 0xE800 + +#define mmDCORE3_RTR4_CTRL_SPECIAL_BASE 0x1000007FFC760E80ull +#define DCORE3_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR4_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR4_H3_BASE 0x1000007FFC761000ull +#define DCORE3_RTR4_H3_MAX_OFFSET 0x1000 +#define DCORE3_RTR4_H3_SECTION 0xE800 + +#define mmDCORE3_RTR4_H3_SPECIAL_BASE 0x1000007FFC761E80ull +#define DCORE3_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR4_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC762000ull +#define DCORE3_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE3_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC762200ull +#define DCORE3_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE3_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC762400ull +#define DCORE3_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE3_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC762600ull +#define DCORE3_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE3_RTR4_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC762800ull +#define DCORE3_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE3_RTR4_MSTR_IF_AXUSER_BASE 0x1000007FFC762A80ull +#define DCORE3_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_RTR4_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE3_RTR4_MSTR_IF_DBG_HBW_BASE 0x1000007FFC762B00ull +#define DCORE3_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_RTR4_MSTR_IF_DBG_LBW_BASE 0x1000007FFC762B80ull +#define DCORE3_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE3_RTR4_MSTR_IF_CORE_HBW_BASE 0x1000007FFC762C00ull +#define DCORE3_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE3_RTR4_MSTR_IF_CORE_LBW_BASE 0x1000007FFC762D80ull +#define DCORE3_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE3_RTR4_MSTR_IF_SPECIAL_BASE 0x1000007FFC762E80ull +#define DCORE3_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR4_ADD_DEC_HBW_BASE 0x1000007FFC763000ull +#define DCORE3_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE3_RTR4_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE3_RTR4_ADD_DEC_LBW_BASE 0x1000007FFC763400ull +#define DCORE3_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE3_RTR4_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE3_RTR4_ADD_DEC_SPECIAL_BASE 0x1000007FFC763E80ull +#define DCORE3_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR4_BASE 0x1000007FFC764000ull +#define DCORE3_RTR4_MAX_OFFSET 0x1000 +#define DCORE3_RTR4_SECTION 0x3000 + +#define mmDCORE3_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC764300ull +#define DCORE3_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR4_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC764340ull +#define DCORE3_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC764380ull +#define DCORE3_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR4_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC7643C0ull +#define DCORE3_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC764400ull +#define DCORE3_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR4_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC764440ull +#define DCORE3_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC764480ull +#define DCORE3_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR4_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC7644C0ull +#define DCORE3_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR4_HBW_MFIFO_BASE 0x1000007FFC764500ull +#define DCORE3_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE3_RTR4_E2E_RD_LL_STAT_BASE 0x1000007FFC764540ull +#define DCORE3_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR4_E2E_WR_LL_STAT_BASE 0x1000007FFC764580ull +#define DCORE3_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR4_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE3_RTR4_RTR_HBW_XACT_STAT_BASE 0x1000007FFC764600ull +#define DCORE3_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE3_RTR4_RTR_LBW_XACT_STAT_BASE 0x1000007FFC764680ull +#define DCORE3_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE3_RTR4_RTR_E2E_XACT_STAT_BASE 0x1000007FFC764700ull +#define DCORE3_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE3_RTR4_SPECIAL_BASE 0x1000007FFC764E80ull +#define DCORE3_RTR4_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR4_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR4_DBG_ADDR_BASE 0x1000007FFC765000ull +#define DCORE3_RTR4_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE3_RTR4_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE3_RTR4_DBG_ADDR_SPECIAL_BASE 0x1000007FFC765E80ull +#define DCORE3_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE3_RTR5_CTRL_BASE 0x1000007FFC768000ull +#define DCORE3_RTR5_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_RTR5_CTRL_SECTION 0xE800 + +#define mmDCORE3_RTR5_CTRL_SPECIAL_BASE 0x1000007FFC768E80ull +#define DCORE3_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR5_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR5_H3_BASE 0x1000007FFC769000ull +#define DCORE3_RTR5_H3_MAX_OFFSET 0x1000 +#define DCORE3_RTR5_H3_SECTION 0xE800 + +#define mmDCORE3_RTR5_H3_SPECIAL_BASE 0x1000007FFC769E80ull +#define DCORE3_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR5_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC76A000ull +#define DCORE3_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE3_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC76A200ull +#define DCORE3_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE3_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC76A400ull +#define DCORE3_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE3_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC76A600ull +#define DCORE3_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE3_RTR5_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC76A800ull +#define DCORE3_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE3_RTR5_MSTR_IF_AXUSER_BASE 0x1000007FFC76AA80ull +#define DCORE3_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_RTR5_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE3_RTR5_MSTR_IF_DBG_HBW_BASE 0x1000007FFC76AB00ull +#define DCORE3_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_RTR5_MSTR_IF_DBG_LBW_BASE 0x1000007FFC76AB80ull +#define DCORE3_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE3_RTR5_MSTR_IF_CORE_HBW_BASE 0x1000007FFC76AC00ull +#define DCORE3_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE3_RTR5_MSTR_IF_CORE_LBW_BASE 0x1000007FFC76AD80ull +#define DCORE3_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE3_RTR5_MSTR_IF_SPECIAL_BASE 0x1000007FFC76AE80ull +#define DCORE3_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR5_ADD_DEC_HBW_BASE 0x1000007FFC76B000ull +#define DCORE3_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE3_RTR5_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE3_RTR5_ADD_DEC_LBW_BASE 0x1000007FFC76B400ull +#define DCORE3_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE3_RTR5_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE3_RTR5_ADD_DEC_SPECIAL_BASE 0x1000007FFC76BE80ull +#define DCORE3_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR5_BASE 0x1000007FFC76C000ull +#define DCORE3_RTR5_MAX_OFFSET 0x1000 +#define DCORE3_RTR5_SECTION 0x3000 + +#define mmDCORE3_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC76C300ull +#define DCORE3_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR5_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC76C340ull +#define DCORE3_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC76C380ull +#define DCORE3_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR5_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC76C3C0ull +#define DCORE3_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC76C400ull +#define DCORE3_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR5_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC76C440ull +#define DCORE3_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC76C480ull +#define DCORE3_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR5_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC76C4C0ull +#define DCORE3_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR5_HBW_MFIFO_BASE 0x1000007FFC76C500ull +#define DCORE3_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE3_RTR5_E2E_RD_LL_STAT_BASE 0x1000007FFC76C540ull +#define DCORE3_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR5_E2E_WR_LL_STAT_BASE 0x1000007FFC76C580ull +#define DCORE3_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR5_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE3_RTR5_RTR_HBW_XACT_STAT_BASE 0x1000007FFC76C600ull +#define DCORE3_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE3_RTR5_RTR_LBW_XACT_STAT_BASE 0x1000007FFC76C680ull +#define DCORE3_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE3_RTR5_RTR_E2E_XACT_STAT_BASE 0x1000007FFC76C700ull +#define DCORE3_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE3_RTR5_SPECIAL_BASE 0x1000007FFC76CE80ull +#define DCORE3_RTR5_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR5_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR5_DBG_ADDR_BASE 0x1000007FFC76D000ull +#define DCORE3_RTR5_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE3_RTR5_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE3_RTR5_DBG_ADDR_SPECIAL_BASE 0x1000007FFC76DE80ull +#define DCORE3_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE3_RTR6_CTRL_BASE 0x1000007FFC770000ull +#define DCORE3_RTR6_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_RTR6_CTRL_SECTION 0xE800 + +#define mmDCORE3_RTR6_CTRL_SPECIAL_BASE 0x1000007FFC770E80ull +#define DCORE3_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR6_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR6_H3_BASE 0x1000007FFC771000ull +#define DCORE3_RTR6_H3_MAX_OFFSET 0x1000 +#define DCORE3_RTR6_H3_SECTION 0xE800 + +#define mmDCORE3_RTR6_H3_SPECIAL_BASE 0x1000007FFC771E80ull +#define DCORE3_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR6_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC772000ull +#define DCORE3_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE3_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC772200ull +#define DCORE3_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE3_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC772400ull +#define DCORE3_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE3_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC772600ull +#define DCORE3_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE3_RTR6_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC772800ull +#define DCORE3_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE3_RTR6_MSTR_IF_AXUSER_BASE 0x1000007FFC772A80ull +#define DCORE3_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_RTR6_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE3_RTR6_MSTR_IF_DBG_HBW_BASE 0x1000007FFC772B00ull +#define DCORE3_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_RTR6_MSTR_IF_DBG_LBW_BASE 0x1000007FFC772B80ull +#define DCORE3_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE3_RTR6_MSTR_IF_CORE_HBW_BASE 0x1000007FFC772C00ull +#define DCORE3_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE3_RTR6_MSTR_IF_CORE_LBW_BASE 0x1000007FFC772D80ull +#define DCORE3_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE3_RTR6_MSTR_IF_SPECIAL_BASE 0x1000007FFC772E80ull +#define DCORE3_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR6_ADD_DEC_HBW_BASE 0x1000007FFC773000ull +#define DCORE3_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE3_RTR6_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE3_RTR6_ADD_DEC_LBW_BASE 0x1000007FFC773400ull +#define DCORE3_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE3_RTR6_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE3_RTR6_ADD_DEC_SPECIAL_BASE 0x1000007FFC773E80ull +#define DCORE3_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR6_BASE 0x1000007FFC774000ull +#define DCORE3_RTR6_MAX_OFFSET 0x1000 +#define DCORE3_RTR6_SECTION 0x3000 + +#define mmDCORE3_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC774300ull +#define DCORE3_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR6_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC774340ull +#define DCORE3_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC774380ull +#define DCORE3_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR6_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC7743C0ull +#define DCORE3_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC774400ull +#define DCORE3_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR6_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC774440ull +#define DCORE3_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC774480ull +#define DCORE3_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR6_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC7744C0ull +#define DCORE3_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR6_HBW_MFIFO_BASE 0x1000007FFC774500ull +#define DCORE3_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE3_RTR6_E2E_RD_LL_STAT_BASE 0x1000007FFC774540ull +#define DCORE3_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR6_E2E_WR_LL_STAT_BASE 0x1000007FFC774580ull +#define DCORE3_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR6_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE3_RTR6_RTR_HBW_XACT_STAT_BASE 0x1000007FFC774600ull +#define DCORE3_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE3_RTR6_RTR_LBW_XACT_STAT_BASE 0x1000007FFC774680ull +#define DCORE3_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE3_RTR6_RTR_E2E_XACT_STAT_BASE 0x1000007FFC774700ull +#define DCORE3_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE3_RTR6_SPECIAL_BASE 0x1000007FFC774E80ull +#define DCORE3_RTR6_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR6_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR6_DBG_ADDR_BASE 0x1000007FFC775000ull +#define DCORE3_RTR6_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE3_RTR6_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE3_RTR6_DBG_ADDR_SPECIAL_BASE 0x1000007FFC775E80ull +#define DCORE3_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE3_RTR7_CTRL_BASE 0x1000007FFC778000ull +#define DCORE3_RTR7_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_RTR7_CTRL_SECTION 0xE800 + +#define mmDCORE3_RTR7_CTRL_SPECIAL_BASE 0x1000007FFC778E80ull +#define DCORE3_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR7_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR7_H3_BASE 0x1000007FFC779000ull +#define DCORE3_RTR7_H3_MAX_OFFSET 0x1000 +#define DCORE3_RTR7_H3_SECTION 0xE800 + +#define mmDCORE3_RTR7_H3_SPECIAL_BASE 0x1000007FFC779E80ull +#define DCORE3_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR7_H3_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC77A000ull +#define DCORE3_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE3_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC77A200ull +#define DCORE3_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE3_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC77A400ull +#define DCORE3_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE3_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC77A600ull +#define DCORE3_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE3_RTR7_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC77A800ull +#define DCORE3_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE3_RTR7_MSTR_IF_AXUSER_BASE 0x1000007FFC77AA80ull +#define DCORE3_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_RTR7_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE3_RTR7_MSTR_IF_DBG_HBW_BASE 0x1000007FFC77AB00ull +#define DCORE3_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_RTR7_MSTR_IF_DBG_LBW_BASE 0x1000007FFC77AB80ull +#define DCORE3_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE3_RTR7_MSTR_IF_CORE_HBW_BASE 0x1000007FFC77AC00ull +#define DCORE3_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE3_RTR7_MSTR_IF_CORE_LBW_BASE 0x1000007FFC77AD80ull +#define DCORE3_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE3_RTR7_MSTR_IF_SPECIAL_BASE 0x1000007FFC77AE80ull +#define DCORE3_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR7_ADD_DEC_HBW_BASE 0x1000007FFC77B000ull +#define DCORE3_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000 +#define DCORE3_RTR7_ADD_DEC_HBW_SECTION 0x4000 + +#define mmDCORE3_RTR7_ADD_DEC_LBW_BASE 0x1000007FFC77B400ull +#define DCORE3_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600 +#define DCORE3_RTR7_ADD_DEC_LBW_SECTION 0xA800 + +#define mmDCORE3_RTR7_ADD_DEC_SPECIAL_BASE 0x1000007FFC77BE80ull +#define DCORE3_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR7_BASE 0x1000007FFC77C000ull +#define DCORE3_RTR7_MAX_OFFSET 0x1000 +#define DCORE3_RTR7_SECTION 0x3000 + +#define mmDCORE3_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x1000007FFC77C300ull +#define DCORE3_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR7_HBW_RD_RS_LL_STAT_BASE 0x1000007FFC77C340ull +#define DCORE3_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x1000007FFC77C380ull +#define DCORE3_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR7_HBW_WR_RS_LL_STAT_BASE 0x1000007FFC77C3C0ull +#define DCORE3_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x1000007FFC77C400ull +#define DCORE3_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR7_LBW_RD_RS_LL_STAT_BASE 0x1000007FFC77C440ull +#define DCORE3_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x1000007FFC77C480ull +#define DCORE3_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR7_LBW_WR_RS_LL_STAT_BASE 0x1000007FFC77C4C0ull +#define DCORE3_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR7_HBW_MFIFO_BASE 0x1000007FFC77C500ull +#define DCORE3_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_HBW_MFIFO_SECTION 0x4000 + +#define mmDCORE3_RTR7_E2E_RD_LL_STAT_BASE 0x1000007FFC77C540ull +#define DCORE3_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_E2E_RD_LL_STAT_SECTION 0x4000 + +#define mmDCORE3_RTR7_E2E_WR_LL_STAT_BASE 0x1000007FFC77C580ull +#define DCORE3_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 +#define DCORE3_RTR7_E2E_WR_LL_STAT_SECTION 0x8000 + +#define mmDCORE3_RTR7_RTR_HBW_XACT_STAT_BASE 0x1000007FFC77C600ull +#define DCORE3_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE3_RTR7_RTR_LBW_XACT_STAT_BASE 0x1000007FFC77C680ull +#define DCORE3_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000 + +#define mmDCORE3_RTR7_RTR_E2E_XACT_STAT_BASE 0x1000007FFC77C700ull +#define DCORE3_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 +#define DCORE3_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800 + +#define mmDCORE3_RTR7_SPECIAL_BASE 0x1000007FFC77CE80ull +#define DCORE3_RTR7_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR7_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_RTR7_DBG_ADDR_BASE 0x1000007FFC77D000ull +#define DCORE3_RTR7_DBG_ADDR_MAX_OFFSET 0x1000 +#define DCORE3_RTR7_DBG_ADDR_SECTION 0xE800 + +#define mmDCORE3_RTR7_DBG_ADDR_SPECIAL_BASE 0x1000007FFC77DE80ull +#define DCORE3_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180 + +#define mmDCORE3_SRAM0_BANK_BASE 0x1000007FFC780000ull +#define DCORE3_SRAM0_BANK_MAX_OFFSET 0x1000 +#define DCORE3_SRAM0_BANK_SECTION 0xE800 + +#define mmDCORE3_SRAM0_BANK_SPECIAL_BASE 0x1000007FFC780E80ull +#define DCORE3_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM0_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_SRAM0_RTR_BASE 0x1000007FFC781000ull +#define DCORE3_SRAM0_RTR_MAX_OFFSET 0x1000 +#define DCORE3_SRAM0_RTR_SECTION 0xE800 + +#define mmDCORE3_SRAM0_RTR_SPECIAL_BASE 0x1000007FFC781E80ull +#define DCORE3_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM0_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC782000ull +#define DCORE3_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC782100ull +#define DCORE3_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC782200ull +#define DCORE3_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC782300ull +#define DCORE3_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC782400ull +#define DCORE3_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC782500ull +#define DCORE3_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC782600ull +#define DCORE3_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC782700ull +#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC782780ull +#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC782800ull +#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC782880ull +#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC782900ull +#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC782980ull +#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC782A00ull +#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC782A80ull +#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE3_SRAM0_DBG_CNT_SPECIAL_BASE 0x1000007FFC782E80ull +#define DCORE3_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE3_SRAM1_BANK_BASE 0x1000007FFC788000ull +#define DCORE3_SRAM1_BANK_MAX_OFFSET 0x1000 +#define DCORE3_SRAM1_BANK_SECTION 0xE800 + +#define mmDCORE3_SRAM1_BANK_SPECIAL_BASE 0x1000007FFC788E80ull +#define DCORE3_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM1_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_SRAM1_RTR_BASE 0x1000007FFC789000ull +#define DCORE3_SRAM1_RTR_MAX_OFFSET 0x1000 +#define DCORE3_SRAM1_RTR_SECTION 0xE800 + +#define mmDCORE3_SRAM1_RTR_SPECIAL_BASE 0x1000007FFC789E80ull +#define DCORE3_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM1_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC78A000ull +#define DCORE3_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC78A100ull +#define DCORE3_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC78A200ull +#define DCORE3_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC78A300ull +#define DCORE3_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC78A400ull +#define DCORE3_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC78A500ull +#define DCORE3_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC78A600ull +#define DCORE3_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC78A700ull +#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC78A780ull +#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC78A800ull +#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC78A880ull +#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC78A900ull +#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC78A980ull +#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC78AA00ull +#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC78AA80ull +#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE3_SRAM1_DBG_CNT_SPECIAL_BASE 0x1000007FFC78AE80ull +#define DCORE3_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE3_SRAM2_BANK_BASE 0x1000007FFC790000ull +#define DCORE3_SRAM2_BANK_MAX_OFFSET 0x1000 +#define DCORE3_SRAM2_BANK_SECTION 0xE800 + +#define mmDCORE3_SRAM2_BANK_SPECIAL_BASE 0x1000007FFC790E80ull +#define DCORE3_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM2_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_SRAM2_RTR_BASE 0x1000007FFC791000ull +#define DCORE3_SRAM2_RTR_MAX_OFFSET 0x1000 +#define DCORE3_SRAM2_RTR_SECTION 0xE800 + +#define mmDCORE3_SRAM2_RTR_SPECIAL_BASE 0x1000007FFC791E80ull +#define DCORE3_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM2_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC792000ull +#define DCORE3_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC792100ull +#define DCORE3_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC792200ull +#define DCORE3_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC792300ull +#define DCORE3_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC792400ull +#define DCORE3_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC792500ull +#define DCORE3_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC792600ull +#define DCORE3_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC792700ull +#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC792780ull +#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC792800ull +#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC792880ull +#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC792900ull +#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC792980ull +#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC792A00ull +#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC792A80ull +#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE3_SRAM2_DBG_CNT_SPECIAL_BASE 0x1000007FFC792E80ull +#define DCORE3_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE3_SRAM3_BANK_BASE 0x1000007FFC798000ull +#define DCORE3_SRAM3_BANK_MAX_OFFSET 0x1000 +#define DCORE3_SRAM3_BANK_SECTION 0xE800 + +#define mmDCORE3_SRAM3_BANK_SPECIAL_BASE 0x1000007FFC798E80ull +#define DCORE3_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM3_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_SRAM3_RTR_BASE 0x1000007FFC799000ull +#define DCORE3_SRAM3_RTR_MAX_OFFSET 0x1000 +#define DCORE3_SRAM3_RTR_SECTION 0xE800 + +#define mmDCORE3_SRAM3_RTR_SPECIAL_BASE 0x1000007FFC799E80ull +#define DCORE3_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM3_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC79A000ull +#define DCORE3_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC79A100ull +#define DCORE3_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC79A200ull +#define DCORE3_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC79A300ull +#define DCORE3_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC79A400ull +#define DCORE3_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC79A500ull +#define DCORE3_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC79A600ull +#define DCORE3_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC79A700ull +#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC79A780ull +#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC79A800ull +#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC79A880ull +#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC79A900ull +#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC79A980ull +#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC79AA00ull +#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC79AA80ull +#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE3_SRAM3_DBG_CNT_SPECIAL_BASE 0x1000007FFC79AE80ull +#define DCORE3_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE3_SRAM4_BANK_BASE 0x1000007FFC7A0000ull +#define DCORE3_SRAM4_BANK_MAX_OFFSET 0x1000 +#define DCORE3_SRAM4_BANK_SECTION 0xE800 + +#define mmDCORE3_SRAM4_BANK_SPECIAL_BASE 0x1000007FFC7A0E80ull +#define DCORE3_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM4_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_SRAM4_RTR_BASE 0x1000007FFC7A1000ull +#define DCORE3_SRAM4_RTR_MAX_OFFSET 0x1000 +#define DCORE3_SRAM4_RTR_SECTION 0xE800 + +#define mmDCORE3_SRAM4_RTR_SPECIAL_BASE 0x1000007FFC7A1E80ull +#define DCORE3_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM4_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC7A2000ull +#define DCORE3_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC7A2100ull +#define DCORE3_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC7A2200ull +#define DCORE3_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC7A2300ull +#define DCORE3_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC7A2400ull +#define DCORE3_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC7A2500ull +#define DCORE3_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC7A2600ull +#define DCORE3_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC7A2700ull +#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC7A2780ull +#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC7A2800ull +#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC7A2880ull +#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC7A2900ull +#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC7A2980ull +#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC7A2A00ull +#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC7A2A80ull +#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE3_SRAM4_DBG_CNT_SPECIAL_BASE 0x1000007FFC7A2E80ull +#define DCORE3_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE3_SRAM5_BANK_BASE 0x1000007FFC7A8000ull +#define DCORE3_SRAM5_BANK_MAX_OFFSET 0x1000 +#define DCORE3_SRAM5_BANK_SECTION 0xE800 + +#define mmDCORE3_SRAM5_BANK_SPECIAL_BASE 0x1000007FFC7A8E80ull +#define DCORE3_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM5_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_SRAM5_RTR_BASE 0x1000007FFC7A9000ull +#define DCORE3_SRAM5_RTR_MAX_OFFSET 0x1000 +#define DCORE3_SRAM5_RTR_SECTION 0xE800 + +#define mmDCORE3_SRAM5_RTR_SPECIAL_BASE 0x1000007FFC7A9E80ull +#define DCORE3_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM5_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC7AA000ull +#define DCORE3_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC7AA100ull +#define DCORE3_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC7AA200ull +#define DCORE3_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC7AA300ull +#define DCORE3_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC7AA400ull +#define DCORE3_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC7AA500ull +#define DCORE3_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC7AA600ull +#define DCORE3_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC7AA700ull +#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC7AA780ull +#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC7AA800ull +#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC7AA880ull +#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC7AA900ull +#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC7AA980ull +#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC7AAA00ull +#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC7AAA80ull +#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE3_SRAM5_DBG_CNT_SPECIAL_BASE 0x1000007FFC7AAE80ull +#define DCORE3_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE3_SRAM6_BANK_BASE 0x1000007FFC7B0000ull +#define DCORE3_SRAM6_BANK_MAX_OFFSET 0x1000 +#define DCORE3_SRAM6_BANK_SECTION 0xE800 + +#define mmDCORE3_SRAM6_BANK_SPECIAL_BASE 0x1000007FFC7B0E80ull +#define DCORE3_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM6_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_SRAM6_RTR_BASE 0x1000007FFC7B1000ull +#define DCORE3_SRAM6_RTR_MAX_OFFSET 0x1000 +#define DCORE3_SRAM6_RTR_SECTION 0xE800 + +#define mmDCORE3_SRAM6_RTR_SPECIAL_BASE 0x1000007FFC7B1E80ull +#define DCORE3_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM6_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC7B2000ull +#define DCORE3_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC7B2100ull +#define DCORE3_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC7B2200ull +#define DCORE3_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC7B2300ull +#define DCORE3_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC7B2400ull +#define DCORE3_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC7B2500ull +#define DCORE3_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC7B2600ull +#define DCORE3_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC7B2700ull +#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC7B2780ull +#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC7B2800ull +#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC7B2880ull +#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC7B2900ull +#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC7B2980ull +#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC7B2A00ull +#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC7B2A80ull +#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE3_SRAM6_DBG_CNT_SPECIAL_BASE 0x1000007FFC7B2E80ull +#define DCORE3_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE3_SRAM7_BANK_BASE 0x1000007FFC7B8000ull +#define DCORE3_SRAM7_BANK_MAX_OFFSET 0x1000 +#define DCORE3_SRAM7_BANK_SECTION 0xE800 + +#define mmDCORE3_SRAM7_BANK_SPECIAL_BASE 0x1000007FFC7B8E80ull +#define DCORE3_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM7_BANK_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_SRAM7_RTR_BASE 0x1000007FFC7B9000ull +#define DCORE3_SRAM7_RTR_MAX_OFFSET 0x1000 +#define DCORE3_SRAM7_RTR_SECTION 0xE800 + +#define mmDCORE3_SRAM7_RTR_SPECIAL_BASE 0x1000007FFC7B9E80ull +#define DCORE3_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM7_RTR_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x1000007FFC7BA000ull +#define DCORE3_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x1000007FFC7BA100ull +#define DCORE3_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x1000007FFC7BA200ull +#define DCORE3_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x1000007FFC7BA300ull +#define DCORE3_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x1000007FFC7BA400ull +#define DCORE3_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x1000007FFC7BA500ull +#define DCORE3_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x1000007FFC7BA600ull +#define DCORE3_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 +#define DCORE3_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 + +#define mmDCORE3_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC7BA700ull +#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC7BA780ull +#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC7BA800ull +#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC7BA880ull +#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x1000007FFC7BA900ull +#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x1000007FFC7BA980ull +#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x1000007FFC7BAA00ull +#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 + +#define mmDCORE3_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x1000007FFC7BAA80ull +#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 +#define DCORE3_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 + +#define mmDCORE3_SRAM7_DBG_CNT_SPECIAL_BASE 0x1000007FFC7BAE80ull +#define DCORE3_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180 + +#define mmDCORE3_EDMA0_QM_DCCM_BASE 0x1000007FFC7C0000ull +#define DCORE3_EDMA0_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_EDMA0_QM_DCCM_SECTION 0x8000 + +#define mmDCORE3_EDMA0_QM_ARC_AUX_BASE 0x1000007FFC7C8000ull +#define DCORE3_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE3_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC7C8E80ull +#define DCORE3_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE3_EDMA0_QM_BASE 0x1000007FFC7CA000ull +#define DCORE3_EDMA0_QM_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_QM_SECTION 0x9000 + +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC7CA900ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC7CA908ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC7CA910ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC7CA918ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC7CA920ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC7CA928ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC7CA930ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC7CA938ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC7CA940ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC7CA948ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC7CA950ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC7CA958ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC7CA960ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC7CA968ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC7CA970ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC7CA978ull +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE3_EDMA0_QM_AXUSER_SECURED_BASE 0x1000007FFC7CAB00ull +#define DCORE3_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE3_EDMA0_QM_AXUSER_NONSECURED_BASE 0x1000007FFC7CAB80ull +#define DCORE3_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE3_EDMA0_QM_DBG_HBW_BASE 0x1000007FFC7CAC00ull +#define DCORE3_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_EDMA0_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_EDMA0_QM_DBG_LBW_BASE 0x1000007FFC7CAC80ull +#define DCORE3_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_EDMA0_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE3_EDMA0_QM_CGM_BASE 0x1000007FFC7CAD80ull +#define DCORE3_EDMA0_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_EDMA0_QM_CGM_SECTION 0x1000 + +#define mmDCORE3_EDMA0_QM_SPECIAL_BASE 0x1000007FFC7CAE80ull +#define DCORE3_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_EDMA0_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_EDMA0_CORE_BASE 0x1000007FFC7CB000ull +#define DCORE3_EDMA0_CORE_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_CORE_SECTION 0x8000 + +#define mmDCORE3_EDMA0_CORE_CTX_AXUSER_BASE 0x1000007FFC7CB800ull +#define DCORE3_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000 + +#define mmDCORE3_EDMA0_CORE_CTX_BASE 0x1000007FFC7CB860ull +#define DCORE3_EDMA0_CORE_CTX_MAX_OFFSET 0x9000 +#define DCORE3_EDMA0_CORE_CTX_SECTION 0x5A00 + +#define mmDCORE3_EDMA0_CORE_KDMA_CGM_BASE 0x1000007FFC7CBE00ull +#define DCORE3_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define DCORE3_EDMA0_CORE_KDMA_CGM_SECTION 0x8000 + +#define mmDCORE3_EDMA0_CORE_SPECIAL_BASE 0x1000007FFC7CBE80ull +#define DCORE3_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_EDMA0_CORE_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC7CC000ull +#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE3_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC7CC200ull +#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE3_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC7CC400ull +#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE3_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC7CC600ull +#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE3_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC7CC800ull +#define DCORE3_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE3_EDMA0_MSTR_IF_AXUSER_BASE 0x1000007FFC7CCA80ull +#define DCORE3_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE3_EDMA0_MSTR_IF_DBG_HBW_BASE 0x1000007FFC7CCB00ull +#define DCORE3_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_EDMA0_MSTR_IF_DBG_LBW_BASE 0x1000007FFC7CCB80ull +#define DCORE3_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE3_EDMA0_MSTR_IF_CORE_HBW_BASE 0x1000007FFC7CCC00ull +#define DCORE3_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE3_EDMA0_MSTR_IF_CORE_LBW_BASE 0x1000007FFC7CCD80ull +#define DCORE3_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE3_EDMA0_MSTR_IF_SPECIAL_BASE 0x1000007FFC7CCE80ull +#define DCORE3_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE3_EDMA1_QM_DCCM_BASE 0x1000007FFC7D0000ull +#define DCORE3_EDMA1_QM_DCCM_MAX_OFFSET 0x4000 +#define DCORE3_EDMA1_QM_DCCM_SECTION 0x8000 + +#define mmDCORE3_EDMA1_QM_ARC_AUX_BASE 0x1000007FFC7D8000ull +#define DCORE3_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_QM_ARC_AUX_SECTION 0xE800 + +#define mmDCORE3_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFC7D8E80ull +#define DCORE3_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmDCORE3_EDMA1_QM_BASE 0x1000007FFC7DA000ull +#define DCORE3_EDMA1_QM_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_QM_SECTION 0x9000 + +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFC7DA900ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFC7DA908ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFC7DA910ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFC7DA918ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFC7DA920ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFC7DA928ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFC7DA930ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFC7DA938ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFC7DA940ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFC7DA948ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFC7DA950ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFC7DA958ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFC7DA960ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFC7DA968ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFC7DA970ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFC7DA978ull +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmDCORE3_EDMA1_QM_AXUSER_SECURED_BASE 0x1000007FFC7DAB00ull +#define DCORE3_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define DCORE3_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmDCORE3_EDMA1_QM_AXUSER_NONSECURED_BASE 0x1000007FFC7DAB80ull +#define DCORE3_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define DCORE3_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmDCORE3_EDMA1_QM_DBG_HBW_BASE 0x1000007FFC7DAC00ull +#define DCORE3_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_EDMA1_QM_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_EDMA1_QM_DBG_LBW_BASE 0x1000007FFC7DAC80ull +#define DCORE3_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_EDMA1_QM_DBG_LBW_SECTION 0x1000 + +#define mmDCORE3_EDMA1_QM_CGM_BASE 0x1000007FFC7DAD80ull +#define DCORE3_EDMA1_QM_CGM_MAX_OFFSET 0xC000 +#define DCORE3_EDMA1_QM_CGM_SECTION 0x1000 + +#define mmDCORE3_EDMA1_QM_SPECIAL_BASE 0x1000007FFC7DAE80ull +#define DCORE3_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_EDMA1_QM_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_EDMA1_CORE_BASE 0x1000007FFC7DB000ull +#define DCORE3_EDMA1_CORE_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_CORE_SECTION 0x8000 + +#define mmDCORE3_EDMA1_CORE_CTX_AXUSER_BASE 0x1000007FFC7DB800ull +#define DCORE3_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000 + +#define mmDCORE3_EDMA1_CORE_CTX_BASE 0x1000007FFC7DB860ull +#define DCORE3_EDMA1_CORE_CTX_MAX_OFFSET 0x9000 +#define DCORE3_EDMA1_CORE_CTX_SECTION 0x5A00 + +#define mmDCORE3_EDMA1_CORE_KDMA_CGM_BASE 0x1000007FFC7DBE00ull +#define DCORE3_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define DCORE3_EDMA1_CORE_KDMA_CGM_SECTION 0x8000 + +#define mmDCORE3_EDMA1_CORE_SPECIAL_BASE 0x1000007FFC7DBE80ull +#define DCORE3_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_EDMA1_CORE_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC7DC000ull +#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE3_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC7DC200ull +#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE3_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC7DC400ull +#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE3_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC7DC600ull +#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE3_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC7DC800ull +#define DCORE3_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE3_EDMA1_MSTR_IF_AXUSER_BASE 0x1000007FFC7DCA80ull +#define DCORE3_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE3_EDMA1_MSTR_IF_DBG_HBW_BASE 0x1000007FFC7DCB00ull +#define DCORE3_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_EDMA1_MSTR_IF_DBG_LBW_BASE 0x1000007FFC7DCB80ull +#define DCORE3_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE3_EDMA1_MSTR_IF_CORE_HBW_BASE 0x1000007FFC7DCC00ull +#define DCORE3_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE3_EDMA1_MSTR_IF_CORE_LBW_BASE 0x1000007FFC7DCD80ull +#define DCORE3_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE3_EDMA1_MSTR_IF_SPECIAL_BASE 0x1000007FFC7DCE80ull +#define DCORE3_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmDCORE3_DEC0_CMD_BASE 0x1000007FFC7E0000ull +#define DCORE3_DEC0_CMD_MAX_OFFSET 0x1100 +#define DCORE3_DEC0_CMD_SECTION 0x1000 + +#define mmDCORE3_DEC0_VSI_BASE 0x1000007FFC7E1000ull +#define DCORE3_DEC0_VSI_MAX_OFFSET 0x6FC0 +#define DCORE3_DEC0_VSI_SECTION 0x1000 + +#define mmDCORE3_DEC0_L2C_BASE 0x1000007FFC7E2000ull +#define DCORE3_DEC0_L2C_MAX_OFFSET 0x39C0 +#define DCORE3_DEC0_L2C_SECTION 0x1000 + +#define mmDCORE3_VDEC0_BRDG_CTRL_BASE 0x1000007FFC7E3000ull +#define DCORE3_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_BRDG_CTRL_SECTION 0x8000 + +#define mmDCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x1000007FFC7E3800ull +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 + +#define mmDCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x1000007FFC7E3900ull +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 + +#define mmDCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x1000007FFC7E3A00ull +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 + +#define mmDCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x1000007FFC7E3B00ull +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 + +#define mmDCORE3_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x1000007FFC7E3C00ull +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define DCORE3_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 + +#define mmDCORE3_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x1000007FFC7E3E80ull +#define DCORE3_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_VDEC0_CTRL_BASE 0x1000007FFC7E4000ull +#define DCORE3_VDEC0_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_CTRL_SECTION 0xE800 + +#define mmDCORE3_VDEC0_CTRL_SPECIAL_BASE 0x1000007FFC7E4E80ull +#define DCORE3_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_VDEC0_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC7E5000ull +#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE3_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC7E5200ull +#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE3_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC7E5400ull +#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE3_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC7E5600ull +#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE3_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC7E5800ull +#define DCORE3_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE3_VDEC0_MSTR_IF_AXUSER_BASE 0x1000007FFC7E5A80ull +#define DCORE3_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE3_VDEC0_MSTR_IF_DBG_HBW_BASE 0x1000007FFC7E5B00ull +#define DCORE3_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_VDEC0_MSTR_IF_DBG_LBW_BASE 0x1000007FFC7E5B80ull +#define DCORE3_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE3_VDEC0_MSTR_IF_CORE_HBW_BASE 0x1000007FFC7E5C00ull +#define DCORE3_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE3_VDEC0_MSTR_IF_CORE_LBW_BASE 0x1000007FFC7E5D80ull +#define DCORE3_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE3_VDEC0_MSTR_IF_SPECIAL_BASE 0x1000007FFC7E5E80ull +#define DCORE3_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180 + +#define mmDCORE3_DEC1_CMD_BASE 0x1000007FFC7F0000ull +#define DCORE3_DEC1_CMD_MAX_OFFSET 0x1100 +#define DCORE3_DEC1_CMD_SECTION 0x1000 + +#define mmDCORE3_DEC1_VSI_BASE 0x1000007FFC7F1000ull +#define DCORE3_DEC1_VSI_MAX_OFFSET 0x6FC0 +#define DCORE3_DEC1_VSI_SECTION 0x1000 + +#define mmDCORE3_DEC1_L2C_BASE 0x1000007FFC7F2000ull +#define DCORE3_DEC1_L2C_MAX_OFFSET 0x39C0 +#define DCORE3_DEC1_L2C_SECTION 0x1000 + +#define mmDCORE3_VDEC1_BRDG_CTRL_BASE 0x1000007FFC7F3000ull +#define DCORE3_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_BRDG_CTRL_SECTION 0x8000 + +#define mmDCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x1000007FFC7F3800ull +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 + +#define mmDCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x1000007FFC7F3900ull +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 + +#define mmDCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x1000007FFC7F3A00ull +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 + +#define mmDCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x1000007FFC7F3B00ull +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 + +#define mmDCORE3_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x1000007FFC7F3C00ull +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define DCORE3_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 + +#define mmDCORE3_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x1000007FFC7F3E80ull +#define DCORE3_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_VDEC1_CTRL_BASE 0x1000007FFC7F4000ull +#define DCORE3_VDEC1_CTRL_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_CTRL_SECTION 0xE800 + +#define mmDCORE3_VDEC1_CTRL_SPECIAL_BASE 0x1000007FFC7F4E80ull +#define DCORE3_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_VDEC1_CTRL_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFC7F5000ull +#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmDCORE3_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFC7F5200ull +#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmDCORE3_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFC7F5400ull +#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmDCORE3_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFC7F5600ull +#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define DCORE3_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmDCORE3_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFC7F5800ull +#define DCORE3_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define DCORE3_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmDCORE3_VDEC1_MSTR_IF_AXUSER_BASE 0x1000007FFC7F5A80ull +#define DCORE3_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define DCORE3_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmDCORE3_VDEC1_MSTR_IF_DBG_HBW_BASE 0x1000007FFC7F5B00ull +#define DCORE3_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define DCORE3_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmDCORE3_VDEC1_MSTR_IF_DBG_LBW_BASE 0x1000007FFC7F5B80ull +#define DCORE3_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define DCORE3_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmDCORE3_VDEC1_MSTR_IF_CORE_HBW_BASE 0x1000007FFC7F5C00ull +#define DCORE3_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define DCORE3_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmDCORE3_VDEC1_MSTR_IF_CORE_LBW_BASE 0x1000007FFC7F5D80ull +#define DCORE3_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define DCORE3_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmDCORE3_VDEC1_MSTR_IF_SPECIAL_BASE 0x1000007FFC7F5E80ull +#define DCORE3_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180 + +#define mmGIC_BASE 0x1000007FFC800000ull +#define GIC_MAX_OFFSET 0x10000 +#define GIC_SECTION 0x401000 + +#define mmPCIE_WRAP_BASE 0x1000007FFCC01000ull +#define PCIE_WRAP_MAX_OFFSET 0x1000 +#define PCIE_WRAP_SECTION 0xE800 + +#define mmPCIE_WRAP_SPECIAL_BASE 0x1000007FFCC01E80ull +#define PCIE_WRAP_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_WRAP_SPECIAL_SECTION 0x1800 + +#define mmPCIE_DBI_BASE 0x1000007FFCC02000ull +#define PCIE_DBI_MAX_OFFSET 0xC040 +#define PCIE_DBI_SECTION 0x2000 + +#define mmPCIE_CORE_BASE 0x1000007FFCC04000ull +#define PCIE_CORE_MAX_OFFSET 0x1000 +#define PCIE_CORE_SECTION 0xE800 + +#define mmPCIE_CORE_SPECIAL_BASE 0x1000007FFCC04E80ull +#define PCIE_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_CORE_SPECIAL_SECTION 0x2180 + +#define mmPCIE_AUX_BASE 0x1000007FFCC07000ull +#define PCIE_AUX_MAX_OFFSET 0x1000 +#define PCIE_AUX_SECTION 0xE800 + +#define mmPCIE_AUX_SPECIAL_BASE 0x1000007FFCC07E80ull +#define PCIE_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_AUX_SPECIAL_SECTION 0x8180 + +#define mmPCIE_PHY_BASE 0x1000007FFCC10000ull +#define PCIE_PHY_MAX_OFFSET 0x1000 +#define PCIE_PHY_SECTION 0xE800 + +#define mmPCIE_PHY_SPECIAL_BASE 0x1000007FFCC10E80ull +#define PCIE_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_PHY_SPECIAL_SECTION 0x2180 + +#define mmPCIE_MSI_BASE 0x1000007FFCC13000ull +#define PCIE_MSI_MAX_OFFSET 0x8000 +#define PCIE_MSI_SECTION 0x1000 + +#define mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCC14000ull +#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmPCIE_ELBI_RR_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCC14200ull +#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCC14400ull +#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmPCIE_ELBI_RR_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCC14600ull +#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PCIE_ELBI_RR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmPCIE_ELBI_RR_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCC14800ull +#define PCIE_ELBI_RR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PCIE_ELBI_RR_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmPCIE_ELBI_RR_MSTR_IF_AXUSER_BASE 0x1000007FFCC14A80ull +#define PCIE_ELBI_RR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PCIE_ELBI_RR_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmPCIE_ELBI_RR_MSTR_IF_DBG_HBW_BASE 0x1000007FFCC14B00ull +#define PCIE_ELBI_RR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PCIE_ELBI_RR_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmPCIE_ELBI_RR_MSTR_IF_DBG_LBW_BASE 0x1000007FFCC14B80ull +#define PCIE_ELBI_RR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PCIE_ELBI_RR_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmPCIE_ELBI_RR_MSTR_IF_CORE_HBW_BASE 0x1000007FFCC14C00ull +#define PCIE_ELBI_RR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PCIE_ELBI_RR_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmPCIE_ELBI_RR_MSTR_IF_CORE_LBW_BASE 0x1000007FFCC14D80ull +#define PCIE_ELBI_RR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PCIE_ELBI_RR_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmPCIE_ELBI_RR_MSTR_IF_SPECIAL_BASE 0x1000007FFCC14E80ull +#define PCIE_ELBI_RR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_ELBI_RR_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCC15000ull +#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmPCIE_MSTR_RR_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCC15200ull +#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCC15400ull +#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmPCIE_MSTR_RR_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCC15600ull +#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PCIE_MSTR_RR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmPCIE_MSTR_RR_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCC15800ull +#define PCIE_MSTR_RR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PCIE_MSTR_RR_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmPCIE_MSTR_RR_MSTR_IF_AXUSER_BASE 0x1000007FFCC15A80ull +#define PCIE_MSTR_RR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PCIE_MSTR_RR_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmPCIE_MSTR_RR_MSTR_IF_DBG_HBW_BASE 0x1000007FFCC15B00ull +#define PCIE_MSTR_RR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PCIE_MSTR_RR_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmPCIE_MSTR_RR_MSTR_IF_DBG_LBW_BASE 0x1000007FFCC15B80ull +#define PCIE_MSTR_RR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PCIE_MSTR_RR_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmPCIE_MSTR_RR_MSTR_IF_CORE_HBW_BASE 0x1000007FFCC15C00ull +#define PCIE_MSTR_RR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PCIE_MSTR_RR_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmPCIE_MSTR_RR_MSTR_IF_CORE_LBW_BASE 0x1000007FFCC15D80ull +#define PCIE_MSTR_RR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PCIE_MSTR_RR_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmPCIE_MSTR_RR_MSTR_IF_SPECIAL_BASE 0x1000007FFCC15E80ull +#define PCIE_MSTR_RR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_MSTR_RR_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCC16000ull +#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmPCIE_LBW_RR_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCC16200ull +#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCC16400ull +#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmPCIE_LBW_RR_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCC16600ull +#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PCIE_LBW_RR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmPCIE_LBW_RR_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCC16800ull +#define PCIE_LBW_RR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PCIE_LBW_RR_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmPCIE_LBW_RR_MSTR_IF_AXUSER_BASE 0x1000007FFCC16A80ull +#define PCIE_LBW_RR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PCIE_LBW_RR_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmPCIE_LBW_RR_MSTR_IF_DBG_HBW_BASE 0x1000007FFCC16B00ull +#define PCIE_LBW_RR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PCIE_LBW_RR_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmPCIE_LBW_RR_MSTR_IF_DBG_LBW_BASE 0x1000007FFCC16B80ull +#define PCIE_LBW_RR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PCIE_LBW_RR_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmPCIE_LBW_RR_MSTR_IF_CORE_HBW_BASE 0x1000007FFCC16C00ull +#define PCIE_LBW_RR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PCIE_LBW_RR_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmPCIE_LBW_RR_MSTR_IF_CORE_LBW_BASE 0x1000007FFCC16D80ull +#define PCIE_LBW_RR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PCIE_LBW_RR_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmPCIE_LBW_RR_MSTR_IF_SPECIAL_BASE 0x1000007FFCC16E80ull +#define PCIE_LBW_RR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_LBW_RR_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmPCIE_MSIX_BASE 0x1000007FFCC17000ull +#define PCIE_MSIX_MAX_OFFSET 0x4000 +#define PCIE_MSIX_SECTION 0x29000 + +#define mmPSOC_I2C_M0_BASE 0x1000007FFCC40000ull +#define PSOC_I2C_M0_MAX_OFFSET 0x1000 +#define PSOC_I2C_M0_SECTION 0x1000 + +#define mmPSOC_I2C_M1_BASE 0x1000007FFCC41000ull +#define PSOC_I2C_M1_MAX_OFFSET 0x1000 +#define PSOC_I2C_M1_SECTION 0x1000 + +#define mmPSOC_I2C_S_BASE 0x1000007FFCC42000ull +#define PSOC_I2C_S_MAX_OFFSET 0x1000 +#define PSOC_I2C_S_SECTION 0x1000 + +#define mmPSOC_SPI_BASE 0x1000007FFCC43000ull +#define PSOC_SPI_MAX_OFFSET 0x1000 +#define PSOC_SPI_SECTION 0x1000 + +#define mmPSOC_QSPI_BASE 0x1000007FFCC44000ull +#define PSOC_QSPI_MAX_OFFSET 0x1000 +#define PSOC_QSPI_SECTION 0x1000 + +#define mmPSOC_UART_0_BASE 0x1000007FFCC45000ull +#define PSOC_UART_0_MAX_OFFSET 0x1000 +#define PSOC_UART_0_SECTION 0x1000 + +#define mmPSOC_UART_1_BASE 0x1000007FFCC46000ull +#define PSOC_UART_1_MAX_OFFSET 0x1000 +#define PSOC_UART_1_SECTION 0x1000 + +#define mmPSOC_TIMER_BASE 0x1000007FFCC47000ull +#define PSOC_TIMER_MAX_OFFSET 0x1000 +#define PSOC_TIMER_SECTION 0x1000 + +#define mmPSOC_WDOG_BASE 0x1000007FFCC48000ull +#define PSOC_WDOG_MAX_OFFSET 0x1000 +#define PSOC_WDOG_SECTION 0x1000 + +#define mmPSOC_TIMESTAMP_BASE 0x1000007FFCC49000ull +#define PSOC_TIMESTAMP_MAX_OFFSET 0x1000 +#define PSOC_TIMESTAMP_SECTION 0x1000 + +#define mmPSOC_EFUSE_BASE 0x1000007FFCC4A000ull +#define PSOC_EFUSE_MAX_OFFSET 0x1000 +#define PSOC_EFUSE_SECTION 0xE800 + +#define mmPSOC_EFUSE_SPECIAL_BASE 0x1000007FFCC4AE80ull +#define PSOC_EFUSE_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_EFUSE_SPECIAL_SECTION 0x1800 + +#define mmPSOC_GLOBAL_CONF_BASE 0x1000007FFCC4B000ull +#define PSOC_GLOBAL_CONF_MAX_OFFSET 0x1000 +#define PSOC_GLOBAL_CONF_SECTION 0xE800 + +#define mmPSOC_GLOBAL_CONF_SPECIAL_BASE 0x1000007FFCC4BE80ull +#define PSOC_GLOBAL_CONF_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_GLOBAL_CONF_SPECIAL_SECTION 0x1800 + +#define mmPSOC_GPIO0_BASE 0x1000007FFCC4C000ull +#define PSOC_GPIO0_MAX_OFFSET 0x1000 +#define PSOC_GPIO0_SECTION 0x1000 + +#define mmPSOC_GPIO1_BASE 0x1000007FFCC4D000ull +#define PSOC_GPIO1_MAX_OFFSET 0x1000 +#define PSOC_GPIO1_SECTION 0x1000 + +#define mmPSOC_BTL_BASE 0x1000007FFCC4E000ull +#define PSOC_BTL_MAX_OFFSET 0x1000 +#define PSOC_BTL_SECTION 0xE800 + +#define mmPSOC_BTL_SPECIAL_BASE 0x1000007FFCC4EE80ull +#define PSOC_BTL_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_BTL_SPECIAL_SECTION 0x1800 + +#define mmPSOC_CS_TRACE_BASE 0x1000007FFCC4F000ull +#define PSOC_CS_TRACE_MAX_OFFSET 0x1000 +#define PSOC_CS_TRACE_SECTION 0xE800 + +#define mmPSOC_CS_TRACE_SPECIAL_BASE 0x1000007FFCC4FE80ull +#define PSOC_CS_TRACE_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_CS_TRACE_SPECIAL_SECTION 0x1800 + +#define mmPSOC_GPIO2_BASE 0x1000007FFCC50000ull +#define PSOC_GPIO2_MAX_OFFSET 0x1000 +#define PSOC_GPIO2_SECTION 0x1000 + +#define mmPSOC_GPIO3_BASE 0x1000007FFCC51000ull +#define PSOC_GPIO3_MAX_OFFSET 0x1000 +#define PSOC_GPIO3_SECTION 0x2000 + +#define mmPSOC_DFT_EFUSE_BASE 0x1000007FFCC53000ull +#define PSOC_DFT_EFUSE_MAX_OFFSET 0x1000 +#define PSOC_DFT_EFUSE_SECTION 0xE800 + +#define mmPSOC_DFT_EFUSE_SPECIAL_BASE 0x1000007FFCC53E80ull +#define PSOC_DFT_EFUSE_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_DFT_EFUSE_SPECIAL_SECTION 0x1800 + +#define mmPSOC_RPM_0_BASE 0x1000007FFCC54000ull +#define PSOC_RPM_0_MAX_OFFSET 0x1000 +#define PSOC_RPM_0_SECTION 0xE800 + +#define mmPSOC_RPM_0_SPECIAL_BASE 0x1000007FFCC54E80ull +#define PSOC_RPM_0_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_RPM_0_SPECIAL_SECTION 0x1800 + +#define mmPSOC_RPM_1_BASE 0x1000007FFCC55000ull +#define PSOC_RPM_1_MAX_OFFSET 0x1000 +#define PSOC_RPM_1_SECTION 0xE800 + +#define mmPSOC_RPM_1_SPECIAL_BASE 0x1000007FFCC55E80ull +#define PSOC_RPM_1_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_RPM_1_SPECIAL_SECTION 0x1800 + +#define mmPSOC_GPIO4_BASE 0x1000007FFCC56000ull +#define PSOC_GPIO4_MAX_OFFSET 0x1000 +#define PSOC_GPIO4_SECTION 0x1000 + +#define mmPSOC_GPIO5_BASE 0x1000007FFCC57000ull +#define PSOC_GPIO5_MAX_OFFSET 0x1000 +#define PSOC_GPIO5_SECTION 0x1000 + +#define mmPSOC_PID_BASE 0x1000007FFCC58000ull +#define PSOC_PID_MAX_OFFSET 0x1000 +#define PSOC_PID_SECTION 0xE800 + +#define mmPSOC_PID_SPECIAL_BASE 0x1000007FFCC58E80ull +#define PSOC_PID_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_PID_SPECIAL_SECTION 0x1800 + +#define mmPSOC_ARC0_CFG_BASE 0x1000007FFCC59000ull +#define PSOC_ARC0_CFG_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CFG_SECTION 0xE800 + +#define mmPSOC_ARC0_CFG_SPECIAL_BASE 0x1000007FFCC59E80ull +#define PSOC_ARC0_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_ARC0_CFG_SPECIAL_SECTION 0x1800 + +#define mmPSOC_ARC0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCC5A000ull +#define PSOC_ARC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PSOC_ARC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmPSOC_ARC0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCC5A200ull +#define PSOC_ARC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PSOC_ARC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmPSOC_ARC0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCC5A400ull +#define PSOC_ARC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PSOC_ARC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmPSOC_ARC0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCC5A600ull +#define PSOC_ARC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PSOC_ARC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmPSOC_ARC0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCC5A800ull +#define PSOC_ARC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PSOC_ARC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmPSOC_ARC0_MSTR_IF_AXUSER_BASE 0x1000007FFCC5AA80ull +#define PSOC_ARC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PSOC_ARC0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmPSOC_ARC0_MSTR_IF_DBG_HBW_BASE 0x1000007FFCC5AB00ull +#define PSOC_ARC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PSOC_ARC0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmPSOC_ARC0_MSTR_IF_DBG_LBW_BASE 0x1000007FFCC5AB80ull +#define PSOC_ARC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PSOC_ARC0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmPSOC_ARC0_MSTR_IF_CORE_HBW_BASE 0x1000007FFCC5AC00ull +#define PSOC_ARC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PSOC_ARC0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmPSOC_ARC0_MSTR_IF_CORE_LBW_BASE 0x1000007FFCC5AD80ull +#define PSOC_ARC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PSOC_ARC0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmPSOC_ARC0_MSTR_IF_SPECIAL_BASE 0x1000007FFCC5AE80ull +#define PSOC_ARC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_ARC0_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmPSOC_ARC0_AUX_BASE 0x1000007FFCC5B000ull +#define PSOC_ARC0_AUX_MAX_OFFSET 0x1000 +#define PSOC_ARC0_AUX_SECTION 0xE800 + +#define mmPSOC_ARC0_AUX_SPECIAL_BASE 0x1000007FFCC5BE80ull +#define PSOC_ARC0_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_ARC0_AUX_SPECIAL_SECTION 0x1800 + +#define mmPSOC_ARC1_CFG_BASE 0x1000007FFCC5C000ull +#define PSOC_ARC1_CFG_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CFG_SECTION 0xE800 + +#define mmPSOC_ARC1_CFG_SPECIAL_BASE 0x1000007FFCC5CE80ull +#define PSOC_ARC1_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_ARC1_CFG_SPECIAL_SECTION 0x1800 + +#define mmPSOC_ARC1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCC5D000ull +#define PSOC_ARC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PSOC_ARC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmPSOC_ARC1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCC5D200ull +#define PSOC_ARC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PSOC_ARC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmPSOC_ARC1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCC5D400ull +#define PSOC_ARC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PSOC_ARC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmPSOC_ARC1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCC5D600ull +#define PSOC_ARC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PSOC_ARC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmPSOC_ARC1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCC5D800ull +#define PSOC_ARC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PSOC_ARC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmPSOC_ARC1_MSTR_IF_AXUSER_BASE 0x1000007FFCC5DA80ull +#define PSOC_ARC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PSOC_ARC1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmPSOC_ARC1_MSTR_IF_DBG_HBW_BASE 0x1000007FFCC5DB00ull +#define PSOC_ARC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PSOC_ARC1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmPSOC_ARC1_MSTR_IF_DBG_LBW_BASE 0x1000007FFCC5DB80ull +#define PSOC_ARC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PSOC_ARC1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmPSOC_ARC1_MSTR_IF_CORE_HBW_BASE 0x1000007FFCC5DC00ull +#define PSOC_ARC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PSOC_ARC1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmPSOC_ARC1_MSTR_IF_CORE_LBW_BASE 0x1000007FFCC5DD80ull +#define PSOC_ARC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PSOC_ARC1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmPSOC_ARC1_MSTR_IF_SPECIAL_BASE 0x1000007FFCC5DE80ull +#define PSOC_ARC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_ARC1_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmPSOC_ARC1_AUX_BASE 0x1000007FFCC5E000ull +#define PSOC_ARC1_AUX_MAX_OFFSET 0x1000 +#define PSOC_ARC1_AUX_SECTION 0xE800 + +#define mmPSOC_ARC1_AUX_SPECIAL_BASE 0x1000007FFCC5EE80ull +#define PSOC_ARC1_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_ARC1_AUX_SPECIAL_SECTION 0x1180 + +#define mmPSOC_SECURITY_BASE 0x1000007FFCC60000ull +#define PSOC_SECURITY_MAX_OFFSET 0x1000 +#define PSOC_SECURITY_SECTION 0xE800 + +#define mmPSOC_SECURITY_SPECIAL_BASE 0x1000007FFCC60E80ull +#define PSOC_SECURITY_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_SECURITY_SPECIAL_SECTION 0x1800 + +#define mmJT_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCC61000ull +#define JT_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define JT_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmJT_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCC61200ull +#define JT_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define JT_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmJT_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCC61400ull +#define JT_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define JT_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmJT_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCC61600ull +#define JT_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define JT_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmJT_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCC61800ull +#define JT_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define JT_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmJT_MSTR_IF_AXUSER_BASE 0x1000007FFCC61A80ull +#define JT_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define JT_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmJT_MSTR_IF_DBG_HBW_BASE 0x1000007FFCC61B00ull +#define JT_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define JT_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmJT_MSTR_IF_DBG_LBW_BASE 0x1000007FFCC61B80ull +#define JT_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define JT_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmJT_MSTR_IF_CORE_HBW_BASE 0x1000007FFCC61C00ull +#define JT_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define JT_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmJT_MSTR_IF_CORE_LBW_BASE 0x1000007FFCC61D80ull +#define JT_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define JT_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmJT_MSTR_IF_SPECIAL_BASE 0x1000007FFCC61E80ull +#define JT_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define JT_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmSMI_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCC62000ull +#define SMI_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SMI_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmSMI_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCC62200ull +#define SMI_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SMI_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmSMI_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCC62400ull +#define SMI_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SMI_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmSMI_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCC62600ull +#define SMI_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SMI_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmSMI_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCC62800ull +#define SMI_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SMI_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmSMI_MSTR_IF_AXUSER_BASE 0x1000007FFCC62A80ull +#define SMI_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SMI_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmSMI_MSTR_IF_DBG_HBW_BASE 0x1000007FFCC62B00ull +#define SMI_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SMI_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmSMI_MSTR_IF_DBG_LBW_BASE 0x1000007FFCC62B80ull +#define SMI_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SMI_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmSMI_MSTR_IF_CORE_HBW_BASE 0x1000007FFCC62C00ull +#define SMI_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SMI_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmSMI_MSTR_IF_CORE_LBW_BASE 0x1000007FFCC62D80ull +#define SMI_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SMI_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmSMI_MSTR_IF_SPECIAL_BASE 0x1000007FFCC62E80ull +#define SMI_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SMI_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmI2C_S_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCC63000ull +#define I2C_S_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define I2C_S_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmI2C_S_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCC63200ull +#define I2C_S_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define I2C_S_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmI2C_S_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCC63400ull +#define I2C_S_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define I2C_S_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmI2C_S_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCC63600ull +#define I2C_S_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define I2C_S_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmI2C_S_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCC63800ull +#define I2C_S_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define I2C_S_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmI2C_S_MSTR_IF_AXUSER_BASE 0x1000007FFCC63A80ull +#define I2C_S_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define I2C_S_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmI2C_S_MSTR_IF_DBG_HBW_BASE 0x1000007FFCC63B00ull +#define I2C_S_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define I2C_S_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmI2C_S_MSTR_IF_DBG_LBW_BASE 0x1000007FFCC63B80ull +#define I2C_S_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define I2C_S_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmI2C_S_MSTR_IF_CORE_HBW_BASE 0x1000007FFCC63C00ull +#define I2C_S_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define I2C_S_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmI2C_S_MSTR_IF_CORE_LBW_BASE 0x1000007FFCC63D80ull +#define I2C_S_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define I2C_S_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmI2C_S_MSTR_IF_SPECIAL_BASE 0x1000007FFCC63E80ull +#define I2C_S_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define I2C_S_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmPSOC_SVID0_BASE 0x1000007FFCC64000ull +#define PSOC_SVID0_MAX_OFFSET 0x1000 +#define PSOC_SVID0_SECTION 0xE800 + +#define mmPSOC_SVID0_SPECIAL_BASE 0x1000007FFCC64E80ull +#define PSOC_SVID0_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_SVID0_SPECIAL_SECTION 0x1800 + +#define mmPSOC_SVID1_BASE 0x1000007FFCC65000ull +#define PSOC_SVID1_MAX_OFFSET 0x1000 +#define PSOC_SVID1_SECTION 0xE800 + +#define mmPSOC_SVID1_SPECIAL_BASE 0x1000007FFCC65E80ull +#define PSOC_SVID1_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_SVID1_SPECIAL_SECTION 0x1800 + +#define mmPSOC_SVID2_BASE 0x1000007FFCC66000ull +#define PSOC_SVID2_MAX_OFFSET 0x1000 +#define PSOC_SVID2_SECTION 0xE800 + +#define mmPSOC_SVID2_SPECIAL_BASE 0x1000007FFCC66E80ull +#define PSOC_SVID2_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_SVID2_SPECIAL_SECTION 0x5180 + +#define mmPSOC_CPU_PLL_CTRL_BASE 0x1000007FFCC6D000ull +#define PSOC_CPU_PLL_CTRL_MAX_OFFSET 0x3540 +#define PSOC_CPU_PLL_CTRL_SECTION 0x3600 + +#define mmPSOC_CPU_PLL_ASIF_SLV_BASE 0x1000007FFCC6D360ull +#define PSOC_CPU_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define PSOC_CPU_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmPSOC_CPU_PLL_DIV_0_RLX_BASE 0x1000007FFCC6D400ull +#define PSOC_CPU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define PSOC_CPU_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmPSOC_CPU_PLL_DIV_1_RLX_BASE 0x1000007FFCC6D800ull +#define PSOC_CPU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define PSOC_CPU_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmPSOC_CPU_PLL_DIV_2_RLX_BASE 0x1000007FFCC6DA00ull +#define PSOC_CPU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define PSOC_CPU_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmPSOC_CPU_PLL_DIV_3_RLX_BASE 0x1000007FFCC6DC00ull +#define PSOC_CPU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define PSOC_CPU_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmPSOC_CPU_PLL_SPECIAL_BASE 0x1000007FFCC6DE80ull +#define PSOC_CPU_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_CPU_PLL_SPECIAL_SECTION 0x1800 + +#define mmPSOC_VID_PLL_CTRL_BASE 0x1000007FFCC6E000ull +#define PSOC_VID_PLL_CTRL_MAX_OFFSET 0x3540 +#define PSOC_VID_PLL_CTRL_SECTION 0x3600 + +#define mmPSOC_VID_PLL_ASIF_SLV_BASE 0x1000007FFCC6E360ull +#define PSOC_VID_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define PSOC_VID_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmPSOC_VID_PLL_DIV_0_RLX_BASE 0x1000007FFCC6E400ull +#define PSOC_VID_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define PSOC_VID_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmPSOC_VID_PLL_DIV_1_RLX_BASE 0x1000007FFCC6E800ull +#define PSOC_VID_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define PSOC_VID_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmPSOC_VID_PLL_DIV_2_RLX_BASE 0x1000007FFCC6EA00ull +#define PSOC_VID_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define PSOC_VID_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmPSOC_VID_PLL_DIV_3_RLX_BASE 0x1000007FFCC6EC00ull +#define PSOC_VID_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define PSOC_VID_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmPSOC_VID_PLL_SPECIAL_BASE 0x1000007FFCC6EE80ull +#define PSOC_VID_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_VID_PLL_SPECIAL_SECTION 0x5180 + +#define mmPSOC_RESET_CONF_BASE 0x1000007FFCC74000ull +#define PSOC_RESET_CONF_MAX_OFFSET 0x1000 +#define PSOC_RESET_CONF_SECTION 0xE800 + +#define mmPSOC_RESET_CONF_SPECIAL_BASE 0x1000007FFCC74E80ull +#define PSOC_RESET_CONF_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_RESET_CONF_SPECIAL_SECTION 0x1800 + +#define mmPSOC_DFT_APB_BASE 0x1000007FFCC75000ull +#define PSOC_DFT_APB_MAX_OFFSET 0x8000 +#define PSOC_DFT_APB_SECTION 0x1000 + +#define mmPSOC_AVS0_BASE 0x1000007FFCC76000ull +#define PSOC_AVS0_MAX_OFFSET 0x1000 +#define PSOC_AVS0_SECTION 0xE800 + +#define mmPSOC_AVS0_SPECIAL_BASE 0x1000007FFCC76E80ull +#define PSOC_AVS0_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_AVS0_SPECIAL_SECTION 0x1800 + +#define mmPSOC_AVS1_BASE 0x1000007FFCC77000ull +#define PSOC_AVS1_MAX_OFFSET 0x1000 +#define PSOC_AVS1_SECTION 0xE800 + +#define mmPSOC_AVS1_SPECIAL_BASE 0x1000007FFCC77E80ull +#define PSOC_AVS1_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_AVS1_SPECIAL_SECTION 0x1800 + +#define mmPSOC_AVS2_BASE 0x1000007FFCC78000ull +#define PSOC_AVS2_MAX_OFFSET 0x1000 +#define PSOC_AVS2_SECTION 0xE800 + +#define mmPSOC_AVS2_SPECIAL_BASE 0x1000007FFCC78E80ull +#define PSOC_AVS2_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_AVS2_SPECIAL_SECTION 0x1800 + +#define mmPSOC_PWM0_BASE 0x1000007FFCC79000ull +#define PSOC_PWM0_MAX_OFFSET 0x1000 +#define PSOC_PWM0_SECTION 0xE800 + +#define mmPSOC_PWM0_SPECIAL_BASE 0x1000007FFCC79E80ull +#define PSOC_PWM0_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_PWM0_SPECIAL_SECTION 0x1800 + +#define mmPSOC_PWM1_BASE 0x1000007FFCC7A000ull +#define PSOC_PWM1_MAX_OFFSET 0x1000 +#define PSOC_PWM1_SECTION 0xE800 + +#define mmPSOC_PWM1_SPECIAL_BASE 0x1000007FFCC7AE80ull +#define PSOC_PWM1_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_PWM1_SPECIAL_SECTION 0x1800 + +#define mmSVID0_AC_BASE 0x1000007FFCC7B000ull +#define SVID0_AC_MAX_OFFSET 0x1000 +#define SVID0_AC_SECTION 0xE800 + +#define mmSVID0_AC_SPECIAL_BASE 0x1000007FFCC7BE80ull +#define SVID0_AC_SPECIAL_MAX_OFFSET 0x1800 +#define SVID0_AC_SPECIAL_SECTION 0x1800 + +#define mmSVID1_AC_BASE 0x1000007FFCC7C000ull +#define SVID1_AC_MAX_OFFSET 0x1000 +#define SVID1_AC_SECTION 0xE800 + +#define mmSVID1_AC_SPECIAL_BASE 0x1000007FFCC7CE80ull +#define SVID1_AC_SPECIAL_MAX_OFFSET 0x1800 +#define SVID1_AC_SPECIAL_SECTION 0x1800 + +#define mmSVID2_AC_BASE 0x1000007FFCC7D000ull +#define SVID2_AC_MAX_OFFSET 0x1000 +#define SVID2_AC_SECTION 0xE800 + +#define mmSVID2_AC_SPECIAL_BASE 0x1000007FFCC7DE80ull +#define SVID2_AC_SPECIAL_MAX_OFFSET 0x1800 +#define SVID2_AC_SPECIAL_SECTION 0x1180 + +#define mmPSOC_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCC7F000ull +#define PSOC_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PSOC_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmPSOC_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCC7F200ull +#define PSOC_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PSOC_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmPSOC_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCC7F400ull +#define PSOC_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PSOC_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmPSOC_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCC7F600ull +#define PSOC_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PSOC_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmPSOC_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCC7F800ull +#define PSOC_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PSOC_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmPSOC_MSTR_IF_AXUSER_BASE 0x1000007FFCC7FA80ull +#define PSOC_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PSOC_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmPSOC_MSTR_IF_DBG_HBW_BASE 0x1000007FFCC7FB00ull +#define PSOC_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PSOC_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmPSOC_MSTR_IF_DBG_LBW_BASE 0x1000007FFCC7FB80ull +#define PSOC_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PSOC_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmPSOC_MSTR_IF_CORE_HBW_BASE 0x1000007FFCC7FC00ull +#define PSOC_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PSOC_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmPSOC_MSTR_IF_CORE_LBW_BASE 0x1000007FFCC7FD80ull +#define PSOC_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PSOC_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmPSOC_MSTR_IF_SPECIAL_BASE 0x1000007FFCC7FE80ull +#define PSOC_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PSOC_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmPDMA0_QM_ARC_DCCM_BASE 0x1000007FFCC80000ull +#define PDMA0_QM_ARC_DCCM_MAX_OFFSET 0x4000 +#define PDMA0_QM_ARC_DCCM_SECTION 0x8000 + +#define mmPDMA0_QM_ARC_AUX_BASE 0x1000007FFCC88000ull +#define PDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define PDMA0_QM_ARC_AUX_SECTION 0xE800 + +#define mmPDMA0_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFCC88E80ull +#define PDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmPDMA0_QM_BASE 0x1000007FFCC8A000ull +#define PDMA0_QM_MAX_OFFSET 0x1000 +#define PDMA0_QM_SECTION 0x9000 + +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFCC8A900ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFCC8A908ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFCC8A910ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFCC8A918ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFCC8A920ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFCC8A928ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFCC8A930ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFCC8A938ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFCC8A940ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFCC8A948ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFCC8A950ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFCC8A958ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFCC8A960ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFCC8A968ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFCC8A970ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmPDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFCC8A978ull +#define PDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define PDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmPDMA0_QM_AXUSER_SECURED_BASE 0x1000007FFCC8AB00ull +#define PDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define PDMA0_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmPDMA0_QM_AXUSER_NONSECURED_BASE 0x1000007FFCC8AB80ull +#define PDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define PDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmPDMA0_QM_DBG_HBW_BASE 0x1000007FFCC8AC00ull +#define PDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define PDMA0_QM_DBG_HBW_SECTION 0x8000 + +#define mmPDMA0_QM_DBG_LBW_BASE 0x1000007FFCC8AC80ull +#define PDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define PDMA0_QM_DBG_LBW_SECTION 0x1000 + +#define mmPDMA0_QM_CGM_BASE 0x1000007FFCC8AD80ull +#define PDMA0_QM_CGM_MAX_OFFSET 0xC000 +#define PDMA0_QM_CGM_SECTION 0x1000 + +#define mmPDMA0_QM_SPECIAL_BASE 0x1000007FFCC8AE80ull +#define PDMA0_QM_SPECIAL_MAX_OFFSET 0x1800 +#define PDMA0_QM_SPECIAL_SECTION 0x1800 + +#define mmPDMA0_CORE_BASE 0x1000007FFCC8B000ull +#define PDMA0_CORE_MAX_OFFSET 0x1000 +#define PDMA0_CORE_SECTION 0x8000 + +#define mmPDMA0_CORE_CTX_AXUSER_BASE 0x1000007FFCC8B800ull +#define PDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define PDMA0_CORE_CTX_AXUSER_SECTION 0x6000 + +#define mmPDMA0_CORE_CTX_BASE 0x1000007FFCC8B860ull +#define PDMA0_CORE_CTX_MAX_OFFSET 0x9000 +#define PDMA0_CORE_CTX_SECTION 0x5A00 + +#define mmPDMA0_CORE_KDMA_CGM_BASE 0x1000007FFCC8BE00ull +#define PDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define PDMA0_CORE_KDMA_CGM_SECTION 0x8000 + +#define mmPDMA0_CORE_SPECIAL_BASE 0x1000007FFCC8BE80ull +#define PDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PDMA0_CORE_SPECIAL_SECTION 0x1800 + +#define mmPDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCC8C000ull +#define PDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmPDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCC8C200ull +#define PDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmPDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCC8C400ull +#define PDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmPDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCC8C600ull +#define PDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmPDMA0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCC8C800ull +#define PDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmPDMA0_MSTR_IF_AXUSER_BASE 0x1000007FFCC8CA80ull +#define PDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PDMA0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmPDMA0_MSTR_IF_DBG_HBW_BASE 0x1000007FFCC8CB00ull +#define PDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmPDMA0_MSTR_IF_DBG_LBW_BASE 0x1000007FFCC8CB80ull +#define PDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmPDMA0_MSTR_IF_CORE_HBW_BASE 0x1000007FFCC8CC00ull +#define PDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmPDMA0_MSTR_IF_CORE_LBW_BASE 0x1000007FFCC8CD80ull +#define PDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmPDMA0_MSTR_IF_SPECIAL_BASE 0x1000007FFCC8CE80ull +#define PDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PDMA0_MSTR_IF_SPECIAL_SECTION 0x3180 + +#define mmPDMA1_QM_ARC_DCCM_BASE 0x1000007FFCC90000ull +#define PDMA1_QM_ARC_DCCM_MAX_OFFSET 0x4000 +#define PDMA1_QM_ARC_DCCM_SECTION 0x8000 + +#define mmPDMA1_QM_ARC_AUX_BASE 0x1000007FFCC98000ull +#define PDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000 +#define PDMA1_QM_ARC_AUX_SECTION 0xE800 + +#define mmPDMA1_QM_ARC_AUX_SPECIAL_BASE 0x1000007FFCC98E80ull +#define PDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 + +#define mmPDMA1_QM_BASE 0x1000007FFCC9A000ull +#define PDMA1_QM_MAX_OFFSET 0x1000 +#define PDMA1_QM_SECTION 0x9000 + +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFCC9A900ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFCC9A908ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFCC9A910ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFCC9A918ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFCC9A920ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFCC9A928ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFCC9A930ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFCC9A938ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFCC9A940ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFCC9A948ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFCC9A950ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFCC9A958ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFCC9A960ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFCC9A968ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFCC9A970ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmPDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFCC9A978ull +#define PDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define PDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmPDMA1_QM_AXUSER_SECURED_BASE 0x1000007FFCC9AB00ull +#define PDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define PDMA1_QM_AXUSER_SECURED_SECTION 0x8000 + +#define mmPDMA1_QM_AXUSER_NONSECURED_BASE 0x1000007FFCC9AB80ull +#define PDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define PDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmPDMA1_QM_DBG_HBW_BASE 0x1000007FFCC9AC00ull +#define PDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800 +#define PDMA1_QM_DBG_HBW_SECTION 0x8000 + +#define mmPDMA1_QM_DBG_LBW_BASE 0x1000007FFCC9AC80ull +#define PDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800 +#define PDMA1_QM_DBG_LBW_SECTION 0x1000 + +#define mmPDMA1_QM_CGM_BASE 0x1000007FFCC9AD80ull +#define PDMA1_QM_CGM_MAX_OFFSET 0xC000 +#define PDMA1_QM_CGM_SECTION 0x1000 + +#define mmPDMA1_QM_SPECIAL_BASE 0x1000007FFCC9AE80ull +#define PDMA1_QM_SPECIAL_MAX_OFFSET 0x1800 +#define PDMA1_QM_SPECIAL_SECTION 0x1800 + +#define mmPDMA1_CORE_BASE 0x1000007FFCC9B000ull +#define PDMA1_CORE_MAX_OFFSET 0x1000 +#define PDMA1_CORE_SECTION 0x8000 + +#define mmPDMA1_CORE_CTX_AXUSER_BASE 0x1000007FFCC9B800ull +#define PDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 +#define PDMA1_CORE_CTX_AXUSER_SECTION 0x6000 + +#define mmPDMA1_CORE_CTX_BASE 0x1000007FFCC9B860ull +#define PDMA1_CORE_CTX_MAX_OFFSET 0x9000 +#define PDMA1_CORE_CTX_SECTION 0x5A00 + +#define mmPDMA1_CORE_KDMA_CGM_BASE 0x1000007FFCC9BE00ull +#define PDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000 +#define PDMA1_CORE_KDMA_CGM_SECTION 0x8000 + +#define mmPDMA1_CORE_SPECIAL_BASE 0x1000007FFCC9BE80ull +#define PDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PDMA1_CORE_SPECIAL_SECTION 0x1800 + +#define mmPDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCC9C000ull +#define PDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmPDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCC9C200ull +#define PDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmPDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCC9C400ull +#define PDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmPDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCC9C600ull +#define PDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmPDMA1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCC9C800ull +#define PDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmPDMA1_MSTR_IF_AXUSER_BASE 0x1000007FFCC9CA80ull +#define PDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PDMA1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmPDMA1_MSTR_IF_DBG_HBW_BASE 0x1000007FFCC9CB00ull +#define PDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmPDMA1_MSTR_IF_DBG_LBW_BASE 0x1000007FFCC9CB80ull +#define PDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmPDMA1_MSTR_IF_CORE_HBW_BASE 0x1000007FFCC9CC00ull +#define PDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmPDMA1_MSTR_IF_CORE_LBW_BASE 0x1000007FFCC9CD80ull +#define PDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmPDMA1_MSTR_IF_SPECIAL_BASE 0x1000007FFCC9CE80ull +#define PDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PDMA1_MSTR_IF_SPECIAL_SECTION 0x23180 + +#define mmCPU_CA53_CFG_BASE 0x1000007FFCCC0000ull +#define CPU_CA53_CFG_MAX_OFFSET 0x1000 +#define CPU_CA53_CFG_SECTION 0xE800 + +#define mmCPU_CA53_CFG_SPECIAL_BASE 0x1000007FFCCC0E80ull +#define CPU_CA53_CFG_SPECIAL_MAX_OFFSET 0x1800 +#define CPU_CA53_CFG_SPECIAL_SECTION 0x1800 + +#define mmCPU_IF_BASE 0x1000007FFCCC1000ull +#define CPU_IF_MAX_OFFSET 0x1000 +#define CPU_IF_SECTION 0xE800 + +#define mmCPU_IF_SPECIAL_BASE 0x1000007FFCCC1E80ull +#define CPU_IF_SPECIAL_MAX_OFFSET 0x1800 +#define CPU_IF_SPECIAL_SECTION 0x1800 + +#define mmCPU_TIMESTAMP_BASE 0x1000007FFCCC2000ull +#define CPU_TIMESTAMP_MAX_OFFSET 0x1000 +#define CPU_TIMESTAMP_SECTION 0x1000 + +#define mmCPU_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCCC3000ull +#define CPU_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define CPU_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmCPU_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCCC3200ull +#define CPU_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define CPU_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmCPU_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCCC3400ull +#define CPU_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define CPU_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmCPU_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCCC3600ull +#define CPU_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define CPU_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmCPU_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCCC3800ull +#define CPU_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define CPU_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmCPU_MSTR_IF_AXUSER_BASE 0x1000007FFCCC3A80ull +#define CPU_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define CPU_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmCPU_MSTR_IF_DBG_HBW_BASE 0x1000007FFCCC3B00ull +#define CPU_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define CPU_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmCPU_MSTR_IF_DBG_LBW_BASE 0x1000007FFCCC3B80ull +#define CPU_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define CPU_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmCPU_MSTR_IF_CORE_HBW_BASE 0x1000007FFCCC3C00ull +#define CPU_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define CPU_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmCPU_MSTR_IF_CORE_LBW_BASE 0x1000007FFCCC3D80ull +#define CPU_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define CPU_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmCPU_MSTR_IF_SPECIAL_BASE 0x1000007FFCCC3E80ull +#define CPU_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define CPU_MSTR_IF_SPECIAL_SECTION 0x3C180 + +#define mmPMMU_HBW_MMU_BASE 0x1000007FFCD00000ull +#define PMMU_HBW_MMU_MAX_OFFSET 0x1000 +#define PMMU_HBW_MMU_SECTION 0xE800 + +#define mmPMMU_HBW_MMU_SPECIAL_BASE 0x1000007FFCD00E80ull +#define PMMU_HBW_MMU_SPECIAL_MAX_OFFSET 0x1800 +#define PMMU_HBW_MMU_SPECIAL_SECTION 0x1800 + +#define mmPMMU_HBW_STLB_BASE 0x1000007FFCD01000ull +#define PMMU_HBW_STLB_MAX_OFFSET 0x1000 +#define PMMU_HBW_STLB_SECTION 0xE800 + +#define mmPMMU_HBW_STLB_SPECIAL_BASE 0x1000007FFCD01E80ull +#define PMMU_HBW_STLB_SPECIAL_MAX_OFFSET 0x1800 +#define PMMU_HBW_STLB_SPECIAL_SECTION 0x1800 + +#define mmPMMU_HBW_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCD02000ull +#define PMMU_HBW_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PMMU_HBW_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmPMMU_HBW_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCD02200ull +#define PMMU_HBW_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PMMU_HBW_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmPMMU_HBW_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCD02400ull +#define PMMU_HBW_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PMMU_HBW_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmPMMU_HBW_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCD02600ull +#define PMMU_HBW_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PMMU_HBW_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmPMMU_HBW_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCD02800ull +#define PMMU_HBW_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PMMU_HBW_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmPMMU_HBW_MSTR_IF_AXUSER_BASE 0x1000007FFCD02A80ull +#define PMMU_HBW_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PMMU_HBW_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmPMMU_HBW_MSTR_IF_DBG_HBW_BASE 0x1000007FFCD02B00ull +#define PMMU_HBW_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PMMU_HBW_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmPMMU_HBW_MSTR_IF_DBG_LBW_BASE 0x1000007FFCD02B80ull +#define PMMU_HBW_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PMMU_HBW_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmPMMU_HBW_MSTR_IF_CORE_HBW_BASE 0x1000007FFCD02C00ull +#define PMMU_HBW_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PMMU_HBW_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmPMMU_HBW_MSTR_IF_CORE_LBW_BASE 0x1000007FFCD02D80ull +#define PMMU_HBW_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PMMU_HBW_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmPMMU_HBW_MSTR_IF_SPECIAL_BASE 0x1000007FFCD02E80ull +#define PMMU_HBW_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PMMU_HBW_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmPMMU_PIF_BASE 0x1000007FFCD03000ull +#define PMMU_PIF_MAX_OFFSET 0x1000 +#define PMMU_PIF_SECTION 0xE800 + +#define mmPMMU_PIF_SPECIAL_BASE 0x1000007FFCD03E80ull +#define PMMU_PIF_SPECIAL_MAX_OFFSET 0x1800 +#define PMMU_PIF_SPECIAL_SECTION 0x1800 + +#define mmPMMU_VID_PLL_CTRL_BASE 0x1000007FFCD05000ull +#define PMMU_VID_PLL_CTRL_MAX_OFFSET 0x3540 +#define PMMU_VID_PLL_CTRL_SECTION 0x3600 + +#define mmPMMU_VID_PLL_ASIF_SLV_BASE 0x1000007FFCD05360ull +#define PMMU_VID_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define PMMU_VID_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmPMMU_VID_PLL_DIV_0_RLX_BASE 0x1000007FFCD05400ull +#define PMMU_VID_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define PMMU_VID_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmPMMU_VID_PLL_DIV_1_RLX_BASE 0x1000007FFCD05800ull +#define PMMU_VID_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define PMMU_VID_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmPMMU_VID_PLL_DIV_2_RLX_BASE 0x1000007FFCD05A00ull +#define PMMU_VID_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define PMMU_VID_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmPMMU_VID_PLL_DIV_3_RLX_BASE 0x1000007FFCD05C00ull +#define PMMU_VID_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define PMMU_VID_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmPMMU_VID_PLL_SPECIAL_BASE 0x1000007FFCD05E80ull +#define PMMU_VID_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define PMMU_VID_PLL_SPECIAL_SECTION 0x3A180 + +#define mmXBAR_MID_0_BASE 0x1000007FFCD40000ull +#define XBAR_MID_0_MAX_OFFSET 0x1000 +#define XBAR_MID_0_SECTION 0xE800 + +#define mmXBAR_MID_0_SPECIAL_BASE 0x1000007FFCD40E80ull +#define XBAR_MID_0_SPECIAL_MAX_OFFSET 0x1800 +#define XBAR_MID_0_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_XBAR_DMA_PLL_CTRL_BASE 0x1000007FFCD41000ull +#define DCORE0_XBAR_DMA_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE0_XBAR_DMA_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE0_XBAR_DMA_PLL_ASIF_SLV_BASE 0x1000007FFCD41360ull +#define DCORE0_XBAR_DMA_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE0_XBAR_DMA_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE0_XBAR_DMA_PLL_DIV_0_RLX_BASE 0x1000007FFCD41400ull +#define DCORE0_XBAR_DMA_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE0_XBAR_DMA_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE0_XBAR_DMA_PLL_DIV_1_RLX_BASE 0x1000007FFCD41800ull +#define DCORE0_XBAR_DMA_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_DMA_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE0_XBAR_DMA_PLL_DIV_2_RLX_BASE 0x1000007FFCD41A00ull +#define DCORE0_XBAR_DMA_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_DMA_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE0_XBAR_DMA_PLL_DIV_3_RLX_BASE 0x1000007FFCD41C00ull +#define DCORE0_XBAR_DMA_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_DMA_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE0_XBAR_DMA_PLL_SPECIAL_BASE 0x1000007FFCD41E80ull +#define DCORE0_XBAR_DMA_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_XBAR_DMA_PLL_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_XBAR_MMU_PLL_CTRL_BASE 0x1000007FFCD42000ull +#define DCORE0_XBAR_MMU_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE0_XBAR_MMU_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE0_XBAR_MMU_PLL_ASIF_SLV_BASE 0x1000007FFCD42360ull +#define DCORE0_XBAR_MMU_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE0_XBAR_MMU_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE0_XBAR_MMU_PLL_DIV_0_RLX_BASE 0x1000007FFCD42400ull +#define DCORE0_XBAR_MMU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE0_XBAR_MMU_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE0_XBAR_MMU_PLL_DIV_1_RLX_BASE 0x1000007FFCD42800ull +#define DCORE0_XBAR_MMU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_MMU_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE0_XBAR_MMU_PLL_DIV_2_RLX_BASE 0x1000007FFCD42A00ull +#define DCORE0_XBAR_MMU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_MMU_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE0_XBAR_MMU_PLL_DIV_3_RLX_BASE 0x1000007FFCD42C00ull +#define DCORE0_XBAR_MMU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_MMU_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE0_XBAR_MMU_PLL_SPECIAL_BASE 0x1000007FFCD42E80ull +#define DCORE0_XBAR_MMU_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_XBAR_MMU_PLL_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_XBAR_IF_PLL_CTRL_BASE 0x1000007FFCD43000ull +#define DCORE0_XBAR_IF_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE0_XBAR_IF_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE0_XBAR_IF_PLL_ASIF_SLV_BASE 0x1000007FFCD43360ull +#define DCORE0_XBAR_IF_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE0_XBAR_IF_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE0_XBAR_IF_PLL_DIV_0_RLX_BASE 0x1000007FFCD43400ull +#define DCORE0_XBAR_IF_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE0_XBAR_IF_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE0_XBAR_IF_PLL_DIV_1_RLX_BASE 0x1000007FFCD43800ull +#define DCORE0_XBAR_IF_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_IF_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE0_XBAR_IF_PLL_DIV_2_RLX_BASE 0x1000007FFCD43A00ull +#define DCORE0_XBAR_IF_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_IF_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE0_XBAR_IF_PLL_DIV_3_RLX_BASE 0x1000007FFCD43C00ull +#define DCORE0_XBAR_IF_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_IF_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE0_XBAR_IF_PLL_SPECIAL_BASE 0x1000007FFCD43E80ull +#define DCORE0_XBAR_IF_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_XBAR_IF_PLL_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_XBAR_MESH_PLL_CTRL_BASE 0x1000007FFCD44000ull +#define DCORE0_XBAR_MESH_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE0_XBAR_MESH_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE0_XBAR_MESH_PLL_ASIF_SLV_BASE 0x1000007FFCD44360ull +#define DCORE0_XBAR_MESH_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE0_XBAR_MESH_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE0_XBAR_MESH_PLL_DIV_0_RLX_BASE 0x1000007FFCD44400ull +#define DCORE0_XBAR_MESH_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE0_XBAR_MESH_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE0_XBAR_MESH_PLL_DIV_1_RLX_BASE 0x1000007FFCD44800ull +#define DCORE0_XBAR_MESH_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_MESH_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE0_XBAR_MESH_PLL_DIV_2_RLX_BASE 0x1000007FFCD44A00ull +#define DCORE0_XBAR_MESH_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_MESH_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE0_XBAR_MESH_PLL_DIV_3_RLX_BASE 0x1000007FFCD44C00ull +#define DCORE0_XBAR_MESH_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE0_XBAR_MESH_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE0_XBAR_MESH_PLL_SPECIAL_BASE 0x1000007FFCD44E80ull +#define DCORE0_XBAR_MESH_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_XBAR_MESH_PLL_SPECIAL_SECTION 0x3180 + +#define mmXBAR_EDGE_0_BASE 0x1000007FFCD48000ull +#define XBAR_EDGE_0_MAX_OFFSET 0x1000 +#define XBAR_EDGE_0_SECTION 0xE800 + +#define mmXBAR_EDGE_0_SPECIAL_BASE 0x1000007FFCD48E80ull +#define XBAR_EDGE_0_SPECIAL_MAX_OFFSET 0x1800 +#define XBAR_EDGE_0_SPECIAL_SECTION 0x7180 + +#define mmXBAR_MID_1_BASE 0x1000007FFCD50000ull +#define XBAR_MID_1_MAX_OFFSET 0x1000 +#define XBAR_MID_1_SECTION 0xE800 + +#define mmXBAR_MID_1_SPECIAL_BASE 0x1000007FFCD50E80ull +#define XBAR_MID_1_SPECIAL_MAX_OFFSET 0x1800 +#define XBAR_MID_1_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_XBAR_DMA_PLL_CTRL_BASE 0x1000007FFCD51000ull +#define DCORE1_XBAR_DMA_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE1_XBAR_DMA_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE1_XBAR_DMA_PLL_ASIF_SLV_BASE 0x1000007FFCD51360ull +#define DCORE1_XBAR_DMA_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_XBAR_DMA_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE1_XBAR_DMA_PLL_DIV_0_RLX_BASE 0x1000007FFCD51400ull +#define DCORE1_XBAR_DMA_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_DMA_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE1_XBAR_DMA_PLL_DIV_1_RLX_BASE 0x1000007FFCD51800ull +#define DCORE1_XBAR_DMA_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_DMA_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE1_XBAR_DMA_PLL_DIV_2_RLX_BASE 0x1000007FFCD51A00ull +#define DCORE1_XBAR_DMA_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_DMA_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE1_XBAR_DMA_PLL_DIV_3_RLX_BASE 0x1000007FFCD51C00ull +#define DCORE1_XBAR_DMA_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_DMA_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE1_XBAR_DMA_PLL_SPECIAL_BASE 0x1000007FFCD51E80ull +#define DCORE1_XBAR_DMA_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_DMA_PLL_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_XBAR_MMU_PLL_CTRL_BASE 0x1000007FFCD52000ull +#define DCORE1_XBAR_MMU_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE1_XBAR_MMU_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE1_XBAR_MMU_PLL_ASIF_SLV_BASE 0x1000007FFCD52360ull +#define DCORE1_XBAR_MMU_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_XBAR_MMU_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE1_XBAR_MMU_PLL_DIV_0_RLX_BASE 0x1000007FFCD52400ull +#define DCORE1_XBAR_MMU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_MMU_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE1_XBAR_MMU_PLL_DIV_1_RLX_BASE 0x1000007FFCD52800ull +#define DCORE1_XBAR_MMU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_MMU_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE1_XBAR_MMU_PLL_DIV_2_RLX_BASE 0x1000007FFCD52A00ull +#define DCORE1_XBAR_MMU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_MMU_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE1_XBAR_MMU_PLL_DIV_3_RLX_BASE 0x1000007FFCD52C00ull +#define DCORE1_XBAR_MMU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_MMU_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE1_XBAR_MMU_PLL_SPECIAL_BASE 0x1000007FFCD52E80ull +#define DCORE1_XBAR_MMU_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_MMU_PLL_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_XBAR_IF_PLL_CTRL_BASE 0x1000007FFCD53000ull +#define DCORE1_XBAR_IF_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE1_XBAR_IF_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE1_XBAR_IF_PLL_ASIF_SLV_BASE 0x1000007FFCD53360ull +#define DCORE1_XBAR_IF_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_XBAR_IF_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE1_XBAR_IF_PLL_DIV_0_RLX_BASE 0x1000007FFCD53400ull +#define DCORE1_XBAR_IF_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_IF_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE1_XBAR_IF_PLL_DIV_1_RLX_BASE 0x1000007FFCD53800ull +#define DCORE1_XBAR_IF_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_IF_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE1_XBAR_IF_PLL_DIV_2_RLX_BASE 0x1000007FFCD53A00ull +#define DCORE1_XBAR_IF_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_IF_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE1_XBAR_IF_PLL_DIV_3_RLX_BASE 0x1000007FFCD53C00ull +#define DCORE1_XBAR_IF_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_IF_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE1_XBAR_IF_PLL_SPECIAL_BASE 0x1000007FFCD53E80ull +#define DCORE1_XBAR_IF_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_IF_PLL_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_XBAR_MESH_PLL_CTRL_BASE 0x1000007FFCD54000ull +#define DCORE1_XBAR_MESH_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE1_XBAR_MESH_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE1_XBAR_MESH_PLL_ASIF_SLV_BASE 0x1000007FFCD54360ull +#define DCORE1_XBAR_MESH_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_XBAR_MESH_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE1_XBAR_MESH_PLL_DIV_0_RLX_BASE 0x1000007FFCD54400ull +#define DCORE1_XBAR_MESH_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_MESH_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE1_XBAR_MESH_PLL_DIV_1_RLX_BASE 0x1000007FFCD54800ull +#define DCORE1_XBAR_MESH_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_MESH_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE1_XBAR_MESH_PLL_DIV_2_RLX_BASE 0x1000007FFCD54A00ull +#define DCORE1_XBAR_MESH_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_MESH_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE1_XBAR_MESH_PLL_DIV_3_RLX_BASE 0x1000007FFCD54C00ull +#define DCORE1_XBAR_MESH_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_MESH_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE1_XBAR_MESH_PLL_SPECIAL_BASE 0x1000007FFCD54E80ull +#define DCORE1_XBAR_MESH_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_MESH_PLL_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_XBAR_HBM_PLL_CTRL_BASE 0x1000007FFCD55000ull +#define DCORE1_XBAR_HBM_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE1_XBAR_HBM_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE1_XBAR_HBM_PLL_ASIF_SLV_BASE 0x1000007FFCD55360ull +#define DCORE1_XBAR_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_XBAR_HBM_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE1_XBAR_HBM_PLL_DIV_0_RLX_BASE 0x1000007FFCD55400ull +#define DCORE1_XBAR_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_HBM_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE1_XBAR_HBM_PLL_DIV_1_RLX_BASE 0x1000007FFCD55800ull +#define DCORE1_XBAR_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_HBM_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE1_XBAR_HBM_PLL_DIV_2_RLX_BASE 0x1000007FFCD55A00ull +#define DCORE1_XBAR_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_HBM_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE1_XBAR_HBM_PLL_DIV_3_RLX_BASE 0x1000007FFCD55C00ull +#define DCORE1_XBAR_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE1_XBAR_HBM_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE1_XBAR_HBM_PLL_SPECIAL_BASE 0x1000007FFCD55E80ull +#define DCORE1_XBAR_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_XBAR_HBM_PLL_SPECIAL_SECTION 0x2180 + +#define mmXBAR_EDGE_1_BASE 0x1000007FFCD58000ull +#define XBAR_EDGE_1_MAX_OFFSET 0x1000 +#define XBAR_EDGE_1_SECTION 0xE800 + +#define mmXBAR_EDGE_1_SPECIAL_BASE 0x1000007FFCD58E80ull +#define XBAR_EDGE_1_SPECIAL_MAX_OFFSET 0x1800 +#define XBAR_EDGE_1_SPECIAL_SECTION 0x7180 + +#define mmXBAR_MID_2_BASE 0x1000007FFCD60000ull +#define XBAR_MID_2_MAX_OFFSET 0x1000 +#define XBAR_MID_2_SECTION 0xE800 + +#define mmXBAR_MID_2_SPECIAL_BASE 0x1000007FFCD60E80ull +#define XBAR_MID_2_SPECIAL_MAX_OFFSET 0x1800 +#define XBAR_MID_2_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_XBAR_DMA_PLL_CTRL_BASE 0x1000007FFCD61000ull +#define DCORE2_XBAR_DMA_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE2_XBAR_DMA_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE2_XBAR_DMA_PLL_ASIF_SLV_BASE 0x1000007FFCD61360ull +#define DCORE2_XBAR_DMA_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE2_XBAR_DMA_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE2_XBAR_DMA_PLL_DIV_0_RLX_BASE 0x1000007FFCD61400ull +#define DCORE2_XBAR_DMA_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_DMA_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE2_XBAR_DMA_PLL_DIV_1_RLX_BASE 0x1000007FFCD61800ull +#define DCORE2_XBAR_DMA_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_DMA_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE2_XBAR_DMA_PLL_DIV_2_RLX_BASE 0x1000007FFCD61A00ull +#define DCORE2_XBAR_DMA_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_DMA_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE2_XBAR_DMA_PLL_DIV_3_RLX_BASE 0x1000007FFCD61C00ull +#define DCORE2_XBAR_DMA_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_DMA_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE2_XBAR_DMA_PLL_SPECIAL_BASE 0x1000007FFCD61E80ull +#define DCORE2_XBAR_DMA_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_DMA_PLL_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_XBAR_MMU_PLL_CTRL_BASE 0x1000007FFCD62000ull +#define DCORE2_XBAR_MMU_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE2_XBAR_MMU_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE2_XBAR_MMU_PLL_ASIF_SLV_BASE 0x1000007FFCD62360ull +#define DCORE2_XBAR_MMU_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE2_XBAR_MMU_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE2_XBAR_MMU_PLL_DIV_0_RLX_BASE 0x1000007FFCD62400ull +#define DCORE2_XBAR_MMU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_MMU_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE2_XBAR_MMU_PLL_DIV_1_RLX_BASE 0x1000007FFCD62800ull +#define DCORE2_XBAR_MMU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_MMU_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE2_XBAR_MMU_PLL_DIV_2_RLX_BASE 0x1000007FFCD62A00ull +#define DCORE2_XBAR_MMU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_MMU_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE2_XBAR_MMU_PLL_DIV_3_RLX_BASE 0x1000007FFCD62C00ull +#define DCORE2_XBAR_MMU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_MMU_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE2_XBAR_MMU_PLL_SPECIAL_BASE 0x1000007FFCD62E80ull +#define DCORE2_XBAR_MMU_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_MMU_PLL_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_XBAR_IF_PLL_CTRL_BASE 0x1000007FFCD63000ull +#define DCORE2_XBAR_IF_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE2_XBAR_IF_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE2_XBAR_IF_PLL_ASIF_SLV_BASE 0x1000007FFCD63360ull +#define DCORE2_XBAR_IF_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE2_XBAR_IF_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE2_XBAR_IF_PLL_DIV_0_RLX_BASE 0x1000007FFCD63400ull +#define DCORE2_XBAR_IF_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_IF_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE2_XBAR_IF_PLL_DIV_1_RLX_BASE 0x1000007FFCD63800ull +#define DCORE2_XBAR_IF_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_IF_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE2_XBAR_IF_PLL_DIV_2_RLX_BASE 0x1000007FFCD63A00ull +#define DCORE2_XBAR_IF_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_IF_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE2_XBAR_IF_PLL_DIV_3_RLX_BASE 0x1000007FFCD63C00ull +#define DCORE2_XBAR_IF_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_IF_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE2_XBAR_IF_PLL_SPECIAL_BASE 0x1000007FFCD63E80ull +#define DCORE2_XBAR_IF_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_IF_PLL_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_XBAR_BANK_PLL_CTRL_BASE 0x1000007FFCD64000ull +#define DCORE2_XBAR_BANK_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE2_XBAR_BANK_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE2_XBAR_BANK_PLL_ASIF_SLV_BASE 0x1000007FFCD64360ull +#define DCORE2_XBAR_BANK_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE2_XBAR_BANK_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE2_XBAR_BANK_PLL_DIV_0_RLX_BASE 0x1000007FFCD64400ull +#define DCORE2_XBAR_BANK_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_BANK_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE2_XBAR_BANK_PLL_DIV_1_RLX_BASE 0x1000007FFCD64800ull +#define DCORE2_XBAR_BANK_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_BANK_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE2_XBAR_BANK_PLL_DIV_2_RLX_BASE 0x1000007FFCD64A00ull +#define DCORE2_XBAR_BANK_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_BANK_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE2_XBAR_BANK_PLL_DIV_3_RLX_BASE 0x1000007FFCD64C00ull +#define DCORE2_XBAR_BANK_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_BANK_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE2_XBAR_BANK_PLL_SPECIAL_BASE 0x1000007FFCD64E80ull +#define DCORE2_XBAR_BANK_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_BANK_PLL_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_XBAR_HBM_PLL_CTRL_BASE 0x1000007FFCD65000ull +#define DCORE2_XBAR_HBM_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE2_XBAR_HBM_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE2_XBAR_HBM_PLL_ASIF_SLV_BASE 0x1000007FFCD65360ull +#define DCORE2_XBAR_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE2_XBAR_HBM_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE2_XBAR_HBM_PLL_DIV_0_RLX_BASE 0x1000007FFCD65400ull +#define DCORE2_XBAR_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_HBM_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE2_XBAR_HBM_PLL_DIV_1_RLX_BASE 0x1000007FFCD65800ull +#define DCORE2_XBAR_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_HBM_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE2_XBAR_HBM_PLL_DIV_2_RLX_BASE 0x1000007FFCD65A00ull +#define DCORE2_XBAR_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_HBM_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE2_XBAR_HBM_PLL_DIV_3_RLX_BASE 0x1000007FFCD65C00ull +#define DCORE2_XBAR_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE2_XBAR_HBM_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE2_XBAR_HBM_PLL_SPECIAL_BASE 0x1000007FFCD65E80ull +#define DCORE2_XBAR_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_XBAR_HBM_PLL_SPECIAL_SECTION 0x2180 + +#define mmXBAR_EDGE_2_BASE 0x1000007FFCD68000ull +#define XBAR_EDGE_2_MAX_OFFSET 0x1000 +#define XBAR_EDGE_2_SECTION 0xE800 + +#define mmXBAR_EDGE_2_SPECIAL_BASE 0x1000007FFCD68E80ull +#define XBAR_EDGE_2_SPECIAL_MAX_OFFSET 0x1800 +#define XBAR_EDGE_2_SPECIAL_SECTION 0x7180 + +#define mmXBAR_MID_3_BASE 0x1000007FFCD70000ull +#define XBAR_MID_3_MAX_OFFSET 0x1000 +#define XBAR_MID_3_SECTION 0xE800 + +#define mmXBAR_MID_3_SPECIAL_BASE 0x1000007FFCD70E80ull +#define XBAR_MID_3_SPECIAL_MAX_OFFSET 0x1800 +#define XBAR_MID_3_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_XBAR_DMA_PLL_CTRL_BASE 0x1000007FFCD71000ull +#define DCORE3_XBAR_DMA_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE3_XBAR_DMA_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE3_XBAR_DMA_PLL_ASIF_SLV_BASE 0x1000007FFCD71360ull +#define DCORE3_XBAR_DMA_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE3_XBAR_DMA_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE3_XBAR_DMA_PLL_DIV_0_RLX_BASE 0x1000007FFCD71400ull +#define DCORE3_XBAR_DMA_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE3_XBAR_DMA_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE3_XBAR_DMA_PLL_DIV_1_RLX_BASE 0x1000007FFCD71800ull +#define DCORE3_XBAR_DMA_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_DMA_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE3_XBAR_DMA_PLL_DIV_2_RLX_BASE 0x1000007FFCD71A00ull +#define DCORE3_XBAR_DMA_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_DMA_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE3_XBAR_DMA_PLL_DIV_3_RLX_BASE 0x1000007FFCD71C00ull +#define DCORE3_XBAR_DMA_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_DMA_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE3_XBAR_DMA_PLL_SPECIAL_BASE 0x1000007FFCD71E80ull +#define DCORE3_XBAR_DMA_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_XBAR_DMA_PLL_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_XBAR_MMU_PLL_CTRL_BASE 0x1000007FFCD72000ull +#define DCORE3_XBAR_MMU_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE3_XBAR_MMU_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE3_XBAR_MMU_PLL_ASIF_SLV_BASE 0x1000007FFCD72360ull +#define DCORE3_XBAR_MMU_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE3_XBAR_MMU_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE3_XBAR_MMU_PLL_DIV_0_RLX_BASE 0x1000007FFCD72400ull +#define DCORE3_XBAR_MMU_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE3_XBAR_MMU_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE3_XBAR_MMU_PLL_DIV_1_RLX_BASE 0x1000007FFCD72800ull +#define DCORE3_XBAR_MMU_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_MMU_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE3_XBAR_MMU_PLL_DIV_2_RLX_BASE 0x1000007FFCD72A00ull +#define DCORE3_XBAR_MMU_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_MMU_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE3_XBAR_MMU_PLL_DIV_3_RLX_BASE 0x1000007FFCD72C00ull +#define DCORE3_XBAR_MMU_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_MMU_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE3_XBAR_MMU_PLL_SPECIAL_BASE 0x1000007FFCD72E80ull +#define DCORE3_XBAR_MMU_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_XBAR_MMU_PLL_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_XBAR_IF_PLL_CTRL_BASE 0x1000007FFCD73000ull +#define DCORE3_XBAR_IF_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE3_XBAR_IF_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE3_XBAR_IF_PLL_ASIF_SLV_BASE 0x1000007FFCD73360ull +#define DCORE3_XBAR_IF_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE3_XBAR_IF_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE3_XBAR_IF_PLL_DIV_0_RLX_BASE 0x1000007FFCD73400ull +#define DCORE3_XBAR_IF_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE3_XBAR_IF_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE3_XBAR_IF_PLL_DIV_1_RLX_BASE 0x1000007FFCD73800ull +#define DCORE3_XBAR_IF_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_IF_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE3_XBAR_IF_PLL_DIV_2_RLX_BASE 0x1000007FFCD73A00ull +#define DCORE3_XBAR_IF_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_IF_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE3_XBAR_IF_PLL_DIV_3_RLX_BASE 0x1000007FFCD73C00ull +#define DCORE3_XBAR_IF_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_IF_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE3_XBAR_IF_PLL_SPECIAL_BASE 0x1000007FFCD73E80ull +#define DCORE3_XBAR_IF_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_XBAR_IF_PLL_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_XBAR_BANK_PLL_CTRL_BASE 0x1000007FFCD74000ull +#define DCORE3_XBAR_BANK_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE3_XBAR_BANK_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE3_XBAR_BANK_PLL_ASIF_SLV_BASE 0x1000007FFCD74360ull +#define DCORE3_XBAR_BANK_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE3_XBAR_BANK_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE3_XBAR_BANK_PLL_DIV_0_RLX_BASE 0x1000007FFCD74400ull +#define DCORE3_XBAR_BANK_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE3_XBAR_BANK_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE3_XBAR_BANK_PLL_DIV_1_RLX_BASE 0x1000007FFCD74800ull +#define DCORE3_XBAR_BANK_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_BANK_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE3_XBAR_BANK_PLL_DIV_2_RLX_BASE 0x1000007FFCD74A00ull +#define DCORE3_XBAR_BANK_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_BANK_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE3_XBAR_BANK_PLL_DIV_3_RLX_BASE 0x1000007FFCD74C00ull +#define DCORE3_XBAR_BANK_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE3_XBAR_BANK_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE3_XBAR_BANK_PLL_SPECIAL_BASE 0x1000007FFCD74E80ull +#define DCORE3_XBAR_BANK_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_XBAR_BANK_PLL_SPECIAL_SECTION 0x3180 + +#define mmXBAR_EDGE_3_BASE 0x1000007FFCD78000ull +#define XBAR_EDGE_3_MAX_OFFSET 0x1000 +#define XBAR_EDGE_3_SECTION 0xE800 + +#define mmXBAR_EDGE_3_SPECIAL_BASE 0x1000007FFCD78E80ull +#define XBAR_EDGE_3_SPECIAL_MAX_OFFSET 0x1800 +#define XBAR_EDGE_3_SPECIAL_SECTION 0x7180 + +#define mmPCIE_PMA_0_BASE 0x1000007FFCD80000ull +#define PCIE_PMA_0_MAX_OFFSET 0x40000 +#define PCIE_PMA_0_SECTION 0x40000 + +#define mmPCIE_PMA_1_BASE 0x1000007FFCDC0000ull +#define PCIE_PMA_1_MAX_OFFSET 0x40000 +#define PCIE_PMA_1_SECTION 0x40000 + +#define mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE 0x1000007FFCE40000ull +#define SFT0_HBW_RTR_IF0_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT0_HBW_RTR_IF0_RTR_CTRL_SECTION 0xE800 + +#define mmSFT0_HBW_RTR_IF0_RTR_CTRL_SPECIAL_BASE 0x1000007FFCE40E80ull +#define SFT0_HBW_RTR_IF0_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_HBW_RTR_IF0_RTR_CTRL_SPECIAL_SECTION 0x1800 + +#define mmSFT0_HBW_RTR_IF0_RTR_H3_BASE 0x1000007FFCE41000ull +#define SFT0_HBW_RTR_IF0_RTR_H3_MAX_OFFSET 0x1000 +#define SFT0_HBW_RTR_IF0_RTR_H3_SECTION 0xE800 + +#define mmSFT0_HBW_RTR_IF0_RTR_H3_SPECIAL_BASE 0x1000007FFCE41E80ull +#define SFT0_HBW_RTR_IF0_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_HBW_RTR_IF0_RTR_H3_SPECIAL_SECTION 0x1800 + +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCE42000ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCE42200ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCE42400ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCE42600ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT0_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCE42800ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT0_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_AXUSER_BASE 0x1000007FFCE42A80ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT0_HBW_RTR_IF0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_DBG_HBW_BASE 0x1000007FFCE42B00ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_DBG_LBW_BASE 0x1000007FFCE42B80ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT0_HBW_RTR_IF0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_CORE_HBW_BASE 0x1000007FFCE42C00ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_CORE_LBW_BASE 0x1000007FFCE42D80ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT0_HBW_RTR_IF0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmSFT0_HBW_RTR_IF0_MSTR_IF_SPECIAL_BASE 0x1000007FFCE42E80ull +#define SFT0_HBW_RTR_IF0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_HBW_RTR_IF0_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmSFT0_HBW_RTR_IF0_ADDR_DEC_HBW_BASE 0x1000007FFCE43000ull +#define SFT0_HBW_RTR_IF0_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT0_HBW_RTR_IF0_ADDR_DEC_HBW_SECTION 0x4000 + +#define mmSFT0_HBW_RTR_IF0_ADDR_DEC_LBW_BASE 0x1000007FFCE43400ull +#define SFT0_HBW_RTR_IF0_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT0_HBW_RTR_IF0_ADDR_DEC_LBW_SECTION 0xA800 + +#define mmSFT0_HBW_RTR_IF0_ADDR_DEC_SPECIAL_BASE 0x1000007FFCE43E80ull +#define SFT0_HBW_RTR_IF0_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_HBW_RTR_IF0_ADDR_DEC_SPECIAL_SECTION 0x1800 + +#define mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE 0x1000007FFCE44000ull +#define SFT0_HBW_RTR_IF1_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT0_HBW_RTR_IF1_RTR_CTRL_SECTION 0xE800 + +#define mmSFT0_HBW_RTR_IF1_RTR_CTRL_SPECIAL_BASE 0x1000007FFCE44E80ull +#define SFT0_HBW_RTR_IF1_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_HBW_RTR_IF1_RTR_CTRL_SPECIAL_SECTION 0x1800 + +#define mmSFT0_HBW_RTR_IF1_RTR_H3_BASE 0x1000007FFCE45000ull +#define SFT0_HBW_RTR_IF1_RTR_H3_MAX_OFFSET 0x1000 +#define SFT0_HBW_RTR_IF1_RTR_H3_SECTION 0xE800 + +#define mmSFT0_HBW_RTR_IF1_RTR_H3_SPECIAL_BASE 0x1000007FFCE45E80ull +#define SFT0_HBW_RTR_IF1_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_HBW_RTR_IF1_RTR_H3_SPECIAL_SECTION 0x1800 + +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCE46000ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCE46200ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCE46400ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCE46600ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT0_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCE46800ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT0_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_AXUSER_BASE 0x1000007FFCE46A80ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT0_HBW_RTR_IF1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_DBG_HBW_BASE 0x1000007FFCE46B00ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_DBG_LBW_BASE 0x1000007FFCE46B80ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT0_HBW_RTR_IF1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_CORE_HBW_BASE 0x1000007FFCE46C00ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_CORE_LBW_BASE 0x1000007FFCE46D80ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT0_HBW_RTR_IF1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmSFT0_HBW_RTR_IF1_MSTR_IF_SPECIAL_BASE 0x1000007FFCE46E80ull +#define SFT0_HBW_RTR_IF1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_HBW_RTR_IF1_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmSFT0_HBW_RTR_IF1_ADDR_DEC_HBW_BASE 0x1000007FFCE47000ull +#define SFT0_HBW_RTR_IF1_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT0_HBW_RTR_IF1_ADDR_DEC_HBW_SECTION 0x4000 + +#define mmSFT0_HBW_RTR_IF1_ADDR_DEC_LBW_BASE 0x1000007FFCE47400ull +#define SFT0_HBW_RTR_IF1_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT0_HBW_RTR_IF1_ADDR_DEC_LBW_SECTION 0xA800 + +#define mmSFT0_HBW_RTR_IF1_ADDR_DEC_SPECIAL_BASE 0x1000007FFCE47E80ull +#define SFT0_HBW_RTR_IF1_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_HBW_RTR_IF1_ADDR_DEC_SPECIAL_SECTION 0x1800 + +#define mmSFT0_LBW_RTR_IF_RTR_CTRL_BASE 0x1000007FFCE48000ull +#define SFT0_LBW_RTR_IF_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT0_LBW_RTR_IF_RTR_CTRL_SECTION 0xE800 + +#define mmSFT0_LBW_RTR_IF_RTR_CTRL_SPECIAL_BASE 0x1000007FFCE48E80ull +#define SFT0_LBW_RTR_IF_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_LBW_RTR_IF_RTR_CTRL_SPECIAL_SECTION 0x1800 + +#define mmSFT0_LBW_RTR_IF_RTR_H3_BASE 0x1000007FFCE49000ull +#define SFT0_LBW_RTR_IF_RTR_H3_MAX_OFFSET 0x1000 +#define SFT0_LBW_RTR_IF_RTR_H3_SECTION 0xE800 + +#define mmSFT0_LBW_RTR_IF_RTR_H3_SPECIAL_BASE 0x1000007FFCE49E80ull +#define SFT0_LBW_RTR_IF_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_LBW_RTR_IF_RTR_H3_SPECIAL_SECTION 0x1800 + +#define mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCE4A000ull +#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmSFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCE4A200ull +#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCE4A400ull +#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmSFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCE4A600ull +#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT0_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmSFT0_LBW_RTR_IF_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCE4A800ull +#define SFT0_LBW_RTR_IF_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT0_LBW_RTR_IF_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmSFT0_LBW_RTR_IF_MSTR_IF_AXUSER_BASE 0x1000007FFCE4AA80ull +#define SFT0_LBW_RTR_IF_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT0_LBW_RTR_IF_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmSFT0_LBW_RTR_IF_MSTR_IF_DBG_HBW_BASE 0x1000007FFCE4AB00ull +#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmSFT0_LBW_RTR_IF_MSTR_IF_DBG_LBW_BASE 0x1000007FFCE4AB80ull +#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT0_LBW_RTR_IF_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmSFT0_LBW_RTR_IF_MSTR_IF_CORE_HBW_BASE 0x1000007FFCE4AC00ull +#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmSFT0_LBW_RTR_IF_MSTR_IF_CORE_LBW_BASE 0x1000007FFCE4AD80ull +#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT0_LBW_RTR_IF_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmSFT0_LBW_RTR_IF_MSTR_IF_SPECIAL_BASE 0x1000007FFCE4AE80ull +#define SFT0_LBW_RTR_IF_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_LBW_RTR_IF_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmSFT0_LBW_RTR_IF_ADDR_DEC_HBW_BASE 0x1000007FFCE4B000ull +#define SFT0_LBW_RTR_IF_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT0_LBW_RTR_IF_ADDR_DEC_HBW_SECTION 0x4000 + +#define mmSFT0_LBW_RTR_IF_ADDR_DEC_LBW_BASE 0x1000007FFCE4B400ull +#define SFT0_LBW_RTR_IF_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT0_LBW_RTR_IF_ADDR_DEC_LBW_SECTION 0xA800 + +#define mmSFT0_LBW_RTR_IF_ADDR_DEC_SPECIAL_BASE 0x1000007FFCE4BE80ull +#define SFT0_LBW_RTR_IF_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_LBW_RTR_IF_ADDR_DEC_SPECIAL_SECTION 0x1800 + +#define mmSFT0_BASE 0x1000007FFCE4C000ull +#define SFT0_MAX_OFFSET 0x1000 +#define SFT0_SECTION 0xE800 + +#define mmSFT0_SPECIAL_BASE 0x1000007FFCE4CE80ull +#define SFT0_SPECIAL_MAX_OFFSET 0x1800 +#define SFT0_SPECIAL_SECTION 0x3180 + +#define mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE 0x1000007FFCE50000ull +#define SFT1_HBW_RTR_IF0_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT1_HBW_RTR_IF0_RTR_CTRL_SECTION 0xE800 + +#define mmSFT1_HBW_RTR_IF0_RTR_CTRL_SPECIAL_BASE 0x1000007FFCE50E80ull +#define SFT1_HBW_RTR_IF0_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_HBW_RTR_IF0_RTR_CTRL_SPECIAL_SECTION 0x1800 + +#define mmSFT1_HBW_RTR_IF0_RTR_H3_BASE 0x1000007FFCE51000ull +#define SFT1_HBW_RTR_IF0_RTR_H3_MAX_OFFSET 0x1000 +#define SFT1_HBW_RTR_IF0_RTR_H3_SECTION 0xE800 + +#define mmSFT1_HBW_RTR_IF0_RTR_H3_SPECIAL_BASE 0x1000007FFCE51E80ull +#define SFT1_HBW_RTR_IF0_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_HBW_RTR_IF0_RTR_H3_SPECIAL_SECTION 0x1800 + +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCE52000ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCE52200ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCE52400ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCE52600ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT1_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCE52800ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT1_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_AXUSER_BASE 0x1000007FFCE52A80ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT1_HBW_RTR_IF0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_DBG_HBW_BASE 0x1000007FFCE52B00ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_DBG_LBW_BASE 0x1000007FFCE52B80ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT1_HBW_RTR_IF0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_CORE_HBW_BASE 0x1000007FFCE52C00ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_CORE_LBW_BASE 0x1000007FFCE52D80ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT1_HBW_RTR_IF0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmSFT1_HBW_RTR_IF0_MSTR_IF_SPECIAL_BASE 0x1000007FFCE52E80ull +#define SFT1_HBW_RTR_IF0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_HBW_RTR_IF0_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmSFT1_HBW_RTR_IF0_ADDR_DEC_HBW_BASE 0x1000007FFCE53000ull +#define SFT1_HBW_RTR_IF0_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT1_HBW_RTR_IF0_ADDR_DEC_HBW_SECTION 0x4000 + +#define mmSFT1_HBW_RTR_IF0_ADDR_DEC_LBW_BASE 0x1000007FFCE53400ull +#define SFT1_HBW_RTR_IF0_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT1_HBW_RTR_IF0_ADDR_DEC_LBW_SECTION 0xA800 + +#define mmSFT1_HBW_RTR_IF0_ADDR_DEC_SPECIAL_BASE 0x1000007FFCE53E80ull +#define SFT1_HBW_RTR_IF0_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_HBW_RTR_IF0_ADDR_DEC_SPECIAL_SECTION 0x1800 + +#define mmSFT1_HBW_RTR_IF1_RTR_CTRL_BASE 0x1000007FFCE54000ull +#define SFT1_HBW_RTR_IF1_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT1_HBW_RTR_IF1_RTR_CTRL_SECTION 0xE800 + +#define mmSFT1_HBW_RTR_IF1_RTR_CTRL_SPECIAL_BASE 0x1000007FFCE54E80ull +#define SFT1_HBW_RTR_IF1_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_HBW_RTR_IF1_RTR_CTRL_SPECIAL_SECTION 0x1800 + +#define mmSFT1_HBW_RTR_IF1_RTR_H3_BASE 0x1000007FFCE55000ull +#define SFT1_HBW_RTR_IF1_RTR_H3_MAX_OFFSET 0x1000 +#define SFT1_HBW_RTR_IF1_RTR_H3_SECTION 0xE800 + +#define mmSFT1_HBW_RTR_IF1_RTR_H3_SPECIAL_BASE 0x1000007FFCE55E80ull +#define SFT1_HBW_RTR_IF1_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_HBW_RTR_IF1_RTR_H3_SPECIAL_SECTION 0x1800 + +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCE56000ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCE56200ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCE56400ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCE56600ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT1_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCE56800ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT1_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_AXUSER_BASE 0x1000007FFCE56A80ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT1_HBW_RTR_IF1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_DBG_HBW_BASE 0x1000007FFCE56B00ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_DBG_LBW_BASE 0x1000007FFCE56B80ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT1_HBW_RTR_IF1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_CORE_HBW_BASE 0x1000007FFCE56C00ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_CORE_LBW_BASE 0x1000007FFCE56D80ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT1_HBW_RTR_IF1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmSFT1_HBW_RTR_IF1_MSTR_IF_SPECIAL_BASE 0x1000007FFCE56E80ull +#define SFT1_HBW_RTR_IF1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_HBW_RTR_IF1_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmSFT1_HBW_RTR_IF1_ADDR_DEC_HBW_BASE 0x1000007FFCE57000ull +#define SFT1_HBW_RTR_IF1_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT1_HBW_RTR_IF1_ADDR_DEC_HBW_SECTION 0x4000 + +#define mmSFT1_HBW_RTR_IF1_ADDR_DEC_LBW_BASE 0x1000007FFCE57400ull +#define SFT1_HBW_RTR_IF1_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT1_HBW_RTR_IF1_ADDR_DEC_LBW_SECTION 0xA800 + +#define mmSFT1_HBW_RTR_IF1_ADDR_DEC_SPECIAL_BASE 0x1000007FFCE57E80ull +#define SFT1_HBW_RTR_IF1_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_HBW_RTR_IF1_ADDR_DEC_SPECIAL_SECTION 0x1800 + +#define mmSFT1_LBW_RTR_IF_RTR_CTRL_BASE 0x1000007FFCE58000ull +#define SFT1_LBW_RTR_IF_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT1_LBW_RTR_IF_RTR_CTRL_SECTION 0xE800 + +#define mmSFT1_LBW_RTR_IF_RTR_CTRL_SPECIAL_BASE 0x1000007FFCE58E80ull +#define SFT1_LBW_RTR_IF_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_LBW_RTR_IF_RTR_CTRL_SPECIAL_SECTION 0x1800 + +#define mmSFT1_LBW_RTR_IF_RTR_H3_BASE 0x1000007FFCE59000ull +#define SFT1_LBW_RTR_IF_RTR_H3_MAX_OFFSET 0x1000 +#define SFT1_LBW_RTR_IF_RTR_H3_SECTION 0xE800 + +#define mmSFT1_LBW_RTR_IF_RTR_H3_SPECIAL_BASE 0x1000007FFCE59E80ull +#define SFT1_LBW_RTR_IF_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_LBW_RTR_IF_RTR_H3_SPECIAL_SECTION 0x1800 + +#define mmSFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCE5A000ull +#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmSFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCE5A200ull +#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmSFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCE5A400ull +#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT1_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmSFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCE5A600ull +#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT1_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmSFT1_LBW_RTR_IF_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCE5A800ull +#define SFT1_LBW_RTR_IF_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT1_LBW_RTR_IF_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmSFT1_LBW_RTR_IF_MSTR_IF_AXUSER_BASE 0x1000007FFCE5AA80ull +#define SFT1_LBW_RTR_IF_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT1_LBW_RTR_IF_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmSFT1_LBW_RTR_IF_MSTR_IF_DBG_HBW_BASE 0x1000007FFCE5AB00ull +#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmSFT1_LBW_RTR_IF_MSTR_IF_DBG_LBW_BASE 0x1000007FFCE5AB80ull +#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT1_LBW_RTR_IF_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmSFT1_LBW_RTR_IF_MSTR_IF_CORE_HBW_BASE 0x1000007FFCE5AC00ull +#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmSFT1_LBW_RTR_IF_MSTR_IF_CORE_LBW_BASE 0x1000007FFCE5AD80ull +#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT1_LBW_RTR_IF_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmSFT1_LBW_RTR_IF_MSTR_IF_SPECIAL_BASE 0x1000007FFCE5AE80ull +#define SFT1_LBW_RTR_IF_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_LBW_RTR_IF_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmSFT1_LBW_RTR_IF_ADDR_DEC_HBW_BASE 0x1000007FFCE5B000ull +#define SFT1_LBW_RTR_IF_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT1_LBW_RTR_IF_ADDR_DEC_HBW_SECTION 0x4000 + +#define mmSFT1_LBW_RTR_IF_ADDR_DEC_LBW_BASE 0x1000007FFCE5B400ull +#define SFT1_LBW_RTR_IF_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT1_LBW_RTR_IF_ADDR_DEC_LBW_SECTION 0xA800 + +#define mmSFT1_LBW_RTR_IF_ADDR_DEC_SPECIAL_BASE 0x1000007FFCE5BE80ull +#define SFT1_LBW_RTR_IF_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_LBW_RTR_IF_ADDR_DEC_SPECIAL_SECTION 0x1800 + +#define mmSFT1_BASE 0x1000007FFCE5C000ull +#define SFT1_MAX_OFFSET 0x1000 +#define SFT1_SECTION 0xE800 + +#define mmSFT1_SPECIAL_BASE 0x1000007FFCE5CE80ull +#define SFT1_SPECIAL_MAX_OFFSET 0x1800 +#define SFT1_SPECIAL_SECTION 0x3180 + +#define mmSFT2_HBW_RTR_IF0_RTR_CTRL_BASE 0x1000007FFCE60000ull +#define SFT2_HBW_RTR_IF0_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT2_HBW_RTR_IF0_RTR_CTRL_SECTION 0xE800 + +#define mmSFT2_HBW_RTR_IF0_RTR_CTRL_SPECIAL_BASE 0x1000007FFCE60E80ull +#define SFT2_HBW_RTR_IF0_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_HBW_RTR_IF0_RTR_CTRL_SPECIAL_SECTION 0x1800 + +#define mmSFT2_HBW_RTR_IF0_RTR_H3_BASE 0x1000007FFCE61000ull +#define SFT2_HBW_RTR_IF0_RTR_H3_MAX_OFFSET 0x1000 +#define SFT2_HBW_RTR_IF0_RTR_H3_SECTION 0xE800 + +#define mmSFT2_HBW_RTR_IF0_RTR_H3_SPECIAL_BASE 0x1000007FFCE61E80ull +#define SFT2_HBW_RTR_IF0_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_HBW_RTR_IF0_RTR_H3_SPECIAL_SECTION 0x1800 + +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCE62000ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCE62200ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCE62400ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCE62600ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT2_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCE62800ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT2_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_AXUSER_BASE 0x1000007FFCE62A80ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT2_HBW_RTR_IF0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_DBG_HBW_BASE 0x1000007FFCE62B00ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_DBG_LBW_BASE 0x1000007FFCE62B80ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT2_HBW_RTR_IF0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_CORE_HBW_BASE 0x1000007FFCE62C00ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_CORE_LBW_BASE 0x1000007FFCE62D80ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT2_HBW_RTR_IF0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmSFT2_HBW_RTR_IF0_MSTR_IF_SPECIAL_BASE 0x1000007FFCE62E80ull +#define SFT2_HBW_RTR_IF0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_HBW_RTR_IF0_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmSFT2_HBW_RTR_IF0_ADDR_DEC_HBW_BASE 0x1000007FFCE63000ull +#define SFT2_HBW_RTR_IF0_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT2_HBW_RTR_IF0_ADDR_DEC_HBW_SECTION 0x4000 + +#define mmSFT2_HBW_RTR_IF0_ADDR_DEC_LBW_BASE 0x1000007FFCE63400ull +#define SFT2_HBW_RTR_IF0_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT2_HBW_RTR_IF0_ADDR_DEC_LBW_SECTION 0xA800 + +#define mmSFT2_HBW_RTR_IF0_ADDR_DEC_SPECIAL_BASE 0x1000007FFCE63E80ull +#define SFT2_HBW_RTR_IF0_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_HBW_RTR_IF0_ADDR_DEC_SPECIAL_SECTION 0x1800 + +#define mmSFT2_HBW_RTR_IF1_RTR_CTRL_BASE 0x1000007FFCE64000ull +#define SFT2_HBW_RTR_IF1_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT2_HBW_RTR_IF1_RTR_CTRL_SECTION 0xE800 + +#define mmSFT2_HBW_RTR_IF1_RTR_CTRL_SPECIAL_BASE 0x1000007FFCE64E80ull +#define SFT2_HBW_RTR_IF1_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_HBW_RTR_IF1_RTR_CTRL_SPECIAL_SECTION 0x1800 + +#define mmSFT2_HBW_RTR_IF1_RTR_H3_BASE 0x1000007FFCE65000ull +#define SFT2_HBW_RTR_IF1_RTR_H3_MAX_OFFSET 0x1000 +#define SFT2_HBW_RTR_IF1_RTR_H3_SECTION 0xE800 + +#define mmSFT2_HBW_RTR_IF1_RTR_H3_SPECIAL_BASE 0x1000007FFCE65E80ull +#define SFT2_HBW_RTR_IF1_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_HBW_RTR_IF1_RTR_H3_SPECIAL_SECTION 0x1800 + +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCE66000ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCE66200ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCE66400ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCE66600ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT2_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCE66800ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT2_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_AXUSER_BASE 0x1000007FFCE66A80ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT2_HBW_RTR_IF1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_DBG_HBW_BASE 0x1000007FFCE66B00ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_DBG_LBW_BASE 0x1000007FFCE66B80ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT2_HBW_RTR_IF1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_CORE_HBW_BASE 0x1000007FFCE66C00ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_CORE_LBW_BASE 0x1000007FFCE66D80ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT2_HBW_RTR_IF1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmSFT2_HBW_RTR_IF1_MSTR_IF_SPECIAL_BASE 0x1000007FFCE66E80ull +#define SFT2_HBW_RTR_IF1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_HBW_RTR_IF1_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmSFT2_HBW_RTR_IF1_ADDR_DEC_HBW_BASE 0x1000007FFCE67000ull +#define SFT2_HBW_RTR_IF1_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT2_HBW_RTR_IF1_ADDR_DEC_HBW_SECTION 0x4000 + +#define mmSFT2_HBW_RTR_IF1_ADDR_DEC_LBW_BASE 0x1000007FFCE67400ull +#define SFT2_HBW_RTR_IF1_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT2_HBW_RTR_IF1_ADDR_DEC_LBW_SECTION 0xA800 + +#define mmSFT2_HBW_RTR_IF1_ADDR_DEC_SPECIAL_BASE 0x1000007FFCE67E80ull +#define SFT2_HBW_RTR_IF1_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_HBW_RTR_IF1_ADDR_DEC_SPECIAL_SECTION 0x1800 + +#define mmSFT2_LBW_RTR_IF_RTR_CTRL_BASE 0x1000007FFCE68000ull +#define SFT2_LBW_RTR_IF_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT2_LBW_RTR_IF_RTR_CTRL_SECTION 0xE800 + +#define mmSFT2_LBW_RTR_IF_RTR_CTRL_SPECIAL_BASE 0x1000007FFCE68E80ull +#define SFT2_LBW_RTR_IF_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_LBW_RTR_IF_RTR_CTRL_SPECIAL_SECTION 0x1800 + +#define mmSFT2_LBW_RTR_IF_RTR_H3_BASE 0x1000007FFCE69000ull +#define SFT2_LBW_RTR_IF_RTR_H3_MAX_OFFSET 0x1000 +#define SFT2_LBW_RTR_IF_RTR_H3_SECTION 0xE800 + +#define mmSFT2_LBW_RTR_IF_RTR_H3_SPECIAL_BASE 0x1000007FFCE69E80ull +#define SFT2_LBW_RTR_IF_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_LBW_RTR_IF_RTR_H3_SPECIAL_SECTION 0x1800 + +#define mmSFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCE6A000ull +#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmSFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCE6A200ull +#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmSFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCE6A400ull +#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT2_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmSFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCE6A600ull +#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT2_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmSFT2_LBW_RTR_IF_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCE6A800ull +#define SFT2_LBW_RTR_IF_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT2_LBW_RTR_IF_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmSFT2_LBW_RTR_IF_MSTR_IF_AXUSER_BASE 0x1000007FFCE6AA80ull +#define SFT2_LBW_RTR_IF_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT2_LBW_RTR_IF_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmSFT2_LBW_RTR_IF_MSTR_IF_DBG_HBW_BASE 0x1000007FFCE6AB00ull +#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmSFT2_LBW_RTR_IF_MSTR_IF_DBG_LBW_BASE 0x1000007FFCE6AB80ull +#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT2_LBW_RTR_IF_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmSFT2_LBW_RTR_IF_MSTR_IF_CORE_HBW_BASE 0x1000007FFCE6AC00ull +#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmSFT2_LBW_RTR_IF_MSTR_IF_CORE_LBW_BASE 0x1000007FFCE6AD80ull +#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT2_LBW_RTR_IF_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmSFT2_LBW_RTR_IF_MSTR_IF_SPECIAL_BASE 0x1000007FFCE6AE80ull +#define SFT2_LBW_RTR_IF_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_LBW_RTR_IF_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmSFT2_LBW_RTR_IF_ADDR_DEC_HBW_BASE 0x1000007FFCE6B000ull +#define SFT2_LBW_RTR_IF_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT2_LBW_RTR_IF_ADDR_DEC_HBW_SECTION 0x4000 + +#define mmSFT2_LBW_RTR_IF_ADDR_DEC_LBW_BASE 0x1000007FFCE6B400ull +#define SFT2_LBW_RTR_IF_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT2_LBW_RTR_IF_ADDR_DEC_LBW_SECTION 0xA800 + +#define mmSFT2_LBW_RTR_IF_ADDR_DEC_SPECIAL_BASE 0x1000007FFCE6BE80ull +#define SFT2_LBW_RTR_IF_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_LBW_RTR_IF_ADDR_DEC_SPECIAL_SECTION 0x1800 + +#define mmSFT2_BASE 0x1000007FFCE6C000ull +#define SFT2_MAX_OFFSET 0x1000 +#define SFT2_SECTION 0xE800 + +#define mmSFT2_SPECIAL_BASE 0x1000007FFCE6CE80ull +#define SFT2_SPECIAL_MAX_OFFSET 0x1800 +#define SFT2_SPECIAL_SECTION 0x3180 + +#define mmSFT3_HBW_RTR_IF0_RTR_CTRL_BASE 0x1000007FFCE70000ull +#define SFT3_HBW_RTR_IF0_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT3_HBW_RTR_IF0_RTR_CTRL_SECTION 0xE800 + +#define mmSFT3_HBW_RTR_IF0_RTR_CTRL_SPECIAL_BASE 0x1000007FFCE70E80ull +#define SFT3_HBW_RTR_IF0_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_HBW_RTR_IF0_RTR_CTRL_SPECIAL_SECTION 0x1800 + +#define mmSFT3_HBW_RTR_IF0_RTR_H3_BASE 0x1000007FFCE71000ull +#define SFT3_HBW_RTR_IF0_RTR_H3_MAX_OFFSET 0x1000 +#define SFT3_HBW_RTR_IF0_RTR_H3_SECTION 0xE800 + +#define mmSFT3_HBW_RTR_IF0_RTR_H3_SPECIAL_BASE 0x1000007FFCE71E80ull +#define SFT3_HBW_RTR_IF0_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_HBW_RTR_IF0_RTR_H3_SPECIAL_SECTION 0x1800 + +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCE72000ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCE72200ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCE72400ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCE72600ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT3_HBW_RTR_IF0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCE72800ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT3_HBW_RTR_IF0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_AXUSER_BASE 0x1000007FFCE72A80ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT3_HBW_RTR_IF0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_DBG_HBW_BASE 0x1000007FFCE72B00ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_DBG_LBW_BASE 0x1000007FFCE72B80ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT3_HBW_RTR_IF0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_CORE_HBW_BASE 0x1000007FFCE72C00ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_CORE_LBW_BASE 0x1000007FFCE72D80ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT3_HBW_RTR_IF0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmSFT3_HBW_RTR_IF0_MSTR_IF_SPECIAL_BASE 0x1000007FFCE72E80ull +#define SFT3_HBW_RTR_IF0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_HBW_RTR_IF0_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmSFT3_HBW_RTR_IF0_ADDR_DEC_HBW_BASE 0x1000007FFCE73000ull +#define SFT3_HBW_RTR_IF0_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT3_HBW_RTR_IF0_ADDR_DEC_HBW_SECTION 0x4000 + +#define mmSFT3_HBW_RTR_IF0_ADDR_DEC_LBW_BASE 0x1000007FFCE73400ull +#define SFT3_HBW_RTR_IF0_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT3_HBW_RTR_IF0_ADDR_DEC_LBW_SECTION 0xA800 + +#define mmSFT3_HBW_RTR_IF0_ADDR_DEC_SPECIAL_BASE 0x1000007FFCE73E80ull +#define SFT3_HBW_RTR_IF0_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_HBW_RTR_IF0_ADDR_DEC_SPECIAL_SECTION 0x1800 + +#define mmSFT3_HBW_RTR_IF1_RTR_CTRL_BASE 0x1000007FFCE74000ull +#define SFT3_HBW_RTR_IF1_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT3_HBW_RTR_IF1_RTR_CTRL_SECTION 0xE800 + +#define mmSFT3_HBW_RTR_IF1_RTR_CTRL_SPECIAL_BASE 0x1000007FFCE74E80ull +#define SFT3_HBW_RTR_IF1_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_HBW_RTR_IF1_RTR_CTRL_SPECIAL_SECTION 0x1800 + +#define mmSFT3_HBW_RTR_IF1_RTR_H3_BASE 0x1000007FFCE75000ull +#define SFT3_HBW_RTR_IF1_RTR_H3_MAX_OFFSET 0x1000 +#define SFT3_HBW_RTR_IF1_RTR_H3_SECTION 0xE800 + +#define mmSFT3_HBW_RTR_IF1_RTR_H3_SPECIAL_BASE 0x1000007FFCE75E80ull +#define SFT3_HBW_RTR_IF1_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_HBW_RTR_IF1_RTR_H3_SPECIAL_SECTION 0x1800 + +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCE76000ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCE76200ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCE76400ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCE76600ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT3_HBW_RTR_IF1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCE76800ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT3_HBW_RTR_IF1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_AXUSER_BASE 0x1000007FFCE76A80ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT3_HBW_RTR_IF1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_DBG_HBW_BASE 0x1000007FFCE76B00ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_DBG_LBW_BASE 0x1000007FFCE76B80ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT3_HBW_RTR_IF1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_CORE_HBW_BASE 0x1000007FFCE76C00ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_CORE_LBW_BASE 0x1000007FFCE76D80ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT3_HBW_RTR_IF1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmSFT3_HBW_RTR_IF1_MSTR_IF_SPECIAL_BASE 0x1000007FFCE76E80ull +#define SFT3_HBW_RTR_IF1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_HBW_RTR_IF1_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmSFT3_HBW_RTR_IF1_ADDR_DEC_HBW_BASE 0x1000007FFCE77000ull +#define SFT3_HBW_RTR_IF1_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT3_HBW_RTR_IF1_ADDR_DEC_HBW_SECTION 0x4000 + +#define mmSFT3_HBW_RTR_IF1_ADDR_DEC_LBW_BASE 0x1000007FFCE77400ull +#define SFT3_HBW_RTR_IF1_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT3_HBW_RTR_IF1_ADDR_DEC_LBW_SECTION 0xA800 + +#define mmSFT3_HBW_RTR_IF1_ADDR_DEC_SPECIAL_BASE 0x1000007FFCE77E80ull +#define SFT3_HBW_RTR_IF1_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_HBW_RTR_IF1_ADDR_DEC_SPECIAL_SECTION 0x1800 + +#define mmSFT3_LBW_RTR_IF_RTR_CTRL_BASE 0x1000007FFCE78000ull +#define SFT3_LBW_RTR_IF_RTR_CTRL_MAX_OFFSET 0x1000 +#define SFT3_LBW_RTR_IF_RTR_CTRL_SECTION 0xE800 + +#define mmSFT3_LBW_RTR_IF_RTR_CTRL_SPECIAL_BASE 0x1000007FFCE78E80ull +#define SFT3_LBW_RTR_IF_RTR_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_LBW_RTR_IF_RTR_CTRL_SPECIAL_SECTION 0x1800 + +#define mmSFT3_LBW_RTR_IF_RTR_H3_BASE 0x1000007FFCE79000ull +#define SFT3_LBW_RTR_IF_RTR_H3_MAX_OFFSET 0x1000 +#define SFT3_LBW_RTR_IF_RTR_H3_SECTION 0xE800 + +#define mmSFT3_LBW_RTR_IF_RTR_H3_SPECIAL_BASE 0x1000007FFCE79E80ull +#define SFT3_LBW_RTR_IF_RTR_H3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_LBW_RTR_IF_RTR_H3_SPECIAL_SECTION 0x1800 + +#define mmSFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCE7A000ull +#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmSFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCE7A200ull +#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmSFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCE7A400ull +#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define SFT3_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmSFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCE7A600ull +#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define SFT3_LBW_RTR_IF_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmSFT3_LBW_RTR_IF_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCE7A800ull +#define SFT3_LBW_RTR_IF_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define SFT3_LBW_RTR_IF_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmSFT3_LBW_RTR_IF_MSTR_IF_AXUSER_BASE 0x1000007FFCE7AA80ull +#define SFT3_LBW_RTR_IF_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define SFT3_LBW_RTR_IF_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmSFT3_LBW_RTR_IF_MSTR_IF_DBG_HBW_BASE 0x1000007FFCE7AB00ull +#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmSFT3_LBW_RTR_IF_MSTR_IF_DBG_LBW_BASE 0x1000007FFCE7AB80ull +#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define SFT3_LBW_RTR_IF_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmSFT3_LBW_RTR_IF_MSTR_IF_CORE_HBW_BASE 0x1000007FFCE7AC00ull +#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmSFT3_LBW_RTR_IF_MSTR_IF_CORE_LBW_BASE 0x1000007FFCE7AD80ull +#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define SFT3_LBW_RTR_IF_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmSFT3_LBW_RTR_IF_MSTR_IF_SPECIAL_BASE 0x1000007FFCE7AE80ull +#define SFT3_LBW_RTR_IF_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_LBW_RTR_IF_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmSFT3_LBW_RTR_IF_ADDR_DEC_HBW_BASE 0x1000007FFCE7B000ull +#define SFT3_LBW_RTR_IF_ADDR_DEC_HBW_MAX_OFFSET 0x4000 +#define SFT3_LBW_RTR_IF_ADDR_DEC_HBW_SECTION 0x4000 + +#define mmSFT3_LBW_RTR_IF_ADDR_DEC_LBW_BASE 0x1000007FFCE7B400ull +#define SFT3_LBW_RTR_IF_ADDR_DEC_LBW_MAX_OFFSET 0xA600 +#define SFT3_LBW_RTR_IF_ADDR_DEC_LBW_SECTION 0xA800 + +#define mmSFT3_LBW_RTR_IF_ADDR_DEC_SPECIAL_BASE 0x1000007FFCE7BE80ull +#define SFT3_LBW_RTR_IF_ADDR_DEC_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_LBW_RTR_IF_ADDR_DEC_SPECIAL_SECTION 0x1800 + +#define mmSFT3_BASE 0x1000007FFCE7C000ull +#define SFT3_MAX_OFFSET 0x1000 +#define SFT3_SECTION 0xE800 + +#define mmSFT3_SPECIAL_BASE 0x1000007FFCE7CE80ull +#define SFT3_SPECIAL_MAX_OFFSET 0x1800 +#define SFT3_SPECIAL_SECTION 0x4180 + +#define mmARC_FARM_FARM_BASE 0x1000007FFCE81000ull +#define ARC_FARM_FARM_MAX_OFFSET 0x1000 +#define ARC_FARM_FARM_SECTION 0xE800 + +#define mmARC_FARM_FARM_SPECIAL_BASE 0x1000007FFCE81E80ull +#define ARC_FARM_FARM_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_FARM_SPECIAL_SECTION 0x1800 + +#define mmARC_FARM_FARM_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCE82000ull +#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmARC_FARM_FARM_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCE82200ull +#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmARC_FARM_FARM_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCE82400ull +#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define ARC_FARM_FARM_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmARC_FARM_FARM_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCE82600ull +#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define ARC_FARM_FARM_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmARC_FARM_FARM_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCE82800ull +#define ARC_FARM_FARM_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define ARC_FARM_FARM_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmARC_FARM_FARM_MSTR_IF_AXUSER_BASE 0x1000007FFCE82A80ull +#define ARC_FARM_FARM_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define ARC_FARM_FARM_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmARC_FARM_FARM_MSTR_IF_DBG_HBW_BASE 0x1000007FFCE82B00ull +#define ARC_FARM_FARM_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define ARC_FARM_FARM_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmARC_FARM_FARM_MSTR_IF_DBG_LBW_BASE 0x1000007FFCE82B80ull +#define ARC_FARM_FARM_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define ARC_FARM_FARM_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmARC_FARM_FARM_MSTR_IF_CORE_HBW_BASE 0x1000007FFCE82C00ull +#define ARC_FARM_FARM_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define ARC_FARM_FARM_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmARC_FARM_FARM_MSTR_IF_CORE_LBW_BASE 0x1000007FFCE82D80ull +#define ARC_FARM_FARM_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define ARC_FARM_FARM_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmARC_FARM_FARM_MSTR_IF_SPECIAL_BASE 0x1000007FFCE82E80ull +#define ARC_FARM_FARM_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_FARM_MSTR_IF_SPECIAL_SECTION 0x5180 + +#define mmARC_FARM_ARC0_AUX_BASE 0x1000007FFCE88000ull +#define ARC_FARM_ARC0_AUX_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC0_AUX_SECTION 0xE800 + +#define mmARC_FARM_ARC0_AUX_SPECIAL_BASE 0x1000007FFCE88E80ull +#define ARC_FARM_ARC0_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC0_AUX_SPECIAL_SECTION 0x1800 + +#define mmARC_FARM_ARC0_DUP_ENG_BASE 0x1000007FFCE89000ull +#define ARC_FARM_ARC0_DUP_ENG_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC0_DUP_ENG_SECTION 0x9000 + +#define mmARC_FARM_ARC0_DUP_ENG_AXUSER_BASE 0x1000007FFCE89900ull +#define ARC_FARM_ARC0_DUP_ENG_AXUSER_MAX_OFFSET 0x5000 +#define ARC_FARM_ARC0_DUP_ENG_AXUSER_SECTION 0x5800 + +#define mmARC_FARM_ARC0_DUP_ENG_SPECIAL_BASE 0x1000007FFCE89E80ull +#define ARC_FARM_ARC0_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC0_DUP_ENG_SPECIAL_SECTION 0x1180 + +#define mmARC_FARM_KDMA_BASE 0x1000007FFCE8B000ull +#define ARC_FARM_KDMA_MAX_OFFSET 0x1000 +#define ARC_FARM_KDMA_SECTION 0x8000 + +#define mmARC_FARM_KDMA_CTX_AXUSER_BASE 0x1000007FFCE8B800ull +#define ARC_FARM_KDMA_CTX_AXUSER_MAX_OFFSET 0x5000 +#define ARC_FARM_KDMA_CTX_AXUSER_SECTION 0x6000 + +#define mmARC_FARM_KDMA_CTX_BASE 0x1000007FFCE8B860ull +#define ARC_FARM_KDMA_CTX_MAX_OFFSET 0x9000 +#define ARC_FARM_KDMA_CTX_SECTION 0x5A00 + +#define mmARC_FARM_KDMA_KDMA_CGM_BASE 0x1000007FFCE8BE00ull +#define ARC_FARM_KDMA_KDMA_CGM_MAX_OFFSET 0xC000 +#define ARC_FARM_KDMA_KDMA_CGM_SECTION 0x8000 + +#define mmARC_FARM_KDMA_SPECIAL_BASE 0x1000007FFCE8BE80ull +#define ARC_FARM_KDMA_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_KDMA_SPECIAL_SECTION 0x1800 + +#define mmARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCE8C000ull +#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmARC_FARM_KDMA_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCE8C200ull +#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmARC_FARM_KDMA_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCE8C400ull +#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define ARC_FARM_KDMA_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmARC_FARM_KDMA_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCE8C600ull +#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define ARC_FARM_KDMA_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmARC_FARM_KDMA_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCE8C800ull +#define ARC_FARM_KDMA_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define ARC_FARM_KDMA_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmARC_FARM_KDMA_MSTR_IF_AXUSER_BASE 0x1000007FFCE8CA80ull +#define ARC_FARM_KDMA_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define ARC_FARM_KDMA_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmARC_FARM_KDMA_MSTR_IF_DBG_HBW_BASE 0x1000007FFCE8CB00ull +#define ARC_FARM_KDMA_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define ARC_FARM_KDMA_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmARC_FARM_KDMA_MSTR_IF_DBG_LBW_BASE 0x1000007FFCE8CB80ull +#define ARC_FARM_KDMA_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define ARC_FARM_KDMA_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmARC_FARM_KDMA_MSTR_IF_CORE_HBW_BASE 0x1000007FFCE8CC00ull +#define ARC_FARM_KDMA_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define ARC_FARM_KDMA_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmARC_FARM_KDMA_MSTR_IF_CORE_LBW_BASE 0x1000007FFCE8CD80ull +#define ARC_FARM_KDMA_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define ARC_FARM_KDMA_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmARC_FARM_KDMA_MSTR_IF_SPECIAL_BASE 0x1000007FFCE8CE80ull +#define ARC_FARM_KDMA_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_KDMA_MSTR_IF_SPECIAL_SECTION 0x2180 + +#define mmARC_FARM_ARC0_ACP_ENG_BASE 0x1000007FFCE8F000ull +#define ARC_FARM_ARC0_ACP_ENG_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC0_ACP_ENG_SECTION 0xE800 + +#define mmARC_FARM_ARC0_ACP_ENG_SPECIAL_BASE 0x1000007FFCE8FE80ull +#define ARC_FARM_ARC0_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC0_ACP_ENG_SPECIAL_SECTION 0x1800 + +#define mmARC_FARM_ARC0_DCCM0_BASE 0x1000007FFCE90000ull +#define ARC_FARM_ARC0_DCCM0_MAX_OFFSET 0x4000 +#define ARC_FARM_ARC0_DCCM0_SECTION 0x8000 + +#define mmARC_FARM_ARC0_DCCM1_BASE 0x1000007FFCE98000ull +#define ARC_FARM_ARC0_DCCM1_MAX_OFFSET 0x4000 +#define ARC_FARM_ARC0_DCCM1_SECTION 0x10000 + +#define mmARC_FARM_ARC1_AUX_BASE 0x1000007FFCEA8000ull +#define ARC_FARM_ARC1_AUX_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC1_AUX_SECTION 0xE800 + +#define mmARC_FARM_ARC1_AUX_SPECIAL_BASE 0x1000007FFCEA8E80ull +#define ARC_FARM_ARC1_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC1_AUX_SPECIAL_SECTION 0x1800 + +#define mmARC_FARM_ARC1_DUP_ENG_BASE 0x1000007FFCEA9000ull +#define ARC_FARM_ARC1_DUP_ENG_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC1_DUP_ENG_SECTION 0x9000 + +#define mmARC_FARM_ARC1_DUP_ENG_AXUSER_BASE 0x1000007FFCEA9900ull +#define ARC_FARM_ARC1_DUP_ENG_AXUSER_MAX_OFFSET 0x5000 +#define ARC_FARM_ARC1_DUP_ENG_AXUSER_SECTION 0x5800 + +#define mmARC_FARM_ARC1_DUP_ENG_SPECIAL_BASE 0x1000007FFCEA9E80ull +#define ARC_FARM_ARC1_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC1_DUP_ENG_SPECIAL_SECTION 0x5180 + +#define mmARC_FARM_ARC1_ACP_ENG_BASE 0x1000007FFCEAF000ull +#define ARC_FARM_ARC1_ACP_ENG_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC1_ACP_ENG_SECTION 0xE800 + +#define mmARC_FARM_ARC1_ACP_ENG_SPECIAL_BASE 0x1000007FFCEAFE80ull +#define ARC_FARM_ARC1_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC1_ACP_ENG_SPECIAL_SECTION 0x1800 + +#define mmARC_FARM_ARC1_DCCM0_BASE 0x1000007FFCEB0000ull +#define ARC_FARM_ARC1_DCCM0_MAX_OFFSET 0x4000 +#define ARC_FARM_ARC1_DCCM0_SECTION 0x8000 + +#define mmARC_FARM_ARC1_DCCM1_BASE 0x1000007FFCEB8000ull +#define ARC_FARM_ARC1_DCCM1_MAX_OFFSET 0x4000 +#define ARC_FARM_ARC1_DCCM1_SECTION 0x10000 + +#define mmARC_FARM_ARC2_AUX_BASE 0x1000007FFCEC8000ull +#define ARC_FARM_ARC2_AUX_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC2_AUX_SECTION 0xE800 + +#define mmARC_FARM_ARC2_AUX_SPECIAL_BASE 0x1000007FFCEC8E80ull +#define ARC_FARM_ARC2_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC2_AUX_SPECIAL_SECTION 0x1800 + +#define mmARC_FARM_ARC2_DUP_ENG_BASE 0x1000007FFCEC9000ull +#define ARC_FARM_ARC2_DUP_ENG_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC2_DUP_ENG_SECTION 0x9000 + +#define mmARC_FARM_ARC2_DUP_ENG_AXUSER_BASE 0x1000007FFCEC9900ull +#define ARC_FARM_ARC2_DUP_ENG_AXUSER_MAX_OFFSET 0x5000 +#define ARC_FARM_ARC2_DUP_ENG_AXUSER_SECTION 0x5800 + +#define mmARC_FARM_ARC2_DUP_ENG_SPECIAL_BASE 0x1000007FFCEC9E80ull +#define ARC_FARM_ARC2_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC2_DUP_ENG_SPECIAL_SECTION 0x5180 + +#define mmARC_FARM_ARC2_ACP_ENG_BASE 0x1000007FFCECF000ull +#define ARC_FARM_ARC2_ACP_ENG_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC2_ACP_ENG_SECTION 0xE800 + +#define mmARC_FARM_ARC2_ACP_ENG_SPECIAL_BASE 0x1000007FFCECFE80ull +#define ARC_FARM_ARC2_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC2_ACP_ENG_SPECIAL_SECTION 0x1800 + +#define mmARC_FARM_ARC2_DCCM0_BASE 0x1000007FFCED0000ull +#define ARC_FARM_ARC2_DCCM0_MAX_OFFSET 0x4000 +#define ARC_FARM_ARC2_DCCM0_SECTION 0x8000 + +#define mmARC_FARM_ARC2_DCCM1_BASE 0x1000007FFCED8000ull +#define ARC_FARM_ARC2_DCCM1_MAX_OFFSET 0x4000 +#define ARC_FARM_ARC2_DCCM1_SECTION 0x10000 + +#define mmARC_FARM_ARC3_AUX_BASE 0x1000007FFCEE8000ull +#define ARC_FARM_ARC3_AUX_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC3_AUX_SECTION 0xE800 + +#define mmARC_FARM_ARC3_AUX_SPECIAL_BASE 0x1000007FFCEE8E80ull +#define ARC_FARM_ARC3_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC3_AUX_SPECIAL_SECTION 0x1800 + +#define mmARC_FARM_ARC3_DUP_ENG_BASE 0x1000007FFCEE9000ull +#define ARC_FARM_ARC3_DUP_ENG_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC3_DUP_ENG_SECTION 0x9000 + +#define mmARC_FARM_ARC3_DUP_ENG_AXUSER_BASE 0x1000007FFCEE9900ull +#define ARC_FARM_ARC3_DUP_ENG_AXUSER_MAX_OFFSET 0x5000 +#define ARC_FARM_ARC3_DUP_ENG_AXUSER_SECTION 0x5800 + +#define mmARC_FARM_ARC3_DUP_ENG_SPECIAL_BASE 0x1000007FFCEE9E80ull +#define ARC_FARM_ARC3_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC3_DUP_ENG_SPECIAL_SECTION 0x5180 + +#define mmARC_FARM_ARC3_ACP_ENG_BASE 0x1000007FFCEEF000ull +#define ARC_FARM_ARC3_ACP_ENG_MAX_OFFSET 0x1000 +#define ARC_FARM_ARC3_ACP_ENG_SECTION 0xE800 + +#define mmARC_FARM_ARC3_ACP_ENG_SPECIAL_BASE 0x1000007FFCEEFE80ull +#define ARC_FARM_ARC3_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800 +#define ARC_FARM_ARC3_ACP_ENG_SPECIAL_SECTION 0x1800 + +#define mmARC_FARM_ARC3_DCCM0_BASE 0x1000007FFCEF0000ull +#define ARC_FARM_ARC3_DCCM0_MAX_OFFSET 0x4000 +#define ARC_FARM_ARC3_DCCM0_SECTION 0x8000 + +#define mmARC_FARM_ARC3_DCCM1_BASE 0x1000007FFCEF8000ull +#define ARC_FARM_ARC3_DCCM1_MAX_OFFSET 0x4000 +#define ARC_FARM_ARC3_DCCM1_SECTION 0x8000 + +#define mmPCIE_DEC0_CMD_BASE 0x1000007FFCF00000ull +#define PCIE_DEC0_CMD_MAX_OFFSET 0x1100 +#define PCIE_DEC0_CMD_SECTION 0x1000 + +#define mmPCIE_DEC0_VSI_BASE 0x1000007FFCF01000ull +#define PCIE_DEC0_VSI_MAX_OFFSET 0x6FC0 +#define PCIE_DEC0_VSI_SECTION 0x1000 + +#define mmPCIE_DEC0_L2C_BASE 0x1000007FFCF02000ull +#define PCIE_DEC0_L2C_MAX_OFFSET 0x39C0 +#define PCIE_DEC0_L2C_SECTION 0x1000 + +#define mmPCIE_VDEC0_BRDG_CTRL_BASE 0x1000007FFCF03000ull +#define PCIE_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_BRDG_CTRL_SECTION 0x8000 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x1000007FFCF03800ull +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x1000007FFCF03900ull +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x1000007FFCF03A00ull +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x1000007FFCF03B00ull +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 + +#define mmPCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x1000007FFCF03C00ull +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define PCIE_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 + +#define mmPCIE_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x1000007FFCF03E80ull +#define PCIE_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800 + +#define mmPCIE_VDEC0_CTRL_BASE 0x1000007FFCF04000ull +#define PCIE_VDEC0_CTRL_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_CTRL_SECTION 0xE800 + +#define mmPCIE_VDEC0_CTRL_SPECIAL_BASE 0x1000007FFCF04E80ull +#define PCIE_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_VDEC0_CTRL_SPECIAL_SECTION 0x1800 + +#define mmPCIE_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCF05000ull +#define PCIE_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PCIE_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmPCIE_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCF05200ull +#define PCIE_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PCIE_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmPCIE_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCF05400ull +#define PCIE_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PCIE_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmPCIE_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCF05600ull +#define PCIE_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PCIE_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmPCIE_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCF05800ull +#define PCIE_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PCIE_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmPCIE_VDEC0_MSTR_IF_AXUSER_BASE 0x1000007FFCF05A80ull +#define PCIE_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PCIE_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmPCIE_VDEC0_MSTR_IF_DBG_HBW_BASE 0x1000007FFCF05B00ull +#define PCIE_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PCIE_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmPCIE_VDEC0_MSTR_IF_DBG_LBW_BASE 0x1000007FFCF05B80ull +#define PCIE_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PCIE_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmPCIE_VDEC0_MSTR_IF_CORE_HBW_BASE 0x1000007FFCF05C00ull +#define PCIE_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PCIE_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmPCIE_VDEC0_MSTR_IF_CORE_LBW_BASE 0x1000007FFCF05D80ull +#define PCIE_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PCIE_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmPCIE_VDEC0_MSTR_IF_SPECIAL_BASE 0x1000007FFCF05E80ull +#define PCIE_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180 + +#define mmPCIE_DEC1_CMD_BASE 0x1000007FFCF10000ull +#define PCIE_DEC1_CMD_MAX_OFFSET 0x1100 +#define PCIE_DEC1_CMD_SECTION 0x1000 + +#define mmPCIE_DEC1_VSI_BASE 0x1000007FFCF11000ull +#define PCIE_DEC1_VSI_MAX_OFFSET 0x6FC0 +#define PCIE_DEC1_VSI_SECTION 0x1000 + +#define mmPCIE_DEC1_L2C_BASE 0x1000007FFCF12000ull +#define PCIE_DEC1_L2C_MAX_OFFSET 0x39C0 +#define PCIE_DEC1_L2C_SECTION 0x1000 + +#define mmPCIE_VDEC1_BRDG_CTRL_BASE 0x1000007FFCF13000ull +#define PCIE_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_BRDG_CTRL_SECTION 0x8000 + +#define mmPCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x1000007FFCF13800ull +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 + +#define mmPCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x1000007FFCF13900ull +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 + +#define mmPCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x1000007FFCF13A00ull +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 + +#define mmPCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x1000007FFCF13B00ull +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 + +#define mmPCIE_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x1000007FFCF13C00ull +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 +#define PCIE_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 + +#define mmPCIE_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x1000007FFCF13E80ull +#define PCIE_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800 + +#define mmPCIE_VDEC1_CTRL_BASE 0x1000007FFCF14000ull +#define PCIE_VDEC1_CTRL_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_CTRL_SECTION 0xE800 + +#define mmPCIE_VDEC1_CTRL_SPECIAL_BASE 0x1000007FFCF14E80ull +#define PCIE_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_VDEC1_CTRL_SPECIAL_SECTION 0x1800 + +#define mmPCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFCF15000ull +#define PCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define PCIE_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmPCIE_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFCF15200ull +#define PCIE_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define PCIE_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmPCIE_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFCF15400ull +#define PCIE_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define PCIE_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmPCIE_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFCF15600ull +#define PCIE_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define PCIE_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmPCIE_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFCF15800ull +#define PCIE_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define PCIE_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmPCIE_VDEC1_MSTR_IF_AXUSER_BASE 0x1000007FFCF15A80ull +#define PCIE_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define PCIE_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmPCIE_VDEC1_MSTR_IF_DBG_HBW_BASE 0x1000007FFCF15B00ull +#define PCIE_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define PCIE_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmPCIE_VDEC1_MSTR_IF_DBG_LBW_BASE 0x1000007FFCF15B80ull +#define PCIE_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define PCIE_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmPCIE_VDEC1_MSTR_IF_CORE_HBW_BASE 0x1000007FFCF15C00ull +#define PCIE_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define PCIE_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmPCIE_VDEC1_MSTR_IF_CORE_LBW_BASE 0x1000007FFCF15D80ull +#define PCIE_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define PCIE_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmPCIE_VDEC1_MSTR_IF_SPECIAL_BASE 0x1000007FFCF15E80ull +#define PCIE_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define PCIE_VDEC1_MSTR_IF_SPECIAL_SECTION 0x2A180 + +#define mmDCORE0_XFT_BASE 0x1000007FFCF40000ull +#define DCORE0_XFT_MAX_OFFSET 0x1000 +#define DCORE0_XFT_SECTION 0xE800 + +#define mmDCORE0_XFT_SPECIAL_BASE 0x1000007FFCF40E80ull +#define DCORE0_XFT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_XFT_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_HBM_PLL_CTRL_BASE 0x1000007FFCF41000ull +#define DCORE0_HBM_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE0_HBM_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE0_HBM_PLL_ASIF_SLV_BASE 0x1000007FFCF41360ull +#define DCORE0_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE0_HBM_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE0_HBM_PLL_DIV_0_RLX_BASE 0x1000007FFCF41400ull +#define DCORE0_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE0_HBM_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE0_HBM_PLL_DIV_1_RLX_BASE 0x1000007FFCF41800ull +#define DCORE0_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE0_HBM_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE0_HBM_PLL_DIV_2_RLX_BASE 0x1000007FFCF41A00ull +#define DCORE0_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE0_HBM_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE0_HBM_PLL_DIV_3_RLX_BASE 0x1000007FFCF41C00ull +#define DCORE0_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE0_HBM_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE0_HBM_PLL_SPECIAL_BASE 0x1000007FFCF41E80ull +#define DCORE0_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_HBM_PLL_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_TPC_PLL_CTRL_BASE 0x1000007FFCF42000ull +#define DCORE0_TPC_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE0_TPC_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE0_TPC_PLL_ASIF_SLV_BASE 0x1000007FFCF42360ull +#define DCORE0_TPC_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE0_TPC_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE0_TPC_PLL_DIV_0_RLX_BASE 0x1000007FFCF42400ull +#define DCORE0_TPC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE0_TPC_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE0_TPC_PLL_DIV_1_RLX_BASE 0x1000007FFCF42800ull +#define DCORE0_TPC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE0_TPC_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE0_TPC_PLL_DIV_2_RLX_BASE 0x1000007FFCF42A00ull +#define DCORE0_TPC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE0_TPC_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE0_TPC_PLL_DIV_3_RLX_BASE 0x1000007FFCF42C00ull +#define DCORE0_TPC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE0_TPC_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE0_TPC_PLL_SPECIAL_BASE 0x1000007FFCF42E80ull +#define DCORE0_TPC_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_TPC_PLL_SPECIAL_SECTION 0x1800 + +#define mmDCORE0_PCI_PLL_CTRL_BASE 0x1000007FFCF43000ull +#define DCORE0_PCI_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE0_PCI_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE0_PCI_PLL_ASIF_SLV_BASE 0x1000007FFCF43360ull +#define DCORE0_PCI_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE0_PCI_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE0_PCI_PLL_DIV_0_RLX_BASE 0x1000007FFCF43400ull +#define DCORE0_PCI_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE0_PCI_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE0_PCI_PLL_DIV_1_RLX_BASE 0x1000007FFCF43800ull +#define DCORE0_PCI_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE0_PCI_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE0_PCI_PLL_DIV_2_RLX_BASE 0x1000007FFCF43A00ull +#define DCORE0_PCI_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE0_PCI_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE0_PCI_PLL_DIV_3_RLX_BASE 0x1000007FFCF43C00ull +#define DCORE0_PCI_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE0_PCI_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE0_PCI_PLL_SPECIAL_BASE 0x1000007FFCF43E80ull +#define DCORE0_PCI_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE0_PCI_PLL_SPECIAL_SECTION 0x1180 + +#define mmDCORE0_TSTDVS_BASE 0x1000007FFCF45000ull +#define DCORE0_TSTDVS_MAX_OFFSET 0x7800 +#define DCORE0_TSTDVS_SECTION 0x1000 + +#define mmDCORE0_TS_WRAP_BASE 0x1000007FFCF46000ull +#define DCORE0_TS_WRAP_MAX_OFFSET 0x2380 +#define DCORE0_TS_WRAP_SECTION 0x2000 + +#define mmDCORE0_TS_WRAP_ASIF_SLV_BASE 0x1000007FFCF46200ull +#define DCORE0_TS_WRAP_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE0_TS_WRAP_ASIF_SLV_SECTION 0x9E00 + +#define mmDCORE1_XFT_BASE 0x1000007FFCF50000ull +#define DCORE1_XFT_MAX_OFFSET 0x1000 +#define DCORE1_XFT_SECTION 0xE800 + +#define mmDCORE1_XFT_SPECIAL_BASE 0x1000007FFCF50E80ull +#define DCORE1_XFT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_XFT_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_HBM_PLL_CTRL_BASE 0x1000007FFCF51000ull +#define DCORE1_HBM_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE1_HBM_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE1_HBM_PLL_ASIF_SLV_BASE 0x1000007FFCF51360ull +#define DCORE1_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_HBM_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE1_HBM_PLL_DIV_0_RLX_BASE 0x1000007FFCF51400ull +#define DCORE1_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE1_HBM_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE1_HBM_PLL_DIV_1_RLX_BASE 0x1000007FFCF51800ull +#define DCORE1_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE1_HBM_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE1_HBM_PLL_DIV_2_RLX_BASE 0x1000007FFCF51A00ull +#define DCORE1_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE1_HBM_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE1_HBM_PLL_DIV_3_RLX_BASE 0x1000007FFCF51C00ull +#define DCORE1_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE1_HBM_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE1_HBM_PLL_SPECIAL_BASE 0x1000007FFCF51E80ull +#define DCORE1_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_HBM_PLL_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_TPC_PLL_CTRL_BASE 0x1000007FFCF52000ull +#define DCORE1_TPC_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE1_TPC_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE1_TPC_PLL_ASIF_SLV_BASE 0x1000007FFCF52360ull +#define DCORE1_TPC_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_TPC_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE1_TPC_PLL_DIV_0_RLX_BASE 0x1000007FFCF52400ull +#define DCORE1_TPC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE1_TPC_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE1_TPC_PLL_DIV_1_RLX_BASE 0x1000007FFCF52800ull +#define DCORE1_TPC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE1_TPC_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE1_TPC_PLL_DIV_2_RLX_BASE 0x1000007FFCF52A00ull +#define DCORE1_TPC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE1_TPC_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE1_TPC_PLL_DIV_3_RLX_BASE 0x1000007FFCF52C00ull +#define DCORE1_TPC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE1_TPC_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE1_TPC_PLL_SPECIAL_BASE 0x1000007FFCF52E80ull +#define DCORE1_TPC_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_TPC_PLL_SPECIAL_SECTION 0x1800 + +#define mmDCORE1_NIC_PLL_CTRL_BASE 0x1000007FFCF53000ull +#define DCORE1_NIC_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE1_NIC_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE1_NIC_PLL_ASIF_SLV_BASE 0x1000007FFCF53360ull +#define DCORE1_NIC_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_NIC_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE1_NIC_PLL_DIV_0_RLX_BASE 0x1000007FFCF53400ull +#define DCORE1_NIC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE1_NIC_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE1_NIC_PLL_DIV_1_RLX_BASE 0x1000007FFCF53800ull +#define DCORE1_NIC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE1_NIC_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE1_NIC_PLL_DIV_2_RLX_BASE 0x1000007FFCF53A00ull +#define DCORE1_NIC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE1_NIC_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE1_NIC_PLL_DIV_3_RLX_BASE 0x1000007FFCF53C00ull +#define DCORE1_NIC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE1_NIC_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE1_NIC_PLL_SPECIAL_BASE 0x1000007FFCF53E80ull +#define DCORE1_NIC_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE1_NIC_PLL_SPECIAL_SECTION 0x1180 + +#define mmDCORE1_TSTDVS_BASE 0x1000007FFCF55000ull +#define DCORE1_TSTDVS_MAX_OFFSET 0x7800 +#define DCORE1_TSTDVS_SECTION 0x1000 + +#define mmDCORE1_TS_WRAP_BASE 0x1000007FFCF56000ull +#define DCORE1_TS_WRAP_MAX_OFFSET 0x2380 +#define DCORE1_TS_WRAP_SECTION 0x2000 + +#define mmDCORE1_TS_WRAP_ASIF_SLV_BASE 0x1000007FFCF56200ull +#define DCORE1_TS_WRAP_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE1_TS_WRAP_ASIF_SLV_SECTION 0x9E00 + +#define mmDCORE2_XFT_BASE 0x1000007FFCF60000ull +#define DCORE2_XFT_MAX_OFFSET 0x1000 +#define DCORE2_XFT_SECTION 0xE800 + +#define mmDCORE2_XFT_SPECIAL_BASE 0x1000007FFCF60E80ull +#define DCORE2_XFT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_XFT_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_HBM_PLL_CTRL_BASE 0x1000007FFCF61000ull +#define DCORE2_HBM_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE2_HBM_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE2_HBM_PLL_ASIF_SLV_BASE 0x1000007FFCF61360ull +#define DCORE2_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE2_HBM_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE2_HBM_PLL_DIV_0_RLX_BASE 0x1000007FFCF61400ull +#define DCORE2_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE2_HBM_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE2_HBM_PLL_DIV_1_RLX_BASE 0x1000007FFCF61800ull +#define DCORE2_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE2_HBM_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE2_HBM_PLL_DIV_2_RLX_BASE 0x1000007FFCF61A00ull +#define DCORE2_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE2_HBM_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE2_HBM_PLL_DIV_3_RLX_BASE 0x1000007FFCF61C00ull +#define DCORE2_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE2_HBM_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE2_HBM_PLL_SPECIAL_BASE 0x1000007FFCF61E80ull +#define DCORE2_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_HBM_PLL_SPECIAL_SECTION 0x1800 + +#define mmDCORE2_TPC_PLL_CTRL_BASE 0x1000007FFCF62000ull +#define DCORE2_TPC_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE2_TPC_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE2_TPC_PLL_ASIF_SLV_BASE 0x1000007FFCF62360ull +#define DCORE2_TPC_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE2_TPC_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE2_TPC_PLL_DIV_0_RLX_BASE 0x1000007FFCF62400ull +#define DCORE2_TPC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE2_TPC_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE2_TPC_PLL_DIV_1_RLX_BASE 0x1000007FFCF62800ull +#define DCORE2_TPC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE2_TPC_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE2_TPC_PLL_DIV_2_RLX_BASE 0x1000007FFCF62A00ull +#define DCORE2_TPC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE2_TPC_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE2_TPC_PLL_DIV_3_RLX_BASE 0x1000007FFCF62C00ull +#define DCORE2_TPC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE2_TPC_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE2_TPC_PLL_SPECIAL_BASE 0x1000007FFCF62E80ull +#define DCORE2_TPC_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE2_TPC_PLL_SPECIAL_SECTION 0x2180 + +#define mmDCORE2_TSTDVS_BASE 0x1000007FFCF65000ull +#define DCORE2_TSTDVS_MAX_OFFSET 0x7800 +#define DCORE2_TSTDVS_SECTION 0x1000 + +#define mmDCORE2_TS_WRAP_BASE 0x1000007FFCF66000ull +#define DCORE2_TS_WRAP_MAX_OFFSET 0x2380 +#define DCORE2_TS_WRAP_SECTION 0x2000 + +#define mmDCORE2_TS_WRAP_ASIF_SLV_BASE 0x1000007FFCF66200ull +#define DCORE2_TS_WRAP_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE2_TS_WRAP_ASIF_SLV_SECTION 0x9E00 + +#define mmDCORE3_XFT_BASE 0x1000007FFCF70000ull +#define DCORE3_XFT_MAX_OFFSET 0x1000 +#define DCORE3_XFT_SECTION 0xE800 + +#define mmDCORE3_XFT_SPECIAL_BASE 0x1000007FFCF70E80ull +#define DCORE3_XFT_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_XFT_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_HBM_PLL_CTRL_BASE 0x1000007FFCF71000ull +#define DCORE3_HBM_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE3_HBM_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE3_HBM_PLL_ASIF_SLV_BASE 0x1000007FFCF71360ull +#define DCORE3_HBM_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE3_HBM_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE3_HBM_PLL_DIV_0_RLX_BASE 0x1000007FFCF71400ull +#define DCORE3_HBM_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE3_HBM_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE3_HBM_PLL_DIV_1_RLX_BASE 0x1000007FFCF71800ull +#define DCORE3_HBM_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE3_HBM_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE3_HBM_PLL_DIV_2_RLX_BASE 0x1000007FFCF71A00ull +#define DCORE3_HBM_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE3_HBM_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE3_HBM_PLL_DIV_3_RLX_BASE 0x1000007FFCF71C00ull +#define DCORE3_HBM_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE3_HBM_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE3_HBM_PLL_SPECIAL_BASE 0x1000007FFCF71E80ull +#define DCORE3_HBM_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_HBM_PLL_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_TPC_PLL_CTRL_BASE 0x1000007FFCF72000ull +#define DCORE3_TPC_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE3_TPC_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE3_TPC_PLL_ASIF_SLV_BASE 0x1000007FFCF72360ull +#define DCORE3_TPC_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE3_TPC_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE3_TPC_PLL_DIV_0_RLX_BASE 0x1000007FFCF72400ull +#define DCORE3_TPC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE3_TPC_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE3_TPC_PLL_DIV_1_RLX_BASE 0x1000007FFCF72800ull +#define DCORE3_TPC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE3_TPC_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE3_TPC_PLL_DIV_2_RLX_BASE 0x1000007FFCF72A00ull +#define DCORE3_TPC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE3_TPC_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE3_TPC_PLL_DIV_3_RLX_BASE 0x1000007FFCF72C00ull +#define DCORE3_TPC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE3_TPC_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE3_TPC_PLL_SPECIAL_BASE 0x1000007FFCF72E80ull +#define DCORE3_TPC_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_TPC_PLL_SPECIAL_SECTION 0x1800 + +#define mmDCORE3_NIC_PLL_CTRL_BASE 0x1000007FFCF73000ull +#define DCORE3_NIC_PLL_CTRL_MAX_OFFSET 0x3540 +#define DCORE3_NIC_PLL_CTRL_SECTION 0x3600 + +#define mmDCORE3_NIC_PLL_ASIF_SLV_BASE 0x1000007FFCF73360ull +#define DCORE3_NIC_PLL_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE3_NIC_PLL_ASIF_SLV_SECTION 0xA000 + +#define mmDCORE3_NIC_PLL_DIV_0_RLX_BASE 0x1000007FFCF73400ull +#define DCORE3_NIC_PLL_DIV_0_RLX_MAX_OFFSET 0x1800 +#define DCORE3_NIC_PLL_DIV_0_RLX_SECTION 0x4000 + +#define mmDCORE3_NIC_PLL_DIV_1_RLX_BASE 0x1000007FFCF73800ull +#define DCORE3_NIC_PLL_DIV_1_RLX_MAX_OFFSET 0xC000 +#define DCORE3_NIC_PLL_DIV_1_RLX_SECTION 0x2000 + +#define mmDCORE3_NIC_PLL_DIV_2_RLX_BASE 0x1000007FFCF73A00ull +#define DCORE3_NIC_PLL_DIV_2_RLX_MAX_OFFSET 0xC000 +#define DCORE3_NIC_PLL_DIV_2_RLX_SECTION 0x2000 + +#define mmDCORE3_NIC_PLL_DIV_3_RLX_BASE 0x1000007FFCF73C00ull +#define DCORE3_NIC_PLL_DIV_3_RLX_MAX_OFFSET 0xC000 +#define DCORE3_NIC_PLL_DIV_3_RLX_SECTION 0x2800 + +#define mmDCORE3_NIC_PLL_SPECIAL_BASE 0x1000007FFCF73E80ull +#define DCORE3_NIC_PLL_SPECIAL_MAX_OFFSET 0x1800 +#define DCORE3_NIC_PLL_SPECIAL_SECTION 0x1180 + +#define mmDCORE3_TSTDVS_BASE 0x1000007FFCF75000ull +#define DCORE3_TSTDVS_MAX_OFFSET 0x7800 +#define DCORE3_TSTDVS_SECTION 0x1000 + +#define mmDCORE3_TS_WRAP_BASE 0x1000007FFCF76000ull +#define DCORE3_TS_WRAP_MAX_OFFSET 0x2380 +#define DCORE3_TS_WRAP_SECTION 0x2000 + +#define mmDCORE3_TS_WRAP_ASIF_SLV_BASE 0x1000007FFCF76200ull +#define DCORE3_TS_WRAP_ASIF_SLV_MAX_OFFSET 0x3800 +#define DCORE3_TS_WRAP_ASIF_SLV_SECTION 0x9E00 + +#define mmPCIE_PMA_2_BASE 0x1000007FFCF80000ull +#define PCIE_PMA_2_MAX_OFFSET 0x40000 +#define PCIE_PMA_2_SECTION 0x40000 + +#define mmPCIE_PMA_3_BASE 0x1000007FFCFC0000ull +#define PCIE_PMA_3_MAX_OFFSET 0x40000 +#define PCIE_PMA_3_SECTION 0x40000 + +#define mmHBM0_MC0_BASE 0x1000007FFD000000ull +#define HBM0_MC0_MAX_OFFSET 0x1000 +#define HBM0_MC0_SECTION 0xE800 + +#define mmHBM0_MC0_SPECIAL_BASE 0x1000007FFD000E80ull +#define HBM0_MC0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0_SPECIAL_SECTION 0x1800 + +#define mmHBM0_MC0BIST0_BASE 0x1000007FFD001000ull +#define HBM0_MC0BIST0_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST0_SECTION 0xE800 + +#define mmHBM0_MC0BIST0_SPECIAL_BASE 0x1000007FFD001E80ull +#define HBM0_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST0_SPECIAL_SECTION 0x1800 + +#define mmHBM0_MC0BIST1_BASE 0x1000007FFD002000ull +#define HBM0_MC0BIST1_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST1_SECTION 0xE800 + +#define mmHBM0_MC0BIST1_SPECIAL_BASE 0x1000007FFD002E80ull +#define HBM0_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST1_SPECIAL_SECTION 0x1800 + +#define mmHBM0_MC0BIST2_BASE 0x1000007FFD003000ull +#define HBM0_MC0BIST2_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST2_SECTION 0xE800 + +#define mmHBM0_MC0BIST2_SPECIAL_BASE 0x1000007FFD003E80ull +#define HBM0_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST2_SPECIAL_SECTION 0x1800 + +#define mmHBM0_MC0BIST3_BASE 0x1000007FFD004000ull +#define HBM0_MC0BIST3_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST3_SECTION 0xE800 + +#define mmHBM0_MC0BIST3_SPECIAL_BASE 0x1000007FFD004E80ull +#define HBM0_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST3_SPECIAL_SECTION 0x1800 + +#define mmHBM0_MC0BIST4_BASE 0x1000007FFD005000ull +#define HBM0_MC0BIST4_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST4_SECTION 0xE800 + +#define mmHBM0_MC0BIST4_SPECIAL_BASE 0x1000007FFD005E80ull +#define HBM0_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST4_SPECIAL_SECTION 0x1800 + +#define mmHBM0_MC0BIST5_BASE 0x1000007FFD006000ull +#define HBM0_MC0BIST5_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST5_SECTION 0xE800 + +#define mmHBM0_MC0BIST5_SPECIAL_BASE 0x1000007FFD006E80ull +#define HBM0_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST5_SPECIAL_SECTION 0x1800 + +#define mmHBM0_MC0BIST6_BASE 0x1000007FFD007000ull +#define HBM0_MC0BIST6_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST6_SECTION 0xE800 + +#define mmHBM0_MC0BIST6_SPECIAL_BASE 0x1000007FFD007E80ull +#define HBM0_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST6_SPECIAL_SECTION 0x1800 + +#define mmHBM0_MC0BIST7_BASE 0x1000007FFD008000ull +#define HBM0_MC0BIST7_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST7_SECTION 0xE800 + +#define mmHBM0_MC0BIST7_SPECIAL_BASE 0x1000007FFD008E80ull +#define HBM0_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST7_SPECIAL_SECTION 0x1800 + +#define mmHBM0_MC0BIST8_MEM_BASE 0x1000007FFD009000ull +#define HBM0_MC0BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM0_MC0BIST8_MEM_SECTION 0xE800 + +#define mmHBM0_MC0BIST8_MEM_SPECIAL_BASE 0x1000007FFD009E80ull +#define HBM0_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC0BIST8_MEM_SPECIAL_SECTION 0x16180 + +#define mmHBM0_MC1_BASE 0x1000007FFD020000ull +#define HBM0_MC1_MAX_OFFSET 0x1000 +#define HBM0_MC1_SECTION 0xE800 + +#define mmHBM0_MC1_SPECIAL_BASE 0x1000007FFD020E80ull +#define HBM0_MC1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1_SPECIAL_SECTION 0x1800 + +#define mmHBM0_MC1BIST0_BASE 0x1000007FFD021000ull +#define HBM0_MC1BIST0_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST0_SECTION 0xE800 + +#define mmHBM0_MC1BIST0_SPECIAL_BASE 0x1000007FFD021E80ull +#define HBM0_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST0_SPECIAL_SECTION 0x1800 + +#define mmHBM0_MC1BIST1_BASE 0x1000007FFD022000ull +#define HBM0_MC1BIST1_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST1_SECTION 0xE800 + +#define mmHBM0_MC1BIST1_SPECIAL_BASE 0x1000007FFD022E80ull +#define HBM0_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST1_SPECIAL_SECTION 0x1800 + +#define mmHBM0_MC1BIST2_BASE 0x1000007FFD023000ull +#define HBM0_MC1BIST2_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST2_SECTION 0xE800 + +#define mmHBM0_MC1BIST2_SPECIAL_BASE 0x1000007FFD023E80ull +#define HBM0_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST2_SPECIAL_SECTION 0x1800 + +#define mmHBM0_MC1BIST3_BASE 0x1000007FFD024000ull +#define HBM0_MC1BIST3_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST3_SECTION 0xE800 + +#define mmHBM0_MC1BIST3_SPECIAL_BASE 0x1000007FFD024E80ull +#define HBM0_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST3_SPECIAL_SECTION 0x1800 + +#define mmHBM0_MC1BIST4_BASE 0x1000007FFD025000ull +#define HBM0_MC1BIST4_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST4_SECTION 0xE800 + +#define mmHBM0_MC1BIST4_SPECIAL_BASE 0x1000007FFD025E80ull +#define HBM0_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST4_SPECIAL_SECTION 0x1800 + +#define mmHBM0_MC1BIST5_BASE 0x1000007FFD026000ull +#define HBM0_MC1BIST5_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST5_SECTION 0xE800 + +#define mmHBM0_MC1BIST5_SPECIAL_BASE 0x1000007FFD026E80ull +#define HBM0_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST5_SPECIAL_SECTION 0x1800 + +#define mmHBM0_MC1BIST6_BASE 0x1000007FFD027000ull +#define HBM0_MC1BIST6_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST6_SECTION 0xE800 + +#define mmHBM0_MC1BIST6_SPECIAL_BASE 0x1000007FFD027E80ull +#define HBM0_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST6_SPECIAL_SECTION 0x1800 + +#define mmHBM0_MC1BIST7_BASE 0x1000007FFD028000ull +#define HBM0_MC1BIST7_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST7_SECTION 0xE800 + +#define mmHBM0_MC1BIST7_SPECIAL_BASE 0x1000007FFD028E80ull +#define HBM0_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST7_SPECIAL_SECTION 0x1800 + +#define mmHBM0_MC1BIST8_MEM_BASE 0x1000007FFD029000ull +#define HBM0_MC1BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM0_MC1BIST8_MEM_SECTION 0xE800 + +#define mmHBM0_MC1BIST8_MEM_SPECIAL_BASE 0x1000007FFD029E80ull +#define HBM0_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM0_MC1BIST8_MEM_SPECIAL_SECTION 0x16180 + +#define mmHBM0_PHY_BASE 0x1000007FFD040000ull +#define HBM0_PHY_MAX_OFFSET 0x4000 +#define HBM0_PHY_SECTION 0x40000 + +#define mmHBM1_MC0_BASE 0x1000007FFD080000ull +#define HBM1_MC0_MAX_OFFSET 0x1000 +#define HBM1_MC0_SECTION 0xE800 + +#define mmHBM1_MC0_SPECIAL_BASE 0x1000007FFD080E80ull +#define HBM1_MC0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0_SPECIAL_SECTION 0x1800 + +#define mmHBM1_MC0BIST0_BASE 0x1000007FFD081000ull +#define HBM1_MC0BIST0_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST0_SECTION 0xE800 + +#define mmHBM1_MC0BIST0_SPECIAL_BASE 0x1000007FFD081E80ull +#define HBM1_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST0_SPECIAL_SECTION 0x1800 + +#define mmHBM1_MC0BIST1_BASE 0x1000007FFD082000ull +#define HBM1_MC0BIST1_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST1_SECTION 0xE800 + +#define mmHBM1_MC0BIST1_SPECIAL_BASE 0x1000007FFD082E80ull +#define HBM1_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST1_SPECIAL_SECTION 0x1800 + +#define mmHBM1_MC0BIST2_BASE 0x1000007FFD083000ull +#define HBM1_MC0BIST2_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST2_SECTION 0xE800 + +#define mmHBM1_MC0BIST2_SPECIAL_BASE 0x1000007FFD083E80ull +#define HBM1_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST2_SPECIAL_SECTION 0x1800 + +#define mmHBM1_MC0BIST3_BASE 0x1000007FFD084000ull +#define HBM1_MC0BIST3_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST3_SECTION 0xE800 + +#define mmHBM1_MC0BIST3_SPECIAL_BASE 0x1000007FFD084E80ull +#define HBM1_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST3_SPECIAL_SECTION 0x1800 + +#define mmHBM1_MC0BIST4_BASE 0x1000007FFD085000ull +#define HBM1_MC0BIST4_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST4_SECTION 0xE800 + +#define mmHBM1_MC0BIST4_SPECIAL_BASE 0x1000007FFD085E80ull +#define HBM1_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST4_SPECIAL_SECTION 0x1800 + +#define mmHBM1_MC0BIST5_BASE 0x1000007FFD086000ull +#define HBM1_MC0BIST5_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST5_SECTION 0xE800 + +#define mmHBM1_MC0BIST5_SPECIAL_BASE 0x1000007FFD086E80ull +#define HBM1_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST5_SPECIAL_SECTION 0x1800 + +#define mmHBM1_MC0BIST6_BASE 0x1000007FFD087000ull +#define HBM1_MC0BIST6_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST6_SECTION 0xE800 + +#define mmHBM1_MC0BIST6_SPECIAL_BASE 0x1000007FFD087E80ull +#define HBM1_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST6_SPECIAL_SECTION 0x1800 + +#define mmHBM1_MC0BIST7_BASE 0x1000007FFD088000ull +#define HBM1_MC0BIST7_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST7_SECTION 0xE800 + +#define mmHBM1_MC0BIST7_SPECIAL_BASE 0x1000007FFD088E80ull +#define HBM1_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST7_SPECIAL_SECTION 0x1800 + +#define mmHBM1_MC0BIST8_MEM_BASE 0x1000007FFD089000ull +#define HBM1_MC0BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM1_MC0BIST8_MEM_SECTION 0xE800 + +#define mmHBM1_MC0BIST8_MEM_SPECIAL_BASE 0x1000007FFD089E80ull +#define HBM1_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC0BIST8_MEM_SPECIAL_SECTION 0x16180 + +#define mmHBM1_MC1_BASE 0x1000007FFD0A0000ull +#define HBM1_MC1_MAX_OFFSET 0x1000 +#define HBM1_MC1_SECTION 0xE800 + +#define mmHBM1_MC1_SPECIAL_BASE 0x1000007FFD0A0E80ull +#define HBM1_MC1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1_SPECIAL_SECTION 0x1800 + +#define mmHBM1_MC1BIST0_BASE 0x1000007FFD0A1000ull +#define HBM1_MC1BIST0_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST0_SECTION 0xE800 + +#define mmHBM1_MC1BIST0_SPECIAL_BASE 0x1000007FFD0A1E80ull +#define HBM1_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST0_SPECIAL_SECTION 0x1800 + +#define mmHBM1_MC1BIST1_BASE 0x1000007FFD0A2000ull +#define HBM1_MC1BIST1_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST1_SECTION 0xE800 + +#define mmHBM1_MC1BIST1_SPECIAL_BASE 0x1000007FFD0A2E80ull +#define HBM1_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST1_SPECIAL_SECTION 0x1800 + +#define mmHBM1_MC1BIST2_BASE 0x1000007FFD0A3000ull +#define HBM1_MC1BIST2_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST2_SECTION 0xE800 + +#define mmHBM1_MC1BIST2_SPECIAL_BASE 0x1000007FFD0A3E80ull +#define HBM1_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST2_SPECIAL_SECTION 0x1800 + +#define mmHBM1_MC1BIST3_BASE 0x1000007FFD0A4000ull +#define HBM1_MC1BIST3_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST3_SECTION 0xE800 + +#define mmHBM1_MC1BIST3_SPECIAL_BASE 0x1000007FFD0A4E80ull +#define HBM1_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST3_SPECIAL_SECTION 0x1800 + +#define mmHBM1_MC1BIST4_BASE 0x1000007FFD0A5000ull +#define HBM1_MC1BIST4_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST4_SECTION 0xE800 + +#define mmHBM1_MC1BIST4_SPECIAL_BASE 0x1000007FFD0A5E80ull +#define HBM1_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST4_SPECIAL_SECTION 0x1800 + +#define mmHBM1_MC1BIST5_BASE 0x1000007FFD0A6000ull +#define HBM1_MC1BIST5_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST5_SECTION 0xE800 + +#define mmHBM1_MC1BIST5_SPECIAL_BASE 0x1000007FFD0A6E80ull +#define HBM1_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST5_SPECIAL_SECTION 0x1800 + +#define mmHBM1_MC1BIST6_BASE 0x1000007FFD0A7000ull +#define HBM1_MC1BIST6_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST6_SECTION 0xE800 + +#define mmHBM1_MC1BIST6_SPECIAL_BASE 0x1000007FFD0A7E80ull +#define HBM1_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST6_SPECIAL_SECTION 0x1800 + +#define mmHBM1_MC1BIST7_BASE 0x1000007FFD0A8000ull +#define HBM1_MC1BIST7_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST7_SECTION 0xE800 + +#define mmHBM1_MC1BIST7_SPECIAL_BASE 0x1000007FFD0A8E80ull +#define HBM1_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST7_SPECIAL_SECTION 0x1800 + +#define mmHBM1_MC1BIST8_MEM_BASE 0x1000007FFD0A9000ull +#define HBM1_MC1BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM1_MC1BIST8_MEM_SECTION 0xE800 + +#define mmHBM1_MC1BIST8_MEM_SPECIAL_BASE 0x1000007FFD0A9E80ull +#define HBM1_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM1_MC1BIST8_MEM_SPECIAL_SECTION 0x16180 + +#define mmHBM1_PHY_BASE 0x1000007FFD0C0000ull +#define HBM1_PHY_MAX_OFFSET 0x4000 +#define HBM1_PHY_SECTION 0x40000 + +#define mmHBM2_MC0_BASE 0x1000007FFD100000ull +#define HBM2_MC0_MAX_OFFSET 0x1000 +#define HBM2_MC0_SECTION 0xE800 + +#define mmHBM2_MC0_SPECIAL_BASE 0x1000007FFD100E80ull +#define HBM2_MC0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0_SPECIAL_SECTION 0x1800 + +#define mmHBM2_MC0BIST0_BASE 0x1000007FFD101000ull +#define HBM2_MC0BIST0_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST0_SECTION 0xE800 + +#define mmHBM2_MC0BIST0_SPECIAL_BASE 0x1000007FFD101E80ull +#define HBM2_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST0_SPECIAL_SECTION 0x1800 + +#define mmHBM2_MC0BIST1_BASE 0x1000007FFD102000ull +#define HBM2_MC0BIST1_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST1_SECTION 0xE800 + +#define mmHBM2_MC0BIST1_SPECIAL_BASE 0x1000007FFD102E80ull +#define HBM2_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST1_SPECIAL_SECTION 0x1800 + +#define mmHBM2_MC0BIST2_BASE 0x1000007FFD103000ull +#define HBM2_MC0BIST2_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST2_SECTION 0xE800 + +#define mmHBM2_MC0BIST2_SPECIAL_BASE 0x1000007FFD103E80ull +#define HBM2_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST2_SPECIAL_SECTION 0x1800 + +#define mmHBM2_MC0BIST3_BASE 0x1000007FFD104000ull +#define HBM2_MC0BIST3_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST3_SECTION 0xE800 + +#define mmHBM2_MC0BIST3_SPECIAL_BASE 0x1000007FFD104E80ull +#define HBM2_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST3_SPECIAL_SECTION 0x1800 + +#define mmHBM2_MC0BIST4_BASE 0x1000007FFD105000ull +#define HBM2_MC0BIST4_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST4_SECTION 0xE800 + +#define mmHBM2_MC0BIST4_SPECIAL_BASE 0x1000007FFD105E80ull +#define HBM2_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST4_SPECIAL_SECTION 0x1800 + +#define mmHBM2_MC0BIST5_BASE 0x1000007FFD106000ull +#define HBM2_MC0BIST5_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST5_SECTION 0xE800 + +#define mmHBM2_MC0BIST5_SPECIAL_BASE 0x1000007FFD106E80ull +#define HBM2_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST5_SPECIAL_SECTION 0x1800 + +#define mmHBM2_MC0BIST6_BASE 0x1000007FFD107000ull +#define HBM2_MC0BIST6_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST6_SECTION 0xE800 + +#define mmHBM2_MC0BIST6_SPECIAL_BASE 0x1000007FFD107E80ull +#define HBM2_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST6_SPECIAL_SECTION 0x1800 + +#define mmHBM2_MC0BIST7_BASE 0x1000007FFD108000ull +#define HBM2_MC0BIST7_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST7_SECTION 0xE800 + +#define mmHBM2_MC0BIST7_SPECIAL_BASE 0x1000007FFD108E80ull +#define HBM2_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST7_SPECIAL_SECTION 0x1800 + +#define mmHBM2_MC0BIST8_MEM_BASE 0x1000007FFD109000ull +#define HBM2_MC0BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM2_MC0BIST8_MEM_SECTION 0xE800 + +#define mmHBM2_MC0BIST8_MEM_SPECIAL_BASE 0x1000007FFD109E80ull +#define HBM2_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC0BIST8_MEM_SPECIAL_SECTION 0x16180 + +#define mmHBM2_MC1_BASE 0x1000007FFD120000ull +#define HBM2_MC1_MAX_OFFSET 0x1000 +#define HBM2_MC1_SECTION 0xE800 + +#define mmHBM2_MC1_SPECIAL_BASE 0x1000007FFD120E80ull +#define HBM2_MC1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1_SPECIAL_SECTION 0x1800 + +#define mmHBM2_MC1BIST0_BASE 0x1000007FFD121000ull +#define HBM2_MC1BIST0_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST0_SECTION 0xE800 + +#define mmHBM2_MC1BIST0_SPECIAL_BASE 0x1000007FFD121E80ull +#define HBM2_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST0_SPECIAL_SECTION 0x1800 + +#define mmHBM2_MC1BIST1_BASE 0x1000007FFD122000ull +#define HBM2_MC1BIST1_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST1_SECTION 0xE800 + +#define mmHBM2_MC1BIST1_SPECIAL_BASE 0x1000007FFD122E80ull +#define HBM2_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST1_SPECIAL_SECTION 0x1800 + +#define mmHBM2_MC1BIST2_BASE 0x1000007FFD123000ull +#define HBM2_MC1BIST2_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST2_SECTION 0xE800 + +#define mmHBM2_MC1BIST2_SPECIAL_BASE 0x1000007FFD123E80ull +#define HBM2_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST2_SPECIAL_SECTION 0x1800 + +#define mmHBM2_MC1BIST3_BASE 0x1000007FFD124000ull +#define HBM2_MC1BIST3_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST3_SECTION 0xE800 + +#define mmHBM2_MC1BIST3_SPECIAL_BASE 0x1000007FFD124E80ull +#define HBM2_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST3_SPECIAL_SECTION 0x1800 + +#define mmHBM2_MC1BIST4_BASE 0x1000007FFD125000ull +#define HBM2_MC1BIST4_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST4_SECTION 0xE800 + +#define mmHBM2_MC1BIST4_SPECIAL_BASE 0x1000007FFD125E80ull +#define HBM2_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST4_SPECIAL_SECTION 0x1800 + +#define mmHBM2_MC1BIST5_BASE 0x1000007FFD126000ull +#define HBM2_MC1BIST5_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST5_SECTION 0xE800 + +#define mmHBM2_MC1BIST5_SPECIAL_BASE 0x1000007FFD126E80ull +#define HBM2_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST5_SPECIAL_SECTION 0x1800 + +#define mmHBM2_MC1BIST6_BASE 0x1000007FFD127000ull +#define HBM2_MC1BIST6_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST6_SECTION 0xE800 + +#define mmHBM2_MC1BIST6_SPECIAL_BASE 0x1000007FFD127E80ull +#define HBM2_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST6_SPECIAL_SECTION 0x1800 + +#define mmHBM2_MC1BIST7_BASE 0x1000007FFD128000ull +#define HBM2_MC1BIST7_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST7_SECTION 0xE800 + +#define mmHBM2_MC1BIST7_SPECIAL_BASE 0x1000007FFD128E80ull +#define HBM2_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST7_SPECIAL_SECTION 0x1800 + +#define mmHBM2_MC1BIST8_MEM_BASE 0x1000007FFD129000ull +#define HBM2_MC1BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM2_MC1BIST8_MEM_SECTION 0xE800 + +#define mmHBM2_MC1BIST8_MEM_SPECIAL_BASE 0x1000007FFD129E80ull +#define HBM2_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM2_MC1BIST8_MEM_SPECIAL_SECTION 0x16180 + +#define mmHBM2_PHY_BASE 0x1000007FFD140000ull +#define HBM2_PHY_MAX_OFFSET 0x4000 +#define HBM2_PHY_SECTION 0x40000 + +#define mmHBM3_MC0_BASE 0x1000007FFD180000ull +#define HBM3_MC0_MAX_OFFSET 0x1000 +#define HBM3_MC0_SECTION 0xE800 + +#define mmHBM3_MC0_SPECIAL_BASE 0x1000007FFD180E80ull +#define HBM3_MC0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0_SPECIAL_SECTION 0x1800 + +#define mmHBM3_MC0BIST0_BASE 0x1000007FFD181000ull +#define HBM3_MC0BIST0_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST0_SECTION 0xE800 + +#define mmHBM3_MC0BIST0_SPECIAL_BASE 0x1000007FFD181E80ull +#define HBM3_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST0_SPECIAL_SECTION 0x1800 + +#define mmHBM3_MC0BIST1_BASE 0x1000007FFD182000ull +#define HBM3_MC0BIST1_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST1_SECTION 0xE800 + +#define mmHBM3_MC0BIST1_SPECIAL_BASE 0x1000007FFD182E80ull +#define HBM3_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST1_SPECIAL_SECTION 0x1800 + +#define mmHBM3_MC0BIST2_BASE 0x1000007FFD183000ull +#define HBM3_MC0BIST2_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST2_SECTION 0xE800 + +#define mmHBM3_MC0BIST2_SPECIAL_BASE 0x1000007FFD183E80ull +#define HBM3_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST2_SPECIAL_SECTION 0x1800 + +#define mmHBM3_MC0BIST3_BASE 0x1000007FFD184000ull +#define HBM3_MC0BIST3_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST3_SECTION 0xE800 + +#define mmHBM3_MC0BIST3_SPECIAL_BASE 0x1000007FFD184E80ull +#define HBM3_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST3_SPECIAL_SECTION 0x1800 + +#define mmHBM3_MC0BIST4_BASE 0x1000007FFD185000ull +#define HBM3_MC0BIST4_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST4_SECTION 0xE800 + +#define mmHBM3_MC0BIST4_SPECIAL_BASE 0x1000007FFD185E80ull +#define HBM3_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST4_SPECIAL_SECTION 0x1800 + +#define mmHBM3_MC0BIST5_BASE 0x1000007FFD186000ull +#define HBM3_MC0BIST5_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST5_SECTION 0xE800 + +#define mmHBM3_MC0BIST5_SPECIAL_BASE 0x1000007FFD186E80ull +#define HBM3_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST5_SPECIAL_SECTION 0x1800 + +#define mmHBM3_MC0BIST6_BASE 0x1000007FFD187000ull +#define HBM3_MC0BIST6_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST6_SECTION 0xE800 + +#define mmHBM3_MC0BIST6_SPECIAL_BASE 0x1000007FFD187E80ull +#define HBM3_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST6_SPECIAL_SECTION 0x1800 + +#define mmHBM3_MC0BIST7_BASE 0x1000007FFD188000ull +#define HBM3_MC0BIST7_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST7_SECTION 0xE800 + +#define mmHBM3_MC0BIST7_SPECIAL_BASE 0x1000007FFD188E80ull +#define HBM3_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST7_SPECIAL_SECTION 0x1800 + +#define mmHBM3_MC0BIST8_MEM_BASE 0x1000007FFD189000ull +#define HBM3_MC0BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM3_MC0BIST8_MEM_SECTION 0xE800 + +#define mmHBM3_MC0BIST8_MEM_SPECIAL_BASE 0x1000007FFD189E80ull +#define HBM3_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC0BIST8_MEM_SPECIAL_SECTION 0x16180 + +#define mmHBM3_MC1_BASE 0x1000007FFD1A0000ull +#define HBM3_MC1_MAX_OFFSET 0x1000 +#define HBM3_MC1_SECTION 0xE800 + +#define mmHBM3_MC1_SPECIAL_BASE 0x1000007FFD1A0E80ull +#define HBM3_MC1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1_SPECIAL_SECTION 0x1800 + +#define mmHBM3_MC1BIST0_BASE 0x1000007FFD1A1000ull +#define HBM3_MC1BIST0_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST0_SECTION 0xE800 + +#define mmHBM3_MC1BIST0_SPECIAL_BASE 0x1000007FFD1A1E80ull +#define HBM3_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST0_SPECIAL_SECTION 0x1800 + +#define mmHBM3_MC1BIST1_BASE 0x1000007FFD1A2000ull +#define HBM3_MC1BIST1_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST1_SECTION 0xE800 + +#define mmHBM3_MC1BIST1_SPECIAL_BASE 0x1000007FFD1A2E80ull +#define HBM3_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST1_SPECIAL_SECTION 0x1800 + +#define mmHBM3_MC1BIST2_BASE 0x1000007FFD1A3000ull +#define HBM3_MC1BIST2_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST2_SECTION 0xE800 + +#define mmHBM3_MC1BIST2_SPECIAL_BASE 0x1000007FFD1A3E80ull +#define HBM3_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST2_SPECIAL_SECTION 0x1800 + +#define mmHBM3_MC1BIST3_BASE 0x1000007FFD1A4000ull +#define HBM3_MC1BIST3_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST3_SECTION 0xE800 + +#define mmHBM3_MC1BIST3_SPECIAL_BASE 0x1000007FFD1A4E80ull +#define HBM3_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST3_SPECIAL_SECTION 0x1800 + +#define mmHBM3_MC1BIST4_BASE 0x1000007FFD1A5000ull +#define HBM3_MC1BIST4_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST4_SECTION 0xE800 + +#define mmHBM3_MC1BIST4_SPECIAL_BASE 0x1000007FFD1A5E80ull +#define HBM3_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST4_SPECIAL_SECTION 0x1800 + +#define mmHBM3_MC1BIST5_BASE 0x1000007FFD1A6000ull +#define HBM3_MC1BIST5_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST5_SECTION 0xE800 + +#define mmHBM3_MC1BIST5_SPECIAL_BASE 0x1000007FFD1A6E80ull +#define HBM3_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST5_SPECIAL_SECTION 0x1800 + +#define mmHBM3_MC1BIST6_BASE 0x1000007FFD1A7000ull +#define HBM3_MC1BIST6_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST6_SECTION 0xE800 + +#define mmHBM3_MC1BIST6_SPECIAL_BASE 0x1000007FFD1A7E80ull +#define HBM3_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST6_SPECIAL_SECTION 0x1800 + +#define mmHBM3_MC1BIST7_BASE 0x1000007FFD1A8000ull +#define HBM3_MC1BIST7_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST7_SECTION 0xE800 + +#define mmHBM3_MC1BIST7_SPECIAL_BASE 0x1000007FFD1A8E80ull +#define HBM3_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST7_SPECIAL_SECTION 0x1800 + +#define mmHBM3_MC1BIST8_MEM_BASE 0x1000007FFD1A9000ull +#define HBM3_MC1BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM3_MC1BIST8_MEM_SECTION 0xE800 + +#define mmHBM3_MC1BIST8_MEM_SPECIAL_BASE 0x1000007FFD1A9E80ull +#define HBM3_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM3_MC1BIST8_MEM_SPECIAL_SECTION 0x16180 + +#define mmHBM3_PHY_BASE 0x1000007FFD1C0000ull +#define HBM3_PHY_MAX_OFFSET 0x4000 +#define HBM3_PHY_SECTION 0x40000 + +#define mmHBM4_MC0_BASE 0x1000007FFD200000ull +#define HBM4_MC0_MAX_OFFSET 0x1000 +#define HBM4_MC0_SECTION 0xE800 + +#define mmHBM4_MC0_SPECIAL_BASE 0x1000007FFD200E80ull +#define HBM4_MC0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0_SPECIAL_SECTION 0x1800 + +#define mmHBM4_MC0BIST0_BASE 0x1000007FFD201000ull +#define HBM4_MC0BIST0_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST0_SECTION 0xE800 + +#define mmHBM4_MC0BIST0_SPECIAL_BASE 0x1000007FFD201E80ull +#define HBM4_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST0_SPECIAL_SECTION 0x1800 + +#define mmHBM4_MC0BIST1_BASE 0x1000007FFD202000ull +#define HBM4_MC0BIST1_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST1_SECTION 0xE800 + +#define mmHBM4_MC0BIST1_SPECIAL_BASE 0x1000007FFD202E80ull +#define HBM4_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST1_SPECIAL_SECTION 0x1800 + +#define mmHBM4_MC0BIST2_BASE 0x1000007FFD203000ull +#define HBM4_MC0BIST2_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST2_SECTION 0xE800 + +#define mmHBM4_MC0BIST2_SPECIAL_BASE 0x1000007FFD203E80ull +#define HBM4_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST2_SPECIAL_SECTION 0x1800 + +#define mmHBM4_MC0BIST3_BASE 0x1000007FFD204000ull +#define HBM4_MC0BIST3_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST3_SECTION 0xE800 + +#define mmHBM4_MC0BIST3_SPECIAL_BASE 0x1000007FFD204E80ull +#define HBM4_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST3_SPECIAL_SECTION 0x1800 + +#define mmHBM4_MC0BIST4_BASE 0x1000007FFD205000ull +#define HBM4_MC0BIST4_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST4_SECTION 0xE800 + +#define mmHBM4_MC0BIST4_SPECIAL_BASE 0x1000007FFD205E80ull +#define HBM4_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST4_SPECIAL_SECTION 0x1800 + +#define mmHBM4_MC0BIST5_BASE 0x1000007FFD206000ull +#define HBM4_MC0BIST5_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST5_SECTION 0xE800 + +#define mmHBM4_MC0BIST5_SPECIAL_BASE 0x1000007FFD206E80ull +#define HBM4_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST5_SPECIAL_SECTION 0x1800 + +#define mmHBM4_MC0BIST6_BASE 0x1000007FFD207000ull +#define HBM4_MC0BIST6_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST6_SECTION 0xE800 + +#define mmHBM4_MC0BIST6_SPECIAL_BASE 0x1000007FFD207E80ull +#define HBM4_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST6_SPECIAL_SECTION 0x1800 + +#define mmHBM4_MC0BIST7_BASE 0x1000007FFD208000ull +#define HBM4_MC0BIST7_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST7_SECTION 0xE800 + +#define mmHBM4_MC0BIST7_SPECIAL_BASE 0x1000007FFD208E80ull +#define HBM4_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST7_SPECIAL_SECTION 0x1800 + +#define mmHBM4_MC0BIST8_MEM_BASE 0x1000007FFD209000ull +#define HBM4_MC0BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM4_MC0BIST8_MEM_SECTION 0xE800 + +#define mmHBM4_MC0BIST8_MEM_SPECIAL_BASE 0x1000007FFD209E80ull +#define HBM4_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC0BIST8_MEM_SPECIAL_SECTION 0x16180 + +#define mmHBM4_MC1_BASE 0x1000007FFD220000ull +#define HBM4_MC1_MAX_OFFSET 0x1000 +#define HBM4_MC1_SECTION 0xE800 + +#define mmHBM4_MC1_SPECIAL_BASE 0x1000007FFD220E80ull +#define HBM4_MC1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1_SPECIAL_SECTION 0x1800 + +#define mmHBM4_MC1BIST0_BASE 0x1000007FFD221000ull +#define HBM4_MC1BIST0_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST0_SECTION 0xE800 + +#define mmHBM4_MC1BIST0_SPECIAL_BASE 0x1000007FFD221E80ull +#define HBM4_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST0_SPECIAL_SECTION 0x1800 + +#define mmHBM4_MC1BIST1_BASE 0x1000007FFD222000ull +#define HBM4_MC1BIST1_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST1_SECTION 0xE800 + +#define mmHBM4_MC1BIST1_SPECIAL_BASE 0x1000007FFD222E80ull +#define HBM4_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST1_SPECIAL_SECTION 0x1800 + +#define mmHBM4_MC1BIST2_BASE 0x1000007FFD223000ull +#define HBM4_MC1BIST2_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST2_SECTION 0xE800 + +#define mmHBM4_MC1BIST2_SPECIAL_BASE 0x1000007FFD223E80ull +#define HBM4_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST2_SPECIAL_SECTION 0x1800 + +#define mmHBM4_MC1BIST3_BASE 0x1000007FFD224000ull +#define HBM4_MC1BIST3_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST3_SECTION 0xE800 + +#define mmHBM4_MC1BIST3_SPECIAL_BASE 0x1000007FFD224E80ull +#define HBM4_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST3_SPECIAL_SECTION 0x1800 + +#define mmHBM4_MC1BIST4_BASE 0x1000007FFD225000ull +#define HBM4_MC1BIST4_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST4_SECTION 0xE800 + +#define mmHBM4_MC1BIST4_SPECIAL_BASE 0x1000007FFD225E80ull +#define HBM4_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST4_SPECIAL_SECTION 0x1800 + +#define mmHBM4_MC1BIST5_BASE 0x1000007FFD226000ull +#define HBM4_MC1BIST5_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST5_SECTION 0xE800 + +#define mmHBM4_MC1BIST5_SPECIAL_BASE 0x1000007FFD226E80ull +#define HBM4_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST5_SPECIAL_SECTION 0x1800 + +#define mmHBM4_MC1BIST6_BASE 0x1000007FFD227000ull +#define HBM4_MC1BIST6_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST6_SECTION 0xE800 + +#define mmHBM4_MC1BIST6_SPECIAL_BASE 0x1000007FFD227E80ull +#define HBM4_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST6_SPECIAL_SECTION 0x1800 + +#define mmHBM4_MC1BIST7_BASE 0x1000007FFD228000ull +#define HBM4_MC1BIST7_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST7_SECTION 0xE800 + +#define mmHBM4_MC1BIST7_SPECIAL_BASE 0x1000007FFD228E80ull +#define HBM4_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST7_SPECIAL_SECTION 0x1800 + +#define mmHBM4_MC1BIST8_MEM_BASE 0x1000007FFD229000ull +#define HBM4_MC1BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM4_MC1BIST8_MEM_SECTION 0xE800 + +#define mmHBM4_MC1BIST8_MEM_SPECIAL_BASE 0x1000007FFD229E80ull +#define HBM4_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM4_MC1BIST8_MEM_SPECIAL_SECTION 0x16180 + +#define mmHBM4_PHY_BASE 0x1000007FFD240000ull +#define HBM4_PHY_MAX_OFFSET 0x4000 +#define HBM4_PHY_SECTION 0x40000 + +#define mmHBM5_MC0_BASE 0x1000007FFD280000ull +#define HBM5_MC0_MAX_OFFSET 0x1000 +#define HBM5_MC0_SECTION 0xE800 + +#define mmHBM5_MC0_SPECIAL_BASE 0x1000007FFD280E80ull +#define HBM5_MC0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0_SPECIAL_SECTION 0x1800 + +#define mmHBM5_MC0BIST0_BASE 0x1000007FFD281000ull +#define HBM5_MC0BIST0_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST0_SECTION 0xE800 + +#define mmHBM5_MC0BIST0_SPECIAL_BASE 0x1000007FFD281E80ull +#define HBM5_MC0BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST0_SPECIAL_SECTION 0x1800 + +#define mmHBM5_MC0BIST1_BASE 0x1000007FFD282000ull +#define HBM5_MC0BIST1_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST1_SECTION 0xE800 + +#define mmHBM5_MC0BIST1_SPECIAL_BASE 0x1000007FFD282E80ull +#define HBM5_MC0BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST1_SPECIAL_SECTION 0x1800 + +#define mmHBM5_MC0BIST2_BASE 0x1000007FFD283000ull +#define HBM5_MC0BIST2_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST2_SECTION 0xE800 + +#define mmHBM5_MC0BIST2_SPECIAL_BASE 0x1000007FFD283E80ull +#define HBM5_MC0BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST2_SPECIAL_SECTION 0x1800 + +#define mmHBM5_MC0BIST3_BASE 0x1000007FFD284000ull +#define HBM5_MC0BIST3_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST3_SECTION 0xE800 + +#define mmHBM5_MC0BIST3_SPECIAL_BASE 0x1000007FFD284E80ull +#define HBM5_MC0BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST3_SPECIAL_SECTION 0x1800 + +#define mmHBM5_MC0BIST4_BASE 0x1000007FFD285000ull +#define HBM5_MC0BIST4_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST4_SECTION 0xE800 + +#define mmHBM5_MC0BIST4_SPECIAL_BASE 0x1000007FFD285E80ull +#define HBM5_MC0BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST4_SPECIAL_SECTION 0x1800 + +#define mmHBM5_MC0BIST5_BASE 0x1000007FFD286000ull +#define HBM5_MC0BIST5_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST5_SECTION 0xE800 + +#define mmHBM5_MC0BIST5_SPECIAL_BASE 0x1000007FFD286E80ull +#define HBM5_MC0BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST5_SPECIAL_SECTION 0x1800 + +#define mmHBM5_MC0BIST6_BASE 0x1000007FFD287000ull +#define HBM5_MC0BIST6_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST6_SECTION 0xE800 + +#define mmHBM5_MC0BIST6_SPECIAL_BASE 0x1000007FFD287E80ull +#define HBM5_MC0BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST6_SPECIAL_SECTION 0x1800 + +#define mmHBM5_MC0BIST7_BASE 0x1000007FFD288000ull +#define HBM5_MC0BIST7_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST7_SECTION 0xE800 + +#define mmHBM5_MC0BIST7_SPECIAL_BASE 0x1000007FFD288E80ull +#define HBM5_MC0BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST7_SPECIAL_SECTION 0x1800 + +#define mmHBM5_MC0BIST8_MEM_BASE 0x1000007FFD289000ull +#define HBM5_MC0BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM5_MC0BIST8_MEM_SECTION 0xE800 + +#define mmHBM5_MC0BIST8_MEM_SPECIAL_BASE 0x1000007FFD289E80ull +#define HBM5_MC0BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC0BIST8_MEM_SPECIAL_SECTION 0x16180 + +#define mmHBM5_MC1_BASE 0x1000007FFD2A0000ull +#define HBM5_MC1_MAX_OFFSET 0x1000 +#define HBM5_MC1_SECTION 0xE800 + +#define mmHBM5_MC1_SPECIAL_BASE 0x1000007FFD2A0E80ull +#define HBM5_MC1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1_SPECIAL_SECTION 0x1800 + +#define mmHBM5_MC1BIST0_BASE 0x1000007FFD2A1000ull +#define HBM5_MC1BIST0_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST0_SECTION 0xE800 + +#define mmHBM5_MC1BIST0_SPECIAL_BASE 0x1000007FFD2A1E80ull +#define HBM5_MC1BIST0_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST0_SPECIAL_SECTION 0x1800 + +#define mmHBM5_MC1BIST1_BASE 0x1000007FFD2A2000ull +#define HBM5_MC1BIST1_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST1_SECTION 0xE800 + +#define mmHBM5_MC1BIST1_SPECIAL_BASE 0x1000007FFD2A2E80ull +#define HBM5_MC1BIST1_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST1_SPECIAL_SECTION 0x1800 + +#define mmHBM5_MC1BIST2_BASE 0x1000007FFD2A3000ull +#define HBM5_MC1BIST2_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST2_SECTION 0xE800 + +#define mmHBM5_MC1BIST2_SPECIAL_BASE 0x1000007FFD2A3E80ull +#define HBM5_MC1BIST2_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST2_SPECIAL_SECTION 0x1800 + +#define mmHBM5_MC1BIST3_BASE 0x1000007FFD2A4000ull +#define HBM5_MC1BIST3_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST3_SECTION 0xE800 + +#define mmHBM5_MC1BIST3_SPECIAL_BASE 0x1000007FFD2A4E80ull +#define HBM5_MC1BIST3_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST3_SPECIAL_SECTION 0x1800 + +#define mmHBM5_MC1BIST4_BASE 0x1000007FFD2A5000ull +#define HBM5_MC1BIST4_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST4_SECTION 0xE800 + +#define mmHBM5_MC1BIST4_SPECIAL_BASE 0x1000007FFD2A5E80ull +#define HBM5_MC1BIST4_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST4_SPECIAL_SECTION 0x1800 + +#define mmHBM5_MC1BIST5_BASE 0x1000007FFD2A6000ull +#define HBM5_MC1BIST5_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST5_SECTION 0xE800 + +#define mmHBM5_MC1BIST5_SPECIAL_BASE 0x1000007FFD2A6E80ull +#define HBM5_MC1BIST5_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST5_SPECIAL_SECTION 0x1800 + +#define mmHBM5_MC1BIST6_BASE 0x1000007FFD2A7000ull +#define HBM5_MC1BIST6_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST6_SECTION 0xE800 + +#define mmHBM5_MC1BIST6_SPECIAL_BASE 0x1000007FFD2A7E80ull +#define HBM5_MC1BIST6_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST6_SPECIAL_SECTION 0x1800 + +#define mmHBM5_MC1BIST7_BASE 0x1000007FFD2A8000ull +#define HBM5_MC1BIST7_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST7_SECTION 0xE800 + +#define mmHBM5_MC1BIST7_SPECIAL_BASE 0x1000007FFD2A8E80ull +#define HBM5_MC1BIST7_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST7_SPECIAL_SECTION 0x1800 + +#define mmHBM5_MC1BIST8_MEM_BASE 0x1000007FFD2A9000ull +#define HBM5_MC1BIST8_MEM_MAX_OFFSET 0x1000 +#define HBM5_MC1BIST8_MEM_SECTION 0xE800 + +#define mmHBM5_MC1BIST8_MEM_SPECIAL_BASE 0x1000007FFD2A9E80ull +#define HBM5_MC1BIST8_MEM_SPECIAL_MAX_OFFSET 0x1800 +#define HBM5_MC1BIST8_MEM_SPECIAL_SECTION 0x16180 + +#define mmHBM5_PHY_BASE 0x1000007FFD2C0000ull +#define HBM5_PHY_MAX_OFFSET 0x4000 +#define HBM5_PHY_SECTION 0x140000 + +#define mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE 0x1000007FFD400000ull +#define NIC0_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR0_0_UNSECURE_DOORBELL1_BASE 0x1000007FFD400080ull +#define NIC0_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD400100ull +#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD400180ull +#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR0_0_SPECIAL_BASE 0x1000007FFD400E80ull +#define NIC0_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_0_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR0_1_UNSECURE_DOORBELL0_BASE 0x1000007FFD401000ull +#define NIC0_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR0_1_UNSECURE_DOORBELL1_BASE 0x1000007FFD401080ull +#define NIC0_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD401100ull +#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD401180ull +#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR0_1_SPECIAL_BASE 0x1000007FFD401E80ull +#define NIC0_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_1_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR0_2_UNSECURE_DOORBELL0_BASE 0x1000007FFD402000ull +#define NIC0_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR0_2_UNSECURE_DOORBELL1_BASE 0x1000007FFD402080ull +#define NIC0_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD402100ull +#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD402180ull +#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR0_2_SPECIAL_BASE 0x1000007FFD402E80ull +#define NIC0_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_2_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR0_3_UNSECURE_DOORBELL0_BASE 0x1000007FFD403000ull +#define NIC0_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR0_3_UNSECURE_DOORBELL1_BASE 0x1000007FFD403080ull +#define NIC0_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD403100ull +#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD403180ull +#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR0_3_SPECIAL_BASE 0x1000007FFD403E80ull +#define NIC0_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_3_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR0_4_UNSECURE_DOORBELL0_BASE 0x1000007FFD404000ull +#define NIC0_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR0_4_UNSECURE_DOORBELL1_BASE 0x1000007FFD404080ull +#define NIC0_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD404100ull +#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD404180ull +#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR0_4_SPECIAL_BASE 0x1000007FFD404E80ull +#define NIC0_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_4_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR0_5_UNSECURE_DOORBELL0_BASE 0x1000007FFD405000ull +#define NIC0_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR0_5_UNSECURE_DOORBELL1_BASE 0x1000007FFD405080ull +#define NIC0_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD405100ull +#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD405180ull +#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR0_5_SPECIAL_BASE 0x1000007FFD405E80ull +#define NIC0_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_5_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR0_6_UNSECURE_DOORBELL0_BASE 0x1000007FFD406000ull +#define NIC0_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR0_6_UNSECURE_DOORBELL1_BASE 0x1000007FFD406080ull +#define NIC0_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD406100ull +#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD406180ull +#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR0_6_SPECIAL_BASE 0x1000007FFD406E80ull +#define NIC0_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_6_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR0_7_UNSECURE_DOORBELL0_BASE 0x1000007FFD407000ull +#define NIC0_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR0_7_UNSECURE_DOORBELL1_BASE 0x1000007FFD407080ull +#define NIC0_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD407100ull +#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD407180ull +#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR0_7_SPECIAL_BASE 0x1000007FFD407E80ull +#define NIC0_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_7_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR0_8_UNSECURE_DOORBELL0_BASE 0x1000007FFD408000ull +#define NIC0_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR0_8_UNSECURE_DOORBELL1_BASE 0x1000007FFD408080ull +#define NIC0_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD408100ull +#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD408180ull +#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR0_8_SPECIAL_BASE 0x1000007FFD408E80ull +#define NIC0_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_8_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR0_9_UNSECURE_DOORBELL0_BASE 0x1000007FFD409000ull +#define NIC0_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR0_9_UNSECURE_DOORBELL1_BASE 0x1000007FFD409080ull +#define NIC0_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD409100ull +#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD409180ull +#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR0_9_SPECIAL_BASE 0x1000007FFD409E80ull +#define NIC0_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_9_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR0_10_UNSECURE_DOORBELL0_BASE 0x1000007FFD40A000ull +#define NIC0_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR0_10_UNSECURE_DOORBELL1_BASE 0x1000007FFD40A080ull +#define NIC0_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD40A100ull +#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD40A180ull +#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR0_10_SPECIAL_BASE 0x1000007FFD40AE80ull +#define NIC0_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_10_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR0_11_UNSECURE_DOORBELL0_BASE 0x1000007FFD40B000ull +#define NIC0_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR0_11_UNSECURE_DOORBELL1_BASE 0x1000007FFD40B080ull +#define NIC0_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD40B100ull +#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD40B180ull +#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR0_11_SPECIAL_BASE 0x1000007FFD40BE80ull +#define NIC0_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_11_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR0_12_UNSECURE_DOORBELL0_BASE 0x1000007FFD40C000ull +#define NIC0_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR0_12_UNSECURE_DOORBELL1_BASE 0x1000007FFD40C080ull +#define NIC0_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD40C100ull +#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD40C180ull +#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR0_12_SPECIAL_BASE 0x1000007FFD40CE80ull +#define NIC0_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_12_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR0_13_UNSECURE_DOORBELL0_BASE 0x1000007FFD40D000ull +#define NIC0_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR0_13_UNSECURE_DOORBELL1_BASE 0x1000007FFD40D080ull +#define NIC0_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD40D100ull +#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD40D180ull +#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR0_13_SPECIAL_BASE 0x1000007FFD40DE80ull +#define NIC0_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_13_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR0_14_UNSECURE_DOORBELL0_BASE 0x1000007FFD40E000ull +#define NIC0_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR0_14_UNSECURE_DOORBELL1_BASE 0x1000007FFD40E080ull +#define NIC0_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD40E100ull +#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD40E180ull +#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR0_14_SPECIAL_BASE 0x1000007FFD40EE80ull +#define NIC0_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR0_14_SPECIAL_SECTION 0x1180 + +#define mmNIC0_QM_DCCM0_BASE 0x1000007FFD410000ull +#define NIC0_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC0_QM_DCCM0_SECTION 0x8000 + +#define mmNIC0_QM_ARC_AUX0_BASE 0x1000007FFD418000ull +#define NIC0_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC0_QM_ARC_AUX0_SECTION 0xE800 + +#define mmNIC0_QM_ARC_AUX0_SPECIAL_BASE 0x1000007FFD418E80ull +#define NIC0_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 + +#define mmNIC0_QM0_BASE 0x1000007FFD41A000ull +#define NIC0_QM0_MAX_OFFSET 0x1000 +#define NIC0_QM0_SECTION 0x9000 + +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFD41A900ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFD41A908ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFD41A910ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFD41A918ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFD41A920ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFD41A928ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFD41A930ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFD41A938ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFD41A940ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFD41A948ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFD41A950ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFD41A958ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFD41A960ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFD41A968ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFD41A970ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmNIC0_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFD41A978ull +#define NIC0_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC0_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmNIC0_QM0_AXUSER_SECURED_BASE 0x1000007FFD41AB00ull +#define NIC0_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC0_QM0_AXUSER_SECURED_SECTION 0x8000 + +#define mmNIC0_QM0_AXUSER_NONSECURED_BASE 0x1000007FFD41AB80ull +#define NIC0_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC0_QM0_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmNIC0_QM0_DBG_HBW_BASE 0x1000007FFD41AC00ull +#define NIC0_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC0_QM0_DBG_HBW_SECTION 0x8000 + +#define mmNIC0_QM0_DBG_LBW_BASE 0x1000007FFD41AC80ull +#define NIC0_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC0_QM0_DBG_LBW_SECTION 0x1000 + +#define mmNIC0_QM0_CGM_BASE 0x1000007FFD41AD80ull +#define NIC0_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC0_QM0_CGM_SECTION 0x1000 + +#define mmNIC0_QM0_SPECIAL_BASE 0x1000007FFD41AE80ull +#define NIC0_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_QM0_SPECIAL_SECTION 0x4180 + +#define mmNIC0_QPC0_BASE 0x1000007FFD41F000ull +#define NIC0_QPC0_MAX_OFFSET 0x1000 +#define NIC0_QPC0_SECTION 0x7200 + +#define mmNIC0_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x1000007FFD41F720ull +#define NIC0_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x1000007FFD41F728ull +#define NIC0_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x1000007FFD41F730ull +#define NIC0_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x1000007FFD41F738ull +#define NIC0_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x1000007FFD41F740ull +#define NIC0_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x1000007FFD41F748ull +#define NIC0_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x1000007FFD41F750ull +#define NIC0_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x1000007FFD41F758ull +#define NIC0_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x1000007FFD41F760ull +#define NIC0_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x1000007FFD41F768ull +#define NIC0_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x1000007FFD41F770ull +#define NIC0_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x1000007FFD41F778ull +#define NIC0_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x1000007FFD41F780ull +#define NIC0_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x1000007FFD41F788ull +#define NIC0_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x1000007FFD41F790ull +#define NIC0_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x1000007FFD41F798ull +#define NIC0_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x1000007FFD41F7A0ull +#define NIC0_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x1000007FFD41F7A8ull +#define NIC0_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x1000007FFD41F7B0ull +#define NIC0_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x1000007FFD41F7B8ull +#define NIC0_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x1000007FFD41F7C0ull +#define NIC0_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x1000007FFD41F7C8ull +#define NIC0_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x1000007FFD41F7D0ull +#define NIC0_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x1000007FFD41F7D8ull +#define NIC0_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x1000007FFD41F7E0ull +#define NIC0_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x1000007FFD41F7E8ull +#define NIC0_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x1000007FFD41F7F0ull +#define NIC0_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x1000007FFD41F7F8ull +#define NIC0_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x1000007FFD41F800ull +#define NIC0_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x1000007FFD41F808ull +#define NIC0_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x1000007FFD41F810ull +#define NIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x1000007FFD41F818ull +#define NIC0_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 + +#define mmNIC0_QPC0_AXUSER_CONG_QUE_BASE 0x1000007FFD41FB80ull +#define NIC0_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC0_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 + +#define mmNIC0_QPC0_AXUSER_RXWQE_BASE 0x1000007FFD41FBE0ull +#define NIC0_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC0_QPC0_AXUSER_RXWQE_SECTION 0x6000 + +#define mmNIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x1000007FFD41FC40ull +#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC0_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 + +#define mmNIC0_QPC0_AXUSER_DB_FIFO_BASE 0x1000007FFD41FCA0ull +#define NIC0_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC0_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 + +#define mmNIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x1000007FFD41FD00ull +#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC0_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 + +#define mmNIC0_QPC0_AXUSER_ERR_FIFO_BASE 0x1000007FFD41FD60ull +#define NIC0_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC0_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 + +#define mmNIC0_QPC0_AXUSER_QPC_RESP_BASE 0x1000007FFD41FDC0ull +#define NIC0_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC0_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 + +#define mmNIC0_QPC0_AXUSER_QPC_REQ_BASE 0x1000007FFD41FE20ull +#define NIC0_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC0_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 + +#define mmNIC0_QPC0_SPECIAL_BASE 0x1000007FFD41FE80ull +#define NIC0_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_QPC0_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR1_0_UNSECURE_DOORBELL0_BASE 0x1000007FFD420000ull +#define NIC0_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR1_0_UNSECURE_DOORBELL1_BASE 0x1000007FFD420080ull +#define NIC0_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD420100ull +#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD420180ull +#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR1_0_SPECIAL_BASE 0x1000007FFD420E80ull +#define NIC0_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_0_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR1_1_UNSECURE_DOORBELL0_BASE 0x1000007FFD421000ull +#define NIC0_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR1_1_UNSECURE_DOORBELL1_BASE 0x1000007FFD421080ull +#define NIC0_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD421100ull +#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD421180ull +#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR1_1_SPECIAL_BASE 0x1000007FFD421E80ull +#define NIC0_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_1_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR1_2_UNSECURE_DOORBELL0_BASE 0x1000007FFD422000ull +#define NIC0_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR1_2_UNSECURE_DOORBELL1_BASE 0x1000007FFD422080ull +#define NIC0_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD422100ull +#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD422180ull +#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR1_2_SPECIAL_BASE 0x1000007FFD422E80ull +#define NIC0_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_2_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR1_3_UNSECURE_DOORBELL0_BASE 0x1000007FFD423000ull +#define NIC0_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR1_3_UNSECURE_DOORBELL1_BASE 0x1000007FFD423080ull +#define NIC0_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD423100ull +#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD423180ull +#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR1_3_SPECIAL_BASE 0x1000007FFD423E80ull +#define NIC0_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_3_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR1_4_UNSECURE_DOORBELL0_BASE 0x1000007FFD424000ull +#define NIC0_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR1_4_UNSECURE_DOORBELL1_BASE 0x1000007FFD424080ull +#define NIC0_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD424100ull +#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD424180ull +#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR1_4_SPECIAL_BASE 0x1000007FFD424E80ull +#define NIC0_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_4_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR1_5_UNSECURE_DOORBELL0_BASE 0x1000007FFD425000ull +#define NIC0_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR1_5_UNSECURE_DOORBELL1_BASE 0x1000007FFD425080ull +#define NIC0_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD425100ull +#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD425180ull +#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR1_5_SPECIAL_BASE 0x1000007FFD425E80ull +#define NIC0_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_5_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR1_6_UNSECURE_DOORBELL0_BASE 0x1000007FFD426000ull +#define NIC0_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR1_6_UNSECURE_DOORBELL1_BASE 0x1000007FFD426080ull +#define NIC0_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD426100ull +#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD426180ull +#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR1_6_SPECIAL_BASE 0x1000007FFD426E80ull +#define NIC0_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_6_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR1_7_UNSECURE_DOORBELL0_BASE 0x1000007FFD427000ull +#define NIC0_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR1_7_UNSECURE_DOORBELL1_BASE 0x1000007FFD427080ull +#define NIC0_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD427100ull +#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD427180ull +#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR1_7_SPECIAL_BASE 0x1000007FFD427E80ull +#define NIC0_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_7_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR1_8_UNSECURE_DOORBELL0_BASE 0x1000007FFD428000ull +#define NIC0_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR1_8_UNSECURE_DOORBELL1_BASE 0x1000007FFD428080ull +#define NIC0_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD428100ull +#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD428180ull +#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR1_8_SPECIAL_BASE 0x1000007FFD428E80ull +#define NIC0_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_8_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR1_9_UNSECURE_DOORBELL0_BASE 0x1000007FFD429000ull +#define NIC0_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR1_9_UNSECURE_DOORBELL1_BASE 0x1000007FFD429080ull +#define NIC0_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD429100ull +#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD429180ull +#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR1_9_SPECIAL_BASE 0x1000007FFD429E80ull +#define NIC0_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_9_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR1_10_UNSECURE_DOORBELL0_BASE 0x1000007FFD42A000ull +#define NIC0_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR1_10_UNSECURE_DOORBELL1_BASE 0x1000007FFD42A080ull +#define NIC0_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD42A100ull +#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD42A180ull +#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR1_10_SPECIAL_BASE 0x1000007FFD42AE80ull +#define NIC0_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_10_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR1_11_UNSECURE_DOORBELL0_BASE 0x1000007FFD42B000ull +#define NIC0_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR1_11_UNSECURE_DOORBELL1_BASE 0x1000007FFD42B080ull +#define NIC0_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD42B100ull +#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD42B180ull +#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR1_11_SPECIAL_BASE 0x1000007FFD42BE80ull +#define NIC0_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_11_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR1_12_UNSECURE_DOORBELL0_BASE 0x1000007FFD42C000ull +#define NIC0_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR1_12_UNSECURE_DOORBELL1_BASE 0x1000007FFD42C080ull +#define NIC0_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD42C100ull +#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD42C180ull +#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR1_12_SPECIAL_BASE 0x1000007FFD42CE80ull +#define NIC0_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_12_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR1_13_UNSECURE_DOORBELL0_BASE 0x1000007FFD42D000ull +#define NIC0_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR1_13_UNSECURE_DOORBELL1_BASE 0x1000007FFD42D080ull +#define NIC0_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD42D100ull +#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD42D180ull +#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR1_13_SPECIAL_BASE 0x1000007FFD42DE80ull +#define NIC0_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_13_SPECIAL_SECTION 0x1800 + +#define mmNIC0_UMR1_14_UNSECURE_DOORBELL0_BASE 0x1000007FFD42E000ull +#define NIC0_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC0_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC0_UMR1_14_UNSECURE_DOORBELL1_BASE 0x1000007FFD42E080ull +#define NIC0_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC0_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC0_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD42E100ull +#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC0_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD42E180ull +#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC0_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC0_UMR1_14_SPECIAL_BASE 0x1000007FFD42EE80ull +#define NIC0_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_UMR1_14_SPECIAL_SECTION 0x1180 + +#define mmNIC0_QM_DCCM1_BASE 0x1000007FFD430000ull +#define NIC0_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC0_QM_DCCM1_SECTION 0x8000 + +#define mmNIC0_QM_ARC_AUX1_BASE 0x1000007FFD438000ull +#define NIC0_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC0_QM_ARC_AUX1_SECTION 0xE800 + +#define mmNIC0_QM_ARC_AUX1_SPECIAL_BASE 0x1000007FFD438E80ull +#define NIC0_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 + +#define mmNIC0_QM1_BASE 0x1000007FFD43A000ull +#define NIC0_QM1_MAX_OFFSET 0x1000 +#define NIC0_QM1_SECTION 0x9000 + +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFD43A900ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFD43A908ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFD43A910ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFD43A918ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFD43A920ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFD43A928ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFD43A930ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFD43A938ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFD43A940ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFD43A948ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFD43A950ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFD43A958ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFD43A960ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFD43A968ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFD43A970ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmNIC0_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFD43A978ull +#define NIC0_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC0_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmNIC0_QM1_AXUSER_SECURED_BASE 0x1000007FFD43AB00ull +#define NIC0_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC0_QM1_AXUSER_SECURED_SECTION 0x8000 + +#define mmNIC0_QM1_AXUSER_NONSECURED_BASE 0x1000007FFD43AB80ull +#define NIC0_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC0_QM1_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmNIC0_QM1_DBG_HBW_BASE 0x1000007FFD43AC00ull +#define NIC0_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC0_QM1_DBG_HBW_SECTION 0x8000 + +#define mmNIC0_QM1_DBG_LBW_BASE 0x1000007FFD43AC80ull +#define NIC0_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC0_QM1_DBG_LBW_SECTION 0x1000 + +#define mmNIC0_QM1_CGM_BASE 0x1000007FFD43AD80ull +#define NIC0_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC0_QM1_CGM_SECTION 0x1000 + +#define mmNIC0_QM1_SPECIAL_BASE 0x1000007FFD43AE80ull +#define NIC0_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_QM1_SPECIAL_SECTION 0x4180 + +#define mmNIC0_QPC1_BASE 0x1000007FFD43F000ull +#define NIC0_QPC1_MAX_OFFSET 0x1000 +#define NIC0_QPC1_SECTION 0x7200 + +#define mmNIC0_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x1000007FFD43F720ull +#define NIC0_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x1000007FFD43F728ull +#define NIC0_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x1000007FFD43F730ull +#define NIC0_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x1000007FFD43F738ull +#define NIC0_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x1000007FFD43F740ull +#define NIC0_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x1000007FFD43F748ull +#define NIC0_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x1000007FFD43F750ull +#define NIC0_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x1000007FFD43F758ull +#define NIC0_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x1000007FFD43F760ull +#define NIC0_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x1000007FFD43F768ull +#define NIC0_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x1000007FFD43F770ull +#define NIC0_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x1000007FFD43F778ull +#define NIC0_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x1000007FFD43F780ull +#define NIC0_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x1000007FFD43F788ull +#define NIC0_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x1000007FFD43F790ull +#define NIC0_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x1000007FFD43F798ull +#define NIC0_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x1000007FFD43F7A0ull +#define NIC0_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x1000007FFD43F7A8ull +#define NIC0_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x1000007FFD43F7B0ull +#define NIC0_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x1000007FFD43F7B8ull +#define NIC0_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x1000007FFD43F7C0ull +#define NIC0_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x1000007FFD43F7C8ull +#define NIC0_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x1000007FFD43F7D0ull +#define NIC0_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x1000007FFD43F7D8ull +#define NIC0_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x1000007FFD43F7E0ull +#define NIC0_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x1000007FFD43F7E8ull +#define NIC0_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x1000007FFD43F7F0ull +#define NIC0_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x1000007FFD43F7F8ull +#define NIC0_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x1000007FFD43F800ull +#define NIC0_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x1000007FFD43F808ull +#define NIC0_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x1000007FFD43F810ull +#define NIC0_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC0_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x1000007FFD43F818ull +#define NIC0_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC0_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 + +#define mmNIC0_QPC1_AXUSER_CONG_QUE_BASE 0x1000007FFD43FB80ull +#define NIC0_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC0_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 + +#define mmNIC0_QPC1_AXUSER_RXWQE_BASE 0x1000007FFD43FBE0ull +#define NIC0_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC0_QPC1_AXUSER_RXWQE_SECTION 0x6000 + +#define mmNIC0_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x1000007FFD43FC40ull +#define NIC0_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC0_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 + +#define mmNIC0_QPC1_AXUSER_DB_FIFO_BASE 0x1000007FFD43FCA0ull +#define NIC0_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC0_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 + +#define mmNIC0_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x1000007FFD43FD00ull +#define NIC0_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC0_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 + +#define mmNIC0_QPC1_AXUSER_ERR_FIFO_BASE 0x1000007FFD43FD60ull +#define NIC0_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC0_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 + +#define mmNIC0_QPC1_AXUSER_QPC_RESP_BASE 0x1000007FFD43FDC0ull +#define NIC0_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC0_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 + +#define mmNIC0_QPC1_AXUSER_QPC_REQ_BASE 0x1000007FFD43FE20ull +#define NIC0_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC0_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 + +#define mmNIC0_QPC1_SPECIAL_BASE 0x1000007FFD43FE80ull +#define NIC0_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_QPC1_SPECIAL_SECTION 0x8180 + +#define mmNIC0_TMR_BASE 0x1000007FFD448000ull +#define NIC0_TMR_MAX_OFFSET 0x1000 +#define NIC0_TMR_SECTION 0xD600 + +#define mmNIC0_TMR_AXUSER_TMR_FREE_LIST_BASE 0x1000007FFD448D60ull +#define NIC0_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC0_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 + +#define mmNIC0_TMR_AXUSER_TMR_FIFO_BASE 0x1000007FFD448DC0ull +#define NIC0_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC0_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 + +#define mmNIC0_TMR_AXUSER_TMR_FSM_BASE 0x1000007FFD448E20ull +#define NIC0_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC0_TMR_AXUSER_TMR_FSM_SECTION 0x6000 + +#define mmNIC0_TMR_SPECIAL_BASE 0x1000007FFD448E80ull +#define NIC0_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_TMR_SPECIAL_SECTION 0x1800 + +#define mmNIC0_RXB_CORE_BASE 0x1000007FFD449000ull +#define NIC0_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC0_RXB_CORE_SECTION 0x6100 + +#define mmNIC0_RXB_CORE_SCT_AWUSER_BASE 0x1000007FFD449610ull +#define NIC0_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC0_RXB_CORE_SCT_AWUSER_SECTION 0x8700 + +#define mmNIC0_RXB_CORE_SPECIAL_BASE 0x1000007FFD449E80ull +#define NIC0_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_RXB_CORE_SPECIAL_SECTION 0x1800 + +#define mmNIC0_RXE0_BASE 0x1000007FFD44A000ull +#define NIC0_RXE0_MAX_OFFSET 0x1000 +#define NIC0_RXE0_SECTION 0x9000 + +#define mmNIC0_RXE0_WQE_ARUSER_BASE 0x1000007FFD44A900ull +#define NIC0_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC0_RXE0_WQE_ARUSER_SECTION 0x5800 + +#define mmNIC0_RXE0_SPECIAL_BASE 0x1000007FFD44AE80ull +#define NIC0_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_RXE0_SPECIAL_SECTION 0x1800 + +#define mmNIC0_RXE1_BASE 0x1000007FFD44B000ull +#define NIC0_RXE1_MAX_OFFSET 0x1000 +#define NIC0_RXE1_SECTION 0x9000 + +#define mmNIC0_RXE1_WQE_ARUSER_BASE 0x1000007FFD44B900ull +#define NIC0_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC0_RXE1_WQE_ARUSER_SECTION 0x5800 + +#define mmNIC0_RXE1_SPECIAL_BASE 0x1000007FFD44BE80ull +#define NIC0_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_RXE1_SPECIAL_SECTION 0x1800 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ0_BASE 0x1000007FFD44C000ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ1_BASE 0x1000007FFD44C050ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ2_BASE 0x1000007FFD44C0A0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ3_BASE 0x1000007FFD44C0F0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ4_BASE 0x1000007FFD44C140ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ5_BASE 0x1000007FFD44C190ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ6_BASE 0x1000007FFD44C1E0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ7_BASE 0x1000007FFD44C230ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ8_BASE 0x1000007FFD44C280ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ9_BASE 0x1000007FFD44C2D0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ10_BASE 0x1000007FFD44C320ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ11_BASE 0x1000007FFD44C370ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ12_BASE 0x1000007FFD44C3C0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ13_BASE 0x1000007FFD44C410ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ14_BASE 0x1000007FFD44C460ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ15_BASE 0x1000007FFD44C4B0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ16_BASE 0x1000007FFD44C500ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ17_BASE 0x1000007FFD44C550ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ18_BASE 0x1000007FFD44C5A0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ19_BASE 0x1000007FFD44C5F0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ20_BASE 0x1000007FFD44C640ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ21_BASE 0x1000007FFD44C690ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ22_BASE 0x1000007FFD44C6E0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ23_BASE 0x1000007FFD44C730ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ24_BASE 0x1000007FFD44C780ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ25_BASE 0x1000007FFD44C7D0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ26_BASE 0x1000007FFD44C820ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ27_BASE 0x1000007FFD44C870ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ28_BASE 0x1000007FFD44C8C0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ29_BASE 0x1000007FFD44C910ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ30_BASE 0x1000007FFD44C960ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 + +#define mmNIC0_RXE0_AXUSER_AXUSER_CQ31_BASE 0x1000007FFD44C9B0ull +#define NIC0_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC0_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 + +#define mmNIC0_RXE0_AXUSER_SPECIAL_BASE 0x1000007FFD44CE80ull +#define NIC0_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_RXE0_AXUSER_SPECIAL_SECTION 0x1800 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ0_BASE 0x1000007FFD44D000ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ1_BASE 0x1000007FFD44D050ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ2_BASE 0x1000007FFD44D0A0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ3_BASE 0x1000007FFD44D0F0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ4_BASE 0x1000007FFD44D140ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ5_BASE 0x1000007FFD44D190ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ6_BASE 0x1000007FFD44D1E0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ7_BASE 0x1000007FFD44D230ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ8_BASE 0x1000007FFD44D280ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ9_BASE 0x1000007FFD44D2D0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ10_BASE 0x1000007FFD44D320ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ11_BASE 0x1000007FFD44D370ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ12_BASE 0x1000007FFD44D3C0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ13_BASE 0x1000007FFD44D410ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ14_BASE 0x1000007FFD44D460ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ15_BASE 0x1000007FFD44D4B0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ16_BASE 0x1000007FFD44D500ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ17_BASE 0x1000007FFD44D550ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ18_BASE 0x1000007FFD44D5A0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ19_BASE 0x1000007FFD44D5F0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ20_BASE 0x1000007FFD44D640ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ21_BASE 0x1000007FFD44D690ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ22_BASE 0x1000007FFD44D6E0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ23_BASE 0x1000007FFD44D730ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ24_BASE 0x1000007FFD44D780ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ25_BASE 0x1000007FFD44D7D0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ26_BASE 0x1000007FFD44D820ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ27_BASE 0x1000007FFD44D870ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ28_BASE 0x1000007FFD44D8C0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ29_BASE 0x1000007FFD44D910ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ30_BASE 0x1000007FFD44D960ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 + +#define mmNIC0_RXE1_AXUSER_AXUSER_CQ31_BASE 0x1000007FFD44D9B0ull +#define NIC0_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC0_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 + +#define mmNIC0_RXE1_AXUSER_SPECIAL_BASE 0x1000007FFD44DE80ull +#define NIC0_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_RXE1_AXUSER_SPECIAL_SECTION 0x2180 + +#define mmNIC0_TXS0_BASE 0x1000007FFD450000ull +#define NIC0_TXS0_MAX_OFFSET 0x1000 +#define NIC0_TXS0_SECTION 0xE800 + +#define mmNIC0_TXS0_SPECIAL_BASE 0x1000007FFD450E80ull +#define NIC0_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_TXS0_SPECIAL_SECTION 0x1800 + +#define mmNIC0_TXS1_BASE 0x1000007FFD451000ull +#define NIC0_TXS1_MAX_OFFSET 0x1000 +#define NIC0_TXS1_SECTION 0xE800 + +#define mmNIC0_TXS1_SPECIAL_BASE 0x1000007FFD451E80ull +#define NIC0_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_TXS1_SPECIAL_SECTION 0x1800 + +#define mmNIC0_TXE0_BASE 0x1000007FFD452000ull +#define NIC0_TXE0_MAX_OFFSET 0x1000 +#define NIC0_TXE0_SECTION 0xE800 + +#define mmNIC0_TXE0_SPECIAL_BASE 0x1000007FFD452E80ull +#define NIC0_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_TXE0_SPECIAL_SECTION 0x1800 + +#define mmNIC0_TXE1_BASE 0x1000007FFD453000ull +#define NIC0_TXE1_MAX_OFFSET 0x1000 +#define NIC0_TXE1_SECTION 0xE800 + +#define mmNIC0_TXE1_SPECIAL_BASE 0x1000007FFD453E80ull +#define NIC0_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_TXE1_SPECIAL_SECTION 0x1800 + +#define mmNIC0_TXB_BASE 0x1000007FFD454000ull +#define NIC0_TXB_MAX_OFFSET 0x1000 +#define NIC0_TXB_SECTION 0xE800 + +#define mmNIC0_TXB_SPECIAL_BASE 0x1000007FFD454E80ull +#define NIC0_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_TXB_SPECIAL_SECTION 0x1800 + +#define mmNIC0_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFD455000ull +#define NIC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmNIC0_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFD455200ull +#define NIC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmNIC0_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFD455400ull +#define NIC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmNIC0_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFD455600ull +#define NIC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmNIC0_MSTR_IF_E2E_CRDT_BASE 0x1000007FFD455800ull +#define NIC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmNIC0_MSTR_IF_AXUSER_BASE 0x1000007FFD455A80ull +#define NIC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC0_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmNIC0_MSTR_IF_DBG_HBW_BASE 0x1000007FFD455B00ull +#define NIC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC0_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmNIC0_MSTR_IF_DBG_LBW_BASE 0x1000007FFD455B80ull +#define NIC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC0_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmNIC0_MSTR_IF_CORE_HBW_BASE 0x1000007FFD455C00ull +#define NIC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC0_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmNIC0_MSTR_IF_CORE_LBW_BASE 0x1000007FFD455D80ull +#define NIC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC0_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmNIC0_MSTR_IF_SPECIAL_BASE 0x1000007FFD455E80ull +#define NIC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmNIC0_TX_AXUSER_BASE 0x1000007FFD456000ull +#define NIC0_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC0_TX_AXUSER_SECTION 0x2000 + +#define mmNIC0_SERDES0_BASE 0x1000007FFD458000ull +#define NIC0_SERDES0_MAX_OFFSET 0x3E40 +#define NIC0_SERDES0_SECTION 0x4000 + +#define mmNIC0_SERDES1_BASE 0x1000007FFD45C000ull +#define NIC0_SERDES1_MAX_OFFSET 0x3E40 +#define NIC0_SERDES1_SECTION 0x4000 + +#define mmNIC0_PHY_BASE 0x1000007FFD460000ull +#define NIC0_PHY_MAX_OFFSET 0x1000 +#define NIC0_PHY_SECTION 0xE800 + +#define mmNIC0_PHY_SPECIAL_BASE 0x1000007FFD460E80ull +#define NIC0_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC0_PHY_SPECIAL_SECTION 0x7180 + +#define mmPRT0_MAC_AUX_BASE 0x1000007FFD468000ull +#define PRT0_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT0_MAC_AUX_SECTION 0xE800 + +#define mmPRT0_MAC_AUX_SPECIAL_BASE 0x1000007FFD468E80ull +#define PRT0_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT0_MAC_AUX_SPECIAL_SECTION 0x1800 + +#define mmPRT0_MAC_CORE_BASE 0x1000007FFD469000ull +#define PRT0_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT0_MAC_CORE_SECTION 0xE800 + +#define mmPRT0_MAC_CORE_SPECIAL_BASE 0x1000007FFD469E80ull +#define PRT0_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT0_MAC_CORE_SPECIAL_SECTION 0x1800 + +#define mmNIC0_MAC_RS_FEC_BASE 0x1000007FFD46A000ull +#define NIC0_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC0_MAC_RS_FEC_SECTION 0x1000 + +#define mmNIC0_MAC_GLOB_STAT_NIC_MAC_STAT_BASE 0x1000007FFD46B000ull +#define NIC0_MAC_GLOB_STAT_NIC_MAC_STAT_MAX_OFFSET 0x4D00 +#define NIC0_MAC_GLOB_STAT_NIC_MAC_STAT_SECTION 0x8000 + +#define mmNIC0_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_BASE 0x1000007FFD46B800ull +#define NIC0_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC0_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_SECTION 0x8000 + +#define mmNIC0_MAC_CH0_MAC_PCS_BASE 0x1000007FFD46C000ull +#define NIC0_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC0_MAC_CH0_MAC_PCS_SECTION 0x4000 + +#define mmNIC0_MAC_CH0_MAC_128_BASE 0x1000007FFD46C400ull +#define NIC0_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC0_MAC_CH0_MAC_128_SECTION 0x4000 + +#define mmNIC0_MAC_CH0_MAC_AN_BASE 0x1000007FFD46C800ull +#define NIC0_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC0_MAC_CH0_MAC_AN_SECTION 0x8000 + +#define mmNIC0_MAC_CH1_MAC_PCS_BASE 0x1000007FFD46D000ull +#define NIC0_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC0_MAC_CH1_MAC_PCS_SECTION 0x4000 + +#define mmNIC0_MAC_CH1_MAC_128_BASE 0x1000007FFD46D400ull +#define NIC0_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC0_MAC_CH1_MAC_128_SECTION 0x4000 + +#define mmNIC0_MAC_CH1_MAC_AN_BASE 0x1000007FFD46D800ull +#define NIC0_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC0_MAC_CH1_MAC_AN_SECTION 0x8000 + +#define mmNIC0_MAC_CH2_MAC_PCS_BASE 0x1000007FFD46E000ull +#define NIC0_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC0_MAC_CH2_MAC_PCS_SECTION 0x4000 + +#define mmNIC0_MAC_CH2_MAC_128_BASE 0x1000007FFD46E400ull +#define NIC0_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC0_MAC_CH2_MAC_128_SECTION 0x4000 + +#define mmNIC0_MAC_CH2_MAC_AN_BASE 0x1000007FFD46E800ull +#define NIC0_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC0_MAC_CH2_MAC_AN_SECTION 0x8000 + +#define mmNIC0_MAC_CH3_MAC_PCS_BASE 0x1000007FFD46F000ull +#define NIC0_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC0_MAC_CH3_MAC_PCS_SECTION 0x4000 + +#define mmNIC0_MAC_CH3_MAC_128_BASE 0x1000007FFD46F400ull +#define NIC0_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC0_MAC_CH3_MAC_128_SECTION 0x4000 + +#define mmNIC0_MAC_CH3_MAC_AN_BASE 0x1000007FFD46F800ull +#define NIC0_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC0_MAC_CH3_MAC_AN_SECTION 0x10800 + +#define mmNIC1_UMR0_0_UNSECURE_DOORBELL0_BASE 0x1000007FFD480000ull +#define NIC1_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR0_0_UNSECURE_DOORBELL1_BASE 0x1000007FFD480080ull +#define NIC1_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD480100ull +#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD480180ull +#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR0_0_SPECIAL_BASE 0x1000007FFD480E80ull +#define NIC1_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_0_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR0_1_UNSECURE_DOORBELL0_BASE 0x1000007FFD481000ull +#define NIC1_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR0_1_UNSECURE_DOORBELL1_BASE 0x1000007FFD481080ull +#define NIC1_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD481100ull +#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD481180ull +#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR0_1_SPECIAL_BASE 0x1000007FFD481E80ull +#define NIC1_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_1_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR0_2_UNSECURE_DOORBELL0_BASE 0x1000007FFD482000ull +#define NIC1_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR0_2_UNSECURE_DOORBELL1_BASE 0x1000007FFD482080ull +#define NIC1_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD482100ull +#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD482180ull +#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR0_2_SPECIAL_BASE 0x1000007FFD482E80ull +#define NIC1_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_2_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR0_3_UNSECURE_DOORBELL0_BASE 0x1000007FFD483000ull +#define NIC1_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR0_3_UNSECURE_DOORBELL1_BASE 0x1000007FFD483080ull +#define NIC1_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD483100ull +#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD483180ull +#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR0_3_SPECIAL_BASE 0x1000007FFD483E80ull +#define NIC1_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_3_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR0_4_UNSECURE_DOORBELL0_BASE 0x1000007FFD484000ull +#define NIC1_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR0_4_UNSECURE_DOORBELL1_BASE 0x1000007FFD484080ull +#define NIC1_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD484100ull +#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD484180ull +#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR0_4_SPECIAL_BASE 0x1000007FFD484E80ull +#define NIC1_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_4_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR0_5_UNSECURE_DOORBELL0_BASE 0x1000007FFD485000ull +#define NIC1_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR0_5_UNSECURE_DOORBELL1_BASE 0x1000007FFD485080ull +#define NIC1_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD485100ull +#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD485180ull +#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR0_5_SPECIAL_BASE 0x1000007FFD485E80ull +#define NIC1_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_5_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR0_6_UNSECURE_DOORBELL0_BASE 0x1000007FFD486000ull +#define NIC1_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR0_6_UNSECURE_DOORBELL1_BASE 0x1000007FFD486080ull +#define NIC1_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD486100ull +#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD486180ull +#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR0_6_SPECIAL_BASE 0x1000007FFD486E80ull +#define NIC1_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_6_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR0_7_UNSECURE_DOORBELL0_BASE 0x1000007FFD487000ull +#define NIC1_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR0_7_UNSECURE_DOORBELL1_BASE 0x1000007FFD487080ull +#define NIC1_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD487100ull +#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD487180ull +#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR0_7_SPECIAL_BASE 0x1000007FFD487E80ull +#define NIC1_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_7_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR0_8_UNSECURE_DOORBELL0_BASE 0x1000007FFD488000ull +#define NIC1_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR0_8_UNSECURE_DOORBELL1_BASE 0x1000007FFD488080ull +#define NIC1_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD488100ull +#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD488180ull +#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR0_8_SPECIAL_BASE 0x1000007FFD488E80ull +#define NIC1_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_8_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR0_9_UNSECURE_DOORBELL0_BASE 0x1000007FFD489000ull +#define NIC1_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR0_9_UNSECURE_DOORBELL1_BASE 0x1000007FFD489080ull +#define NIC1_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD489100ull +#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD489180ull +#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR0_9_SPECIAL_BASE 0x1000007FFD489E80ull +#define NIC1_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_9_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR0_10_UNSECURE_DOORBELL0_BASE 0x1000007FFD48A000ull +#define NIC1_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR0_10_UNSECURE_DOORBELL1_BASE 0x1000007FFD48A080ull +#define NIC1_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD48A100ull +#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD48A180ull +#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR0_10_SPECIAL_BASE 0x1000007FFD48AE80ull +#define NIC1_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_10_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR0_11_UNSECURE_DOORBELL0_BASE 0x1000007FFD48B000ull +#define NIC1_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR0_11_UNSECURE_DOORBELL1_BASE 0x1000007FFD48B080ull +#define NIC1_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD48B100ull +#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD48B180ull +#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR0_11_SPECIAL_BASE 0x1000007FFD48BE80ull +#define NIC1_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_11_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR0_12_UNSECURE_DOORBELL0_BASE 0x1000007FFD48C000ull +#define NIC1_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR0_12_UNSECURE_DOORBELL1_BASE 0x1000007FFD48C080ull +#define NIC1_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD48C100ull +#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD48C180ull +#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR0_12_SPECIAL_BASE 0x1000007FFD48CE80ull +#define NIC1_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_12_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR0_13_UNSECURE_DOORBELL0_BASE 0x1000007FFD48D000ull +#define NIC1_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR0_13_UNSECURE_DOORBELL1_BASE 0x1000007FFD48D080ull +#define NIC1_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD48D100ull +#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD48D180ull +#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR0_13_SPECIAL_BASE 0x1000007FFD48DE80ull +#define NIC1_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_13_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR0_14_UNSECURE_DOORBELL0_BASE 0x1000007FFD48E000ull +#define NIC1_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR0_14_UNSECURE_DOORBELL1_BASE 0x1000007FFD48E080ull +#define NIC1_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD48E100ull +#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD48E180ull +#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR0_14_SPECIAL_BASE 0x1000007FFD48EE80ull +#define NIC1_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR0_14_SPECIAL_SECTION 0x1180 + +#define mmNIC1_QM_DCCM0_BASE 0x1000007FFD490000ull +#define NIC1_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC1_QM_DCCM0_SECTION 0x8000 + +#define mmNIC1_QM_ARC_AUX0_BASE 0x1000007FFD498000ull +#define NIC1_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC1_QM_ARC_AUX0_SECTION 0xE800 + +#define mmNIC1_QM_ARC_AUX0_SPECIAL_BASE 0x1000007FFD498E80ull +#define NIC1_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 + +#define mmNIC1_QM0_BASE 0x1000007FFD49A000ull +#define NIC1_QM0_MAX_OFFSET 0x1000 +#define NIC1_QM0_SECTION 0x9000 + +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFD49A900ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFD49A908ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFD49A910ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFD49A918ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFD49A920ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFD49A928ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFD49A930ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFD49A938ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFD49A940ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFD49A948ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFD49A950ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFD49A958ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFD49A960ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFD49A968ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFD49A970ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmNIC1_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFD49A978ull +#define NIC1_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC1_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmNIC1_QM0_AXUSER_SECURED_BASE 0x1000007FFD49AB00ull +#define NIC1_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC1_QM0_AXUSER_SECURED_SECTION 0x8000 + +#define mmNIC1_QM0_AXUSER_NONSECURED_BASE 0x1000007FFD49AB80ull +#define NIC1_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC1_QM0_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmNIC1_QM0_DBG_HBW_BASE 0x1000007FFD49AC00ull +#define NIC1_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC1_QM0_DBG_HBW_SECTION 0x8000 + +#define mmNIC1_QM0_DBG_LBW_BASE 0x1000007FFD49AC80ull +#define NIC1_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC1_QM0_DBG_LBW_SECTION 0x1000 + +#define mmNIC1_QM0_CGM_BASE 0x1000007FFD49AD80ull +#define NIC1_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC1_QM0_CGM_SECTION 0x1000 + +#define mmNIC1_QM0_SPECIAL_BASE 0x1000007FFD49AE80ull +#define NIC1_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_QM0_SPECIAL_SECTION 0x4180 + +#define mmNIC1_QPC0_BASE 0x1000007FFD49F000ull +#define NIC1_QPC0_MAX_OFFSET 0x1000 +#define NIC1_QPC0_SECTION 0x7200 + +#define mmNIC1_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x1000007FFD49F720ull +#define NIC1_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x1000007FFD49F728ull +#define NIC1_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x1000007FFD49F730ull +#define NIC1_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x1000007FFD49F738ull +#define NIC1_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x1000007FFD49F740ull +#define NIC1_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x1000007FFD49F748ull +#define NIC1_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x1000007FFD49F750ull +#define NIC1_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x1000007FFD49F758ull +#define NIC1_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x1000007FFD49F760ull +#define NIC1_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x1000007FFD49F768ull +#define NIC1_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x1000007FFD49F770ull +#define NIC1_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x1000007FFD49F778ull +#define NIC1_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x1000007FFD49F780ull +#define NIC1_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x1000007FFD49F788ull +#define NIC1_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x1000007FFD49F790ull +#define NIC1_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x1000007FFD49F798ull +#define NIC1_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x1000007FFD49F7A0ull +#define NIC1_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x1000007FFD49F7A8ull +#define NIC1_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x1000007FFD49F7B0ull +#define NIC1_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x1000007FFD49F7B8ull +#define NIC1_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x1000007FFD49F7C0ull +#define NIC1_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x1000007FFD49F7C8ull +#define NIC1_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x1000007FFD49F7D0ull +#define NIC1_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x1000007FFD49F7D8ull +#define NIC1_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x1000007FFD49F7E0ull +#define NIC1_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x1000007FFD49F7E8ull +#define NIC1_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x1000007FFD49F7F0ull +#define NIC1_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x1000007FFD49F7F8ull +#define NIC1_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x1000007FFD49F800ull +#define NIC1_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x1000007FFD49F808ull +#define NIC1_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x1000007FFD49F810ull +#define NIC1_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x1000007FFD49F818ull +#define NIC1_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 + +#define mmNIC1_QPC0_AXUSER_CONG_QUE_BASE 0x1000007FFD49FB80ull +#define NIC1_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC1_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 + +#define mmNIC1_QPC0_AXUSER_RXWQE_BASE 0x1000007FFD49FBE0ull +#define NIC1_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC1_QPC0_AXUSER_RXWQE_SECTION 0x6000 + +#define mmNIC1_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x1000007FFD49FC40ull +#define NIC1_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC1_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 + +#define mmNIC1_QPC0_AXUSER_DB_FIFO_BASE 0x1000007FFD49FCA0ull +#define NIC1_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC1_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 + +#define mmNIC1_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x1000007FFD49FD00ull +#define NIC1_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC1_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 + +#define mmNIC1_QPC0_AXUSER_ERR_FIFO_BASE 0x1000007FFD49FD60ull +#define NIC1_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC1_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 + +#define mmNIC1_QPC0_AXUSER_QPC_RESP_BASE 0x1000007FFD49FDC0ull +#define NIC1_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC1_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 + +#define mmNIC1_QPC0_AXUSER_QPC_REQ_BASE 0x1000007FFD49FE20ull +#define NIC1_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC1_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 + +#define mmNIC1_QPC0_SPECIAL_BASE 0x1000007FFD49FE80ull +#define NIC1_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_QPC0_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR1_0_UNSECURE_DOORBELL0_BASE 0x1000007FFD4A0000ull +#define NIC1_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR1_0_UNSECURE_DOORBELL1_BASE 0x1000007FFD4A0080ull +#define NIC1_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD4A0100ull +#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD4A0180ull +#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR1_0_SPECIAL_BASE 0x1000007FFD4A0E80ull +#define NIC1_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_0_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR1_1_UNSECURE_DOORBELL0_BASE 0x1000007FFD4A1000ull +#define NIC1_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR1_1_UNSECURE_DOORBELL1_BASE 0x1000007FFD4A1080ull +#define NIC1_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD4A1100ull +#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD4A1180ull +#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR1_1_SPECIAL_BASE 0x1000007FFD4A1E80ull +#define NIC1_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_1_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR1_2_UNSECURE_DOORBELL0_BASE 0x1000007FFD4A2000ull +#define NIC1_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR1_2_UNSECURE_DOORBELL1_BASE 0x1000007FFD4A2080ull +#define NIC1_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD4A2100ull +#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD4A2180ull +#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR1_2_SPECIAL_BASE 0x1000007FFD4A2E80ull +#define NIC1_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_2_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR1_3_UNSECURE_DOORBELL0_BASE 0x1000007FFD4A3000ull +#define NIC1_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR1_3_UNSECURE_DOORBELL1_BASE 0x1000007FFD4A3080ull +#define NIC1_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD4A3100ull +#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD4A3180ull +#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR1_3_SPECIAL_BASE 0x1000007FFD4A3E80ull +#define NIC1_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_3_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR1_4_UNSECURE_DOORBELL0_BASE 0x1000007FFD4A4000ull +#define NIC1_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR1_4_UNSECURE_DOORBELL1_BASE 0x1000007FFD4A4080ull +#define NIC1_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD4A4100ull +#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD4A4180ull +#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR1_4_SPECIAL_BASE 0x1000007FFD4A4E80ull +#define NIC1_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_4_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR1_5_UNSECURE_DOORBELL0_BASE 0x1000007FFD4A5000ull +#define NIC1_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR1_5_UNSECURE_DOORBELL1_BASE 0x1000007FFD4A5080ull +#define NIC1_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD4A5100ull +#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD4A5180ull +#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR1_5_SPECIAL_BASE 0x1000007FFD4A5E80ull +#define NIC1_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_5_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR1_6_UNSECURE_DOORBELL0_BASE 0x1000007FFD4A6000ull +#define NIC1_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR1_6_UNSECURE_DOORBELL1_BASE 0x1000007FFD4A6080ull +#define NIC1_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD4A6100ull +#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD4A6180ull +#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR1_6_SPECIAL_BASE 0x1000007FFD4A6E80ull +#define NIC1_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_6_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR1_7_UNSECURE_DOORBELL0_BASE 0x1000007FFD4A7000ull +#define NIC1_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR1_7_UNSECURE_DOORBELL1_BASE 0x1000007FFD4A7080ull +#define NIC1_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD4A7100ull +#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD4A7180ull +#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR1_7_SPECIAL_BASE 0x1000007FFD4A7E80ull +#define NIC1_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_7_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR1_8_UNSECURE_DOORBELL0_BASE 0x1000007FFD4A8000ull +#define NIC1_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR1_8_UNSECURE_DOORBELL1_BASE 0x1000007FFD4A8080ull +#define NIC1_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD4A8100ull +#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD4A8180ull +#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR1_8_SPECIAL_BASE 0x1000007FFD4A8E80ull +#define NIC1_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_8_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR1_9_UNSECURE_DOORBELL0_BASE 0x1000007FFD4A9000ull +#define NIC1_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR1_9_UNSECURE_DOORBELL1_BASE 0x1000007FFD4A9080ull +#define NIC1_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD4A9100ull +#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD4A9180ull +#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR1_9_SPECIAL_BASE 0x1000007FFD4A9E80ull +#define NIC1_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_9_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR1_10_UNSECURE_DOORBELL0_BASE 0x1000007FFD4AA000ull +#define NIC1_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR1_10_UNSECURE_DOORBELL1_BASE 0x1000007FFD4AA080ull +#define NIC1_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD4AA100ull +#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD4AA180ull +#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR1_10_SPECIAL_BASE 0x1000007FFD4AAE80ull +#define NIC1_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_10_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR1_11_UNSECURE_DOORBELL0_BASE 0x1000007FFD4AB000ull +#define NIC1_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR1_11_UNSECURE_DOORBELL1_BASE 0x1000007FFD4AB080ull +#define NIC1_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD4AB100ull +#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD4AB180ull +#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR1_11_SPECIAL_BASE 0x1000007FFD4ABE80ull +#define NIC1_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_11_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR1_12_UNSECURE_DOORBELL0_BASE 0x1000007FFD4AC000ull +#define NIC1_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR1_12_UNSECURE_DOORBELL1_BASE 0x1000007FFD4AC080ull +#define NIC1_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD4AC100ull +#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD4AC180ull +#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR1_12_SPECIAL_BASE 0x1000007FFD4ACE80ull +#define NIC1_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_12_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR1_13_UNSECURE_DOORBELL0_BASE 0x1000007FFD4AD000ull +#define NIC1_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR1_13_UNSECURE_DOORBELL1_BASE 0x1000007FFD4AD080ull +#define NIC1_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD4AD100ull +#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD4AD180ull +#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR1_13_SPECIAL_BASE 0x1000007FFD4ADE80ull +#define NIC1_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_13_SPECIAL_SECTION 0x1800 + +#define mmNIC1_UMR1_14_UNSECURE_DOORBELL0_BASE 0x1000007FFD4AE000ull +#define NIC1_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC1_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC1_UMR1_14_UNSECURE_DOORBELL1_BASE 0x1000007FFD4AE080ull +#define NIC1_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC1_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC1_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD4AE100ull +#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC1_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD4AE180ull +#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC1_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC1_UMR1_14_SPECIAL_BASE 0x1000007FFD4AEE80ull +#define NIC1_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_UMR1_14_SPECIAL_SECTION 0x1180 + +#define mmNIC1_QM_DCCM1_BASE 0x1000007FFD4B0000ull +#define NIC1_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC1_QM_DCCM1_SECTION 0x8000 + +#define mmNIC1_QM_ARC_AUX1_BASE 0x1000007FFD4B8000ull +#define NIC1_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC1_QM_ARC_AUX1_SECTION 0xE800 + +#define mmNIC1_QM_ARC_AUX1_SPECIAL_BASE 0x1000007FFD4B8E80ull +#define NIC1_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 + +#define mmNIC1_QM1_BASE 0x1000007FFD4BA000ull +#define NIC1_QM1_MAX_OFFSET 0x1000 +#define NIC1_QM1_SECTION 0x9000 + +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFD4BA900ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFD4BA908ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFD4BA910ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFD4BA918ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFD4BA920ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFD4BA928ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFD4BA930ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFD4BA938ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFD4BA940ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFD4BA948ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFD4BA950ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFD4BA958ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFD4BA960ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFD4BA968ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFD4BA970ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmNIC1_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFD4BA978ull +#define NIC1_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC1_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmNIC1_QM1_AXUSER_SECURED_BASE 0x1000007FFD4BAB00ull +#define NIC1_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC1_QM1_AXUSER_SECURED_SECTION 0x8000 + +#define mmNIC1_QM1_AXUSER_NONSECURED_BASE 0x1000007FFD4BAB80ull +#define NIC1_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC1_QM1_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmNIC1_QM1_DBG_HBW_BASE 0x1000007FFD4BAC00ull +#define NIC1_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC1_QM1_DBG_HBW_SECTION 0x8000 + +#define mmNIC1_QM1_DBG_LBW_BASE 0x1000007FFD4BAC80ull +#define NIC1_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC1_QM1_DBG_LBW_SECTION 0x1000 + +#define mmNIC1_QM1_CGM_BASE 0x1000007FFD4BAD80ull +#define NIC1_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC1_QM1_CGM_SECTION 0x1000 + +#define mmNIC1_QM1_SPECIAL_BASE 0x1000007FFD4BAE80ull +#define NIC1_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_QM1_SPECIAL_SECTION 0x4180 + +#define mmNIC1_QPC1_BASE 0x1000007FFD4BF000ull +#define NIC1_QPC1_MAX_OFFSET 0x1000 +#define NIC1_QPC1_SECTION 0x7200 + +#define mmNIC1_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x1000007FFD4BF720ull +#define NIC1_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x1000007FFD4BF728ull +#define NIC1_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x1000007FFD4BF730ull +#define NIC1_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x1000007FFD4BF738ull +#define NIC1_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x1000007FFD4BF740ull +#define NIC1_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x1000007FFD4BF748ull +#define NIC1_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x1000007FFD4BF750ull +#define NIC1_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x1000007FFD4BF758ull +#define NIC1_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x1000007FFD4BF760ull +#define NIC1_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x1000007FFD4BF768ull +#define NIC1_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x1000007FFD4BF770ull +#define NIC1_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x1000007FFD4BF778ull +#define NIC1_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x1000007FFD4BF780ull +#define NIC1_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x1000007FFD4BF788ull +#define NIC1_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x1000007FFD4BF790ull +#define NIC1_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x1000007FFD4BF798ull +#define NIC1_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x1000007FFD4BF7A0ull +#define NIC1_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x1000007FFD4BF7A8ull +#define NIC1_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x1000007FFD4BF7B0ull +#define NIC1_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x1000007FFD4BF7B8ull +#define NIC1_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x1000007FFD4BF7C0ull +#define NIC1_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x1000007FFD4BF7C8ull +#define NIC1_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x1000007FFD4BF7D0ull +#define NIC1_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x1000007FFD4BF7D8ull +#define NIC1_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x1000007FFD4BF7E0ull +#define NIC1_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x1000007FFD4BF7E8ull +#define NIC1_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x1000007FFD4BF7F0ull +#define NIC1_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x1000007FFD4BF7F8ull +#define NIC1_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x1000007FFD4BF800ull +#define NIC1_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x1000007FFD4BF808ull +#define NIC1_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x1000007FFD4BF810ull +#define NIC1_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC1_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x1000007FFD4BF818ull +#define NIC1_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC1_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 + +#define mmNIC1_QPC1_AXUSER_CONG_QUE_BASE 0x1000007FFD4BFB80ull +#define NIC1_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC1_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 + +#define mmNIC1_QPC1_AXUSER_RXWQE_BASE 0x1000007FFD4BFBE0ull +#define NIC1_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC1_QPC1_AXUSER_RXWQE_SECTION 0x6000 + +#define mmNIC1_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x1000007FFD4BFC40ull +#define NIC1_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC1_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 + +#define mmNIC1_QPC1_AXUSER_DB_FIFO_BASE 0x1000007FFD4BFCA0ull +#define NIC1_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC1_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 + +#define mmNIC1_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x1000007FFD4BFD00ull +#define NIC1_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC1_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 + +#define mmNIC1_QPC1_AXUSER_ERR_FIFO_BASE 0x1000007FFD4BFD60ull +#define NIC1_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC1_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 + +#define mmNIC1_QPC1_AXUSER_QPC_RESP_BASE 0x1000007FFD4BFDC0ull +#define NIC1_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC1_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 + +#define mmNIC1_QPC1_AXUSER_QPC_REQ_BASE 0x1000007FFD4BFE20ull +#define NIC1_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC1_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 + +#define mmNIC1_QPC1_SPECIAL_BASE 0x1000007FFD4BFE80ull +#define NIC1_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_QPC1_SPECIAL_SECTION 0x8180 + +#define mmNIC1_TMR_BASE 0x1000007FFD4C8000ull +#define NIC1_TMR_MAX_OFFSET 0x1000 +#define NIC1_TMR_SECTION 0xD600 + +#define mmNIC1_TMR_AXUSER_TMR_FREE_LIST_BASE 0x1000007FFD4C8D60ull +#define NIC1_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC1_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 + +#define mmNIC1_TMR_AXUSER_TMR_FIFO_BASE 0x1000007FFD4C8DC0ull +#define NIC1_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC1_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 + +#define mmNIC1_TMR_AXUSER_TMR_FSM_BASE 0x1000007FFD4C8E20ull +#define NIC1_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC1_TMR_AXUSER_TMR_FSM_SECTION 0x6000 + +#define mmNIC1_TMR_SPECIAL_BASE 0x1000007FFD4C8E80ull +#define NIC1_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_TMR_SPECIAL_SECTION 0x1800 + +#define mmNIC1_RXB_CORE_BASE 0x1000007FFD4C9000ull +#define NIC1_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC1_RXB_CORE_SECTION 0x6100 + +#define mmNIC1_RXB_CORE_SCT_AWUSER_BASE 0x1000007FFD4C9610ull +#define NIC1_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC1_RXB_CORE_SCT_AWUSER_SECTION 0x8700 + +#define mmNIC1_RXB_CORE_SPECIAL_BASE 0x1000007FFD4C9E80ull +#define NIC1_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_RXB_CORE_SPECIAL_SECTION 0x1800 + +#define mmNIC1_RXE0_BASE 0x1000007FFD4CA000ull +#define NIC1_RXE0_MAX_OFFSET 0x1000 +#define NIC1_RXE0_SECTION 0x9000 + +#define mmNIC1_RXE0_WQE_ARUSER_BASE 0x1000007FFD4CA900ull +#define NIC1_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC1_RXE0_WQE_ARUSER_SECTION 0x5800 + +#define mmNIC1_RXE0_SPECIAL_BASE 0x1000007FFD4CAE80ull +#define NIC1_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_RXE0_SPECIAL_SECTION 0x1800 + +#define mmNIC1_RXE1_BASE 0x1000007FFD4CB000ull +#define NIC1_RXE1_MAX_OFFSET 0x1000 +#define NIC1_RXE1_SECTION 0x9000 + +#define mmNIC1_RXE1_WQE_ARUSER_BASE 0x1000007FFD4CB900ull +#define NIC1_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC1_RXE1_WQE_ARUSER_SECTION 0x5800 + +#define mmNIC1_RXE1_SPECIAL_BASE 0x1000007FFD4CBE80ull +#define NIC1_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_RXE1_SPECIAL_SECTION 0x1800 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ0_BASE 0x1000007FFD4CC000ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ1_BASE 0x1000007FFD4CC050ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ2_BASE 0x1000007FFD4CC0A0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ3_BASE 0x1000007FFD4CC0F0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ4_BASE 0x1000007FFD4CC140ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ5_BASE 0x1000007FFD4CC190ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ6_BASE 0x1000007FFD4CC1E0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ7_BASE 0x1000007FFD4CC230ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ8_BASE 0x1000007FFD4CC280ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ9_BASE 0x1000007FFD4CC2D0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ10_BASE 0x1000007FFD4CC320ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ11_BASE 0x1000007FFD4CC370ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ12_BASE 0x1000007FFD4CC3C0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ13_BASE 0x1000007FFD4CC410ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ14_BASE 0x1000007FFD4CC460ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ15_BASE 0x1000007FFD4CC4B0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ16_BASE 0x1000007FFD4CC500ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ17_BASE 0x1000007FFD4CC550ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ18_BASE 0x1000007FFD4CC5A0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ19_BASE 0x1000007FFD4CC5F0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ20_BASE 0x1000007FFD4CC640ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ21_BASE 0x1000007FFD4CC690ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ22_BASE 0x1000007FFD4CC6E0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ23_BASE 0x1000007FFD4CC730ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ24_BASE 0x1000007FFD4CC780ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ25_BASE 0x1000007FFD4CC7D0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ26_BASE 0x1000007FFD4CC820ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ27_BASE 0x1000007FFD4CC870ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ28_BASE 0x1000007FFD4CC8C0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ29_BASE 0x1000007FFD4CC910ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ30_BASE 0x1000007FFD4CC960ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 + +#define mmNIC1_RXE0_AXUSER_AXUSER_CQ31_BASE 0x1000007FFD4CC9B0ull +#define NIC1_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC1_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 + +#define mmNIC1_RXE0_AXUSER_SPECIAL_BASE 0x1000007FFD4CCE80ull +#define NIC1_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_RXE0_AXUSER_SPECIAL_SECTION 0x1800 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ0_BASE 0x1000007FFD4CD000ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ1_BASE 0x1000007FFD4CD050ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ2_BASE 0x1000007FFD4CD0A0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ3_BASE 0x1000007FFD4CD0F0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ4_BASE 0x1000007FFD4CD140ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ5_BASE 0x1000007FFD4CD190ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ6_BASE 0x1000007FFD4CD1E0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ7_BASE 0x1000007FFD4CD230ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ8_BASE 0x1000007FFD4CD280ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ9_BASE 0x1000007FFD4CD2D0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ10_BASE 0x1000007FFD4CD320ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ11_BASE 0x1000007FFD4CD370ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ12_BASE 0x1000007FFD4CD3C0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ13_BASE 0x1000007FFD4CD410ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ14_BASE 0x1000007FFD4CD460ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ15_BASE 0x1000007FFD4CD4B0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ16_BASE 0x1000007FFD4CD500ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ17_BASE 0x1000007FFD4CD550ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ18_BASE 0x1000007FFD4CD5A0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ19_BASE 0x1000007FFD4CD5F0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ20_BASE 0x1000007FFD4CD640ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ21_BASE 0x1000007FFD4CD690ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ22_BASE 0x1000007FFD4CD6E0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ23_BASE 0x1000007FFD4CD730ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ24_BASE 0x1000007FFD4CD780ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ25_BASE 0x1000007FFD4CD7D0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ26_BASE 0x1000007FFD4CD820ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ27_BASE 0x1000007FFD4CD870ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ28_BASE 0x1000007FFD4CD8C0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ29_BASE 0x1000007FFD4CD910ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ30_BASE 0x1000007FFD4CD960ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 + +#define mmNIC1_RXE1_AXUSER_AXUSER_CQ31_BASE 0x1000007FFD4CD9B0ull +#define NIC1_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC1_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 + +#define mmNIC1_RXE1_AXUSER_SPECIAL_BASE 0x1000007FFD4CDE80ull +#define NIC1_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_RXE1_AXUSER_SPECIAL_SECTION 0x2180 + +#define mmNIC1_TXS0_BASE 0x1000007FFD4D0000ull +#define NIC1_TXS0_MAX_OFFSET 0x1000 +#define NIC1_TXS0_SECTION 0xE800 + +#define mmNIC1_TXS0_SPECIAL_BASE 0x1000007FFD4D0E80ull +#define NIC1_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_TXS0_SPECIAL_SECTION 0x1800 + +#define mmNIC1_TXS1_BASE 0x1000007FFD4D1000ull +#define NIC1_TXS1_MAX_OFFSET 0x1000 +#define NIC1_TXS1_SECTION 0xE800 + +#define mmNIC1_TXS1_SPECIAL_BASE 0x1000007FFD4D1E80ull +#define NIC1_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_TXS1_SPECIAL_SECTION 0x1800 + +#define mmNIC1_TXE0_BASE 0x1000007FFD4D2000ull +#define NIC1_TXE0_MAX_OFFSET 0x1000 +#define NIC1_TXE0_SECTION 0xE800 + +#define mmNIC1_TXE0_SPECIAL_BASE 0x1000007FFD4D2E80ull +#define NIC1_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_TXE0_SPECIAL_SECTION 0x1800 + +#define mmNIC1_TXE1_BASE 0x1000007FFD4D3000ull +#define NIC1_TXE1_MAX_OFFSET 0x1000 +#define NIC1_TXE1_SECTION 0xE800 + +#define mmNIC1_TXE1_SPECIAL_BASE 0x1000007FFD4D3E80ull +#define NIC1_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_TXE1_SPECIAL_SECTION 0x1800 + +#define mmNIC1_TXB_BASE 0x1000007FFD4D4000ull +#define NIC1_TXB_MAX_OFFSET 0x1000 +#define NIC1_TXB_SECTION 0xE800 + +#define mmNIC1_TXB_SPECIAL_BASE 0x1000007FFD4D4E80ull +#define NIC1_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_TXB_SPECIAL_SECTION 0x1800 + +#define mmNIC1_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFD4D5000ull +#define NIC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmNIC1_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFD4D5200ull +#define NIC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmNIC1_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFD4D5400ull +#define NIC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmNIC1_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFD4D5600ull +#define NIC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmNIC1_MSTR_IF_E2E_CRDT_BASE 0x1000007FFD4D5800ull +#define NIC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmNIC1_MSTR_IF_AXUSER_BASE 0x1000007FFD4D5A80ull +#define NIC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC1_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmNIC1_MSTR_IF_DBG_HBW_BASE 0x1000007FFD4D5B00ull +#define NIC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC1_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmNIC1_MSTR_IF_DBG_LBW_BASE 0x1000007FFD4D5B80ull +#define NIC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC1_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmNIC1_MSTR_IF_CORE_HBW_BASE 0x1000007FFD4D5C00ull +#define NIC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC1_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmNIC1_MSTR_IF_CORE_LBW_BASE 0x1000007FFD4D5D80ull +#define NIC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC1_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmNIC1_MSTR_IF_SPECIAL_BASE 0x1000007FFD4D5E80ull +#define NIC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmNIC1_TX_AXUSER_BASE 0x1000007FFD4D6000ull +#define NIC1_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC1_TX_AXUSER_SECTION 0x2000 + +#define mmNIC1_SERDES0_BASE 0x1000007FFD4D8000ull +#define NIC1_SERDES0_MAX_OFFSET 0x3E40 +#define NIC1_SERDES0_SECTION 0x4000 + +#define mmNIC1_SERDES1_BASE 0x1000007FFD4DC000ull +#define NIC1_SERDES1_MAX_OFFSET 0x3E40 +#define NIC1_SERDES1_SECTION 0x4000 + +#define mmNIC1_PHY_BASE 0x1000007FFD4E0000ull +#define NIC1_PHY_MAX_OFFSET 0x1000 +#define NIC1_PHY_SECTION 0xE800 + +#define mmNIC1_PHY_SPECIAL_BASE 0x1000007FFD4E0E80ull +#define NIC1_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC1_PHY_SPECIAL_SECTION 0x7180 + +#define mmPRT1_MAC_AUX_BASE 0x1000007FFD4E8000ull +#define PRT1_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT1_MAC_AUX_SECTION 0xE800 + +#define mmPRT1_MAC_AUX_SPECIAL_BASE 0x1000007FFD4E8E80ull +#define PRT1_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT1_MAC_AUX_SPECIAL_SECTION 0x1800 + +#define mmPRT1_MAC_CORE_BASE 0x1000007FFD4E9000ull +#define PRT1_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT1_MAC_CORE_SECTION 0xE800 + +#define mmPRT1_MAC_CORE_SPECIAL_BASE 0x1000007FFD4E9E80ull +#define PRT1_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT1_MAC_CORE_SPECIAL_SECTION 0x1800 + +#define mmNIC1_MAC_RS_FEC_BASE 0x1000007FFD4EA000ull +#define NIC1_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC1_MAC_RS_FEC_SECTION 0x1000 + +#define mmNIC1_MAC_GLOB_STAT_NIC_MAC_STAT_BASE 0x1000007FFD4EB000ull +#define NIC1_MAC_GLOB_STAT_NIC_MAC_STAT_MAX_OFFSET 0x4D00 +#define NIC1_MAC_GLOB_STAT_NIC_MAC_STAT_SECTION 0x8000 + +#define mmNIC1_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_BASE 0x1000007FFD4EB800ull +#define NIC1_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC1_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_SECTION 0x8000 + +#define mmNIC1_MAC_CH0_MAC_PCS_BASE 0x1000007FFD4EC000ull +#define NIC1_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC1_MAC_CH0_MAC_PCS_SECTION 0x4000 + +#define mmNIC1_MAC_CH0_MAC_128_BASE 0x1000007FFD4EC400ull +#define NIC1_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC1_MAC_CH0_MAC_128_SECTION 0x4000 + +#define mmNIC1_MAC_CH0_MAC_AN_BASE 0x1000007FFD4EC800ull +#define NIC1_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC1_MAC_CH0_MAC_AN_SECTION 0x8000 + +#define mmNIC1_MAC_CH1_MAC_PCS_BASE 0x1000007FFD4ED000ull +#define NIC1_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC1_MAC_CH1_MAC_PCS_SECTION 0x4000 + +#define mmNIC1_MAC_CH1_MAC_128_BASE 0x1000007FFD4ED400ull +#define NIC1_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC1_MAC_CH1_MAC_128_SECTION 0x4000 + +#define mmNIC1_MAC_CH1_MAC_AN_BASE 0x1000007FFD4ED800ull +#define NIC1_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC1_MAC_CH1_MAC_AN_SECTION 0x8000 + +#define mmNIC1_MAC_CH2_MAC_PCS_BASE 0x1000007FFD4EE000ull +#define NIC1_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC1_MAC_CH2_MAC_PCS_SECTION 0x4000 + +#define mmNIC1_MAC_CH2_MAC_128_BASE 0x1000007FFD4EE400ull +#define NIC1_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC1_MAC_CH2_MAC_128_SECTION 0x4000 + +#define mmNIC1_MAC_CH2_MAC_AN_BASE 0x1000007FFD4EE800ull +#define NIC1_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC1_MAC_CH2_MAC_AN_SECTION 0x8000 + +#define mmNIC1_MAC_CH3_MAC_PCS_BASE 0x1000007FFD4EF000ull +#define NIC1_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC1_MAC_CH3_MAC_PCS_SECTION 0x4000 + +#define mmNIC1_MAC_CH3_MAC_128_BASE 0x1000007FFD4EF400ull +#define NIC1_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC1_MAC_CH3_MAC_128_SECTION 0x4000 + +#define mmNIC1_MAC_CH3_MAC_AN_BASE 0x1000007FFD4EF800ull +#define NIC1_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC1_MAC_CH3_MAC_AN_SECTION 0x10800 + +#define mmNIC2_UMR0_0_UNSECURE_DOORBELL0_BASE 0x1000007FFD500000ull +#define NIC2_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR0_0_UNSECURE_DOORBELL1_BASE 0x1000007FFD500080ull +#define NIC2_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD500100ull +#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD500180ull +#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR0_0_SPECIAL_BASE 0x1000007FFD500E80ull +#define NIC2_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_0_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR0_1_UNSECURE_DOORBELL0_BASE 0x1000007FFD501000ull +#define NIC2_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR0_1_UNSECURE_DOORBELL1_BASE 0x1000007FFD501080ull +#define NIC2_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD501100ull +#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD501180ull +#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR0_1_SPECIAL_BASE 0x1000007FFD501E80ull +#define NIC2_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_1_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR0_2_UNSECURE_DOORBELL0_BASE 0x1000007FFD502000ull +#define NIC2_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR0_2_UNSECURE_DOORBELL1_BASE 0x1000007FFD502080ull +#define NIC2_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD502100ull +#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD502180ull +#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR0_2_SPECIAL_BASE 0x1000007FFD502E80ull +#define NIC2_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_2_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR0_3_UNSECURE_DOORBELL0_BASE 0x1000007FFD503000ull +#define NIC2_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR0_3_UNSECURE_DOORBELL1_BASE 0x1000007FFD503080ull +#define NIC2_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD503100ull +#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD503180ull +#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR0_3_SPECIAL_BASE 0x1000007FFD503E80ull +#define NIC2_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_3_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR0_4_UNSECURE_DOORBELL0_BASE 0x1000007FFD504000ull +#define NIC2_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR0_4_UNSECURE_DOORBELL1_BASE 0x1000007FFD504080ull +#define NIC2_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD504100ull +#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD504180ull +#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR0_4_SPECIAL_BASE 0x1000007FFD504E80ull +#define NIC2_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_4_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR0_5_UNSECURE_DOORBELL0_BASE 0x1000007FFD505000ull +#define NIC2_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR0_5_UNSECURE_DOORBELL1_BASE 0x1000007FFD505080ull +#define NIC2_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD505100ull +#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD505180ull +#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR0_5_SPECIAL_BASE 0x1000007FFD505E80ull +#define NIC2_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_5_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR0_6_UNSECURE_DOORBELL0_BASE 0x1000007FFD506000ull +#define NIC2_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR0_6_UNSECURE_DOORBELL1_BASE 0x1000007FFD506080ull +#define NIC2_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD506100ull +#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD506180ull +#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR0_6_SPECIAL_BASE 0x1000007FFD506E80ull +#define NIC2_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_6_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR0_7_UNSECURE_DOORBELL0_BASE 0x1000007FFD507000ull +#define NIC2_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR0_7_UNSECURE_DOORBELL1_BASE 0x1000007FFD507080ull +#define NIC2_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD507100ull +#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD507180ull +#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR0_7_SPECIAL_BASE 0x1000007FFD507E80ull +#define NIC2_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_7_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR0_8_UNSECURE_DOORBELL0_BASE 0x1000007FFD508000ull +#define NIC2_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR0_8_UNSECURE_DOORBELL1_BASE 0x1000007FFD508080ull +#define NIC2_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD508100ull +#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD508180ull +#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR0_8_SPECIAL_BASE 0x1000007FFD508E80ull +#define NIC2_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_8_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR0_9_UNSECURE_DOORBELL0_BASE 0x1000007FFD509000ull +#define NIC2_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR0_9_UNSECURE_DOORBELL1_BASE 0x1000007FFD509080ull +#define NIC2_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD509100ull +#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD509180ull +#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR0_9_SPECIAL_BASE 0x1000007FFD509E80ull +#define NIC2_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_9_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR0_10_UNSECURE_DOORBELL0_BASE 0x1000007FFD50A000ull +#define NIC2_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR0_10_UNSECURE_DOORBELL1_BASE 0x1000007FFD50A080ull +#define NIC2_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD50A100ull +#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD50A180ull +#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR0_10_SPECIAL_BASE 0x1000007FFD50AE80ull +#define NIC2_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_10_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR0_11_UNSECURE_DOORBELL0_BASE 0x1000007FFD50B000ull +#define NIC2_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR0_11_UNSECURE_DOORBELL1_BASE 0x1000007FFD50B080ull +#define NIC2_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD50B100ull +#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD50B180ull +#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR0_11_SPECIAL_BASE 0x1000007FFD50BE80ull +#define NIC2_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_11_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR0_12_UNSECURE_DOORBELL0_BASE 0x1000007FFD50C000ull +#define NIC2_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR0_12_UNSECURE_DOORBELL1_BASE 0x1000007FFD50C080ull +#define NIC2_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD50C100ull +#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD50C180ull +#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR0_12_SPECIAL_BASE 0x1000007FFD50CE80ull +#define NIC2_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_12_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR0_13_UNSECURE_DOORBELL0_BASE 0x1000007FFD50D000ull +#define NIC2_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR0_13_UNSECURE_DOORBELL1_BASE 0x1000007FFD50D080ull +#define NIC2_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD50D100ull +#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD50D180ull +#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR0_13_SPECIAL_BASE 0x1000007FFD50DE80ull +#define NIC2_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_13_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR0_14_UNSECURE_DOORBELL0_BASE 0x1000007FFD50E000ull +#define NIC2_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR0_14_UNSECURE_DOORBELL1_BASE 0x1000007FFD50E080ull +#define NIC2_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD50E100ull +#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD50E180ull +#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR0_14_SPECIAL_BASE 0x1000007FFD50EE80ull +#define NIC2_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR0_14_SPECIAL_SECTION 0x1180 + +#define mmNIC2_QM_DCCM0_BASE 0x1000007FFD510000ull +#define NIC2_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC2_QM_DCCM0_SECTION 0x8000 + +#define mmNIC2_QM_ARC_AUX0_BASE 0x1000007FFD518000ull +#define NIC2_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC2_QM_ARC_AUX0_SECTION 0xE800 + +#define mmNIC2_QM_ARC_AUX0_SPECIAL_BASE 0x1000007FFD518E80ull +#define NIC2_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 + +#define mmNIC2_QM0_BASE 0x1000007FFD51A000ull +#define NIC2_QM0_MAX_OFFSET 0x1000 +#define NIC2_QM0_SECTION 0x9000 + +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFD51A900ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFD51A908ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFD51A910ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFD51A918ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFD51A920ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFD51A928ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFD51A930ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFD51A938ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFD51A940ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFD51A948ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFD51A950ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFD51A958ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFD51A960ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFD51A968ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFD51A970ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmNIC2_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFD51A978ull +#define NIC2_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC2_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmNIC2_QM0_AXUSER_SECURED_BASE 0x1000007FFD51AB00ull +#define NIC2_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC2_QM0_AXUSER_SECURED_SECTION 0x8000 + +#define mmNIC2_QM0_AXUSER_NONSECURED_BASE 0x1000007FFD51AB80ull +#define NIC2_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC2_QM0_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmNIC2_QM0_DBG_HBW_BASE 0x1000007FFD51AC00ull +#define NIC2_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC2_QM0_DBG_HBW_SECTION 0x8000 + +#define mmNIC2_QM0_DBG_LBW_BASE 0x1000007FFD51AC80ull +#define NIC2_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC2_QM0_DBG_LBW_SECTION 0x1000 + +#define mmNIC2_QM0_CGM_BASE 0x1000007FFD51AD80ull +#define NIC2_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC2_QM0_CGM_SECTION 0x1000 + +#define mmNIC2_QM0_SPECIAL_BASE 0x1000007FFD51AE80ull +#define NIC2_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_QM0_SPECIAL_SECTION 0x4180 + +#define mmNIC2_QPC0_BASE 0x1000007FFD51F000ull +#define NIC2_QPC0_MAX_OFFSET 0x1000 +#define NIC2_QPC0_SECTION 0x7200 + +#define mmNIC2_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x1000007FFD51F720ull +#define NIC2_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x1000007FFD51F728ull +#define NIC2_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x1000007FFD51F730ull +#define NIC2_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x1000007FFD51F738ull +#define NIC2_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x1000007FFD51F740ull +#define NIC2_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x1000007FFD51F748ull +#define NIC2_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x1000007FFD51F750ull +#define NIC2_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x1000007FFD51F758ull +#define NIC2_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x1000007FFD51F760ull +#define NIC2_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x1000007FFD51F768ull +#define NIC2_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x1000007FFD51F770ull +#define NIC2_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x1000007FFD51F778ull +#define NIC2_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x1000007FFD51F780ull +#define NIC2_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x1000007FFD51F788ull +#define NIC2_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x1000007FFD51F790ull +#define NIC2_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x1000007FFD51F798ull +#define NIC2_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x1000007FFD51F7A0ull +#define NIC2_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x1000007FFD51F7A8ull +#define NIC2_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x1000007FFD51F7B0ull +#define NIC2_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x1000007FFD51F7B8ull +#define NIC2_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x1000007FFD51F7C0ull +#define NIC2_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x1000007FFD51F7C8ull +#define NIC2_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x1000007FFD51F7D0ull +#define NIC2_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x1000007FFD51F7D8ull +#define NIC2_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x1000007FFD51F7E0ull +#define NIC2_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x1000007FFD51F7E8ull +#define NIC2_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x1000007FFD51F7F0ull +#define NIC2_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x1000007FFD51F7F8ull +#define NIC2_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x1000007FFD51F800ull +#define NIC2_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x1000007FFD51F808ull +#define NIC2_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x1000007FFD51F810ull +#define NIC2_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x1000007FFD51F818ull +#define NIC2_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 + +#define mmNIC2_QPC0_AXUSER_CONG_QUE_BASE 0x1000007FFD51FB80ull +#define NIC2_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC2_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 + +#define mmNIC2_QPC0_AXUSER_RXWQE_BASE 0x1000007FFD51FBE0ull +#define NIC2_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC2_QPC0_AXUSER_RXWQE_SECTION 0x6000 + +#define mmNIC2_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x1000007FFD51FC40ull +#define NIC2_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC2_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 + +#define mmNIC2_QPC0_AXUSER_DB_FIFO_BASE 0x1000007FFD51FCA0ull +#define NIC2_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC2_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 + +#define mmNIC2_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x1000007FFD51FD00ull +#define NIC2_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC2_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 + +#define mmNIC2_QPC0_AXUSER_ERR_FIFO_BASE 0x1000007FFD51FD60ull +#define NIC2_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC2_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 + +#define mmNIC2_QPC0_AXUSER_QPC_RESP_BASE 0x1000007FFD51FDC0ull +#define NIC2_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC2_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 + +#define mmNIC2_QPC0_AXUSER_QPC_REQ_BASE 0x1000007FFD51FE20ull +#define NIC2_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC2_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 + +#define mmNIC2_QPC0_SPECIAL_BASE 0x1000007FFD51FE80ull +#define NIC2_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_QPC0_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR1_0_UNSECURE_DOORBELL0_BASE 0x1000007FFD520000ull +#define NIC2_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR1_0_UNSECURE_DOORBELL1_BASE 0x1000007FFD520080ull +#define NIC2_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD520100ull +#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD520180ull +#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR1_0_SPECIAL_BASE 0x1000007FFD520E80ull +#define NIC2_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_0_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR1_1_UNSECURE_DOORBELL0_BASE 0x1000007FFD521000ull +#define NIC2_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR1_1_UNSECURE_DOORBELL1_BASE 0x1000007FFD521080ull +#define NIC2_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD521100ull +#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD521180ull +#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR1_1_SPECIAL_BASE 0x1000007FFD521E80ull +#define NIC2_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_1_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR1_2_UNSECURE_DOORBELL0_BASE 0x1000007FFD522000ull +#define NIC2_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR1_2_UNSECURE_DOORBELL1_BASE 0x1000007FFD522080ull +#define NIC2_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD522100ull +#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD522180ull +#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR1_2_SPECIAL_BASE 0x1000007FFD522E80ull +#define NIC2_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_2_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR1_3_UNSECURE_DOORBELL0_BASE 0x1000007FFD523000ull +#define NIC2_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR1_3_UNSECURE_DOORBELL1_BASE 0x1000007FFD523080ull +#define NIC2_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD523100ull +#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD523180ull +#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR1_3_SPECIAL_BASE 0x1000007FFD523E80ull +#define NIC2_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_3_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR1_4_UNSECURE_DOORBELL0_BASE 0x1000007FFD524000ull +#define NIC2_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR1_4_UNSECURE_DOORBELL1_BASE 0x1000007FFD524080ull +#define NIC2_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD524100ull +#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD524180ull +#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR1_4_SPECIAL_BASE 0x1000007FFD524E80ull +#define NIC2_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_4_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR1_5_UNSECURE_DOORBELL0_BASE 0x1000007FFD525000ull +#define NIC2_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR1_5_UNSECURE_DOORBELL1_BASE 0x1000007FFD525080ull +#define NIC2_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD525100ull +#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD525180ull +#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR1_5_SPECIAL_BASE 0x1000007FFD525E80ull +#define NIC2_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_5_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR1_6_UNSECURE_DOORBELL0_BASE 0x1000007FFD526000ull +#define NIC2_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR1_6_UNSECURE_DOORBELL1_BASE 0x1000007FFD526080ull +#define NIC2_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD526100ull +#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD526180ull +#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR1_6_SPECIAL_BASE 0x1000007FFD526E80ull +#define NIC2_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_6_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR1_7_UNSECURE_DOORBELL0_BASE 0x1000007FFD527000ull +#define NIC2_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR1_7_UNSECURE_DOORBELL1_BASE 0x1000007FFD527080ull +#define NIC2_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD527100ull +#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD527180ull +#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR1_7_SPECIAL_BASE 0x1000007FFD527E80ull +#define NIC2_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_7_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR1_8_UNSECURE_DOORBELL0_BASE 0x1000007FFD528000ull +#define NIC2_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR1_8_UNSECURE_DOORBELL1_BASE 0x1000007FFD528080ull +#define NIC2_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD528100ull +#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD528180ull +#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR1_8_SPECIAL_BASE 0x1000007FFD528E80ull +#define NIC2_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_8_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR1_9_UNSECURE_DOORBELL0_BASE 0x1000007FFD529000ull +#define NIC2_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR1_9_UNSECURE_DOORBELL1_BASE 0x1000007FFD529080ull +#define NIC2_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD529100ull +#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD529180ull +#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR1_9_SPECIAL_BASE 0x1000007FFD529E80ull +#define NIC2_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_9_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR1_10_UNSECURE_DOORBELL0_BASE 0x1000007FFD52A000ull +#define NIC2_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR1_10_UNSECURE_DOORBELL1_BASE 0x1000007FFD52A080ull +#define NIC2_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD52A100ull +#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD52A180ull +#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR1_10_SPECIAL_BASE 0x1000007FFD52AE80ull +#define NIC2_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_10_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR1_11_UNSECURE_DOORBELL0_BASE 0x1000007FFD52B000ull +#define NIC2_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR1_11_UNSECURE_DOORBELL1_BASE 0x1000007FFD52B080ull +#define NIC2_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD52B100ull +#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD52B180ull +#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR1_11_SPECIAL_BASE 0x1000007FFD52BE80ull +#define NIC2_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_11_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR1_12_UNSECURE_DOORBELL0_BASE 0x1000007FFD52C000ull +#define NIC2_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR1_12_UNSECURE_DOORBELL1_BASE 0x1000007FFD52C080ull +#define NIC2_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD52C100ull +#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD52C180ull +#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR1_12_SPECIAL_BASE 0x1000007FFD52CE80ull +#define NIC2_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_12_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR1_13_UNSECURE_DOORBELL0_BASE 0x1000007FFD52D000ull +#define NIC2_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR1_13_UNSECURE_DOORBELL1_BASE 0x1000007FFD52D080ull +#define NIC2_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD52D100ull +#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD52D180ull +#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR1_13_SPECIAL_BASE 0x1000007FFD52DE80ull +#define NIC2_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_13_SPECIAL_SECTION 0x1800 + +#define mmNIC2_UMR1_14_UNSECURE_DOORBELL0_BASE 0x1000007FFD52E000ull +#define NIC2_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC2_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC2_UMR1_14_UNSECURE_DOORBELL1_BASE 0x1000007FFD52E080ull +#define NIC2_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC2_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC2_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD52E100ull +#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC2_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD52E180ull +#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC2_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC2_UMR1_14_SPECIAL_BASE 0x1000007FFD52EE80ull +#define NIC2_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_UMR1_14_SPECIAL_SECTION 0x1180 + +#define mmNIC2_QM_DCCM1_BASE 0x1000007FFD530000ull +#define NIC2_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC2_QM_DCCM1_SECTION 0x8000 + +#define mmNIC2_QM_ARC_AUX1_BASE 0x1000007FFD538000ull +#define NIC2_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC2_QM_ARC_AUX1_SECTION 0xE800 + +#define mmNIC2_QM_ARC_AUX1_SPECIAL_BASE 0x1000007FFD538E80ull +#define NIC2_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 + +#define mmNIC2_QM1_BASE 0x1000007FFD53A000ull +#define NIC2_QM1_MAX_OFFSET 0x1000 +#define NIC2_QM1_SECTION 0x9000 + +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFD53A900ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFD53A908ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFD53A910ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFD53A918ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFD53A920ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFD53A928ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFD53A930ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFD53A938ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFD53A940ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFD53A948ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFD53A950ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFD53A958ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFD53A960ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFD53A968ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFD53A970ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmNIC2_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFD53A978ull +#define NIC2_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC2_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmNIC2_QM1_AXUSER_SECURED_BASE 0x1000007FFD53AB00ull +#define NIC2_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC2_QM1_AXUSER_SECURED_SECTION 0x8000 + +#define mmNIC2_QM1_AXUSER_NONSECURED_BASE 0x1000007FFD53AB80ull +#define NIC2_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC2_QM1_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmNIC2_QM1_DBG_HBW_BASE 0x1000007FFD53AC00ull +#define NIC2_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC2_QM1_DBG_HBW_SECTION 0x8000 + +#define mmNIC2_QM1_DBG_LBW_BASE 0x1000007FFD53AC80ull +#define NIC2_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC2_QM1_DBG_LBW_SECTION 0x1000 + +#define mmNIC2_QM1_CGM_BASE 0x1000007FFD53AD80ull +#define NIC2_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC2_QM1_CGM_SECTION 0x1000 + +#define mmNIC2_QM1_SPECIAL_BASE 0x1000007FFD53AE80ull +#define NIC2_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_QM1_SPECIAL_SECTION 0x4180 + +#define mmNIC2_QPC1_BASE 0x1000007FFD53F000ull +#define NIC2_QPC1_MAX_OFFSET 0x1000 +#define NIC2_QPC1_SECTION 0x7200 + +#define mmNIC2_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x1000007FFD53F720ull +#define NIC2_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x1000007FFD53F728ull +#define NIC2_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x1000007FFD53F730ull +#define NIC2_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x1000007FFD53F738ull +#define NIC2_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x1000007FFD53F740ull +#define NIC2_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x1000007FFD53F748ull +#define NIC2_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x1000007FFD53F750ull +#define NIC2_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x1000007FFD53F758ull +#define NIC2_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x1000007FFD53F760ull +#define NIC2_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x1000007FFD53F768ull +#define NIC2_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x1000007FFD53F770ull +#define NIC2_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x1000007FFD53F778ull +#define NIC2_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x1000007FFD53F780ull +#define NIC2_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x1000007FFD53F788ull +#define NIC2_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x1000007FFD53F790ull +#define NIC2_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x1000007FFD53F798ull +#define NIC2_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x1000007FFD53F7A0ull +#define NIC2_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x1000007FFD53F7A8ull +#define NIC2_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x1000007FFD53F7B0ull +#define NIC2_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x1000007FFD53F7B8ull +#define NIC2_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x1000007FFD53F7C0ull +#define NIC2_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x1000007FFD53F7C8ull +#define NIC2_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x1000007FFD53F7D0ull +#define NIC2_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x1000007FFD53F7D8ull +#define NIC2_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x1000007FFD53F7E0ull +#define NIC2_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x1000007FFD53F7E8ull +#define NIC2_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x1000007FFD53F7F0ull +#define NIC2_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x1000007FFD53F7F8ull +#define NIC2_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x1000007FFD53F800ull +#define NIC2_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x1000007FFD53F808ull +#define NIC2_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x1000007FFD53F810ull +#define NIC2_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC2_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x1000007FFD53F818ull +#define NIC2_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC2_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 + +#define mmNIC2_QPC1_AXUSER_CONG_QUE_BASE 0x1000007FFD53FB80ull +#define NIC2_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC2_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 + +#define mmNIC2_QPC1_AXUSER_RXWQE_BASE 0x1000007FFD53FBE0ull +#define NIC2_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC2_QPC1_AXUSER_RXWQE_SECTION 0x6000 + +#define mmNIC2_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x1000007FFD53FC40ull +#define NIC2_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC2_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 + +#define mmNIC2_QPC1_AXUSER_DB_FIFO_BASE 0x1000007FFD53FCA0ull +#define NIC2_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC2_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 + +#define mmNIC2_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x1000007FFD53FD00ull +#define NIC2_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC2_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 + +#define mmNIC2_QPC1_AXUSER_ERR_FIFO_BASE 0x1000007FFD53FD60ull +#define NIC2_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC2_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 + +#define mmNIC2_QPC1_AXUSER_QPC_RESP_BASE 0x1000007FFD53FDC0ull +#define NIC2_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC2_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 + +#define mmNIC2_QPC1_AXUSER_QPC_REQ_BASE 0x1000007FFD53FE20ull +#define NIC2_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC2_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 + +#define mmNIC2_QPC1_SPECIAL_BASE 0x1000007FFD53FE80ull +#define NIC2_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_QPC1_SPECIAL_SECTION 0x8180 + +#define mmNIC2_TMR_BASE 0x1000007FFD548000ull +#define NIC2_TMR_MAX_OFFSET 0x1000 +#define NIC2_TMR_SECTION 0xD600 + +#define mmNIC2_TMR_AXUSER_TMR_FREE_LIST_BASE 0x1000007FFD548D60ull +#define NIC2_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC2_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 + +#define mmNIC2_TMR_AXUSER_TMR_FIFO_BASE 0x1000007FFD548DC0ull +#define NIC2_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC2_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 + +#define mmNIC2_TMR_AXUSER_TMR_FSM_BASE 0x1000007FFD548E20ull +#define NIC2_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC2_TMR_AXUSER_TMR_FSM_SECTION 0x6000 + +#define mmNIC2_TMR_SPECIAL_BASE 0x1000007FFD548E80ull +#define NIC2_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_TMR_SPECIAL_SECTION 0x1800 + +#define mmNIC2_RXB_CORE_BASE 0x1000007FFD549000ull +#define NIC2_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC2_RXB_CORE_SECTION 0x6100 + +#define mmNIC2_RXB_CORE_SCT_AWUSER_BASE 0x1000007FFD549610ull +#define NIC2_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC2_RXB_CORE_SCT_AWUSER_SECTION 0x8700 + +#define mmNIC2_RXB_CORE_SPECIAL_BASE 0x1000007FFD549E80ull +#define NIC2_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_RXB_CORE_SPECIAL_SECTION 0x1800 + +#define mmNIC2_RXE0_BASE 0x1000007FFD54A000ull +#define NIC2_RXE0_MAX_OFFSET 0x1000 +#define NIC2_RXE0_SECTION 0x9000 + +#define mmNIC2_RXE0_WQE_ARUSER_BASE 0x1000007FFD54A900ull +#define NIC2_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC2_RXE0_WQE_ARUSER_SECTION 0x5800 + +#define mmNIC2_RXE0_SPECIAL_BASE 0x1000007FFD54AE80ull +#define NIC2_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_RXE0_SPECIAL_SECTION 0x1800 + +#define mmNIC2_RXE1_BASE 0x1000007FFD54B000ull +#define NIC2_RXE1_MAX_OFFSET 0x1000 +#define NIC2_RXE1_SECTION 0x9000 + +#define mmNIC2_RXE1_WQE_ARUSER_BASE 0x1000007FFD54B900ull +#define NIC2_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC2_RXE1_WQE_ARUSER_SECTION 0x5800 + +#define mmNIC2_RXE1_SPECIAL_BASE 0x1000007FFD54BE80ull +#define NIC2_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_RXE1_SPECIAL_SECTION 0x1800 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ0_BASE 0x1000007FFD54C000ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ1_BASE 0x1000007FFD54C050ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ2_BASE 0x1000007FFD54C0A0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ3_BASE 0x1000007FFD54C0F0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ4_BASE 0x1000007FFD54C140ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ5_BASE 0x1000007FFD54C190ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ6_BASE 0x1000007FFD54C1E0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ7_BASE 0x1000007FFD54C230ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ8_BASE 0x1000007FFD54C280ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ9_BASE 0x1000007FFD54C2D0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ10_BASE 0x1000007FFD54C320ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ11_BASE 0x1000007FFD54C370ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ12_BASE 0x1000007FFD54C3C0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ13_BASE 0x1000007FFD54C410ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ14_BASE 0x1000007FFD54C460ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ15_BASE 0x1000007FFD54C4B0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ16_BASE 0x1000007FFD54C500ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ17_BASE 0x1000007FFD54C550ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ18_BASE 0x1000007FFD54C5A0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ19_BASE 0x1000007FFD54C5F0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ20_BASE 0x1000007FFD54C640ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ21_BASE 0x1000007FFD54C690ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ22_BASE 0x1000007FFD54C6E0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ23_BASE 0x1000007FFD54C730ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ24_BASE 0x1000007FFD54C780ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ25_BASE 0x1000007FFD54C7D0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ26_BASE 0x1000007FFD54C820ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ27_BASE 0x1000007FFD54C870ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ28_BASE 0x1000007FFD54C8C0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ29_BASE 0x1000007FFD54C910ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ30_BASE 0x1000007FFD54C960ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 + +#define mmNIC2_RXE0_AXUSER_AXUSER_CQ31_BASE 0x1000007FFD54C9B0ull +#define NIC2_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC2_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 + +#define mmNIC2_RXE0_AXUSER_SPECIAL_BASE 0x1000007FFD54CE80ull +#define NIC2_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_RXE0_AXUSER_SPECIAL_SECTION 0x1800 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ0_BASE 0x1000007FFD54D000ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ1_BASE 0x1000007FFD54D050ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ2_BASE 0x1000007FFD54D0A0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ3_BASE 0x1000007FFD54D0F0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ4_BASE 0x1000007FFD54D140ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ5_BASE 0x1000007FFD54D190ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ6_BASE 0x1000007FFD54D1E0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ7_BASE 0x1000007FFD54D230ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ8_BASE 0x1000007FFD54D280ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ9_BASE 0x1000007FFD54D2D0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ10_BASE 0x1000007FFD54D320ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ11_BASE 0x1000007FFD54D370ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ12_BASE 0x1000007FFD54D3C0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ13_BASE 0x1000007FFD54D410ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ14_BASE 0x1000007FFD54D460ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ15_BASE 0x1000007FFD54D4B0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ16_BASE 0x1000007FFD54D500ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ17_BASE 0x1000007FFD54D550ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ18_BASE 0x1000007FFD54D5A0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ19_BASE 0x1000007FFD54D5F0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ20_BASE 0x1000007FFD54D640ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ21_BASE 0x1000007FFD54D690ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ22_BASE 0x1000007FFD54D6E0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ23_BASE 0x1000007FFD54D730ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ24_BASE 0x1000007FFD54D780ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ25_BASE 0x1000007FFD54D7D0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ26_BASE 0x1000007FFD54D820ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ27_BASE 0x1000007FFD54D870ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ28_BASE 0x1000007FFD54D8C0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ29_BASE 0x1000007FFD54D910ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ30_BASE 0x1000007FFD54D960ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 + +#define mmNIC2_RXE1_AXUSER_AXUSER_CQ31_BASE 0x1000007FFD54D9B0ull +#define NIC2_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC2_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 + +#define mmNIC2_RXE1_AXUSER_SPECIAL_BASE 0x1000007FFD54DE80ull +#define NIC2_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_RXE1_AXUSER_SPECIAL_SECTION 0x2180 + +#define mmNIC2_TXS0_BASE 0x1000007FFD550000ull +#define NIC2_TXS0_MAX_OFFSET 0x1000 +#define NIC2_TXS0_SECTION 0xE800 + +#define mmNIC2_TXS0_SPECIAL_BASE 0x1000007FFD550E80ull +#define NIC2_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_TXS0_SPECIAL_SECTION 0x1800 + +#define mmNIC2_TXS1_BASE 0x1000007FFD551000ull +#define NIC2_TXS1_MAX_OFFSET 0x1000 +#define NIC2_TXS1_SECTION 0xE800 + +#define mmNIC2_TXS1_SPECIAL_BASE 0x1000007FFD551E80ull +#define NIC2_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_TXS1_SPECIAL_SECTION 0x1800 + +#define mmNIC2_TXE0_BASE 0x1000007FFD552000ull +#define NIC2_TXE0_MAX_OFFSET 0x1000 +#define NIC2_TXE0_SECTION 0xE800 + +#define mmNIC2_TXE0_SPECIAL_BASE 0x1000007FFD552E80ull +#define NIC2_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_TXE0_SPECIAL_SECTION 0x1800 + +#define mmNIC2_TXE1_BASE 0x1000007FFD553000ull +#define NIC2_TXE1_MAX_OFFSET 0x1000 +#define NIC2_TXE1_SECTION 0xE800 + +#define mmNIC2_TXE1_SPECIAL_BASE 0x1000007FFD553E80ull +#define NIC2_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_TXE1_SPECIAL_SECTION 0x1800 + +#define mmNIC2_TXB_BASE 0x1000007FFD554000ull +#define NIC2_TXB_MAX_OFFSET 0x1000 +#define NIC2_TXB_SECTION 0xE800 + +#define mmNIC2_TXB_SPECIAL_BASE 0x1000007FFD554E80ull +#define NIC2_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_TXB_SPECIAL_SECTION 0x1800 + +#define mmNIC2_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFD555000ull +#define NIC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmNIC2_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFD555200ull +#define NIC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmNIC2_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFD555400ull +#define NIC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmNIC2_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFD555600ull +#define NIC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmNIC2_MSTR_IF_E2E_CRDT_BASE 0x1000007FFD555800ull +#define NIC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC2_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmNIC2_MSTR_IF_AXUSER_BASE 0x1000007FFD555A80ull +#define NIC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC2_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmNIC2_MSTR_IF_DBG_HBW_BASE 0x1000007FFD555B00ull +#define NIC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC2_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmNIC2_MSTR_IF_DBG_LBW_BASE 0x1000007FFD555B80ull +#define NIC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC2_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmNIC2_MSTR_IF_CORE_HBW_BASE 0x1000007FFD555C00ull +#define NIC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC2_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmNIC2_MSTR_IF_CORE_LBW_BASE 0x1000007FFD555D80ull +#define NIC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC2_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmNIC2_MSTR_IF_SPECIAL_BASE 0x1000007FFD555E80ull +#define NIC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmNIC2_TX_AXUSER_BASE 0x1000007FFD556000ull +#define NIC2_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC2_TX_AXUSER_SECTION 0x2000 + +#define mmNIC2_SERDES0_BASE 0x1000007FFD558000ull +#define NIC2_SERDES0_MAX_OFFSET 0x3E40 +#define NIC2_SERDES0_SECTION 0x4000 + +#define mmNIC2_SERDES1_BASE 0x1000007FFD55C000ull +#define NIC2_SERDES1_MAX_OFFSET 0x3E40 +#define NIC2_SERDES1_SECTION 0x4000 + +#define mmNIC2_PHY_BASE 0x1000007FFD560000ull +#define NIC2_PHY_MAX_OFFSET 0x1000 +#define NIC2_PHY_SECTION 0xE800 + +#define mmNIC2_PHY_SPECIAL_BASE 0x1000007FFD560E80ull +#define NIC2_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC2_PHY_SPECIAL_SECTION 0x7180 + +#define mmPRT2_MAC_AUX_BASE 0x1000007FFD568000ull +#define PRT2_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT2_MAC_AUX_SECTION 0xE800 + +#define mmPRT2_MAC_AUX_SPECIAL_BASE 0x1000007FFD568E80ull +#define PRT2_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT2_MAC_AUX_SPECIAL_SECTION 0x1800 + +#define mmPRT2_MAC_CORE_BASE 0x1000007FFD569000ull +#define PRT2_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT2_MAC_CORE_SECTION 0xE800 + +#define mmPRT2_MAC_CORE_SPECIAL_BASE 0x1000007FFD569E80ull +#define PRT2_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT2_MAC_CORE_SPECIAL_SECTION 0x1800 + +#define mmNIC2_MAC_RS_FEC_BASE 0x1000007FFD56A000ull +#define NIC2_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC2_MAC_RS_FEC_SECTION 0x1000 + +#define mmNIC2_MAC_GLOB_STAT_NIC_MAC_STAT_BASE 0x1000007FFD56B000ull +#define NIC2_MAC_GLOB_STAT_NIC_MAC_STAT_MAX_OFFSET 0x4D00 +#define NIC2_MAC_GLOB_STAT_NIC_MAC_STAT_SECTION 0x8000 + +#define mmNIC2_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_BASE 0x1000007FFD56B800ull +#define NIC2_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC2_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_SECTION 0x8000 + +#define mmNIC2_MAC_CH0_MAC_PCS_BASE 0x1000007FFD56C000ull +#define NIC2_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC2_MAC_CH0_MAC_PCS_SECTION 0x4000 + +#define mmNIC2_MAC_CH0_MAC_128_BASE 0x1000007FFD56C400ull +#define NIC2_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC2_MAC_CH0_MAC_128_SECTION 0x4000 + +#define mmNIC2_MAC_CH0_MAC_AN_BASE 0x1000007FFD56C800ull +#define NIC2_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC2_MAC_CH0_MAC_AN_SECTION 0x8000 + +#define mmNIC2_MAC_CH1_MAC_PCS_BASE 0x1000007FFD56D000ull +#define NIC2_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC2_MAC_CH1_MAC_PCS_SECTION 0x4000 + +#define mmNIC2_MAC_CH1_MAC_128_BASE 0x1000007FFD56D400ull +#define NIC2_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC2_MAC_CH1_MAC_128_SECTION 0x4000 + +#define mmNIC2_MAC_CH1_MAC_AN_BASE 0x1000007FFD56D800ull +#define NIC2_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC2_MAC_CH1_MAC_AN_SECTION 0x8000 + +#define mmNIC2_MAC_CH2_MAC_PCS_BASE 0x1000007FFD56E000ull +#define NIC2_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC2_MAC_CH2_MAC_PCS_SECTION 0x4000 + +#define mmNIC2_MAC_CH2_MAC_128_BASE 0x1000007FFD56E400ull +#define NIC2_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC2_MAC_CH2_MAC_128_SECTION 0x4000 + +#define mmNIC2_MAC_CH2_MAC_AN_BASE 0x1000007FFD56E800ull +#define NIC2_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC2_MAC_CH2_MAC_AN_SECTION 0x8000 + +#define mmNIC2_MAC_CH3_MAC_PCS_BASE 0x1000007FFD56F000ull +#define NIC2_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC2_MAC_CH3_MAC_PCS_SECTION 0x4000 + +#define mmNIC2_MAC_CH3_MAC_128_BASE 0x1000007FFD56F400ull +#define NIC2_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC2_MAC_CH3_MAC_128_SECTION 0x4000 + +#define mmNIC2_MAC_CH3_MAC_AN_BASE 0x1000007FFD56F800ull +#define NIC2_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC2_MAC_CH3_MAC_AN_SECTION 0x10800 + +#define mmNIC3_UMR0_0_UNSECURE_DOORBELL0_BASE 0x1000007FFD580000ull +#define NIC3_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR0_0_UNSECURE_DOORBELL1_BASE 0x1000007FFD580080ull +#define NIC3_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD580100ull +#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD580180ull +#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR0_0_SPECIAL_BASE 0x1000007FFD580E80ull +#define NIC3_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_0_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR0_1_UNSECURE_DOORBELL0_BASE 0x1000007FFD581000ull +#define NIC3_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR0_1_UNSECURE_DOORBELL1_BASE 0x1000007FFD581080ull +#define NIC3_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD581100ull +#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD581180ull +#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR0_1_SPECIAL_BASE 0x1000007FFD581E80ull +#define NIC3_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_1_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR0_2_UNSECURE_DOORBELL0_BASE 0x1000007FFD582000ull +#define NIC3_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR0_2_UNSECURE_DOORBELL1_BASE 0x1000007FFD582080ull +#define NIC3_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD582100ull +#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD582180ull +#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR0_2_SPECIAL_BASE 0x1000007FFD582E80ull +#define NIC3_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_2_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR0_3_UNSECURE_DOORBELL0_BASE 0x1000007FFD583000ull +#define NIC3_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR0_3_UNSECURE_DOORBELL1_BASE 0x1000007FFD583080ull +#define NIC3_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD583100ull +#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD583180ull +#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR0_3_SPECIAL_BASE 0x1000007FFD583E80ull +#define NIC3_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_3_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR0_4_UNSECURE_DOORBELL0_BASE 0x1000007FFD584000ull +#define NIC3_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR0_4_UNSECURE_DOORBELL1_BASE 0x1000007FFD584080ull +#define NIC3_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD584100ull +#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD584180ull +#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR0_4_SPECIAL_BASE 0x1000007FFD584E80ull +#define NIC3_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_4_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR0_5_UNSECURE_DOORBELL0_BASE 0x1000007FFD585000ull +#define NIC3_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR0_5_UNSECURE_DOORBELL1_BASE 0x1000007FFD585080ull +#define NIC3_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD585100ull +#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD585180ull +#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR0_5_SPECIAL_BASE 0x1000007FFD585E80ull +#define NIC3_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_5_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR0_6_UNSECURE_DOORBELL0_BASE 0x1000007FFD586000ull +#define NIC3_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR0_6_UNSECURE_DOORBELL1_BASE 0x1000007FFD586080ull +#define NIC3_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD586100ull +#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD586180ull +#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR0_6_SPECIAL_BASE 0x1000007FFD586E80ull +#define NIC3_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_6_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR0_7_UNSECURE_DOORBELL0_BASE 0x1000007FFD587000ull +#define NIC3_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR0_7_UNSECURE_DOORBELL1_BASE 0x1000007FFD587080ull +#define NIC3_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD587100ull +#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD587180ull +#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR0_7_SPECIAL_BASE 0x1000007FFD587E80ull +#define NIC3_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_7_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR0_8_UNSECURE_DOORBELL0_BASE 0x1000007FFD588000ull +#define NIC3_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR0_8_UNSECURE_DOORBELL1_BASE 0x1000007FFD588080ull +#define NIC3_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD588100ull +#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD588180ull +#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR0_8_SPECIAL_BASE 0x1000007FFD588E80ull +#define NIC3_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_8_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR0_9_UNSECURE_DOORBELL0_BASE 0x1000007FFD589000ull +#define NIC3_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR0_9_UNSECURE_DOORBELL1_BASE 0x1000007FFD589080ull +#define NIC3_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD589100ull +#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD589180ull +#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR0_9_SPECIAL_BASE 0x1000007FFD589E80ull +#define NIC3_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_9_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR0_10_UNSECURE_DOORBELL0_BASE 0x1000007FFD58A000ull +#define NIC3_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR0_10_UNSECURE_DOORBELL1_BASE 0x1000007FFD58A080ull +#define NIC3_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD58A100ull +#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD58A180ull +#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR0_10_SPECIAL_BASE 0x1000007FFD58AE80ull +#define NIC3_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_10_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR0_11_UNSECURE_DOORBELL0_BASE 0x1000007FFD58B000ull +#define NIC3_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR0_11_UNSECURE_DOORBELL1_BASE 0x1000007FFD58B080ull +#define NIC3_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD58B100ull +#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD58B180ull +#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR0_11_SPECIAL_BASE 0x1000007FFD58BE80ull +#define NIC3_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_11_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR0_12_UNSECURE_DOORBELL0_BASE 0x1000007FFD58C000ull +#define NIC3_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR0_12_UNSECURE_DOORBELL1_BASE 0x1000007FFD58C080ull +#define NIC3_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD58C100ull +#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD58C180ull +#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR0_12_SPECIAL_BASE 0x1000007FFD58CE80ull +#define NIC3_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_12_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR0_13_UNSECURE_DOORBELL0_BASE 0x1000007FFD58D000ull +#define NIC3_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR0_13_UNSECURE_DOORBELL1_BASE 0x1000007FFD58D080ull +#define NIC3_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD58D100ull +#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD58D180ull +#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR0_13_SPECIAL_BASE 0x1000007FFD58DE80ull +#define NIC3_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_13_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR0_14_UNSECURE_DOORBELL0_BASE 0x1000007FFD58E000ull +#define NIC3_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR0_14_UNSECURE_DOORBELL1_BASE 0x1000007FFD58E080ull +#define NIC3_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD58E100ull +#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD58E180ull +#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR0_14_SPECIAL_BASE 0x1000007FFD58EE80ull +#define NIC3_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR0_14_SPECIAL_SECTION 0x1180 + +#define mmNIC3_QM_DCCM0_BASE 0x1000007FFD590000ull +#define NIC3_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC3_QM_DCCM0_SECTION 0x8000 + +#define mmNIC3_QM_ARC_AUX0_BASE 0x1000007FFD598000ull +#define NIC3_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC3_QM_ARC_AUX0_SECTION 0xE800 + +#define mmNIC3_QM_ARC_AUX0_SPECIAL_BASE 0x1000007FFD598E80ull +#define NIC3_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 + +#define mmNIC3_QM0_BASE 0x1000007FFD59A000ull +#define NIC3_QM0_MAX_OFFSET 0x1000 +#define NIC3_QM0_SECTION 0x9000 + +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFD59A900ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFD59A908ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFD59A910ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFD59A918ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFD59A920ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFD59A928ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFD59A930ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFD59A938ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFD59A940ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFD59A948ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFD59A950ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFD59A958ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFD59A960ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFD59A968ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFD59A970ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmNIC3_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFD59A978ull +#define NIC3_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC3_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmNIC3_QM0_AXUSER_SECURED_BASE 0x1000007FFD59AB00ull +#define NIC3_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC3_QM0_AXUSER_SECURED_SECTION 0x8000 + +#define mmNIC3_QM0_AXUSER_NONSECURED_BASE 0x1000007FFD59AB80ull +#define NIC3_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC3_QM0_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmNIC3_QM0_DBG_HBW_BASE 0x1000007FFD59AC00ull +#define NIC3_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC3_QM0_DBG_HBW_SECTION 0x8000 + +#define mmNIC3_QM0_DBG_LBW_BASE 0x1000007FFD59AC80ull +#define NIC3_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC3_QM0_DBG_LBW_SECTION 0x1000 + +#define mmNIC3_QM0_CGM_BASE 0x1000007FFD59AD80ull +#define NIC3_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC3_QM0_CGM_SECTION 0x1000 + +#define mmNIC3_QM0_SPECIAL_BASE 0x1000007FFD59AE80ull +#define NIC3_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_QM0_SPECIAL_SECTION 0x4180 + +#define mmNIC3_QPC0_BASE 0x1000007FFD59F000ull +#define NIC3_QPC0_MAX_OFFSET 0x1000 +#define NIC3_QPC0_SECTION 0x7200 + +#define mmNIC3_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x1000007FFD59F720ull +#define NIC3_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x1000007FFD59F728ull +#define NIC3_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x1000007FFD59F730ull +#define NIC3_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x1000007FFD59F738ull +#define NIC3_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x1000007FFD59F740ull +#define NIC3_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x1000007FFD59F748ull +#define NIC3_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x1000007FFD59F750ull +#define NIC3_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x1000007FFD59F758ull +#define NIC3_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x1000007FFD59F760ull +#define NIC3_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x1000007FFD59F768ull +#define NIC3_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x1000007FFD59F770ull +#define NIC3_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x1000007FFD59F778ull +#define NIC3_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x1000007FFD59F780ull +#define NIC3_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x1000007FFD59F788ull +#define NIC3_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x1000007FFD59F790ull +#define NIC3_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x1000007FFD59F798ull +#define NIC3_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x1000007FFD59F7A0ull +#define NIC3_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x1000007FFD59F7A8ull +#define NIC3_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x1000007FFD59F7B0ull +#define NIC3_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x1000007FFD59F7B8ull +#define NIC3_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x1000007FFD59F7C0ull +#define NIC3_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x1000007FFD59F7C8ull +#define NIC3_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x1000007FFD59F7D0ull +#define NIC3_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x1000007FFD59F7D8ull +#define NIC3_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x1000007FFD59F7E0ull +#define NIC3_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x1000007FFD59F7E8ull +#define NIC3_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x1000007FFD59F7F0ull +#define NIC3_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x1000007FFD59F7F8ull +#define NIC3_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x1000007FFD59F800ull +#define NIC3_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x1000007FFD59F808ull +#define NIC3_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x1000007FFD59F810ull +#define NIC3_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x1000007FFD59F818ull +#define NIC3_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 + +#define mmNIC3_QPC0_AXUSER_CONG_QUE_BASE 0x1000007FFD59FB80ull +#define NIC3_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC3_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 + +#define mmNIC3_QPC0_AXUSER_RXWQE_BASE 0x1000007FFD59FBE0ull +#define NIC3_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC3_QPC0_AXUSER_RXWQE_SECTION 0x6000 + +#define mmNIC3_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x1000007FFD59FC40ull +#define NIC3_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC3_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 + +#define mmNIC3_QPC0_AXUSER_DB_FIFO_BASE 0x1000007FFD59FCA0ull +#define NIC3_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC3_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 + +#define mmNIC3_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x1000007FFD59FD00ull +#define NIC3_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC3_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 + +#define mmNIC3_QPC0_AXUSER_ERR_FIFO_BASE 0x1000007FFD59FD60ull +#define NIC3_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC3_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 + +#define mmNIC3_QPC0_AXUSER_QPC_RESP_BASE 0x1000007FFD59FDC0ull +#define NIC3_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC3_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 + +#define mmNIC3_QPC0_AXUSER_QPC_REQ_BASE 0x1000007FFD59FE20ull +#define NIC3_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC3_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 + +#define mmNIC3_QPC0_SPECIAL_BASE 0x1000007FFD59FE80ull +#define NIC3_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_QPC0_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR1_0_UNSECURE_DOORBELL0_BASE 0x1000007FFD5A0000ull +#define NIC3_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR1_0_UNSECURE_DOORBELL1_BASE 0x1000007FFD5A0080ull +#define NIC3_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD5A0100ull +#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD5A0180ull +#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR1_0_SPECIAL_BASE 0x1000007FFD5A0E80ull +#define NIC3_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_0_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR1_1_UNSECURE_DOORBELL0_BASE 0x1000007FFD5A1000ull +#define NIC3_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR1_1_UNSECURE_DOORBELL1_BASE 0x1000007FFD5A1080ull +#define NIC3_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD5A1100ull +#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD5A1180ull +#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR1_1_SPECIAL_BASE 0x1000007FFD5A1E80ull +#define NIC3_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_1_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR1_2_UNSECURE_DOORBELL0_BASE 0x1000007FFD5A2000ull +#define NIC3_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR1_2_UNSECURE_DOORBELL1_BASE 0x1000007FFD5A2080ull +#define NIC3_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD5A2100ull +#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD5A2180ull +#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR1_2_SPECIAL_BASE 0x1000007FFD5A2E80ull +#define NIC3_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_2_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR1_3_UNSECURE_DOORBELL0_BASE 0x1000007FFD5A3000ull +#define NIC3_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR1_3_UNSECURE_DOORBELL1_BASE 0x1000007FFD5A3080ull +#define NIC3_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD5A3100ull +#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD5A3180ull +#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR1_3_SPECIAL_BASE 0x1000007FFD5A3E80ull +#define NIC3_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_3_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR1_4_UNSECURE_DOORBELL0_BASE 0x1000007FFD5A4000ull +#define NIC3_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR1_4_UNSECURE_DOORBELL1_BASE 0x1000007FFD5A4080ull +#define NIC3_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD5A4100ull +#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD5A4180ull +#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR1_4_SPECIAL_BASE 0x1000007FFD5A4E80ull +#define NIC3_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_4_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR1_5_UNSECURE_DOORBELL0_BASE 0x1000007FFD5A5000ull +#define NIC3_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR1_5_UNSECURE_DOORBELL1_BASE 0x1000007FFD5A5080ull +#define NIC3_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD5A5100ull +#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD5A5180ull +#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR1_5_SPECIAL_BASE 0x1000007FFD5A5E80ull +#define NIC3_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_5_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR1_6_UNSECURE_DOORBELL0_BASE 0x1000007FFD5A6000ull +#define NIC3_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR1_6_UNSECURE_DOORBELL1_BASE 0x1000007FFD5A6080ull +#define NIC3_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD5A6100ull +#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD5A6180ull +#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR1_6_SPECIAL_BASE 0x1000007FFD5A6E80ull +#define NIC3_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_6_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR1_7_UNSECURE_DOORBELL0_BASE 0x1000007FFD5A7000ull +#define NIC3_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR1_7_UNSECURE_DOORBELL1_BASE 0x1000007FFD5A7080ull +#define NIC3_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD5A7100ull +#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD5A7180ull +#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR1_7_SPECIAL_BASE 0x1000007FFD5A7E80ull +#define NIC3_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_7_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR1_8_UNSECURE_DOORBELL0_BASE 0x1000007FFD5A8000ull +#define NIC3_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR1_8_UNSECURE_DOORBELL1_BASE 0x1000007FFD5A8080ull +#define NIC3_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD5A8100ull +#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD5A8180ull +#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR1_8_SPECIAL_BASE 0x1000007FFD5A8E80ull +#define NIC3_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_8_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR1_9_UNSECURE_DOORBELL0_BASE 0x1000007FFD5A9000ull +#define NIC3_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR1_9_UNSECURE_DOORBELL1_BASE 0x1000007FFD5A9080ull +#define NIC3_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD5A9100ull +#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD5A9180ull +#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR1_9_SPECIAL_BASE 0x1000007FFD5A9E80ull +#define NIC3_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_9_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR1_10_UNSECURE_DOORBELL0_BASE 0x1000007FFD5AA000ull +#define NIC3_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR1_10_UNSECURE_DOORBELL1_BASE 0x1000007FFD5AA080ull +#define NIC3_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD5AA100ull +#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD5AA180ull +#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR1_10_SPECIAL_BASE 0x1000007FFD5AAE80ull +#define NIC3_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_10_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR1_11_UNSECURE_DOORBELL0_BASE 0x1000007FFD5AB000ull +#define NIC3_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR1_11_UNSECURE_DOORBELL1_BASE 0x1000007FFD5AB080ull +#define NIC3_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD5AB100ull +#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD5AB180ull +#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR1_11_SPECIAL_BASE 0x1000007FFD5ABE80ull +#define NIC3_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_11_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR1_12_UNSECURE_DOORBELL0_BASE 0x1000007FFD5AC000ull +#define NIC3_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR1_12_UNSECURE_DOORBELL1_BASE 0x1000007FFD5AC080ull +#define NIC3_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD5AC100ull +#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD5AC180ull +#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR1_12_SPECIAL_BASE 0x1000007FFD5ACE80ull +#define NIC3_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_12_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR1_13_UNSECURE_DOORBELL0_BASE 0x1000007FFD5AD000ull +#define NIC3_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR1_13_UNSECURE_DOORBELL1_BASE 0x1000007FFD5AD080ull +#define NIC3_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD5AD100ull +#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD5AD180ull +#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR1_13_SPECIAL_BASE 0x1000007FFD5ADE80ull +#define NIC3_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_13_SPECIAL_SECTION 0x1800 + +#define mmNIC3_UMR1_14_UNSECURE_DOORBELL0_BASE 0x1000007FFD5AE000ull +#define NIC3_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC3_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC3_UMR1_14_UNSECURE_DOORBELL1_BASE 0x1000007FFD5AE080ull +#define NIC3_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC3_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC3_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD5AE100ull +#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC3_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD5AE180ull +#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC3_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC3_UMR1_14_SPECIAL_BASE 0x1000007FFD5AEE80ull +#define NIC3_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_UMR1_14_SPECIAL_SECTION 0x1180 + +#define mmNIC3_QM_DCCM1_BASE 0x1000007FFD5B0000ull +#define NIC3_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC3_QM_DCCM1_SECTION 0x8000 + +#define mmNIC3_QM_ARC_AUX1_BASE 0x1000007FFD5B8000ull +#define NIC3_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC3_QM_ARC_AUX1_SECTION 0xE800 + +#define mmNIC3_QM_ARC_AUX1_SPECIAL_BASE 0x1000007FFD5B8E80ull +#define NIC3_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 + +#define mmNIC3_QM1_BASE 0x1000007FFD5BA000ull +#define NIC3_QM1_MAX_OFFSET 0x1000 +#define NIC3_QM1_SECTION 0x9000 + +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFD5BA900ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFD5BA908ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFD5BA910ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFD5BA918ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFD5BA920ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFD5BA928ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFD5BA930ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFD5BA938ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFD5BA940ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFD5BA948ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFD5BA950ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFD5BA958ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFD5BA960ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFD5BA968ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFD5BA970ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmNIC3_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFD5BA978ull +#define NIC3_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC3_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmNIC3_QM1_AXUSER_SECURED_BASE 0x1000007FFD5BAB00ull +#define NIC3_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC3_QM1_AXUSER_SECURED_SECTION 0x8000 + +#define mmNIC3_QM1_AXUSER_NONSECURED_BASE 0x1000007FFD5BAB80ull +#define NIC3_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC3_QM1_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmNIC3_QM1_DBG_HBW_BASE 0x1000007FFD5BAC00ull +#define NIC3_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC3_QM1_DBG_HBW_SECTION 0x8000 + +#define mmNIC3_QM1_DBG_LBW_BASE 0x1000007FFD5BAC80ull +#define NIC3_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC3_QM1_DBG_LBW_SECTION 0x1000 + +#define mmNIC3_QM1_CGM_BASE 0x1000007FFD5BAD80ull +#define NIC3_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC3_QM1_CGM_SECTION 0x1000 + +#define mmNIC3_QM1_SPECIAL_BASE 0x1000007FFD5BAE80ull +#define NIC3_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_QM1_SPECIAL_SECTION 0x4180 + +#define mmNIC3_QPC1_BASE 0x1000007FFD5BF000ull +#define NIC3_QPC1_MAX_OFFSET 0x1000 +#define NIC3_QPC1_SECTION 0x7200 + +#define mmNIC3_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x1000007FFD5BF720ull +#define NIC3_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x1000007FFD5BF728ull +#define NIC3_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x1000007FFD5BF730ull +#define NIC3_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x1000007FFD5BF738ull +#define NIC3_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x1000007FFD5BF740ull +#define NIC3_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x1000007FFD5BF748ull +#define NIC3_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x1000007FFD5BF750ull +#define NIC3_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x1000007FFD5BF758ull +#define NIC3_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x1000007FFD5BF760ull +#define NIC3_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x1000007FFD5BF768ull +#define NIC3_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x1000007FFD5BF770ull +#define NIC3_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x1000007FFD5BF778ull +#define NIC3_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x1000007FFD5BF780ull +#define NIC3_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x1000007FFD5BF788ull +#define NIC3_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x1000007FFD5BF790ull +#define NIC3_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x1000007FFD5BF798ull +#define NIC3_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x1000007FFD5BF7A0ull +#define NIC3_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x1000007FFD5BF7A8ull +#define NIC3_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x1000007FFD5BF7B0ull +#define NIC3_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x1000007FFD5BF7B8ull +#define NIC3_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x1000007FFD5BF7C0ull +#define NIC3_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x1000007FFD5BF7C8ull +#define NIC3_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x1000007FFD5BF7D0ull +#define NIC3_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x1000007FFD5BF7D8ull +#define NIC3_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x1000007FFD5BF7E0ull +#define NIC3_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x1000007FFD5BF7E8ull +#define NIC3_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x1000007FFD5BF7F0ull +#define NIC3_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x1000007FFD5BF7F8ull +#define NIC3_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x1000007FFD5BF800ull +#define NIC3_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x1000007FFD5BF808ull +#define NIC3_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x1000007FFD5BF810ull +#define NIC3_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC3_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x1000007FFD5BF818ull +#define NIC3_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC3_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 + +#define mmNIC3_QPC1_AXUSER_CONG_QUE_BASE 0x1000007FFD5BFB80ull +#define NIC3_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC3_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 + +#define mmNIC3_QPC1_AXUSER_RXWQE_BASE 0x1000007FFD5BFBE0ull +#define NIC3_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC3_QPC1_AXUSER_RXWQE_SECTION 0x6000 + +#define mmNIC3_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x1000007FFD5BFC40ull +#define NIC3_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC3_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 + +#define mmNIC3_QPC1_AXUSER_DB_FIFO_BASE 0x1000007FFD5BFCA0ull +#define NIC3_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC3_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 + +#define mmNIC3_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x1000007FFD5BFD00ull +#define NIC3_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC3_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 + +#define mmNIC3_QPC1_AXUSER_ERR_FIFO_BASE 0x1000007FFD5BFD60ull +#define NIC3_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC3_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 + +#define mmNIC3_QPC1_AXUSER_QPC_RESP_BASE 0x1000007FFD5BFDC0ull +#define NIC3_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC3_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 + +#define mmNIC3_QPC1_AXUSER_QPC_REQ_BASE 0x1000007FFD5BFE20ull +#define NIC3_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC3_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 + +#define mmNIC3_QPC1_SPECIAL_BASE 0x1000007FFD5BFE80ull +#define NIC3_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_QPC1_SPECIAL_SECTION 0x8180 + +#define mmNIC3_TMR_BASE 0x1000007FFD5C8000ull +#define NIC3_TMR_MAX_OFFSET 0x1000 +#define NIC3_TMR_SECTION 0xD600 + +#define mmNIC3_TMR_AXUSER_TMR_FREE_LIST_BASE 0x1000007FFD5C8D60ull +#define NIC3_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC3_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 + +#define mmNIC3_TMR_AXUSER_TMR_FIFO_BASE 0x1000007FFD5C8DC0ull +#define NIC3_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC3_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 + +#define mmNIC3_TMR_AXUSER_TMR_FSM_BASE 0x1000007FFD5C8E20ull +#define NIC3_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC3_TMR_AXUSER_TMR_FSM_SECTION 0x6000 + +#define mmNIC3_TMR_SPECIAL_BASE 0x1000007FFD5C8E80ull +#define NIC3_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_TMR_SPECIAL_SECTION 0x1800 + +#define mmNIC3_RXB_CORE_BASE 0x1000007FFD5C9000ull +#define NIC3_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC3_RXB_CORE_SECTION 0x6100 + +#define mmNIC3_RXB_CORE_SCT_AWUSER_BASE 0x1000007FFD5C9610ull +#define NIC3_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC3_RXB_CORE_SCT_AWUSER_SECTION 0x8700 + +#define mmNIC3_RXB_CORE_SPECIAL_BASE 0x1000007FFD5C9E80ull +#define NIC3_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_RXB_CORE_SPECIAL_SECTION 0x1800 + +#define mmNIC3_RXE0_BASE 0x1000007FFD5CA000ull +#define NIC3_RXE0_MAX_OFFSET 0x1000 +#define NIC3_RXE0_SECTION 0x9000 + +#define mmNIC3_RXE0_WQE_ARUSER_BASE 0x1000007FFD5CA900ull +#define NIC3_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC3_RXE0_WQE_ARUSER_SECTION 0x5800 + +#define mmNIC3_RXE0_SPECIAL_BASE 0x1000007FFD5CAE80ull +#define NIC3_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_RXE0_SPECIAL_SECTION 0x1800 + +#define mmNIC3_RXE1_BASE 0x1000007FFD5CB000ull +#define NIC3_RXE1_MAX_OFFSET 0x1000 +#define NIC3_RXE1_SECTION 0x9000 + +#define mmNIC3_RXE1_WQE_ARUSER_BASE 0x1000007FFD5CB900ull +#define NIC3_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC3_RXE1_WQE_ARUSER_SECTION 0x5800 + +#define mmNIC3_RXE1_SPECIAL_BASE 0x1000007FFD5CBE80ull +#define NIC3_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_RXE1_SPECIAL_SECTION 0x1800 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ0_BASE 0x1000007FFD5CC000ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ1_BASE 0x1000007FFD5CC050ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ2_BASE 0x1000007FFD5CC0A0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ3_BASE 0x1000007FFD5CC0F0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ4_BASE 0x1000007FFD5CC140ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ5_BASE 0x1000007FFD5CC190ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ6_BASE 0x1000007FFD5CC1E0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ7_BASE 0x1000007FFD5CC230ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ8_BASE 0x1000007FFD5CC280ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ9_BASE 0x1000007FFD5CC2D0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ10_BASE 0x1000007FFD5CC320ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ11_BASE 0x1000007FFD5CC370ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ12_BASE 0x1000007FFD5CC3C0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ13_BASE 0x1000007FFD5CC410ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ14_BASE 0x1000007FFD5CC460ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ15_BASE 0x1000007FFD5CC4B0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ16_BASE 0x1000007FFD5CC500ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ17_BASE 0x1000007FFD5CC550ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ18_BASE 0x1000007FFD5CC5A0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ19_BASE 0x1000007FFD5CC5F0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ20_BASE 0x1000007FFD5CC640ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ21_BASE 0x1000007FFD5CC690ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ22_BASE 0x1000007FFD5CC6E0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ23_BASE 0x1000007FFD5CC730ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ24_BASE 0x1000007FFD5CC780ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ25_BASE 0x1000007FFD5CC7D0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ26_BASE 0x1000007FFD5CC820ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ27_BASE 0x1000007FFD5CC870ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ28_BASE 0x1000007FFD5CC8C0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ29_BASE 0x1000007FFD5CC910ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ30_BASE 0x1000007FFD5CC960ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 + +#define mmNIC3_RXE0_AXUSER_AXUSER_CQ31_BASE 0x1000007FFD5CC9B0ull +#define NIC3_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC3_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 + +#define mmNIC3_RXE0_AXUSER_SPECIAL_BASE 0x1000007FFD5CCE80ull +#define NIC3_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_RXE0_AXUSER_SPECIAL_SECTION 0x1800 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ0_BASE 0x1000007FFD5CD000ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ1_BASE 0x1000007FFD5CD050ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ2_BASE 0x1000007FFD5CD0A0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ3_BASE 0x1000007FFD5CD0F0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ4_BASE 0x1000007FFD5CD140ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ5_BASE 0x1000007FFD5CD190ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ6_BASE 0x1000007FFD5CD1E0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ7_BASE 0x1000007FFD5CD230ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ8_BASE 0x1000007FFD5CD280ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ9_BASE 0x1000007FFD5CD2D0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ10_BASE 0x1000007FFD5CD320ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ11_BASE 0x1000007FFD5CD370ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ12_BASE 0x1000007FFD5CD3C0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ13_BASE 0x1000007FFD5CD410ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ14_BASE 0x1000007FFD5CD460ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ15_BASE 0x1000007FFD5CD4B0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ16_BASE 0x1000007FFD5CD500ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ17_BASE 0x1000007FFD5CD550ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ18_BASE 0x1000007FFD5CD5A0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ19_BASE 0x1000007FFD5CD5F0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ20_BASE 0x1000007FFD5CD640ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ21_BASE 0x1000007FFD5CD690ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ22_BASE 0x1000007FFD5CD6E0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ23_BASE 0x1000007FFD5CD730ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ24_BASE 0x1000007FFD5CD780ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ25_BASE 0x1000007FFD5CD7D0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ26_BASE 0x1000007FFD5CD820ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ27_BASE 0x1000007FFD5CD870ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ28_BASE 0x1000007FFD5CD8C0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ29_BASE 0x1000007FFD5CD910ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ30_BASE 0x1000007FFD5CD960ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 + +#define mmNIC3_RXE1_AXUSER_AXUSER_CQ31_BASE 0x1000007FFD5CD9B0ull +#define NIC3_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC3_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 + +#define mmNIC3_RXE1_AXUSER_SPECIAL_BASE 0x1000007FFD5CDE80ull +#define NIC3_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_RXE1_AXUSER_SPECIAL_SECTION 0x2180 + +#define mmNIC3_TXS0_BASE 0x1000007FFD5D0000ull +#define NIC3_TXS0_MAX_OFFSET 0x1000 +#define NIC3_TXS0_SECTION 0xE800 + +#define mmNIC3_TXS0_SPECIAL_BASE 0x1000007FFD5D0E80ull +#define NIC3_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_TXS0_SPECIAL_SECTION 0x1800 + +#define mmNIC3_TXS1_BASE 0x1000007FFD5D1000ull +#define NIC3_TXS1_MAX_OFFSET 0x1000 +#define NIC3_TXS1_SECTION 0xE800 + +#define mmNIC3_TXS1_SPECIAL_BASE 0x1000007FFD5D1E80ull +#define NIC3_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_TXS1_SPECIAL_SECTION 0x1800 + +#define mmNIC3_TXE0_BASE 0x1000007FFD5D2000ull +#define NIC3_TXE0_MAX_OFFSET 0x1000 +#define NIC3_TXE0_SECTION 0xE800 + +#define mmNIC3_TXE0_SPECIAL_BASE 0x1000007FFD5D2E80ull +#define NIC3_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_TXE0_SPECIAL_SECTION 0x1800 + +#define mmNIC3_TXE1_BASE 0x1000007FFD5D3000ull +#define NIC3_TXE1_MAX_OFFSET 0x1000 +#define NIC3_TXE1_SECTION 0xE800 + +#define mmNIC3_TXE1_SPECIAL_BASE 0x1000007FFD5D3E80ull +#define NIC3_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_TXE1_SPECIAL_SECTION 0x1800 + +#define mmNIC3_TXB_BASE 0x1000007FFD5D4000ull +#define NIC3_TXB_MAX_OFFSET 0x1000 +#define NIC3_TXB_SECTION 0xE800 + +#define mmNIC3_TXB_SPECIAL_BASE 0x1000007FFD5D4E80ull +#define NIC3_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_TXB_SPECIAL_SECTION 0x1800 + +#define mmNIC3_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFD5D5000ull +#define NIC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmNIC3_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFD5D5200ull +#define NIC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmNIC3_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFD5D5400ull +#define NIC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmNIC3_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFD5D5600ull +#define NIC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmNIC3_MSTR_IF_E2E_CRDT_BASE 0x1000007FFD5D5800ull +#define NIC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC3_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmNIC3_MSTR_IF_AXUSER_BASE 0x1000007FFD5D5A80ull +#define NIC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC3_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmNIC3_MSTR_IF_DBG_HBW_BASE 0x1000007FFD5D5B00ull +#define NIC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC3_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmNIC3_MSTR_IF_DBG_LBW_BASE 0x1000007FFD5D5B80ull +#define NIC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC3_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmNIC3_MSTR_IF_CORE_HBW_BASE 0x1000007FFD5D5C00ull +#define NIC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC3_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmNIC3_MSTR_IF_CORE_LBW_BASE 0x1000007FFD5D5D80ull +#define NIC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC3_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmNIC3_MSTR_IF_SPECIAL_BASE 0x1000007FFD5D5E80ull +#define NIC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmNIC3_TX_AXUSER_BASE 0x1000007FFD5D6000ull +#define NIC3_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC3_TX_AXUSER_SECTION 0x2000 + +#define mmNIC3_SERDES0_BASE 0x1000007FFD5D8000ull +#define NIC3_SERDES0_MAX_OFFSET 0x3E40 +#define NIC3_SERDES0_SECTION 0x4000 + +#define mmNIC3_SERDES1_BASE 0x1000007FFD5DC000ull +#define NIC3_SERDES1_MAX_OFFSET 0x3E40 +#define NIC3_SERDES1_SECTION 0x4000 + +#define mmNIC3_PHY_BASE 0x1000007FFD5E0000ull +#define NIC3_PHY_MAX_OFFSET 0x1000 +#define NIC3_PHY_SECTION 0xE800 + +#define mmNIC3_PHY_SPECIAL_BASE 0x1000007FFD5E0E80ull +#define NIC3_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC3_PHY_SPECIAL_SECTION 0x7180 + +#define mmPRT3_MAC_AUX_BASE 0x1000007FFD5E8000ull +#define PRT3_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT3_MAC_AUX_SECTION 0xE800 + +#define mmPRT3_MAC_AUX_SPECIAL_BASE 0x1000007FFD5E8E80ull +#define PRT3_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT3_MAC_AUX_SPECIAL_SECTION 0x1800 + +#define mmPRT3_MAC_CORE_BASE 0x1000007FFD5E9000ull +#define PRT3_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT3_MAC_CORE_SECTION 0xE800 + +#define mmPRT3_MAC_CORE_SPECIAL_BASE 0x1000007FFD5E9E80ull +#define PRT3_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT3_MAC_CORE_SPECIAL_SECTION 0x1800 + +#define mmNIC3_MAC_RS_FEC_BASE 0x1000007FFD5EA000ull +#define NIC3_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC3_MAC_RS_FEC_SECTION 0x1000 + +#define mmNIC3_MAC_GLOB_STAT_NIC_MAC_STAT_BASE 0x1000007FFD5EB000ull +#define NIC3_MAC_GLOB_STAT_NIC_MAC_STAT_MAX_OFFSET 0x4D00 +#define NIC3_MAC_GLOB_STAT_NIC_MAC_STAT_SECTION 0x8000 + +#define mmNIC3_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_BASE 0x1000007FFD5EB800ull +#define NIC3_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC3_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_SECTION 0x8000 + +#define mmNIC3_MAC_CH0_MAC_PCS_BASE 0x1000007FFD5EC000ull +#define NIC3_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC3_MAC_CH0_MAC_PCS_SECTION 0x4000 + +#define mmNIC3_MAC_CH0_MAC_128_BASE 0x1000007FFD5EC400ull +#define NIC3_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC3_MAC_CH0_MAC_128_SECTION 0x4000 + +#define mmNIC3_MAC_CH0_MAC_AN_BASE 0x1000007FFD5EC800ull +#define NIC3_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC3_MAC_CH0_MAC_AN_SECTION 0x8000 + +#define mmNIC3_MAC_CH1_MAC_PCS_BASE 0x1000007FFD5ED000ull +#define NIC3_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC3_MAC_CH1_MAC_PCS_SECTION 0x4000 + +#define mmNIC3_MAC_CH1_MAC_128_BASE 0x1000007FFD5ED400ull +#define NIC3_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC3_MAC_CH1_MAC_128_SECTION 0x4000 + +#define mmNIC3_MAC_CH1_MAC_AN_BASE 0x1000007FFD5ED800ull +#define NIC3_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC3_MAC_CH1_MAC_AN_SECTION 0x8000 + +#define mmNIC3_MAC_CH2_MAC_PCS_BASE 0x1000007FFD5EE000ull +#define NIC3_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC3_MAC_CH2_MAC_PCS_SECTION 0x4000 + +#define mmNIC3_MAC_CH2_MAC_128_BASE 0x1000007FFD5EE400ull +#define NIC3_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC3_MAC_CH2_MAC_128_SECTION 0x4000 + +#define mmNIC3_MAC_CH2_MAC_AN_BASE 0x1000007FFD5EE800ull +#define NIC3_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC3_MAC_CH2_MAC_AN_SECTION 0x8000 + +#define mmNIC3_MAC_CH3_MAC_PCS_BASE 0x1000007FFD5EF000ull +#define NIC3_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC3_MAC_CH3_MAC_PCS_SECTION 0x4000 + +#define mmNIC3_MAC_CH3_MAC_128_BASE 0x1000007FFD5EF400ull +#define NIC3_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC3_MAC_CH3_MAC_128_SECTION 0x4000 + +#define mmNIC3_MAC_CH3_MAC_AN_BASE 0x1000007FFD5EF800ull +#define NIC3_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC3_MAC_CH3_MAC_AN_SECTION 0x10800 + +#define mmNIC4_UMR0_0_UNSECURE_DOORBELL0_BASE 0x1000007FFD600000ull +#define NIC4_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR0_0_UNSECURE_DOORBELL1_BASE 0x1000007FFD600080ull +#define NIC4_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD600100ull +#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD600180ull +#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR0_0_SPECIAL_BASE 0x1000007FFD600E80ull +#define NIC4_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_0_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR0_1_UNSECURE_DOORBELL0_BASE 0x1000007FFD601000ull +#define NIC4_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR0_1_UNSECURE_DOORBELL1_BASE 0x1000007FFD601080ull +#define NIC4_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD601100ull +#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD601180ull +#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR0_1_SPECIAL_BASE 0x1000007FFD601E80ull +#define NIC4_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_1_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR0_2_UNSECURE_DOORBELL0_BASE 0x1000007FFD602000ull +#define NIC4_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR0_2_UNSECURE_DOORBELL1_BASE 0x1000007FFD602080ull +#define NIC4_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD602100ull +#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD602180ull +#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR0_2_SPECIAL_BASE 0x1000007FFD602E80ull +#define NIC4_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_2_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR0_3_UNSECURE_DOORBELL0_BASE 0x1000007FFD603000ull +#define NIC4_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR0_3_UNSECURE_DOORBELL1_BASE 0x1000007FFD603080ull +#define NIC4_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD603100ull +#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD603180ull +#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR0_3_SPECIAL_BASE 0x1000007FFD603E80ull +#define NIC4_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_3_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR0_4_UNSECURE_DOORBELL0_BASE 0x1000007FFD604000ull +#define NIC4_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR0_4_UNSECURE_DOORBELL1_BASE 0x1000007FFD604080ull +#define NIC4_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD604100ull +#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD604180ull +#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR0_4_SPECIAL_BASE 0x1000007FFD604E80ull +#define NIC4_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_4_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR0_5_UNSECURE_DOORBELL0_BASE 0x1000007FFD605000ull +#define NIC4_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR0_5_UNSECURE_DOORBELL1_BASE 0x1000007FFD605080ull +#define NIC4_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD605100ull +#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD605180ull +#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR0_5_SPECIAL_BASE 0x1000007FFD605E80ull +#define NIC4_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_5_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR0_6_UNSECURE_DOORBELL0_BASE 0x1000007FFD606000ull +#define NIC4_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR0_6_UNSECURE_DOORBELL1_BASE 0x1000007FFD606080ull +#define NIC4_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD606100ull +#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD606180ull +#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR0_6_SPECIAL_BASE 0x1000007FFD606E80ull +#define NIC4_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_6_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR0_7_UNSECURE_DOORBELL0_BASE 0x1000007FFD607000ull +#define NIC4_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR0_7_UNSECURE_DOORBELL1_BASE 0x1000007FFD607080ull +#define NIC4_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD607100ull +#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD607180ull +#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR0_7_SPECIAL_BASE 0x1000007FFD607E80ull +#define NIC4_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_7_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR0_8_UNSECURE_DOORBELL0_BASE 0x1000007FFD608000ull +#define NIC4_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR0_8_UNSECURE_DOORBELL1_BASE 0x1000007FFD608080ull +#define NIC4_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD608100ull +#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD608180ull +#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR0_8_SPECIAL_BASE 0x1000007FFD608E80ull +#define NIC4_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_8_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR0_9_UNSECURE_DOORBELL0_BASE 0x1000007FFD609000ull +#define NIC4_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR0_9_UNSECURE_DOORBELL1_BASE 0x1000007FFD609080ull +#define NIC4_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD609100ull +#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD609180ull +#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR0_9_SPECIAL_BASE 0x1000007FFD609E80ull +#define NIC4_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_9_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR0_10_UNSECURE_DOORBELL0_BASE 0x1000007FFD60A000ull +#define NIC4_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR0_10_UNSECURE_DOORBELL1_BASE 0x1000007FFD60A080ull +#define NIC4_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD60A100ull +#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD60A180ull +#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR0_10_SPECIAL_BASE 0x1000007FFD60AE80ull +#define NIC4_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_10_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR0_11_UNSECURE_DOORBELL0_BASE 0x1000007FFD60B000ull +#define NIC4_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR0_11_UNSECURE_DOORBELL1_BASE 0x1000007FFD60B080ull +#define NIC4_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD60B100ull +#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD60B180ull +#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR0_11_SPECIAL_BASE 0x1000007FFD60BE80ull +#define NIC4_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_11_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR0_12_UNSECURE_DOORBELL0_BASE 0x1000007FFD60C000ull +#define NIC4_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR0_12_UNSECURE_DOORBELL1_BASE 0x1000007FFD60C080ull +#define NIC4_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD60C100ull +#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD60C180ull +#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR0_12_SPECIAL_BASE 0x1000007FFD60CE80ull +#define NIC4_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_12_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR0_13_UNSECURE_DOORBELL0_BASE 0x1000007FFD60D000ull +#define NIC4_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR0_13_UNSECURE_DOORBELL1_BASE 0x1000007FFD60D080ull +#define NIC4_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD60D100ull +#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD60D180ull +#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR0_13_SPECIAL_BASE 0x1000007FFD60DE80ull +#define NIC4_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_13_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR0_14_UNSECURE_DOORBELL0_BASE 0x1000007FFD60E000ull +#define NIC4_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR0_14_UNSECURE_DOORBELL1_BASE 0x1000007FFD60E080ull +#define NIC4_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD60E100ull +#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD60E180ull +#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR0_14_SPECIAL_BASE 0x1000007FFD60EE80ull +#define NIC4_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR0_14_SPECIAL_SECTION 0x1180 + +#define mmNIC4_QM_DCCM0_BASE 0x1000007FFD610000ull +#define NIC4_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC4_QM_DCCM0_SECTION 0x8000 + +#define mmNIC4_QM_ARC_AUX0_BASE 0x1000007FFD618000ull +#define NIC4_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC4_QM_ARC_AUX0_SECTION 0xE800 + +#define mmNIC4_QM_ARC_AUX0_SPECIAL_BASE 0x1000007FFD618E80ull +#define NIC4_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 + +#define mmNIC4_QM0_BASE 0x1000007FFD61A000ull +#define NIC4_QM0_MAX_OFFSET 0x1000 +#define NIC4_QM0_SECTION 0x9000 + +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFD61A900ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFD61A908ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFD61A910ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFD61A918ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFD61A920ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFD61A928ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFD61A930ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFD61A938ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFD61A940ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFD61A948ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFD61A950ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFD61A958ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFD61A960ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFD61A968ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFD61A970ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmNIC4_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFD61A978ull +#define NIC4_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC4_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmNIC4_QM0_AXUSER_SECURED_BASE 0x1000007FFD61AB00ull +#define NIC4_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC4_QM0_AXUSER_SECURED_SECTION 0x8000 + +#define mmNIC4_QM0_AXUSER_NONSECURED_BASE 0x1000007FFD61AB80ull +#define NIC4_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC4_QM0_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmNIC4_QM0_DBG_HBW_BASE 0x1000007FFD61AC00ull +#define NIC4_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC4_QM0_DBG_HBW_SECTION 0x8000 + +#define mmNIC4_QM0_DBG_LBW_BASE 0x1000007FFD61AC80ull +#define NIC4_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC4_QM0_DBG_LBW_SECTION 0x1000 + +#define mmNIC4_QM0_CGM_BASE 0x1000007FFD61AD80ull +#define NIC4_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC4_QM0_CGM_SECTION 0x1000 + +#define mmNIC4_QM0_SPECIAL_BASE 0x1000007FFD61AE80ull +#define NIC4_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_QM0_SPECIAL_SECTION 0x4180 + +#define mmNIC4_QPC0_BASE 0x1000007FFD61F000ull +#define NIC4_QPC0_MAX_OFFSET 0x1000 +#define NIC4_QPC0_SECTION 0x7200 + +#define mmNIC4_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x1000007FFD61F720ull +#define NIC4_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x1000007FFD61F728ull +#define NIC4_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x1000007FFD61F730ull +#define NIC4_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x1000007FFD61F738ull +#define NIC4_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x1000007FFD61F740ull +#define NIC4_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x1000007FFD61F748ull +#define NIC4_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x1000007FFD61F750ull +#define NIC4_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x1000007FFD61F758ull +#define NIC4_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x1000007FFD61F760ull +#define NIC4_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x1000007FFD61F768ull +#define NIC4_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x1000007FFD61F770ull +#define NIC4_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x1000007FFD61F778ull +#define NIC4_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x1000007FFD61F780ull +#define NIC4_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x1000007FFD61F788ull +#define NIC4_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x1000007FFD61F790ull +#define NIC4_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x1000007FFD61F798ull +#define NIC4_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x1000007FFD61F7A0ull +#define NIC4_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x1000007FFD61F7A8ull +#define NIC4_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x1000007FFD61F7B0ull +#define NIC4_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x1000007FFD61F7B8ull +#define NIC4_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x1000007FFD61F7C0ull +#define NIC4_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x1000007FFD61F7C8ull +#define NIC4_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x1000007FFD61F7D0ull +#define NIC4_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x1000007FFD61F7D8ull +#define NIC4_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x1000007FFD61F7E0ull +#define NIC4_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x1000007FFD61F7E8ull +#define NIC4_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x1000007FFD61F7F0ull +#define NIC4_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x1000007FFD61F7F8ull +#define NIC4_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x1000007FFD61F800ull +#define NIC4_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x1000007FFD61F808ull +#define NIC4_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x1000007FFD61F810ull +#define NIC4_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x1000007FFD61F818ull +#define NIC4_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 + +#define mmNIC4_QPC0_AXUSER_CONG_QUE_BASE 0x1000007FFD61FB80ull +#define NIC4_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC4_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 + +#define mmNIC4_QPC0_AXUSER_RXWQE_BASE 0x1000007FFD61FBE0ull +#define NIC4_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC4_QPC0_AXUSER_RXWQE_SECTION 0x6000 + +#define mmNIC4_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x1000007FFD61FC40ull +#define NIC4_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC4_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 + +#define mmNIC4_QPC0_AXUSER_DB_FIFO_BASE 0x1000007FFD61FCA0ull +#define NIC4_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC4_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 + +#define mmNIC4_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x1000007FFD61FD00ull +#define NIC4_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC4_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 + +#define mmNIC4_QPC0_AXUSER_ERR_FIFO_BASE 0x1000007FFD61FD60ull +#define NIC4_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC4_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 + +#define mmNIC4_QPC0_AXUSER_QPC_RESP_BASE 0x1000007FFD61FDC0ull +#define NIC4_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC4_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 + +#define mmNIC4_QPC0_AXUSER_QPC_REQ_BASE 0x1000007FFD61FE20ull +#define NIC4_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC4_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 + +#define mmNIC4_QPC0_SPECIAL_BASE 0x1000007FFD61FE80ull +#define NIC4_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_QPC0_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR1_0_UNSECURE_DOORBELL0_BASE 0x1000007FFD620000ull +#define NIC4_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR1_0_UNSECURE_DOORBELL1_BASE 0x1000007FFD620080ull +#define NIC4_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD620100ull +#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD620180ull +#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR1_0_SPECIAL_BASE 0x1000007FFD620E80ull +#define NIC4_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_0_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR1_1_UNSECURE_DOORBELL0_BASE 0x1000007FFD621000ull +#define NIC4_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR1_1_UNSECURE_DOORBELL1_BASE 0x1000007FFD621080ull +#define NIC4_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD621100ull +#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD621180ull +#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR1_1_SPECIAL_BASE 0x1000007FFD621E80ull +#define NIC4_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_1_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR1_2_UNSECURE_DOORBELL0_BASE 0x1000007FFD622000ull +#define NIC4_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR1_2_UNSECURE_DOORBELL1_BASE 0x1000007FFD622080ull +#define NIC4_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD622100ull +#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD622180ull +#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR1_2_SPECIAL_BASE 0x1000007FFD622E80ull +#define NIC4_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_2_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR1_3_UNSECURE_DOORBELL0_BASE 0x1000007FFD623000ull +#define NIC4_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR1_3_UNSECURE_DOORBELL1_BASE 0x1000007FFD623080ull +#define NIC4_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD623100ull +#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD623180ull +#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR1_3_SPECIAL_BASE 0x1000007FFD623E80ull +#define NIC4_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_3_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR1_4_UNSECURE_DOORBELL0_BASE 0x1000007FFD624000ull +#define NIC4_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR1_4_UNSECURE_DOORBELL1_BASE 0x1000007FFD624080ull +#define NIC4_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD624100ull +#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD624180ull +#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR1_4_SPECIAL_BASE 0x1000007FFD624E80ull +#define NIC4_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_4_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR1_5_UNSECURE_DOORBELL0_BASE 0x1000007FFD625000ull +#define NIC4_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR1_5_UNSECURE_DOORBELL1_BASE 0x1000007FFD625080ull +#define NIC4_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD625100ull +#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD625180ull +#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR1_5_SPECIAL_BASE 0x1000007FFD625E80ull +#define NIC4_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_5_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR1_6_UNSECURE_DOORBELL0_BASE 0x1000007FFD626000ull +#define NIC4_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR1_6_UNSECURE_DOORBELL1_BASE 0x1000007FFD626080ull +#define NIC4_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD626100ull +#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD626180ull +#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR1_6_SPECIAL_BASE 0x1000007FFD626E80ull +#define NIC4_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_6_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR1_7_UNSECURE_DOORBELL0_BASE 0x1000007FFD627000ull +#define NIC4_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR1_7_UNSECURE_DOORBELL1_BASE 0x1000007FFD627080ull +#define NIC4_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD627100ull +#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD627180ull +#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR1_7_SPECIAL_BASE 0x1000007FFD627E80ull +#define NIC4_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_7_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR1_8_UNSECURE_DOORBELL0_BASE 0x1000007FFD628000ull +#define NIC4_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR1_8_UNSECURE_DOORBELL1_BASE 0x1000007FFD628080ull +#define NIC4_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD628100ull +#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD628180ull +#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR1_8_SPECIAL_BASE 0x1000007FFD628E80ull +#define NIC4_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_8_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR1_9_UNSECURE_DOORBELL0_BASE 0x1000007FFD629000ull +#define NIC4_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR1_9_UNSECURE_DOORBELL1_BASE 0x1000007FFD629080ull +#define NIC4_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD629100ull +#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD629180ull +#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR1_9_SPECIAL_BASE 0x1000007FFD629E80ull +#define NIC4_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_9_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR1_10_UNSECURE_DOORBELL0_BASE 0x1000007FFD62A000ull +#define NIC4_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR1_10_UNSECURE_DOORBELL1_BASE 0x1000007FFD62A080ull +#define NIC4_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD62A100ull +#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD62A180ull +#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR1_10_SPECIAL_BASE 0x1000007FFD62AE80ull +#define NIC4_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_10_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR1_11_UNSECURE_DOORBELL0_BASE 0x1000007FFD62B000ull +#define NIC4_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR1_11_UNSECURE_DOORBELL1_BASE 0x1000007FFD62B080ull +#define NIC4_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD62B100ull +#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD62B180ull +#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR1_11_SPECIAL_BASE 0x1000007FFD62BE80ull +#define NIC4_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_11_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR1_12_UNSECURE_DOORBELL0_BASE 0x1000007FFD62C000ull +#define NIC4_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR1_12_UNSECURE_DOORBELL1_BASE 0x1000007FFD62C080ull +#define NIC4_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD62C100ull +#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD62C180ull +#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR1_12_SPECIAL_BASE 0x1000007FFD62CE80ull +#define NIC4_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_12_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR1_13_UNSECURE_DOORBELL0_BASE 0x1000007FFD62D000ull +#define NIC4_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR1_13_UNSECURE_DOORBELL1_BASE 0x1000007FFD62D080ull +#define NIC4_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD62D100ull +#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD62D180ull +#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR1_13_SPECIAL_BASE 0x1000007FFD62DE80ull +#define NIC4_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_13_SPECIAL_SECTION 0x1800 + +#define mmNIC4_UMR1_14_UNSECURE_DOORBELL0_BASE 0x1000007FFD62E000ull +#define NIC4_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC4_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC4_UMR1_14_UNSECURE_DOORBELL1_BASE 0x1000007FFD62E080ull +#define NIC4_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC4_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC4_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD62E100ull +#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC4_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD62E180ull +#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC4_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC4_UMR1_14_SPECIAL_BASE 0x1000007FFD62EE80ull +#define NIC4_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_UMR1_14_SPECIAL_SECTION 0x1180 + +#define mmNIC4_QM_DCCM1_BASE 0x1000007FFD630000ull +#define NIC4_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC4_QM_DCCM1_SECTION 0x8000 + +#define mmNIC4_QM_ARC_AUX1_BASE 0x1000007FFD638000ull +#define NIC4_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC4_QM_ARC_AUX1_SECTION 0xE800 + +#define mmNIC4_QM_ARC_AUX1_SPECIAL_BASE 0x1000007FFD638E80ull +#define NIC4_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 + +#define mmNIC4_QM1_BASE 0x1000007FFD63A000ull +#define NIC4_QM1_MAX_OFFSET 0x1000 +#define NIC4_QM1_SECTION 0x9000 + +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFD63A900ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFD63A908ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFD63A910ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFD63A918ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFD63A920ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFD63A928ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFD63A930ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFD63A938ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFD63A940ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFD63A948ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFD63A950ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFD63A958ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFD63A960ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFD63A968ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFD63A970ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmNIC4_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFD63A978ull +#define NIC4_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC4_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmNIC4_QM1_AXUSER_SECURED_BASE 0x1000007FFD63AB00ull +#define NIC4_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC4_QM1_AXUSER_SECURED_SECTION 0x8000 + +#define mmNIC4_QM1_AXUSER_NONSECURED_BASE 0x1000007FFD63AB80ull +#define NIC4_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC4_QM1_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmNIC4_QM1_DBG_HBW_BASE 0x1000007FFD63AC00ull +#define NIC4_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC4_QM1_DBG_HBW_SECTION 0x8000 + +#define mmNIC4_QM1_DBG_LBW_BASE 0x1000007FFD63AC80ull +#define NIC4_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC4_QM1_DBG_LBW_SECTION 0x1000 + +#define mmNIC4_QM1_CGM_BASE 0x1000007FFD63AD80ull +#define NIC4_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC4_QM1_CGM_SECTION 0x1000 + +#define mmNIC4_QM1_SPECIAL_BASE 0x1000007FFD63AE80ull +#define NIC4_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_QM1_SPECIAL_SECTION 0x4180 + +#define mmNIC4_QPC1_BASE 0x1000007FFD63F000ull +#define NIC4_QPC1_MAX_OFFSET 0x1000 +#define NIC4_QPC1_SECTION 0x7200 + +#define mmNIC4_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x1000007FFD63F720ull +#define NIC4_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x1000007FFD63F728ull +#define NIC4_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x1000007FFD63F730ull +#define NIC4_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x1000007FFD63F738ull +#define NIC4_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x1000007FFD63F740ull +#define NIC4_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x1000007FFD63F748ull +#define NIC4_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x1000007FFD63F750ull +#define NIC4_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x1000007FFD63F758ull +#define NIC4_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x1000007FFD63F760ull +#define NIC4_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x1000007FFD63F768ull +#define NIC4_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x1000007FFD63F770ull +#define NIC4_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x1000007FFD63F778ull +#define NIC4_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x1000007FFD63F780ull +#define NIC4_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x1000007FFD63F788ull +#define NIC4_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x1000007FFD63F790ull +#define NIC4_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x1000007FFD63F798ull +#define NIC4_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x1000007FFD63F7A0ull +#define NIC4_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x1000007FFD63F7A8ull +#define NIC4_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x1000007FFD63F7B0ull +#define NIC4_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x1000007FFD63F7B8ull +#define NIC4_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x1000007FFD63F7C0ull +#define NIC4_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x1000007FFD63F7C8ull +#define NIC4_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x1000007FFD63F7D0ull +#define NIC4_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x1000007FFD63F7D8ull +#define NIC4_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x1000007FFD63F7E0ull +#define NIC4_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x1000007FFD63F7E8ull +#define NIC4_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x1000007FFD63F7F0ull +#define NIC4_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x1000007FFD63F7F8ull +#define NIC4_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x1000007FFD63F800ull +#define NIC4_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x1000007FFD63F808ull +#define NIC4_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x1000007FFD63F810ull +#define NIC4_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC4_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x1000007FFD63F818ull +#define NIC4_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC4_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 + +#define mmNIC4_QPC1_AXUSER_CONG_QUE_BASE 0x1000007FFD63FB80ull +#define NIC4_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC4_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 + +#define mmNIC4_QPC1_AXUSER_RXWQE_BASE 0x1000007FFD63FBE0ull +#define NIC4_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC4_QPC1_AXUSER_RXWQE_SECTION 0x6000 + +#define mmNIC4_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x1000007FFD63FC40ull +#define NIC4_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC4_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 + +#define mmNIC4_QPC1_AXUSER_DB_FIFO_BASE 0x1000007FFD63FCA0ull +#define NIC4_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC4_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 + +#define mmNIC4_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x1000007FFD63FD00ull +#define NIC4_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC4_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 + +#define mmNIC4_QPC1_AXUSER_ERR_FIFO_BASE 0x1000007FFD63FD60ull +#define NIC4_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC4_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 + +#define mmNIC4_QPC1_AXUSER_QPC_RESP_BASE 0x1000007FFD63FDC0ull +#define NIC4_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC4_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 + +#define mmNIC4_QPC1_AXUSER_QPC_REQ_BASE 0x1000007FFD63FE20ull +#define NIC4_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC4_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 + +#define mmNIC4_QPC1_SPECIAL_BASE 0x1000007FFD63FE80ull +#define NIC4_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_QPC1_SPECIAL_SECTION 0x8180 + +#define mmNIC4_TMR_BASE 0x1000007FFD648000ull +#define NIC4_TMR_MAX_OFFSET 0x1000 +#define NIC4_TMR_SECTION 0xD600 + +#define mmNIC4_TMR_AXUSER_TMR_FREE_LIST_BASE 0x1000007FFD648D60ull +#define NIC4_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC4_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 + +#define mmNIC4_TMR_AXUSER_TMR_FIFO_BASE 0x1000007FFD648DC0ull +#define NIC4_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC4_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 + +#define mmNIC4_TMR_AXUSER_TMR_FSM_BASE 0x1000007FFD648E20ull +#define NIC4_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC4_TMR_AXUSER_TMR_FSM_SECTION 0x6000 + +#define mmNIC4_TMR_SPECIAL_BASE 0x1000007FFD648E80ull +#define NIC4_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_TMR_SPECIAL_SECTION 0x1800 + +#define mmNIC4_RXB_CORE_BASE 0x1000007FFD649000ull +#define NIC4_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC4_RXB_CORE_SECTION 0x6100 + +#define mmNIC4_RXB_CORE_SCT_AWUSER_BASE 0x1000007FFD649610ull +#define NIC4_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC4_RXB_CORE_SCT_AWUSER_SECTION 0x8700 + +#define mmNIC4_RXB_CORE_SPECIAL_BASE 0x1000007FFD649E80ull +#define NIC4_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_RXB_CORE_SPECIAL_SECTION 0x1800 + +#define mmNIC4_RXE0_BASE 0x1000007FFD64A000ull +#define NIC4_RXE0_MAX_OFFSET 0x1000 +#define NIC4_RXE0_SECTION 0x9000 + +#define mmNIC4_RXE0_WQE_ARUSER_BASE 0x1000007FFD64A900ull +#define NIC4_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC4_RXE0_WQE_ARUSER_SECTION 0x5800 + +#define mmNIC4_RXE0_SPECIAL_BASE 0x1000007FFD64AE80ull +#define NIC4_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_RXE0_SPECIAL_SECTION 0x1800 + +#define mmNIC4_RXE1_BASE 0x1000007FFD64B000ull +#define NIC4_RXE1_MAX_OFFSET 0x1000 +#define NIC4_RXE1_SECTION 0x9000 + +#define mmNIC4_RXE1_WQE_ARUSER_BASE 0x1000007FFD64B900ull +#define NIC4_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC4_RXE1_WQE_ARUSER_SECTION 0x5800 + +#define mmNIC4_RXE1_SPECIAL_BASE 0x1000007FFD64BE80ull +#define NIC4_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_RXE1_SPECIAL_SECTION 0x1800 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ0_BASE 0x1000007FFD64C000ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ1_BASE 0x1000007FFD64C050ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ2_BASE 0x1000007FFD64C0A0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ3_BASE 0x1000007FFD64C0F0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ4_BASE 0x1000007FFD64C140ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ5_BASE 0x1000007FFD64C190ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ6_BASE 0x1000007FFD64C1E0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ7_BASE 0x1000007FFD64C230ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ8_BASE 0x1000007FFD64C280ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ9_BASE 0x1000007FFD64C2D0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ10_BASE 0x1000007FFD64C320ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ11_BASE 0x1000007FFD64C370ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ12_BASE 0x1000007FFD64C3C0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ13_BASE 0x1000007FFD64C410ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ14_BASE 0x1000007FFD64C460ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ15_BASE 0x1000007FFD64C4B0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ16_BASE 0x1000007FFD64C500ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ17_BASE 0x1000007FFD64C550ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ18_BASE 0x1000007FFD64C5A0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ19_BASE 0x1000007FFD64C5F0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ20_BASE 0x1000007FFD64C640ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ21_BASE 0x1000007FFD64C690ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ22_BASE 0x1000007FFD64C6E0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ23_BASE 0x1000007FFD64C730ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ24_BASE 0x1000007FFD64C780ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ25_BASE 0x1000007FFD64C7D0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ26_BASE 0x1000007FFD64C820ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ27_BASE 0x1000007FFD64C870ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ28_BASE 0x1000007FFD64C8C0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ29_BASE 0x1000007FFD64C910ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ30_BASE 0x1000007FFD64C960ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 + +#define mmNIC4_RXE0_AXUSER_AXUSER_CQ31_BASE 0x1000007FFD64C9B0ull +#define NIC4_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC4_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 + +#define mmNIC4_RXE0_AXUSER_SPECIAL_BASE 0x1000007FFD64CE80ull +#define NIC4_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_RXE0_AXUSER_SPECIAL_SECTION 0x1800 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ0_BASE 0x1000007FFD64D000ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ1_BASE 0x1000007FFD64D050ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ2_BASE 0x1000007FFD64D0A0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ3_BASE 0x1000007FFD64D0F0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ4_BASE 0x1000007FFD64D140ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ5_BASE 0x1000007FFD64D190ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ6_BASE 0x1000007FFD64D1E0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ7_BASE 0x1000007FFD64D230ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ8_BASE 0x1000007FFD64D280ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ9_BASE 0x1000007FFD64D2D0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ10_BASE 0x1000007FFD64D320ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ11_BASE 0x1000007FFD64D370ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ12_BASE 0x1000007FFD64D3C0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ13_BASE 0x1000007FFD64D410ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ14_BASE 0x1000007FFD64D460ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ15_BASE 0x1000007FFD64D4B0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ16_BASE 0x1000007FFD64D500ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ17_BASE 0x1000007FFD64D550ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ18_BASE 0x1000007FFD64D5A0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ19_BASE 0x1000007FFD64D5F0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ20_BASE 0x1000007FFD64D640ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ21_BASE 0x1000007FFD64D690ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ22_BASE 0x1000007FFD64D6E0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ23_BASE 0x1000007FFD64D730ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ24_BASE 0x1000007FFD64D780ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ25_BASE 0x1000007FFD64D7D0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ26_BASE 0x1000007FFD64D820ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ27_BASE 0x1000007FFD64D870ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ28_BASE 0x1000007FFD64D8C0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ29_BASE 0x1000007FFD64D910ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ30_BASE 0x1000007FFD64D960ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 + +#define mmNIC4_RXE1_AXUSER_AXUSER_CQ31_BASE 0x1000007FFD64D9B0ull +#define NIC4_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC4_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 + +#define mmNIC4_RXE1_AXUSER_SPECIAL_BASE 0x1000007FFD64DE80ull +#define NIC4_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_RXE1_AXUSER_SPECIAL_SECTION 0x2180 + +#define mmNIC4_TXS0_BASE 0x1000007FFD650000ull +#define NIC4_TXS0_MAX_OFFSET 0x1000 +#define NIC4_TXS0_SECTION 0xE800 + +#define mmNIC4_TXS0_SPECIAL_BASE 0x1000007FFD650E80ull +#define NIC4_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_TXS0_SPECIAL_SECTION 0x1800 + +#define mmNIC4_TXS1_BASE 0x1000007FFD651000ull +#define NIC4_TXS1_MAX_OFFSET 0x1000 +#define NIC4_TXS1_SECTION 0xE800 + +#define mmNIC4_TXS1_SPECIAL_BASE 0x1000007FFD651E80ull +#define NIC4_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_TXS1_SPECIAL_SECTION 0x1800 + +#define mmNIC4_TXE0_BASE 0x1000007FFD652000ull +#define NIC4_TXE0_MAX_OFFSET 0x1000 +#define NIC4_TXE0_SECTION 0xE800 + +#define mmNIC4_TXE0_SPECIAL_BASE 0x1000007FFD652E80ull +#define NIC4_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_TXE0_SPECIAL_SECTION 0x1800 + +#define mmNIC4_TXE1_BASE 0x1000007FFD653000ull +#define NIC4_TXE1_MAX_OFFSET 0x1000 +#define NIC4_TXE1_SECTION 0xE800 + +#define mmNIC4_TXE1_SPECIAL_BASE 0x1000007FFD653E80ull +#define NIC4_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_TXE1_SPECIAL_SECTION 0x1800 + +#define mmNIC4_TXB_BASE 0x1000007FFD654000ull +#define NIC4_TXB_MAX_OFFSET 0x1000 +#define NIC4_TXB_SECTION 0xE800 + +#define mmNIC4_TXB_SPECIAL_BASE 0x1000007FFD654E80ull +#define NIC4_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_TXB_SPECIAL_SECTION 0x1800 + +#define mmNIC4_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFD655000ull +#define NIC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmNIC4_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFD655200ull +#define NIC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmNIC4_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFD655400ull +#define NIC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmNIC4_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFD655600ull +#define NIC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmNIC4_MSTR_IF_E2E_CRDT_BASE 0x1000007FFD655800ull +#define NIC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC4_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmNIC4_MSTR_IF_AXUSER_BASE 0x1000007FFD655A80ull +#define NIC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC4_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmNIC4_MSTR_IF_DBG_HBW_BASE 0x1000007FFD655B00ull +#define NIC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC4_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmNIC4_MSTR_IF_DBG_LBW_BASE 0x1000007FFD655B80ull +#define NIC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC4_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmNIC4_MSTR_IF_CORE_HBW_BASE 0x1000007FFD655C00ull +#define NIC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC4_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmNIC4_MSTR_IF_CORE_LBW_BASE 0x1000007FFD655D80ull +#define NIC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC4_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmNIC4_MSTR_IF_SPECIAL_BASE 0x1000007FFD655E80ull +#define NIC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmNIC4_TX_AXUSER_BASE 0x1000007FFD656000ull +#define NIC4_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC4_TX_AXUSER_SECTION 0x2000 + +#define mmNIC4_SERDES0_BASE 0x1000007FFD658000ull +#define NIC4_SERDES0_MAX_OFFSET 0x3E40 +#define NIC4_SERDES0_SECTION 0x4000 + +#define mmNIC4_SERDES1_BASE 0x1000007FFD65C000ull +#define NIC4_SERDES1_MAX_OFFSET 0x3E40 +#define NIC4_SERDES1_SECTION 0x4000 + +#define mmNIC4_PHY_BASE 0x1000007FFD660000ull +#define NIC4_PHY_MAX_OFFSET 0x1000 +#define NIC4_PHY_SECTION 0xE800 + +#define mmNIC4_PHY_SPECIAL_BASE 0x1000007FFD660E80ull +#define NIC4_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC4_PHY_SPECIAL_SECTION 0x7180 + +#define mmPRT4_MAC_AUX_BASE 0x1000007FFD668000ull +#define PRT4_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT4_MAC_AUX_SECTION 0xE800 + +#define mmPRT4_MAC_AUX_SPECIAL_BASE 0x1000007FFD668E80ull +#define PRT4_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT4_MAC_AUX_SPECIAL_SECTION 0x1800 + +#define mmPRT4_MAC_CORE_BASE 0x1000007FFD669000ull +#define PRT4_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT4_MAC_CORE_SECTION 0xE800 + +#define mmPRT4_MAC_CORE_SPECIAL_BASE 0x1000007FFD669E80ull +#define PRT4_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT4_MAC_CORE_SPECIAL_SECTION 0x1800 + +#define mmNIC4_MAC_RS_FEC_BASE 0x1000007FFD66A000ull +#define NIC4_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC4_MAC_RS_FEC_SECTION 0x1000 + +#define mmNIC4_MAC_GLOB_STAT_NIC_MAC_STAT_BASE 0x1000007FFD66B000ull +#define NIC4_MAC_GLOB_STAT_NIC_MAC_STAT_MAX_OFFSET 0x4D00 +#define NIC4_MAC_GLOB_STAT_NIC_MAC_STAT_SECTION 0x8000 + +#define mmNIC4_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_BASE 0x1000007FFD66B800ull +#define NIC4_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC4_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_SECTION 0x8000 + +#define mmNIC4_MAC_CH0_MAC_PCS_BASE 0x1000007FFD66C000ull +#define NIC4_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC4_MAC_CH0_MAC_PCS_SECTION 0x4000 + +#define mmNIC4_MAC_CH0_MAC_128_BASE 0x1000007FFD66C400ull +#define NIC4_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC4_MAC_CH0_MAC_128_SECTION 0x4000 + +#define mmNIC4_MAC_CH0_MAC_AN_BASE 0x1000007FFD66C800ull +#define NIC4_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC4_MAC_CH0_MAC_AN_SECTION 0x8000 + +#define mmNIC4_MAC_CH1_MAC_PCS_BASE 0x1000007FFD66D000ull +#define NIC4_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC4_MAC_CH1_MAC_PCS_SECTION 0x4000 + +#define mmNIC4_MAC_CH1_MAC_128_BASE 0x1000007FFD66D400ull +#define NIC4_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC4_MAC_CH1_MAC_128_SECTION 0x4000 + +#define mmNIC4_MAC_CH1_MAC_AN_BASE 0x1000007FFD66D800ull +#define NIC4_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC4_MAC_CH1_MAC_AN_SECTION 0x8000 + +#define mmNIC4_MAC_CH2_MAC_PCS_BASE 0x1000007FFD66E000ull +#define NIC4_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC4_MAC_CH2_MAC_PCS_SECTION 0x4000 + +#define mmNIC4_MAC_CH2_MAC_128_BASE 0x1000007FFD66E400ull +#define NIC4_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC4_MAC_CH2_MAC_128_SECTION 0x4000 + +#define mmNIC4_MAC_CH2_MAC_AN_BASE 0x1000007FFD66E800ull +#define NIC4_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC4_MAC_CH2_MAC_AN_SECTION 0x8000 + +#define mmNIC4_MAC_CH3_MAC_PCS_BASE 0x1000007FFD66F000ull +#define NIC4_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC4_MAC_CH3_MAC_PCS_SECTION 0x4000 + +#define mmNIC4_MAC_CH3_MAC_128_BASE 0x1000007FFD66F400ull +#define NIC4_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC4_MAC_CH3_MAC_128_SECTION 0x4000 + +#define mmNIC4_MAC_CH3_MAC_AN_BASE 0x1000007FFD66F800ull +#define NIC4_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC4_MAC_CH3_MAC_AN_SECTION 0x10800 + +#define mmNIC5_UMR0_0_UNSECURE_DOORBELL0_BASE 0x1000007FFD680000ull +#define NIC5_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR0_0_UNSECURE_DOORBELL1_BASE 0x1000007FFD680080ull +#define NIC5_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD680100ull +#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD680180ull +#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR0_0_SPECIAL_BASE 0x1000007FFD680E80ull +#define NIC5_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_0_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR0_1_UNSECURE_DOORBELL0_BASE 0x1000007FFD681000ull +#define NIC5_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR0_1_UNSECURE_DOORBELL1_BASE 0x1000007FFD681080ull +#define NIC5_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD681100ull +#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD681180ull +#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR0_1_SPECIAL_BASE 0x1000007FFD681E80ull +#define NIC5_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_1_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR0_2_UNSECURE_DOORBELL0_BASE 0x1000007FFD682000ull +#define NIC5_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR0_2_UNSECURE_DOORBELL1_BASE 0x1000007FFD682080ull +#define NIC5_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD682100ull +#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD682180ull +#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR0_2_SPECIAL_BASE 0x1000007FFD682E80ull +#define NIC5_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_2_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR0_3_UNSECURE_DOORBELL0_BASE 0x1000007FFD683000ull +#define NIC5_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR0_3_UNSECURE_DOORBELL1_BASE 0x1000007FFD683080ull +#define NIC5_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD683100ull +#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD683180ull +#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR0_3_SPECIAL_BASE 0x1000007FFD683E80ull +#define NIC5_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_3_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR0_4_UNSECURE_DOORBELL0_BASE 0x1000007FFD684000ull +#define NIC5_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR0_4_UNSECURE_DOORBELL1_BASE 0x1000007FFD684080ull +#define NIC5_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD684100ull +#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD684180ull +#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR0_4_SPECIAL_BASE 0x1000007FFD684E80ull +#define NIC5_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_4_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR0_5_UNSECURE_DOORBELL0_BASE 0x1000007FFD685000ull +#define NIC5_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR0_5_UNSECURE_DOORBELL1_BASE 0x1000007FFD685080ull +#define NIC5_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD685100ull +#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD685180ull +#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR0_5_SPECIAL_BASE 0x1000007FFD685E80ull +#define NIC5_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_5_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR0_6_UNSECURE_DOORBELL0_BASE 0x1000007FFD686000ull +#define NIC5_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR0_6_UNSECURE_DOORBELL1_BASE 0x1000007FFD686080ull +#define NIC5_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD686100ull +#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD686180ull +#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR0_6_SPECIAL_BASE 0x1000007FFD686E80ull +#define NIC5_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_6_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR0_7_UNSECURE_DOORBELL0_BASE 0x1000007FFD687000ull +#define NIC5_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR0_7_UNSECURE_DOORBELL1_BASE 0x1000007FFD687080ull +#define NIC5_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD687100ull +#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD687180ull +#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR0_7_SPECIAL_BASE 0x1000007FFD687E80ull +#define NIC5_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_7_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR0_8_UNSECURE_DOORBELL0_BASE 0x1000007FFD688000ull +#define NIC5_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR0_8_UNSECURE_DOORBELL1_BASE 0x1000007FFD688080ull +#define NIC5_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD688100ull +#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD688180ull +#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR0_8_SPECIAL_BASE 0x1000007FFD688E80ull +#define NIC5_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_8_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR0_9_UNSECURE_DOORBELL0_BASE 0x1000007FFD689000ull +#define NIC5_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR0_9_UNSECURE_DOORBELL1_BASE 0x1000007FFD689080ull +#define NIC5_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD689100ull +#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD689180ull +#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR0_9_SPECIAL_BASE 0x1000007FFD689E80ull +#define NIC5_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_9_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR0_10_UNSECURE_DOORBELL0_BASE 0x1000007FFD68A000ull +#define NIC5_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR0_10_UNSECURE_DOORBELL1_BASE 0x1000007FFD68A080ull +#define NIC5_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD68A100ull +#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD68A180ull +#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR0_10_SPECIAL_BASE 0x1000007FFD68AE80ull +#define NIC5_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_10_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR0_11_UNSECURE_DOORBELL0_BASE 0x1000007FFD68B000ull +#define NIC5_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR0_11_UNSECURE_DOORBELL1_BASE 0x1000007FFD68B080ull +#define NIC5_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD68B100ull +#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD68B180ull +#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR0_11_SPECIAL_BASE 0x1000007FFD68BE80ull +#define NIC5_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_11_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR0_12_UNSECURE_DOORBELL0_BASE 0x1000007FFD68C000ull +#define NIC5_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR0_12_UNSECURE_DOORBELL1_BASE 0x1000007FFD68C080ull +#define NIC5_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD68C100ull +#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD68C180ull +#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR0_12_SPECIAL_BASE 0x1000007FFD68CE80ull +#define NIC5_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_12_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR0_13_UNSECURE_DOORBELL0_BASE 0x1000007FFD68D000ull +#define NIC5_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR0_13_UNSECURE_DOORBELL1_BASE 0x1000007FFD68D080ull +#define NIC5_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD68D100ull +#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD68D180ull +#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR0_13_SPECIAL_BASE 0x1000007FFD68DE80ull +#define NIC5_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_13_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR0_14_UNSECURE_DOORBELL0_BASE 0x1000007FFD68E000ull +#define NIC5_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR0_14_UNSECURE_DOORBELL1_BASE 0x1000007FFD68E080ull +#define NIC5_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD68E100ull +#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD68E180ull +#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR0_14_SPECIAL_BASE 0x1000007FFD68EE80ull +#define NIC5_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR0_14_SPECIAL_SECTION 0x1180 + +#define mmNIC5_QM_DCCM0_BASE 0x1000007FFD690000ull +#define NIC5_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC5_QM_DCCM0_SECTION 0x8000 + +#define mmNIC5_QM_ARC_AUX0_BASE 0x1000007FFD698000ull +#define NIC5_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC5_QM_ARC_AUX0_SECTION 0xE800 + +#define mmNIC5_QM_ARC_AUX0_SPECIAL_BASE 0x1000007FFD698E80ull +#define NIC5_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 + +#define mmNIC5_QM0_BASE 0x1000007FFD69A000ull +#define NIC5_QM0_MAX_OFFSET 0x1000 +#define NIC5_QM0_SECTION 0x9000 + +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFD69A900ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFD69A908ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFD69A910ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFD69A918ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFD69A920ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFD69A928ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFD69A930ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFD69A938ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFD69A940ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFD69A948ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFD69A950ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFD69A958ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFD69A960ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFD69A968ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFD69A970ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmNIC5_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFD69A978ull +#define NIC5_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC5_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmNIC5_QM0_AXUSER_SECURED_BASE 0x1000007FFD69AB00ull +#define NIC5_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC5_QM0_AXUSER_SECURED_SECTION 0x8000 + +#define mmNIC5_QM0_AXUSER_NONSECURED_BASE 0x1000007FFD69AB80ull +#define NIC5_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC5_QM0_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmNIC5_QM0_DBG_HBW_BASE 0x1000007FFD69AC00ull +#define NIC5_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC5_QM0_DBG_HBW_SECTION 0x8000 + +#define mmNIC5_QM0_DBG_LBW_BASE 0x1000007FFD69AC80ull +#define NIC5_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC5_QM0_DBG_LBW_SECTION 0x1000 + +#define mmNIC5_QM0_CGM_BASE 0x1000007FFD69AD80ull +#define NIC5_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC5_QM0_CGM_SECTION 0x1000 + +#define mmNIC5_QM0_SPECIAL_BASE 0x1000007FFD69AE80ull +#define NIC5_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_QM0_SPECIAL_SECTION 0x4180 + +#define mmNIC5_QPC0_BASE 0x1000007FFD69F000ull +#define NIC5_QPC0_MAX_OFFSET 0x1000 +#define NIC5_QPC0_SECTION 0x7200 + +#define mmNIC5_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x1000007FFD69F720ull +#define NIC5_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x1000007FFD69F728ull +#define NIC5_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x1000007FFD69F730ull +#define NIC5_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x1000007FFD69F738ull +#define NIC5_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x1000007FFD69F740ull +#define NIC5_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x1000007FFD69F748ull +#define NIC5_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x1000007FFD69F750ull +#define NIC5_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x1000007FFD69F758ull +#define NIC5_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x1000007FFD69F760ull +#define NIC5_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x1000007FFD69F768ull +#define NIC5_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x1000007FFD69F770ull +#define NIC5_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x1000007FFD69F778ull +#define NIC5_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x1000007FFD69F780ull +#define NIC5_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x1000007FFD69F788ull +#define NIC5_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x1000007FFD69F790ull +#define NIC5_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x1000007FFD69F798ull +#define NIC5_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x1000007FFD69F7A0ull +#define NIC5_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x1000007FFD69F7A8ull +#define NIC5_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x1000007FFD69F7B0ull +#define NIC5_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x1000007FFD69F7B8ull +#define NIC5_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x1000007FFD69F7C0ull +#define NIC5_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x1000007FFD69F7C8ull +#define NIC5_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x1000007FFD69F7D0ull +#define NIC5_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x1000007FFD69F7D8ull +#define NIC5_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x1000007FFD69F7E0ull +#define NIC5_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x1000007FFD69F7E8ull +#define NIC5_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x1000007FFD69F7F0ull +#define NIC5_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x1000007FFD69F7F8ull +#define NIC5_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x1000007FFD69F800ull +#define NIC5_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x1000007FFD69F808ull +#define NIC5_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x1000007FFD69F810ull +#define NIC5_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x1000007FFD69F818ull +#define NIC5_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 + +#define mmNIC5_QPC0_AXUSER_CONG_QUE_BASE 0x1000007FFD69FB80ull +#define NIC5_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC5_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 + +#define mmNIC5_QPC0_AXUSER_RXWQE_BASE 0x1000007FFD69FBE0ull +#define NIC5_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC5_QPC0_AXUSER_RXWQE_SECTION 0x6000 + +#define mmNIC5_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x1000007FFD69FC40ull +#define NIC5_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC5_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 + +#define mmNIC5_QPC0_AXUSER_DB_FIFO_BASE 0x1000007FFD69FCA0ull +#define NIC5_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC5_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 + +#define mmNIC5_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x1000007FFD69FD00ull +#define NIC5_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC5_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 + +#define mmNIC5_QPC0_AXUSER_ERR_FIFO_BASE 0x1000007FFD69FD60ull +#define NIC5_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC5_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 + +#define mmNIC5_QPC0_AXUSER_QPC_RESP_BASE 0x1000007FFD69FDC0ull +#define NIC5_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC5_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 + +#define mmNIC5_QPC0_AXUSER_QPC_REQ_BASE 0x1000007FFD69FE20ull +#define NIC5_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC5_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 + +#define mmNIC5_QPC0_SPECIAL_BASE 0x1000007FFD69FE80ull +#define NIC5_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_QPC0_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR1_0_UNSECURE_DOORBELL0_BASE 0x1000007FFD6A0000ull +#define NIC5_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR1_0_UNSECURE_DOORBELL1_BASE 0x1000007FFD6A0080ull +#define NIC5_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD6A0100ull +#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD6A0180ull +#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR1_0_SPECIAL_BASE 0x1000007FFD6A0E80ull +#define NIC5_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_0_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR1_1_UNSECURE_DOORBELL0_BASE 0x1000007FFD6A1000ull +#define NIC5_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR1_1_UNSECURE_DOORBELL1_BASE 0x1000007FFD6A1080ull +#define NIC5_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD6A1100ull +#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD6A1180ull +#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR1_1_SPECIAL_BASE 0x1000007FFD6A1E80ull +#define NIC5_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_1_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR1_2_UNSECURE_DOORBELL0_BASE 0x1000007FFD6A2000ull +#define NIC5_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR1_2_UNSECURE_DOORBELL1_BASE 0x1000007FFD6A2080ull +#define NIC5_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD6A2100ull +#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD6A2180ull +#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR1_2_SPECIAL_BASE 0x1000007FFD6A2E80ull +#define NIC5_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_2_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR1_3_UNSECURE_DOORBELL0_BASE 0x1000007FFD6A3000ull +#define NIC5_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR1_3_UNSECURE_DOORBELL1_BASE 0x1000007FFD6A3080ull +#define NIC5_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD6A3100ull +#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD6A3180ull +#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR1_3_SPECIAL_BASE 0x1000007FFD6A3E80ull +#define NIC5_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_3_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR1_4_UNSECURE_DOORBELL0_BASE 0x1000007FFD6A4000ull +#define NIC5_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR1_4_UNSECURE_DOORBELL1_BASE 0x1000007FFD6A4080ull +#define NIC5_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD6A4100ull +#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD6A4180ull +#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR1_4_SPECIAL_BASE 0x1000007FFD6A4E80ull +#define NIC5_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_4_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR1_5_UNSECURE_DOORBELL0_BASE 0x1000007FFD6A5000ull +#define NIC5_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR1_5_UNSECURE_DOORBELL1_BASE 0x1000007FFD6A5080ull +#define NIC5_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD6A5100ull +#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD6A5180ull +#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR1_5_SPECIAL_BASE 0x1000007FFD6A5E80ull +#define NIC5_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_5_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR1_6_UNSECURE_DOORBELL0_BASE 0x1000007FFD6A6000ull +#define NIC5_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR1_6_UNSECURE_DOORBELL1_BASE 0x1000007FFD6A6080ull +#define NIC5_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD6A6100ull +#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD6A6180ull +#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR1_6_SPECIAL_BASE 0x1000007FFD6A6E80ull +#define NIC5_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_6_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR1_7_UNSECURE_DOORBELL0_BASE 0x1000007FFD6A7000ull +#define NIC5_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR1_7_UNSECURE_DOORBELL1_BASE 0x1000007FFD6A7080ull +#define NIC5_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD6A7100ull +#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD6A7180ull +#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR1_7_SPECIAL_BASE 0x1000007FFD6A7E80ull +#define NIC5_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_7_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR1_8_UNSECURE_DOORBELL0_BASE 0x1000007FFD6A8000ull +#define NIC5_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR1_8_UNSECURE_DOORBELL1_BASE 0x1000007FFD6A8080ull +#define NIC5_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD6A8100ull +#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD6A8180ull +#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR1_8_SPECIAL_BASE 0x1000007FFD6A8E80ull +#define NIC5_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_8_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR1_9_UNSECURE_DOORBELL0_BASE 0x1000007FFD6A9000ull +#define NIC5_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR1_9_UNSECURE_DOORBELL1_BASE 0x1000007FFD6A9080ull +#define NIC5_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD6A9100ull +#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD6A9180ull +#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR1_9_SPECIAL_BASE 0x1000007FFD6A9E80ull +#define NIC5_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_9_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR1_10_UNSECURE_DOORBELL0_BASE 0x1000007FFD6AA000ull +#define NIC5_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR1_10_UNSECURE_DOORBELL1_BASE 0x1000007FFD6AA080ull +#define NIC5_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD6AA100ull +#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD6AA180ull +#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR1_10_SPECIAL_BASE 0x1000007FFD6AAE80ull +#define NIC5_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_10_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR1_11_UNSECURE_DOORBELL0_BASE 0x1000007FFD6AB000ull +#define NIC5_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR1_11_UNSECURE_DOORBELL1_BASE 0x1000007FFD6AB080ull +#define NIC5_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD6AB100ull +#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD6AB180ull +#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR1_11_SPECIAL_BASE 0x1000007FFD6ABE80ull +#define NIC5_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_11_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR1_12_UNSECURE_DOORBELL0_BASE 0x1000007FFD6AC000ull +#define NIC5_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR1_12_UNSECURE_DOORBELL1_BASE 0x1000007FFD6AC080ull +#define NIC5_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD6AC100ull +#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD6AC180ull +#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR1_12_SPECIAL_BASE 0x1000007FFD6ACE80ull +#define NIC5_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_12_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR1_13_UNSECURE_DOORBELL0_BASE 0x1000007FFD6AD000ull +#define NIC5_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR1_13_UNSECURE_DOORBELL1_BASE 0x1000007FFD6AD080ull +#define NIC5_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD6AD100ull +#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD6AD180ull +#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR1_13_SPECIAL_BASE 0x1000007FFD6ADE80ull +#define NIC5_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_13_SPECIAL_SECTION 0x1800 + +#define mmNIC5_UMR1_14_UNSECURE_DOORBELL0_BASE 0x1000007FFD6AE000ull +#define NIC5_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC5_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC5_UMR1_14_UNSECURE_DOORBELL1_BASE 0x1000007FFD6AE080ull +#define NIC5_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC5_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC5_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD6AE100ull +#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC5_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD6AE180ull +#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC5_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC5_UMR1_14_SPECIAL_BASE 0x1000007FFD6AEE80ull +#define NIC5_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_UMR1_14_SPECIAL_SECTION 0x1180 + +#define mmNIC5_QM_DCCM1_BASE 0x1000007FFD6B0000ull +#define NIC5_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC5_QM_DCCM1_SECTION 0x8000 + +#define mmNIC5_QM_ARC_AUX1_BASE 0x1000007FFD6B8000ull +#define NIC5_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC5_QM_ARC_AUX1_SECTION 0xE800 + +#define mmNIC5_QM_ARC_AUX1_SPECIAL_BASE 0x1000007FFD6B8E80ull +#define NIC5_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 + +#define mmNIC5_QM1_BASE 0x1000007FFD6BA000ull +#define NIC5_QM1_MAX_OFFSET 0x1000 +#define NIC5_QM1_SECTION 0x9000 + +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFD6BA900ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFD6BA908ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFD6BA910ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFD6BA918ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFD6BA920ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFD6BA928ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFD6BA930ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFD6BA938ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFD6BA940ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFD6BA948ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFD6BA950ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFD6BA958ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFD6BA960ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFD6BA968ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFD6BA970ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmNIC5_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFD6BA978ull +#define NIC5_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC5_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmNIC5_QM1_AXUSER_SECURED_BASE 0x1000007FFD6BAB00ull +#define NIC5_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC5_QM1_AXUSER_SECURED_SECTION 0x8000 + +#define mmNIC5_QM1_AXUSER_NONSECURED_BASE 0x1000007FFD6BAB80ull +#define NIC5_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC5_QM1_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmNIC5_QM1_DBG_HBW_BASE 0x1000007FFD6BAC00ull +#define NIC5_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC5_QM1_DBG_HBW_SECTION 0x8000 + +#define mmNIC5_QM1_DBG_LBW_BASE 0x1000007FFD6BAC80ull +#define NIC5_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC5_QM1_DBG_LBW_SECTION 0x1000 + +#define mmNIC5_QM1_CGM_BASE 0x1000007FFD6BAD80ull +#define NIC5_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC5_QM1_CGM_SECTION 0x1000 + +#define mmNIC5_QM1_SPECIAL_BASE 0x1000007FFD6BAE80ull +#define NIC5_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_QM1_SPECIAL_SECTION 0x4180 + +#define mmNIC5_QPC1_BASE 0x1000007FFD6BF000ull +#define NIC5_QPC1_MAX_OFFSET 0x1000 +#define NIC5_QPC1_SECTION 0x7200 + +#define mmNIC5_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x1000007FFD6BF720ull +#define NIC5_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x1000007FFD6BF728ull +#define NIC5_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x1000007FFD6BF730ull +#define NIC5_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x1000007FFD6BF738ull +#define NIC5_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x1000007FFD6BF740ull +#define NIC5_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x1000007FFD6BF748ull +#define NIC5_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x1000007FFD6BF750ull +#define NIC5_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x1000007FFD6BF758ull +#define NIC5_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x1000007FFD6BF760ull +#define NIC5_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x1000007FFD6BF768ull +#define NIC5_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x1000007FFD6BF770ull +#define NIC5_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x1000007FFD6BF778ull +#define NIC5_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x1000007FFD6BF780ull +#define NIC5_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x1000007FFD6BF788ull +#define NIC5_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x1000007FFD6BF790ull +#define NIC5_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x1000007FFD6BF798ull +#define NIC5_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x1000007FFD6BF7A0ull +#define NIC5_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x1000007FFD6BF7A8ull +#define NIC5_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x1000007FFD6BF7B0ull +#define NIC5_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x1000007FFD6BF7B8ull +#define NIC5_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x1000007FFD6BF7C0ull +#define NIC5_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x1000007FFD6BF7C8ull +#define NIC5_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x1000007FFD6BF7D0ull +#define NIC5_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x1000007FFD6BF7D8ull +#define NIC5_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x1000007FFD6BF7E0ull +#define NIC5_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x1000007FFD6BF7E8ull +#define NIC5_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x1000007FFD6BF7F0ull +#define NIC5_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x1000007FFD6BF7F8ull +#define NIC5_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x1000007FFD6BF800ull +#define NIC5_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x1000007FFD6BF808ull +#define NIC5_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x1000007FFD6BF810ull +#define NIC5_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC5_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x1000007FFD6BF818ull +#define NIC5_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC5_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 + +#define mmNIC5_QPC1_AXUSER_CONG_QUE_BASE 0x1000007FFD6BFB80ull +#define NIC5_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC5_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 + +#define mmNIC5_QPC1_AXUSER_RXWQE_BASE 0x1000007FFD6BFBE0ull +#define NIC5_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC5_QPC1_AXUSER_RXWQE_SECTION 0x6000 + +#define mmNIC5_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x1000007FFD6BFC40ull +#define NIC5_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC5_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 + +#define mmNIC5_QPC1_AXUSER_DB_FIFO_BASE 0x1000007FFD6BFCA0ull +#define NIC5_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC5_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 + +#define mmNIC5_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x1000007FFD6BFD00ull +#define NIC5_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC5_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 + +#define mmNIC5_QPC1_AXUSER_ERR_FIFO_BASE 0x1000007FFD6BFD60ull +#define NIC5_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC5_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 + +#define mmNIC5_QPC1_AXUSER_QPC_RESP_BASE 0x1000007FFD6BFDC0ull +#define NIC5_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC5_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 + +#define mmNIC5_QPC1_AXUSER_QPC_REQ_BASE 0x1000007FFD6BFE20ull +#define NIC5_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC5_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 + +#define mmNIC5_QPC1_SPECIAL_BASE 0x1000007FFD6BFE80ull +#define NIC5_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_QPC1_SPECIAL_SECTION 0x8180 + +#define mmNIC5_TMR_BASE 0x1000007FFD6C8000ull +#define NIC5_TMR_MAX_OFFSET 0x1000 +#define NIC5_TMR_SECTION 0xD600 + +#define mmNIC5_TMR_AXUSER_TMR_FREE_LIST_BASE 0x1000007FFD6C8D60ull +#define NIC5_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC5_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 + +#define mmNIC5_TMR_AXUSER_TMR_FIFO_BASE 0x1000007FFD6C8DC0ull +#define NIC5_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC5_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 + +#define mmNIC5_TMR_AXUSER_TMR_FSM_BASE 0x1000007FFD6C8E20ull +#define NIC5_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC5_TMR_AXUSER_TMR_FSM_SECTION 0x6000 + +#define mmNIC5_TMR_SPECIAL_BASE 0x1000007FFD6C8E80ull +#define NIC5_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_TMR_SPECIAL_SECTION 0x1800 + +#define mmNIC5_RXB_CORE_BASE 0x1000007FFD6C9000ull +#define NIC5_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC5_RXB_CORE_SECTION 0x6100 + +#define mmNIC5_RXB_CORE_SCT_AWUSER_BASE 0x1000007FFD6C9610ull +#define NIC5_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC5_RXB_CORE_SCT_AWUSER_SECTION 0x8700 + +#define mmNIC5_RXB_CORE_SPECIAL_BASE 0x1000007FFD6C9E80ull +#define NIC5_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_RXB_CORE_SPECIAL_SECTION 0x1800 + +#define mmNIC5_RXE0_BASE 0x1000007FFD6CA000ull +#define NIC5_RXE0_MAX_OFFSET 0x1000 +#define NIC5_RXE0_SECTION 0x9000 + +#define mmNIC5_RXE0_WQE_ARUSER_BASE 0x1000007FFD6CA900ull +#define NIC5_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC5_RXE0_WQE_ARUSER_SECTION 0x5800 + +#define mmNIC5_RXE0_SPECIAL_BASE 0x1000007FFD6CAE80ull +#define NIC5_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_RXE0_SPECIAL_SECTION 0x1800 + +#define mmNIC5_RXE1_BASE 0x1000007FFD6CB000ull +#define NIC5_RXE1_MAX_OFFSET 0x1000 +#define NIC5_RXE1_SECTION 0x9000 + +#define mmNIC5_RXE1_WQE_ARUSER_BASE 0x1000007FFD6CB900ull +#define NIC5_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC5_RXE1_WQE_ARUSER_SECTION 0x5800 + +#define mmNIC5_RXE1_SPECIAL_BASE 0x1000007FFD6CBE80ull +#define NIC5_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_RXE1_SPECIAL_SECTION 0x1800 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ0_BASE 0x1000007FFD6CC000ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ1_BASE 0x1000007FFD6CC050ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ2_BASE 0x1000007FFD6CC0A0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ3_BASE 0x1000007FFD6CC0F0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ4_BASE 0x1000007FFD6CC140ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ5_BASE 0x1000007FFD6CC190ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ6_BASE 0x1000007FFD6CC1E0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ7_BASE 0x1000007FFD6CC230ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ8_BASE 0x1000007FFD6CC280ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ9_BASE 0x1000007FFD6CC2D0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ10_BASE 0x1000007FFD6CC320ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ11_BASE 0x1000007FFD6CC370ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ12_BASE 0x1000007FFD6CC3C0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ13_BASE 0x1000007FFD6CC410ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ14_BASE 0x1000007FFD6CC460ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ15_BASE 0x1000007FFD6CC4B0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ16_BASE 0x1000007FFD6CC500ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ17_BASE 0x1000007FFD6CC550ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ18_BASE 0x1000007FFD6CC5A0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ19_BASE 0x1000007FFD6CC5F0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ20_BASE 0x1000007FFD6CC640ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ21_BASE 0x1000007FFD6CC690ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ22_BASE 0x1000007FFD6CC6E0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ23_BASE 0x1000007FFD6CC730ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ24_BASE 0x1000007FFD6CC780ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ25_BASE 0x1000007FFD6CC7D0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ26_BASE 0x1000007FFD6CC820ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ27_BASE 0x1000007FFD6CC870ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ28_BASE 0x1000007FFD6CC8C0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ29_BASE 0x1000007FFD6CC910ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ30_BASE 0x1000007FFD6CC960ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 + +#define mmNIC5_RXE0_AXUSER_AXUSER_CQ31_BASE 0x1000007FFD6CC9B0ull +#define NIC5_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC5_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 + +#define mmNIC5_RXE0_AXUSER_SPECIAL_BASE 0x1000007FFD6CCE80ull +#define NIC5_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_RXE0_AXUSER_SPECIAL_SECTION 0x1800 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ0_BASE 0x1000007FFD6CD000ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ1_BASE 0x1000007FFD6CD050ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ2_BASE 0x1000007FFD6CD0A0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ3_BASE 0x1000007FFD6CD0F0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ4_BASE 0x1000007FFD6CD140ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ5_BASE 0x1000007FFD6CD190ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ6_BASE 0x1000007FFD6CD1E0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ7_BASE 0x1000007FFD6CD230ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ8_BASE 0x1000007FFD6CD280ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ9_BASE 0x1000007FFD6CD2D0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ10_BASE 0x1000007FFD6CD320ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ11_BASE 0x1000007FFD6CD370ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ12_BASE 0x1000007FFD6CD3C0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ13_BASE 0x1000007FFD6CD410ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ14_BASE 0x1000007FFD6CD460ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ15_BASE 0x1000007FFD6CD4B0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ16_BASE 0x1000007FFD6CD500ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ17_BASE 0x1000007FFD6CD550ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ18_BASE 0x1000007FFD6CD5A0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ19_BASE 0x1000007FFD6CD5F0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ20_BASE 0x1000007FFD6CD640ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ21_BASE 0x1000007FFD6CD690ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ22_BASE 0x1000007FFD6CD6E0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ23_BASE 0x1000007FFD6CD730ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ24_BASE 0x1000007FFD6CD780ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ25_BASE 0x1000007FFD6CD7D0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ26_BASE 0x1000007FFD6CD820ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ27_BASE 0x1000007FFD6CD870ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ28_BASE 0x1000007FFD6CD8C0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ29_BASE 0x1000007FFD6CD910ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ30_BASE 0x1000007FFD6CD960ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 + +#define mmNIC5_RXE1_AXUSER_AXUSER_CQ31_BASE 0x1000007FFD6CD9B0ull +#define NIC5_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC5_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 + +#define mmNIC5_RXE1_AXUSER_SPECIAL_BASE 0x1000007FFD6CDE80ull +#define NIC5_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_RXE1_AXUSER_SPECIAL_SECTION 0x2180 + +#define mmNIC5_TXS0_BASE 0x1000007FFD6D0000ull +#define NIC5_TXS0_MAX_OFFSET 0x1000 +#define NIC5_TXS0_SECTION 0xE800 + +#define mmNIC5_TXS0_SPECIAL_BASE 0x1000007FFD6D0E80ull +#define NIC5_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_TXS0_SPECIAL_SECTION 0x1800 + +#define mmNIC5_TXS1_BASE 0x1000007FFD6D1000ull +#define NIC5_TXS1_MAX_OFFSET 0x1000 +#define NIC5_TXS1_SECTION 0xE800 + +#define mmNIC5_TXS1_SPECIAL_BASE 0x1000007FFD6D1E80ull +#define NIC5_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_TXS1_SPECIAL_SECTION 0x1800 + +#define mmNIC5_TXE0_BASE 0x1000007FFD6D2000ull +#define NIC5_TXE0_MAX_OFFSET 0x1000 +#define NIC5_TXE0_SECTION 0xE800 + +#define mmNIC5_TXE0_SPECIAL_BASE 0x1000007FFD6D2E80ull +#define NIC5_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_TXE0_SPECIAL_SECTION 0x1800 + +#define mmNIC5_TXE1_BASE 0x1000007FFD6D3000ull +#define NIC5_TXE1_MAX_OFFSET 0x1000 +#define NIC5_TXE1_SECTION 0xE800 + +#define mmNIC5_TXE1_SPECIAL_BASE 0x1000007FFD6D3E80ull +#define NIC5_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_TXE1_SPECIAL_SECTION 0x1800 + +#define mmNIC5_TXB_BASE 0x1000007FFD6D4000ull +#define NIC5_TXB_MAX_OFFSET 0x1000 +#define NIC5_TXB_SECTION 0xE800 + +#define mmNIC5_TXB_SPECIAL_BASE 0x1000007FFD6D4E80ull +#define NIC5_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_TXB_SPECIAL_SECTION 0x1800 + +#define mmNIC5_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFD6D5000ull +#define NIC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmNIC5_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFD6D5200ull +#define NIC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmNIC5_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFD6D5400ull +#define NIC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmNIC5_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFD6D5600ull +#define NIC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmNIC5_MSTR_IF_E2E_CRDT_BASE 0x1000007FFD6D5800ull +#define NIC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC5_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmNIC5_MSTR_IF_AXUSER_BASE 0x1000007FFD6D5A80ull +#define NIC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC5_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmNIC5_MSTR_IF_DBG_HBW_BASE 0x1000007FFD6D5B00ull +#define NIC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC5_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmNIC5_MSTR_IF_DBG_LBW_BASE 0x1000007FFD6D5B80ull +#define NIC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC5_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmNIC5_MSTR_IF_CORE_HBW_BASE 0x1000007FFD6D5C00ull +#define NIC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC5_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmNIC5_MSTR_IF_CORE_LBW_BASE 0x1000007FFD6D5D80ull +#define NIC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC5_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmNIC5_MSTR_IF_SPECIAL_BASE 0x1000007FFD6D5E80ull +#define NIC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmNIC5_TX_AXUSER_BASE 0x1000007FFD6D6000ull +#define NIC5_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC5_TX_AXUSER_SECTION 0x2000 + +#define mmNIC5_SERDES0_BASE 0x1000007FFD6D8000ull +#define NIC5_SERDES0_MAX_OFFSET 0x3E40 +#define NIC5_SERDES0_SECTION 0x4000 + +#define mmNIC5_SERDES1_BASE 0x1000007FFD6DC000ull +#define NIC5_SERDES1_MAX_OFFSET 0x3E40 +#define NIC5_SERDES1_SECTION 0x4000 + +#define mmNIC5_PHY_BASE 0x1000007FFD6E0000ull +#define NIC5_PHY_MAX_OFFSET 0x1000 +#define NIC5_PHY_SECTION 0xE800 + +#define mmNIC5_PHY_SPECIAL_BASE 0x1000007FFD6E0E80ull +#define NIC5_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC5_PHY_SPECIAL_SECTION 0x7180 + +#define mmPRT5_MAC_AUX_BASE 0x1000007FFD6E8000ull +#define PRT5_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT5_MAC_AUX_SECTION 0xE800 + +#define mmPRT5_MAC_AUX_SPECIAL_BASE 0x1000007FFD6E8E80ull +#define PRT5_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT5_MAC_AUX_SPECIAL_SECTION 0x1800 + +#define mmPRT5_MAC_CORE_BASE 0x1000007FFD6E9000ull +#define PRT5_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT5_MAC_CORE_SECTION 0xE800 + +#define mmPRT5_MAC_CORE_SPECIAL_BASE 0x1000007FFD6E9E80ull +#define PRT5_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT5_MAC_CORE_SPECIAL_SECTION 0x1800 + +#define mmNIC5_MAC_RS_FEC_BASE 0x1000007FFD6EA000ull +#define NIC5_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC5_MAC_RS_FEC_SECTION 0x1000 + +#define mmNIC5_MAC_GLOB_STAT_NIC_MAC_STAT_BASE 0x1000007FFD6EB000ull +#define NIC5_MAC_GLOB_STAT_NIC_MAC_STAT_MAX_OFFSET 0x4D00 +#define NIC5_MAC_GLOB_STAT_NIC_MAC_STAT_SECTION 0x8000 + +#define mmNIC5_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_BASE 0x1000007FFD6EB800ull +#define NIC5_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC5_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_SECTION 0x8000 + +#define mmNIC5_MAC_CH0_MAC_PCS_BASE 0x1000007FFD6EC000ull +#define NIC5_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC5_MAC_CH0_MAC_PCS_SECTION 0x4000 + +#define mmNIC5_MAC_CH0_MAC_128_BASE 0x1000007FFD6EC400ull +#define NIC5_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC5_MAC_CH0_MAC_128_SECTION 0x4000 + +#define mmNIC5_MAC_CH0_MAC_AN_BASE 0x1000007FFD6EC800ull +#define NIC5_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC5_MAC_CH0_MAC_AN_SECTION 0x8000 + +#define mmNIC5_MAC_CH1_MAC_PCS_BASE 0x1000007FFD6ED000ull +#define NIC5_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC5_MAC_CH1_MAC_PCS_SECTION 0x4000 + +#define mmNIC5_MAC_CH1_MAC_128_BASE 0x1000007FFD6ED400ull +#define NIC5_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC5_MAC_CH1_MAC_128_SECTION 0x4000 + +#define mmNIC5_MAC_CH1_MAC_AN_BASE 0x1000007FFD6ED800ull +#define NIC5_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC5_MAC_CH1_MAC_AN_SECTION 0x8000 + +#define mmNIC5_MAC_CH2_MAC_PCS_BASE 0x1000007FFD6EE000ull +#define NIC5_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC5_MAC_CH2_MAC_PCS_SECTION 0x4000 + +#define mmNIC5_MAC_CH2_MAC_128_BASE 0x1000007FFD6EE400ull +#define NIC5_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC5_MAC_CH2_MAC_128_SECTION 0x4000 + +#define mmNIC5_MAC_CH2_MAC_AN_BASE 0x1000007FFD6EE800ull +#define NIC5_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC5_MAC_CH2_MAC_AN_SECTION 0x8000 + +#define mmNIC5_MAC_CH3_MAC_PCS_BASE 0x1000007FFD6EF000ull +#define NIC5_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC5_MAC_CH3_MAC_PCS_SECTION 0x4000 + +#define mmNIC5_MAC_CH3_MAC_128_BASE 0x1000007FFD6EF400ull +#define NIC5_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC5_MAC_CH3_MAC_128_SECTION 0x4000 + +#define mmNIC5_MAC_CH3_MAC_AN_BASE 0x1000007FFD6EF800ull +#define NIC5_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC5_MAC_CH3_MAC_AN_SECTION 0x10800 + +#define mmNIC6_UMR0_0_UNSECURE_DOORBELL0_BASE 0x1000007FFD700000ull +#define NIC6_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR0_0_UNSECURE_DOORBELL1_BASE 0x1000007FFD700080ull +#define NIC6_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD700100ull +#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD700180ull +#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR0_0_SPECIAL_BASE 0x1000007FFD700E80ull +#define NIC6_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_0_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR0_1_UNSECURE_DOORBELL0_BASE 0x1000007FFD701000ull +#define NIC6_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR0_1_UNSECURE_DOORBELL1_BASE 0x1000007FFD701080ull +#define NIC6_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD701100ull +#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD701180ull +#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR0_1_SPECIAL_BASE 0x1000007FFD701E80ull +#define NIC6_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_1_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR0_2_UNSECURE_DOORBELL0_BASE 0x1000007FFD702000ull +#define NIC6_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR0_2_UNSECURE_DOORBELL1_BASE 0x1000007FFD702080ull +#define NIC6_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD702100ull +#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD702180ull +#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR0_2_SPECIAL_BASE 0x1000007FFD702E80ull +#define NIC6_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_2_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR0_3_UNSECURE_DOORBELL0_BASE 0x1000007FFD703000ull +#define NIC6_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR0_3_UNSECURE_DOORBELL1_BASE 0x1000007FFD703080ull +#define NIC6_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD703100ull +#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD703180ull +#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR0_3_SPECIAL_BASE 0x1000007FFD703E80ull +#define NIC6_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_3_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR0_4_UNSECURE_DOORBELL0_BASE 0x1000007FFD704000ull +#define NIC6_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR0_4_UNSECURE_DOORBELL1_BASE 0x1000007FFD704080ull +#define NIC6_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD704100ull +#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD704180ull +#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR0_4_SPECIAL_BASE 0x1000007FFD704E80ull +#define NIC6_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_4_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR0_5_UNSECURE_DOORBELL0_BASE 0x1000007FFD705000ull +#define NIC6_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR0_5_UNSECURE_DOORBELL1_BASE 0x1000007FFD705080ull +#define NIC6_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD705100ull +#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD705180ull +#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR0_5_SPECIAL_BASE 0x1000007FFD705E80ull +#define NIC6_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_5_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR0_6_UNSECURE_DOORBELL0_BASE 0x1000007FFD706000ull +#define NIC6_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR0_6_UNSECURE_DOORBELL1_BASE 0x1000007FFD706080ull +#define NIC6_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD706100ull +#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD706180ull +#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR0_6_SPECIAL_BASE 0x1000007FFD706E80ull +#define NIC6_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_6_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR0_7_UNSECURE_DOORBELL0_BASE 0x1000007FFD707000ull +#define NIC6_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR0_7_UNSECURE_DOORBELL1_BASE 0x1000007FFD707080ull +#define NIC6_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD707100ull +#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD707180ull +#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR0_7_SPECIAL_BASE 0x1000007FFD707E80ull +#define NIC6_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_7_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR0_8_UNSECURE_DOORBELL0_BASE 0x1000007FFD708000ull +#define NIC6_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR0_8_UNSECURE_DOORBELL1_BASE 0x1000007FFD708080ull +#define NIC6_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD708100ull +#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD708180ull +#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR0_8_SPECIAL_BASE 0x1000007FFD708E80ull +#define NIC6_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_8_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR0_9_UNSECURE_DOORBELL0_BASE 0x1000007FFD709000ull +#define NIC6_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR0_9_UNSECURE_DOORBELL1_BASE 0x1000007FFD709080ull +#define NIC6_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD709100ull +#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD709180ull +#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR0_9_SPECIAL_BASE 0x1000007FFD709E80ull +#define NIC6_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_9_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR0_10_UNSECURE_DOORBELL0_BASE 0x1000007FFD70A000ull +#define NIC6_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR0_10_UNSECURE_DOORBELL1_BASE 0x1000007FFD70A080ull +#define NIC6_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD70A100ull +#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD70A180ull +#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR0_10_SPECIAL_BASE 0x1000007FFD70AE80ull +#define NIC6_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_10_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR0_11_UNSECURE_DOORBELL0_BASE 0x1000007FFD70B000ull +#define NIC6_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR0_11_UNSECURE_DOORBELL1_BASE 0x1000007FFD70B080ull +#define NIC6_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD70B100ull +#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD70B180ull +#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR0_11_SPECIAL_BASE 0x1000007FFD70BE80ull +#define NIC6_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_11_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR0_12_UNSECURE_DOORBELL0_BASE 0x1000007FFD70C000ull +#define NIC6_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR0_12_UNSECURE_DOORBELL1_BASE 0x1000007FFD70C080ull +#define NIC6_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD70C100ull +#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD70C180ull +#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR0_12_SPECIAL_BASE 0x1000007FFD70CE80ull +#define NIC6_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_12_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR0_13_UNSECURE_DOORBELL0_BASE 0x1000007FFD70D000ull +#define NIC6_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR0_13_UNSECURE_DOORBELL1_BASE 0x1000007FFD70D080ull +#define NIC6_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD70D100ull +#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD70D180ull +#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR0_13_SPECIAL_BASE 0x1000007FFD70DE80ull +#define NIC6_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_13_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR0_14_UNSECURE_DOORBELL0_BASE 0x1000007FFD70E000ull +#define NIC6_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR0_14_UNSECURE_DOORBELL1_BASE 0x1000007FFD70E080ull +#define NIC6_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD70E100ull +#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD70E180ull +#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR0_14_SPECIAL_BASE 0x1000007FFD70EE80ull +#define NIC6_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR0_14_SPECIAL_SECTION 0x1180 + +#define mmNIC6_QM_DCCM0_BASE 0x1000007FFD710000ull +#define NIC6_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC6_QM_DCCM0_SECTION 0x8000 + +#define mmNIC6_QM_ARC_AUX0_BASE 0x1000007FFD718000ull +#define NIC6_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC6_QM_ARC_AUX0_SECTION 0xE800 + +#define mmNIC6_QM_ARC_AUX0_SPECIAL_BASE 0x1000007FFD718E80ull +#define NIC6_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 + +#define mmNIC6_QM0_BASE 0x1000007FFD71A000ull +#define NIC6_QM0_MAX_OFFSET 0x1000 +#define NIC6_QM0_SECTION 0x9000 + +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFD71A900ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFD71A908ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFD71A910ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFD71A918ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFD71A920ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFD71A928ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFD71A930ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFD71A938ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFD71A940ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFD71A948ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFD71A950ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFD71A958ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFD71A960ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFD71A968ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFD71A970ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmNIC6_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFD71A978ull +#define NIC6_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC6_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmNIC6_QM0_AXUSER_SECURED_BASE 0x1000007FFD71AB00ull +#define NIC6_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC6_QM0_AXUSER_SECURED_SECTION 0x8000 + +#define mmNIC6_QM0_AXUSER_NONSECURED_BASE 0x1000007FFD71AB80ull +#define NIC6_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC6_QM0_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmNIC6_QM0_DBG_HBW_BASE 0x1000007FFD71AC00ull +#define NIC6_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC6_QM0_DBG_HBW_SECTION 0x8000 + +#define mmNIC6_QM0_DBG_LBW_BASE 0x1000007FFD71AC80ull +#define NIC6_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC6_QM0_DBG_LBW_SECTION 0x1000 + +#define mmNIC6_QM0_CGM_BASE 0x1000007FFD71AD80ull +#define NIC6_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC6_QM0_CGM_SECTION 0x1000 + +#define mmNIC6_QM0_SPECIAL_BASE 0x1000007FFD71AE80ull +#define NIC6_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_QM0_SPECIAL_SECTION 0x4180 + +#define mmNIC6_QPC0_BASE 0x1000007FFD71F000ull +#define NIC6_QPC0_MAX_OFFSET 0x1000 +#define NIC6_QPC0_SECTION 0x7200 + +#define mmNIC6_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x1000007FFD71F720ull +#define NIC6_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x1000007FFD71F728ull +#define NIC6_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x1000007FFD71F730ull +#define NIC6_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x1000007FFD71F738ull +#define NIC6_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x1000007FFD71F740ull +#define NIC6_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x1000007FFD71F748ull +#define NIC6_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x1000007FFD71F750ull +#define NIC6_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x1000007FFD71F758ull +#define NIC6_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x1000007FFD71F760ull +#define NIC6_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x1000007FFD71F768ull +#define NIC6_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x1000007FFD71F770ull +#define NIC6_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x1000007FFD71F778ull +#define NIC6_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x1000007FFD71F780ull +#define NIC6_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x1000007FFD71F788ull +#define NIC6_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x1000007FFD71F790ull +#define NIC6_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x1000007FFD71F798ull +#define NIC6_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x1000007FFD71F7A0ull +#define NIC6_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x1000007FFD71F7A8ull +#define NIC6_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x1000007FFD71F7B0ull +#define NIC6_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x1000007FFD71F7B8ull +#define NIC6_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x1000007FFD71F7C0ull +#define NIC6_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x1000007FFD71F7C8ull +#define NIC6_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x1000007FFD71F7D0ull +#define NIC6_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x1000007FFD71F7D8ull +#define NIC6_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x1000007FFD71F7E0ull +#define NIC6_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x1000007FFD71F7E8ull +#define NIC6_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x1000007FFD71F7F0ull +#define NIC6_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x1000007FFD71F7F8ull +#define NIC6_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x1000007FFD71F800ull +#define NIC6_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x1000007FFD71F808ull +#define NIC6_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x1000007FFD71F810ull +#define NIC6_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x1000007FFD71F818ull +#define NIC6_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 + +#define mmNIC6_QPC0_AXUSER_CONG_QUE_BASE 0x1000007FFD71FB80ull +#define NIC6_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC6_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 + +#define mmNIC6_QPC0_AXUSER_RXWQE_BASE 0x1000007FFD71FBE0ull +#define NIC6_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC6_QPC0_AXUSER_RXWQE_SECTION 0x6000 + +#define mmNIC6_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x1000007FFD71FC40ull +#define NIC6_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC6_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 + +#define mmNIC6_QPC0_AXUSER_DB_FIFO_BASE 0x1000007FFD71FCA0ull +#define NIC6_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC6_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 + +#define mmNIC6_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x1000007FFD71FD00ull +#define NIC6_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC6_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 + +#define mmNIC6_QPC0_AXUSER_ERR_FIFO_BASE 0x1000007FFD71FD60ull +#define NIC6_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC6_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 + +#define mmNIC6_QPC0_AXUSER_QPC_RESP_BASE 0x1000007FFD71FDC0ull +#define NIC6_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC6_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 + +#define mmNIC6_QPC0_AXUSER_QPC_REQ_BASE 0x1000007FFD71FE20ull +#define NIC6_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC6_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 + +#define mmNIC6_QPC0_SPECIAL_BASE 0x1000007FFD71FE80ull +#define NIC6_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_QPC0_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR1_0_UNSECURE_DOORBELL0_BASE 0x1000007FFD720000ull +#define NIC6_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR1_0_UNSECURE_DOORBELL1_BASE 0x1000007FFD720080ull +#define NIC6_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD720100ull +#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD720180ull +#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR1_0_SPECIAL_BASE 0x1000007FFD720E80ull +#define NIC6_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_0_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR1_1_UNSECURE_DOORBELL0_BASE 0x1000007FFD721000ull +#define NIC6_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR1_1_UNSECURE_DOORBELL1_BASE 0x1000007FFD721080ull +#define NIC6_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD721100ull +#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD721180ull +#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR1_1_SPECIAL_BASE 0x1000007FFD721E80ull +#define NIC6_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_1_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR1_2_UNSECURE_DOORBELL0_BASE 0x1000007FFD722000ull +#define NIC6_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR1_2_UNSECURE_DOORBELL1_BASE 0x1000007FFD722080ull +#define NIC6_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD722100ull +#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD722180ull +#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR1_2_SPECIAL_BASE 0x1000007FFD722E80ull +#define NIC6_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_2_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR1_3_UNSECURE_DOORBELL0_BASE 0x1000007FFD723000ull +#define NIC6_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR1_3_UNSECURE_DOORBELL1_BASE 0x1000007FFD723080ull +#define NIC6_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD723100ull +#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD723180ull +#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR1_3_SPECIAL_BASE 0x1000007FFD723E80ull +#define NIC6_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_3_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR1_4_UNSECURE_DOORBELL0_BASE 0x1000007FFD724000ull +#define NIC6_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR1_4_UNSECURE_DOORBELL1_BASE 0x1000007FFD724080ull +#define NIC6_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD724100ull +#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD724180ull +#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR1_4_SPECIAL_BASE 0x1000007FFD724E80ull +#define NIC6_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_4_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR1_5_UNSECURE_DOORBELL0_BASE 0x1000007FFD725000ull +#define NIC6_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR1_5_UNSECURE_DOORBELL1_BASE 0x1000007FFD725080ull +#define NIC6_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD725100ull +#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD725180ull +#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR1_5_SPECIAL_BASE 0x1000007FFD725E80ull +#define NIC6_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_5_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR1_6_UNSECURE_DOORBELL0_BASE 0x1000007FFD726000ull +#define NIC6_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR1_6_UNSECURE_DOORBELL1_BASE 0x1000007FFD726080ull +#define NIC6_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD726100ull +#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD726180ull +#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR1_6_SPECIAL_BASE 0x1000007FFD726E80ull +#define NIC6_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_6_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR1_7_UNSECURE_DOORBELL0_BASE 0x1000007FFD727000ull +#define NIC6_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR1_7_UNSECURE_DOORBELL1_BASE 0x1000007FFD727080ull +#define NIC6_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD727100ull +#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD727180ull +#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR1_7_SPECIAL_BASE 0x1000007FFD727E80ull +#define NIC6_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_7_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR1_8_UNSECURE_DOORBELL0_BASE 0x1000007FFD728000ull +#define NIC6_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR1_8_UNSECURE_DOORBELL1_BASE 0x1000007FFD728080ull +#define NIC6_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD728100ull +#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD728180ull +#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR1_8_SPECIAL_BASE 0x1000007FFD728E80ull +#define NIC6_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_8_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR1_9_UNSECURE_DOORBELL0_BASE 0x1000007FFD729000ull +#define NIC6_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR1_9_UNSECURE_DOORBELL1_BASE 0x1000007FFD729080ull +#define NIC6_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD729100ull +#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD729180ull +#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR1_9_SPECIAL_BASE 0x1000007FFD729E80ull +#define NIC6_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_9_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR1_10_UNSECURE_DOORBELL0_BASE 0x1000007FFD72A000ull +#define NIC6_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR1_10_UNSECURE_DOORBELL1_BASE 0x1000007FFD72A080ull +#define NIC6_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD72A100ull +#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD72A180ull +#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR1_10_SPECIAL_BASE 0x1000007FFD72AE80ull +#define NIC6_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_10_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR1_11_UNSECURE_DOORBELL0_BASE 0x1000007FFD72B000ull +#define NIC6_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR1_11_UNSECURE_DOORBELL1_BASE 0x1000007FFD72B080ull +#define NIC6_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD72B100ull +#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD72B180ull +#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR1_11_SPECIAL_BASE 0x1000007FFD72BE80ull +#define NIC6_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_11_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR1_12_UNSECURE_DOORBELL0_BASE 0x1000007FFD72C000ull +#define NIC6_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR1_12_UNSECURE_DOORBELL1_BASE 0x1000007FFD72C080ull +#define NIC6_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD72C100ull +#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD72C180ull +#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR1_12_SPECIAL_BASE 0x1000007FFD72CE80ull +#define NIC6_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_12_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR1_13_UNSECURE_DOORBELL0_BASE 0x1000007FFD72D000ull +#define NIC6_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR1_13_UNSECURE_DOORBELL1_BASE 0x1000007FFD72D080ull +#define NIC6_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD72D100ull +#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD72D180ull +#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR1_13_SPECIAL_BASE 0x1000007FFD72DE80ull +#define NIC6_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_13_SPECIAL_SECTION 0x1800 + +#define mmNIC6_UMR1_14_UNSECURE_DOORBELL0_BASE 0x1000007FFD72E000ull +#define NIC6_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC6_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC6_UMR1_14_UNSECURE_DOORBELL1_BASE 0x1000007FFD72E080ull +#define NIC6_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC6_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC6_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD72E100ull +#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC6_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD72E180ull +#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC6_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC6_UMR1_14_SPECIAL_BASE 0x1000007FFD72EE80ull +#define NIC6_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_UMR1_14_SPECIAL_SECTION 0x1180 + +#define mmNIC6_QM_DCCM1_BASE 0x1000007FFD730000ull +#define NIC6_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC6_QM_DCCM1_SECTION 0x8000 + +#define mmNIC6_QM_ARC_AUX1_BASE 0x1000007FFD738000ull +#define NIC6_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC6_QM_ARC_AUX1_SECTION 0xE800 + +#define mmNIC6_QM_ARC_AUX1_SPECIAL_BASE 0x1000007FFD738E80ull +#define NIC6_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 + +#define mmNIC6_QM1_BASE 0x1000007FFD73A000ull +#define NIC6_QM1_MAX_OFFSET 0x1000 +#define NIC6_QM1_SECTION 0x9000 + +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFD73A900ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFD73A908ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFD73A910ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFD73A918ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFD73A920ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFD73A928ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFD73A930ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFD73A938ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFD73A940ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFD73A948ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFD73A950ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFD73A958ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFD73A960ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFD73A968ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFD73A970ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmNIC6_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFD73A978ull +#define NIC6_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC6_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmNIC6_QM1_AXUSER_SECURED_BASE 0x1000007FFD73AB00ull +#define NIC6_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC6_QM1_AXUSER_SECURED_SECTION 0x8000 + +#define mmNIC6_QM1_AXUSER_NONSECURED_BASE 0x1000007FFD73AB80ull +#define NIC6_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC6_QM1_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmNIC6_QM1_DBG_HBW_BASE 0x1000007FFD73AC00ull +#define NIC6_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC6_QM1_DBG_HBW_SECTION 0x8000 + +#define mmNIC6_QM1_DBG_LBW_BASE 0x1000007FFD73AC80ull +#define NIC6_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC6_QM1_DBG_LBW_SECTION 0x1000 + +#define mmNIC6_QM1_CGM_BASE 0x1000007FFD73AD80ull +#define NIC6_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC6_QM1_CGM_SECTION 0x1000 + +#define mmNIC6_QM1_SPECIAL_BASE 0x1000007FFD73AE80ull +#define NIC6_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_QM1_SPECIAL_SECTION 0x4180 + +#define mmNIC6_QPC1_BASE 0x1000007FFD73F000ull +#define NIC6_QPC1_MAX_OFFSET 0x1000 +#define NIC6_QPC1_SECTION 0x7200 + +#define mmNIC6_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x1000007FFD73F720ull +#define NIC6_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x1000007FFD73F728ull +#define NIC6_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x1000007FFD73F730ull +#define NIC6_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x1000007FFD73F738ull +#define NIC6_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x1000007FFD73F740ull +#define NIC6_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x1000007FFD73F748ull +#define NIC6_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x1000007FFD73F750ull +#define NIC6_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x1000007FFD73F758ull +#define NIC6_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x1000007FFD73F760ull +#define NIC6_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x1000007FFD73F768ull +#define NIC6_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x1000007FFD73F770ull +#define NIC6_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x1000007FFD73F778ull +#define NIC6_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x1000007FFD73F780ull +#define NIC6_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x1000007FFD73F788ull +#define NIC6_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x1000007FFD73F790ull +#define NIC6_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x1000007FFD73F798ull +#define NIC6_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x1000007FFD73F7A0ull +#define NIC6_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x1000007FFD73F7A8ull +#define NIC6_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x1000007FFD73F7B0ull +#define NIC6_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x1000007FFD73F7B8ull +#define NIC6_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x1000007FFD73F7C0ull +#define NIC6_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x1000007FFD73F7C8ull +#define NIC6_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x1000007FFD73F7D0ull +#define NIC6_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x1000007FFD73F7D8ull +#define NIC6_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x1000007FFD73F7E0ull +#define NIC6_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x1000007FFD73F7E8ull +#define NIC6_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x1000007FFD73F7F0ull +#define NIC6_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x1000007FFD73F7F8ull +#define NIC6_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x1000007FFD73F800ull +#define NIC6_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x1000007FFD73F808ull +#define NIC6_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x1000007FFD73F810ull +#define NIC6_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC6_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x1000007FFD73F818ull +#define NIC6_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC6_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 + +#define mmNIC6_QPC1_AXUSER_CONG_QUE_BASE 0x1000007FFD73FB80ull +#define NIC6_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC6_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 + +#define mmNIC6_QPC1_AXUSER_RXWQE_BASE 0x1000007FFD73FBE0ull +#define NIC6_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC6_QPC1_AXUSER_RXWQE_SECTION 0x6000 + +#define mmNIC6_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x1000007FFD73FC40ull +#define NIC6_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC6_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 + +#define mmNIC6_QPC1_AXUSER_DB_FIFO_BASE 0x1000007FFD73FCA0ull +#define NIC6_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC6_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 + +#define mmNIC6_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x1000007FFD73FD00ull +#define NIC6_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC6_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 + +#define mmNIC6_QPC1_AXUSER_ERR_FIFO_BASE 0x1000007FFD73FD60ull +#define NIC6_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC6_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 + +#define mmNIC6_QPC1_AXUSER_QPC_RESP_BASE 0x1000007FFD73FDC0ull +#define NIC6_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC6_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 + +#define mmNIC6_QPC1_AXUSER_QPC_REQ_BASE 0x1000007FFD73FE20ull +#define NIC6_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC6_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 + +#define mmNIC6_QPC1_SPECIAL_BASE 0x1000007FFD73FE80ull +#define NIC6_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_QPC1_SPECIAL_SECTION 0x8180 + +#define mmNIC6_TMR_BASE 0x1000007FFD748000ull +#define NIC6_TMR_MAX_OFFSET 0x1000 +#define NIC6_TMR_SECTION 0xD600 + +#define mmNIC6_TMR_AXUSER_TMR_FREE_LIST_BASE 0x1000007FFD748D60ull +#define NIC6_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC6_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 + +#define mmNIC6_TMR_AXUSER_TMR_FIFO_BASE 0x1000007FFD748DC0ull +#define NIC6_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC6_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 + +#define mmNIC6_TMR_AXUSER_TMR_FSM_BASE 0x1000007FFD748E20ull +#define NIC6_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC6_TMR_AXUSER_TMR_FSM_SECTION 0x6000 + +#define mmNIC6_TMR_SPECIAL_BASE 0x1000007FFD748E80ull +#define NIC6_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_TMR_SPECIAL_SECTION 0x1800 + +#define mmNIC6_RXB_CORE_BASE 0x1000007FFD749000ull +#define NIC6_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC6_RXB_CORE_SECTION 0x6100 + +#define mmNIC6_RXB_CORE_SCT_AWUSER_BASE 0x1000007FFD749610ull +#define NIC6_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC6_RXB_CORE_SCT_AWUSER_SECTION 0x8700 + +#define mmNIC6_RXB_CORE_SPECIAL_BASE 0x1000007FFD749E80ull +#define NIC6_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_RXB_CORE_SPECIAL_SECTION 0x1800 + +#define mmNIC6_RXE0_BASE 0x1000007FFD74A000ull +#define NIC6_RXE0_MAX_OFFSET 0x1000 +#define NIC6_RXE0_SECTION 0x9000 + +#define mmNIC6_RXE0_WQE_ARUSER_BASE 0x1000007FFD74A900ull +#define NIC6_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC6_RXE0_WQE_ARUSER_SECTION 0x5800 + +#define mmNIC6_RXE0_SPECIAL_BASE 0x1000007FFD74AE80ull +#define NIC6_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_RXE0_SPECIAL_SECTION 0x1800 + +#define mmNIC6_RXE1_BASE 0x1000007FFD74B000ull +#define NIC6_RXE1_MAX_OFFSET 0x1000 +#define NIC6_RXE1_SECTION 0x9000 + +#define mmNIC6_RXE1_WQE_ARUSER_BASE 0x1000007FFD74B900ull +#define NIC6_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC6_RXE1_WQE_ARUSER_SECTION 0x5800 + +#define mmNIC6_RXE1_SPECIAL_BASE 0x1000007FFD74BE80ull +#define NIC6_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_RXE1_SPECIAL_SECTION 0x1800 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ0_BASE 0x1000007FFD74C000ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ1_BASE 0x1000007FFD74C050ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ2_BASE 0x1000007FFD74C0A0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ3_BASE 0x1000007FFD74C0F0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ4_BASE 0x1000007FFD74C140ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ5_BASE 0x1000007FFD74C190ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ6_BASE 0x1000007FFD74C1E0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ7_BASE 0x1000007FFD74C230ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ8_BASE 0x1000007FFD74C280ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ9_BASE 0x1000007FFD74C2D0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ10_BASE 0x1000007FFD74C320ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ11_BASE 0x1000007FFD74C370ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ12_BASE 0x1000007FFD74C3C0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ13_BASE 0x1000007FFD74C410ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ14_BASE 0x1000007FFD74C460ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ15_BASE 0x1000007FFD74C4B0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ16_BASE 0x1000007FFD74C500ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ17_BASE 0x1000007FFD74C550ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ18_BASE 0x1000007FFD74C5A0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ19_BASE 0x1000007FFD74C5F0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ20_BASE 0x1000007FFD74C640ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ21_BASE 0x1000007FFD74C690ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ22_BASE 0x1000007FFD74C6E0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ23_BASE 0x1000007FFD74C730ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ24_BASE 0x1000007FFD74C780ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ25_BASE 0x1000007FFD74C7D0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ26_BASE 0x1000007FFD74C820ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ27_BASE 0x1000007FFD74C870ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ28_BASE 0x1000007FFD74C8C0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ29_BASE 0x1000007FFD74C910ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ30_BASE 0x1000007FFD74C960ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 + +#define mmNIC6_RXE0_AXUSER_AXUSER_CQ31_BASE 0x1000007FFD74C9B0ull +#define NIC6_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC6_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 + +#define mmNIC6_RXE0_AXUSER_SPECIAL_BASE 0x1000007FFD74CE80ull +#define NIC6_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_RXE0_AXUSER_SPECIAL_SECTION 0x1800 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ0_BASE 0x1000007FFD74D000ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ1_BASE 0x1000007FFD74D050ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ2_BASE 0x1000007FFD74D0A0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ3_BASE 0x1000007FFD74D0F0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ4_BASE 0x1000007FFD74D140ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ5_BASE 0x1000007FFD74D190ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ6_BASE 0x1000007FFD74D1E0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ7_BASE 0x1000007FFD74D230ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ8_BASE 0x1000007FFD74D280ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ9_BASE 0x1000007FFD74D2D0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ10_BASE 0x1000007FFD74D320ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ11_BASE 0x1000007FFD74D370ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ12_BASE 0x1000007FFD74D3C0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ13_BASE 0x1000007FFD74D410ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ14_BASE 0x1000007FFD74D460ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ15_BASE 0x1000007FFD74D4B0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ16_BASE 0x1000007FFD74D500ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ17_BASE 0x1000007FFD74D550ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ18_BASE 0x1000007FFD74D5A0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ19_BASE 0x1000007FFD74D5F0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ20_BASE 0x1000007FFD74D640ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ21_BASE 0x1000007FFD74D690ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ22_BASE 0x1000007FFD74D6E0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ23_BASE 0x1000007FFD74D730ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ24_BASE 0x1000007FFD74D780ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ25_BASE 0x1000007FFD74D7D0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ26_BASE 0x1000007FFD74D820ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ27_BASE 0x1000007FFD74D870ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ28_BASE 0x1000007FFD74D8C0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ29_BASE 0x1000007FFD74D910ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ30_BASE 0x1000007FFD74D960ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 + +#define mmNIC6_RXE1_AXUSER_AXUSER_CQ31_BASE 0x1000007FFD74D9B0ull +#define NIC6_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC6_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 + +#define mmNIC6_RXE1_AXUSER_SPECIAL_BASE 0x1000007FFD74DE80ull +#define NIC6_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_RXE1_AXUSER_SPECIAL_SECTION 0x2180 + +#define mmNIC6_TXS0_BASE 0x1000007FFD750000ull +#define NIC6_TXS0_MAX_OFFSET 0x1000 +#define NIC6_TXS0_SECTION 0xE800 + +#define mmNIC6_TXS0_SPECIAL_BASE 0x1000007FFD750E80ull +#define NIC6_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_TXS0_SPECIAL_SECTION 0x1800 + +#define mmNIC6_TXS1_BASE 0x1000007FFD751000ull +#define NIC6_TXS1_MAX_OFFSET 0x1000 +#define NIC6_TXS1_SECTION 0xE800 + +#define mmNIC6_TXS1_SPECIAL_BASE 0x1000007FFD751E80ull +#define NIC6_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_TXS1_SPECIAL_SECTION 0x1800 + +#define mmNIC6_TXE0_BASE 0x1000007FFD752000ull +#define NIC6_TXE0_MAX_OFFSET 0x1000 +#define NIC6_TXE0_SECTION 0xE800 + +#define mmNIC6_TXE0_SPECIAL_BASE 0x1000007FFD752E80ull +#define NIC6_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_TXE0_SPECIAL_SECTION 0x1800 + +#define mmNIC6_TXE1_BASE 0x1000007FFD753000ull +#define NIC6_TXE1_MAX_OFFSET 0x1000 +#define NIC6_TXE1_SECTION 0xE800 + +#define mmNIC6_TXE1_SPECIAL_BASE 0x1000007FFD753E80ull +#define NIC6_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_TXE1_SPECIAL_SECTION 0x1800 + +#define mmNIC6_TXB_BASE 0x1000007FFD754000ull +#define NIC6_TXB_MAX_OFFSET 0x1000 +#define NIC6_TXB_SECTION 0xE800 + +#define mmNIC6_TXB_SPECIAL_BASE 0x1000007FFD754E80ull +#define NIC6_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_TXB_SPECIAL_SECTION 0x1800 + +#define mmNIC6_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFD755000ull +#define NIC6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmNIC6_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFD755200ull +#define NIC6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmNIC6_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFD755400ull +#define NIC6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmNIC6_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFD755600ull +#define NIC6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmNIC6_MSTR_IF_E2E_CRDT_BASE 0x1000007FFD755800ull +#define NIC6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC6_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmNIC6_MSTR_IF_AXUSER_BASE 0x1000007FFD755A80ull +#define NIC6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC6_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmNIC6_MSTR_IF_DBG_HBW_BASE 0x1000007FFD755B00ull +#define NIC6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC6_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmNIC6_MSTR_IF_DBG_LBW_BASE 0x1000007FFD755B80ull +#define NIC6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC6_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmNIC6_MSTR_IF_CORE_HBW_BASE 0x1000007FFD755C00ull +#define NIC6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC6_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmNIC6_MSTR_IF_CORE_LBW_BASE 0x1000007FFD755D80ull +#define NIC6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC6_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmNIC6_MSTR_IF_SPECIAL_BASE 0x1000007FFD755E80ull +#define NIC6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmNIC6_TX_AXUSER_BASE 0x1000007FFD756000ull +#define NIC6_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC6_TX_AXUSER_SECTION 0x2000 + +#define mmNIC6_SERDES0_BASE 0x1000007FFD758000ull +#define NIC6_SERDES0_MAX_OFFSET 0x3E40 +#define NIC6_SERDES0_SECTION 0x4000 + +#define mmNIC6_SERDES1_BASE 0x1000007FFD75C000ull +#define NIC6_SERDES1_MAX_OFFSET 0x3E40 +#define NIC6_SERDES1_SECTION 0x4000 + +#define mmNIC6_PHY_BASE 0x1000007FFD760000ull +#define NIC6_PHY_MAX_OFFSET 0x1000 +#define NIC6_PHY_SECTION 0xE800 + +#define mmNIC6_PHY_SPECIAL_BASE 0x1000007FFD760E80ull +#define NIC6_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC6_PHY_SPECIAL_SECTION 0x7180 + +#define mmPRT6_MAC_AUX_BASE 0x1000007FFD768000ull +#define PRT6_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT6_MAC_AUX_SECTION 0xE800 + +#define mmPRT6_MAC_AUX_SPECIAL_BASE 0x1000007FFD768E80ull +#define PRT6_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT6_MAC_AUX_SPECIAL_SECTION 0x1800 + +#define mmPRT6_MAC_CORE_BASE 0x1000007FFD769000ull +#define PRT6_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT6_MAC_CORE_SECTION 0xE800 + +#define mmPRT6_MAC_CORE_SPECIAL_BASE 0x1000007FFD769E80ull +#define PRT6_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT6_MAC_CORE_SPECIAL_SECTION 0x1800 + +#define mmNIC6_MAC_RS_FEC_BASE 0x1000007FFD76A000ull +#define NIC6_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC6_MAC_RS_FEC_SECTION 0x1000 + +#define mmNIC6_MAC_GLOB_STAT_NIC_MAC_STAT_BASE 0x1000007FFD76B000ull +#define NIC6_MAC_GLOB_STAT_NIC_MAC_STAT_MAX_OFFSET 0x4D00 +#define NIC6_MAC_GLOB_STAT_NIC_MAC_STAT_SECTION 0x8000 + +#define mmNIC6_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_BASE 0x1000007FFD76B800ull +#define NIC6_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC6_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_SECTION 0x8000 + +#define mmNIC6_MAC_CH0_MAC_PCS_BASE 0x1000007FFD76C000ull +#define NIC6_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC6_MAC_CH0_MAC_PCS_SECTION 0x4000 + +#define mmNIC6_MAC_CH0_MAC_128_BASE 0x1000007FFD76C400ull +#define NIC6_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC6_MAC_CH0_MAC_128_SECTION 0x4000 + +#define mmNIC6_MAC_CH0_MAC_AN_BASE 0x1000007FFD76C800ull +#define NIC6_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC6_MAC_CH0_MAC_AN_SECTION 0x8000 + +#define mmNIC6_MAC_CH1_MAC_PCS_BASE 0x1000007FFD76D000ull +#define NIC6_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC6_MAC_CH1_MAC_PCS_SECTION 0x4000 + +#define mmNIC6_MAC_CH1_MAC_128_BASE 0x1000007FFD76D400ull +#define NIC6_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC6_MAC_CH1_MAC_128_SECTION 0x4000 + +#define mmNIC6_MAC_CH1_MAC_AN_BASE 0x1000007FFD76D800ull +#define NIC6_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC6_MAC_CH1_MAC_AN_SECTION 0x8000 + +#define mmNIC6_MAC_CH2_MAC_PCS_BASE 0x1000007FFD76E000ull +#define NIC6_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC6_MAC_CH2_MAC_PCS_SECTION 0x4000 + +#define mmNIC6_MAC_CH2_MAC_128_BASE 0x1000007FFD76E400ull +#define NIC6_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC6_MAC_CH2_MAC_128_SECTION 0x4000 + +#define mmNIC6_MAC_CH2_MAC_AN_BASE 0x1000007FFD76E800ull +#define NIC6_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC6_MAC_CH2_MAC_AN_SECTION 0x8000 + +#define mmNIC6_MAC_CH3_MAC_PCS_BASE 0x1000007FFD76F000ull +#define NIC6_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC6_MAC_CH3_MAC_PCS_SECTION 0x4000 + +#define mmNIC6_MAC_CH3_MAC_128_BASE 0x1000007FFD76F400ull +#define NIC6_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC6_MAC_CH3_MAC_128_SECTION 0x4000 + +#define mmNIC6_MAC_CH3_MAC_AN_BASE 0x1000007FFD76F800ull +#define NIC6_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC6_MAC_CH3_MAC_AN_SECTION 0x10800 + +#define mmNIC7_UMR0_0_UNSECURE_DOORBELL0_BASE 0x1000007FFD780000ull +#define NIC7_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR0_0_UNSECURE_DOORBELL1_BASE 0x1000007FFD780080ull +#define NIC7_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD780100ull +#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD780180ull +#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR0_0_SPECIAL_BASE 0x1000007FFD780E80ull +#define NIC7_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_0_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR0_1_UNSECURE_DOORBELL0_BASE 0x1000007FFD781000ull +#define NIC7_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR0_1_UNSECURE_DOORBELL1_BASE 0x1000007FFD781080ull +#define NIC7_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD781100ull +#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD781180ull +#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR0_1_SPECIAL_BASE 0x1000007FFD781E80ull +#define NIC7_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_1_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR0_2_UNSECURE_DOORBELL0_BASE 0x1000007FFD782000ull +#define NIC7_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR0_2_UNSECURE_DOORBELL1_BASE 0x1000007FFD782080ull +#define NIC7_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD782100ull +#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD782180ull +#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR0_2_SPECIAL_BASE 0x1000007FFD782E80ull +#define NIC7_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_2_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR0_3_UNSECURE_DOORBELL0_BASE 0x1000007FFD783000ull +#define NIC7_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR0_3_UNSECURE_DOORBELL1_BASE 0x1000007FFD783080ull +#define NIC7_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD783100ull +#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD783180ull +#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR0_3_SPECIAL_BASE 0x1000007FFD783E80ull +#define NIC7_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_3_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR0_4_UNSECURE_DOORBELL0_BASE 0x1000007FFD784000ull +#define NIC7_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR0_4_UNSECURE_DOORBELL1_BASE 0x1000007FFD784080ull +#define NIC7_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD784100ull +#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD784180ull +#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR0_4_SPECIAL_BASE 0x1000007FFD784E80ull +#define NIC7_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_4_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR0_5_UNSECURE_DOORBELL0_BASE 0x1000007FFD785000ull +#define NIC7_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR0_5_UNSECURE_DOORBELL1_BASE 0x1000007FFD785080ull +#define NIC7_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD785100ull +#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD785180ull +#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR0_5_SPECIAL_BASE 0x1000007FFD785E80ull +#define NIC7_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_5_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR0_6_UNSECURE_DOORBELL0_BASE 0x1000007FFD786000ull +#define NIC7_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR0_6_UNSECURE_DOORBELL1_BASE 0x1000007FFD786080ull +#define NIC7_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD786100ull +#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD786180ull +#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR0_6_SPECIAL_BASE 0x1000007FFD786E80ull +#define NIC7_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_6_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR0_7_UNSECURE_DOORBELL0_BASE 0x1000007FFD787000ull +#define NIC7_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR0_7_UNSECURE_DOORBELL1_BASE 0x1000007FFD787080ull +#define NIC7_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD787100ull +#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD787180ull +#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR0_7_SPECIAL_BASE 0x1000007FFD787E80ull +#define NIC7_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_7_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR0_8_UNSECURE_DOORBELL0_BASE 0x1000007FFD788000ull +#define NIC7_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR0_8_UNSECURE_DOORBELL1_BASE 0x1000007FFD788080ull +#define NIC7_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD788100ull +#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD788180ull +#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR0_8_SPECIAL_BASE 0x1000007FFD788E80ull +#define NIC7_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_8_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR0_9_UNSECURE_DOORBELL0_BASE 0x1000007FFD789000ull +#define NIC7_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR0_9_UNSECURE_DOORBELL1_BASE 0x1000007FFD789080ull +#define NIC7_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD789100ull +#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD789180ull +#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR0_9_SPECIAL_BASE 0x1000007FFD789E80ull +#define NIC7_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_9_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR0_10_UNSECURE_DOORBELL0_BASE 0x1000007FFD78A000ull +#define NIC7_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR0_10_UNSECURE_DOORBELL1_BASE 0x1000007FFD78A080ull +#define NIC7_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD78A100ull +#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD78A180ull +#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR0_10_SPECIAL_BASE 0x1000007FFD78AE80ull +#define NIC7_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_10_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR0_11_UNSECURE_DOORBELL0_BASE 0x1000007FFD78B000ull +#define NIC7_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR0_11_UNSECURE_DOORBELL1_BASE 0x1000007FFD78B080ull +#define NIC7_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD78B100ull +#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD78B180ull +#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR0_11_SPECIAL_BASE 0x1000007FFD78BE80ull +#define NIC7_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_11_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR0_12_UNSECURE_DOORBELL0_BASE 0x1000007FFD78C000ull +#define NIC7_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR0_12_UNSECURE_DOORBELL1_BASE 0x1000007FFD78C080ull +#define NIC7_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD78C100ull +#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD78C180ull +#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR0_12_SPECIAL_BASE 0x1000007FFD78CE80ull +#define NIC7_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_12_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR0_13_UNSECURE_DOORBELL0_BASE 0x1000007FFD78D000ull +#define NIC7_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR0_13_UNSECURE_DOORBELL1_BASE 0x1000007FFD78D080ull +#define NIC7_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD78D100ull +#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD78D180ull +#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR0_13_SPECIAL_BASE 0x1000007FFD78DE80ull +#define NIC7_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_13_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR0_14_UNSECURE_DOORBELL0_BASE 0x1000007FFD78E000ull +#define NIC7_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR0_14_UNSECURE_DOORBELL1_BASE 0x1000007FFD78E080ull +#define NIC7_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD78E100ull +#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD78E180ull +#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR0_14_SPECIAL_BASE 0x1000007FFD78EE80ull +#define NIC7_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR0_14_SPECIAL_SECTION 0x1180 + +#define mmNIC7_QM_DCCM0_BASE 0x1000007FFD790000ull +#define NIC7_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC7_QM_DCCM0_SECTION 0x8000 + +#define mmNIC7_QM_ARC_AUX0_BASE 0x1000007FFD798000ull +#define NIC7_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC7_QM_ARC_AUX0_SECTION 0xE800 + +#define mmNIC7_QM_ARC_AUX0_SPECIAL_BASE 0x1000007FFD798E80ull +#define NIC7_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 + +#define mmNIC7_QM0_BASE 0x1000007FFD79A000ull +#define NIC7_QM0_MAX_OFFSET 0x1000 +#define NIC7_QM0_SECTION 0x9000 + +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFD79A900ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFD79A908ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFD79A910ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFD79A918ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFD79A920ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFD79A928ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFD79A930ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFD79A938ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFD79A940ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFD79A948ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFD79A950ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFD79A958ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFD79A960ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFD79A968ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFD79A970ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmNIC7_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFD79A978ull +#define NIC7_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC7_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmNIC7_QM0_AXUSER_SECURED_BASE 0x1000007FFD79AB00ull +#define NIC7_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC7_QM0_AXUSER_SECURED_SECTION 0x8000 + +#define mmNIC7_QM0_AXUSER_NONSECURED_BASE 0x1000007FFD79AB80ull +#define NIC7_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC7_QM0_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmNIC7_QM0_DBG_HBW_BASE 0x1000007FFD79AC00ull +#define NIC7_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC7_QM0_DBG_HBW_SECTION 0x8000 + +#define mmNIC7_QM0_DBG_LBW_BASE 0x1000007FFD79AC80ull +#define NIC7_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC7_QM0_DBG_LBW_SECTION 0x1000 + +#define mmNIC7_QM0_CGM_BASE 0x1000007FFD79AD80ull +#define NIC7_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC7_QM0_CGM_SECTION 0x1000 + +#define mmNIC7_QM0_SPECIAL_BASE 0x1000007FFD79AE80ull +#define NIC7_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_QM0_SPECIAL_SECTION 0x4180 + +#define mmNIC7_QPC0_BASE 0x1000007FFD79F000ull +#define NIC7_QPC0_MAX_OFFSET 0x1000 +#define NIC7_QPC0_SECTION 0x7200 + +#define mmNIC7_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x1000007FFD79F720ull +#define NIC7_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x1000007FFD79F728ull +#define NIC7_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x1000007FFD79F730ull +#define NIC7_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x1000007FFD79F738ull +#define NIC7_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x1000007FFD79F740ull +#define NIC7_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x1000007FFD79F748ull +#define NIC7_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x1000007FFD79F750ull +#define NIC7_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x1000007FFD79F758ull +#define NIC7_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x1000007FFD79F760ull +#define NIC7_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x1000007FFD79F768ull +#define NIC7_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x1000007FFD79F770ull +#define NIC7_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x1000007FFD79F778ull +#define NIC7_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x1000007FFD79F780ull +#define NIC7_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x1000007FFD79F788ull +#define NIC7_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x1000007FFD79F790ull +#define NIC7_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x1000007FFD79F798ull +#define NIC7_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x1000007FFD79F7A0ull +#define NIC7_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x1000007FFD79F7A8ull +#define NIC7_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x1000007FFD79F7B0ull +#define NIC7_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x1000007FFD79F7B8ull +#define NIC7_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x1000007FFD79F7C0ull +#define NIC7_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x1000007FFD79F7C8ull +#define NIC7_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x1000007FFD79F7D0ull +#define NIC7_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x1000007FFD79F7D8ull +#define NIC7_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x1000007FFD79F7E0ull +#define NIC7_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x1000007FFD79F7E8ull +#define NIC7_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x1000007FFD79F7F0ull +#define NIC7_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x1000007FFD79F7F8ull +#define NIC7_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x1000007FFD79F800ull +#define NIC7_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x1000007FFD79F808ull +#define NIC7_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x1000007FFD79F810ull +#define NIC7_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x1000007FFD79F818ull +#define NIC7_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 + +#define mmNIC7_QPC0_AXUSER_CONG_QUE_BASE 0x1000007FFD79FB80ull +#define NIC7_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC7_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 + +#define mmNIC7_QPC0_AXUSER_RXWQE_BASE 0x1000007FFD79FBE0ull +#define NIC7_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC7_QPC0_AXUSER_RXWQE_SECTION 0x6000 + +#define mmNIC7_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x1000007FFD79FC40ull +#define NIC7_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC7_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 + +#define mmNIC7_QPC0_AXUSER_DB_FIFO_BASE 0x1000007FFD79FCA0ull +#define NIC7_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC7_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 + +#define mmNIC7_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x1000007FFD79FD00ull +#define NIC7_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC7_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 + +#define mmNIC7_QPC0_AXUSER_ERR_FIFO_BASE 0x1000007FFD79FD60ull +#define NIC7_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC7_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 + +#define mmNIC7_QPC0_AXUSER_QPC_RESP_BASE 0x1000007FFD79FDC0ull +#define NIC7_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC7_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 + +#define mmNIC7_QPC0_AXUSER_QPC_REQ_BASE 0x1000007FFD79FE20ull +#define NIC7_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC7_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 + +#define mmNIC7_QPC0_SPECIAL_BASE 0x1000007FFD79FE80ull +#define NIC7_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_QPC0_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR1_0_UNSECURE_DOORBELL0_BASE 0x1000007FFD7A0000ull +#define NIC7_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR1_0_UNSECURE_DOORBELL1_BASE 0x1000007FFD7A0080ull +#define NIC7_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD7A0100ull +#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD7A0180ull +#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR1_0_SPECIAL_BASE 0x1000007FFD7A0E80ull +#define NIC7_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_0_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR1_1_UNSECURE_DOORBELL0_BASE 0x1000007FFD7A1000ull +#define NIC7_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR1_1_UNSECURE_DOORBELL1_BASE 0x1000007FFD7A1080ull +#define NIC7_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD7A1100ull +#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD7A1180ull +#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR1_1_SPECIAL_BASE 0x1000007FFD7A1E80ull +#define NIC7_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_1_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR1_2_UNSECURE_DOORBELL0_BASE 0x1000007FFD7A2000ull +#define NIC7_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR1_2_UNSECURE_DOORBELL1_BASE 0x1000007FFD7A2080ull +#define NIC7_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD7A2100ull +#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD7A2180ull +#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR1_2_SPECIAL_BASE 0x1000007FFD7A2E80ull +#define NIC7_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_2_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR1_3_UNSECURE_DOORBELL0_BASE 0x1000007FFD7A3000ull +#define NIC7_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR1_3_UNSECURE_DOORBELL1_BASE 0x1000007FFD7A3080ull +#define NIC7_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD7A3100ull +#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD7A3180ull +#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR1_3_SPECIAL_BASE 0x1000007FFD7A3E80ull +#define NIC7_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_3_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR1_4_UNSECURE_DOORBELL0_BASE 0x1000007FFD7A4000ull +#define NIC7_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR1_4_UNSECURE_DOORBELL1_BASE 0x1000007FFD7A4080ull +#define NIC7_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD7A4100ull +#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD7A4180ull +#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR1_4_SPECIAL_BASE 0x1000007FFD7A4E80ull +#define NIC7_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_4_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR1_5_UNSECURE_DOORBELL0_BASE 0x1000007FFD7A5000ull +#define NIC7_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR1_5_UNSECURE_DOORBELL1_BASE 0x1000007FFD7A5080ull +#define NIC7_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD7A5100ull +#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD7A5180ull +#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR1_5_SPECIAL_BASE 0x1000007FFD7A5E80ull +#define NIC7_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_5_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR1_6_UNSECURE_DOORBELL0_BASE 0x1000007FFD7A6000ull +#define NIC7_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR1_6_UNSECURE_DOORBELL1_BASE 0x1000007FFD7A6080ull +#define NIC7_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD7A6100ull +#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD7A6180ull +#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR1_6_SPECIAL_BASE 0x1000007FFD7A6E80ull +#define NIC7_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_6_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR1_7_UNSECURE_DOORBELL0_BASE 0x1000007FFD7A7000ull +#define NIC7_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR1_7_UNSECURE_DOORBELL1_BASE 0x1000007FFD7A7080ull +#define NIC7_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD7A7100ull +#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD7A7180ull +#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR1_7_SPECIAL_BASE 0x1000007FFD7A7E80ull +#define NIC7_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_7_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR1_8_UNSECURE_DOORBELL0_BASE 0x1000007FFD7A8000ull +#define NIC7_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR1_8_UNSECURE_DOORBELL1_BASE 0x1000007FFD7A8080ull +#define NIC7_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD7A8100ull +#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD7A8180ull +#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR1_8_SPECIAL_BASE 0x1000007FFD7A8E80ull +#define NIC7_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_8_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR1_9_UNSECURE_DOORBELL0_BASE 0x1000007FFD7A9000ull +#define NIC7_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR1_9_UNSECURE_DOORBELL1_BASE 0x1000007FFD7A9080ull +#define NIC7_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD7A9100ull +#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD7A9180ull +#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR1_9_SPECIAL_BASE 0x1000007FFD7A9E80ull +#define NIC7_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_9_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR1_10_UNSECURE_DOORBELL0_BASE 0x1000007FFD7AA000ull +#define NIC7_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR1_10_UNSECURE_DOORBELL1_BASE 0x1000007FFD7AA080ull +#define NIC7_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD7AA100ull +#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD7AA180ull +#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR1_10_SPECIAL_BASE 0x1000007FFD7AAE80ull +#define NIC7_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_10_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR1_11_UNSECURE_DOORBELL0_BASE 0x1000007FFD7AB000ull +#define NIC7_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR1_11_UNSECURE_DOORBELL1_BASE 0x1000007FFD7AB080ull +#define NIC7_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD7AB100ull +#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD7AB180ull +#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR1_11_SPECIAL_BASE 0x1000007FFD7ABE80ull +#define NIC7_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_11_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR1_12_UNSECURE_DOORBELL0_BASE 0x1000007FFD7AC000ull +#define NIC7_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR1_12_UNSECURE_DOORBELL1_BASE 0x1000007FFD7AC080ull +#define NIC7_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD7AC100ull +#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD7AC180ull +#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR1_12_SPECIAL_BASE 0x1000007FFD7ACE80ull +#define NIC7_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_12_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR1_13_UNSECURE_DOORBELL0_BASE 0x1000007FFD7AD000ull +#define NIC7_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR1_13_UNSECURE_DOORBELL1_BASE 0x1000007FFD7AD080ull +#define NIC7_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD7AD100ull +#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD7AD180ull +#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR1_13_SPECIAL_BASE 0x1000007FFD7ADE80ull +#define NIC7_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_13_SPECIAL_SECTION 0x1800 + +#define mmNIC7_UMR1_14_UNSECURE_DOORBELL0_BASE 0x1000007FFD7AE000ull +#define NIC7_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC7_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC7_UMR1_14_UNSECURE_DOORBELL1_BASE 0x1000007FFD7AE080ull +#define NIC7_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC7_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC7_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD7AE100ull +#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC7_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD7AE180ull +#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC7_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC7_UMR1_14_SPECIAL_BASE 0x1000007FFD7AEE80ull +#define NIC7_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_UMR1_14_SPECIAL_SECTION 0x1180 + +#define mmNIC7_QM_DCCM1_BASE 0x1000007FFD7B0000ull +#define NIC7_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC7_QM_DCCM1_SECTION 0x8000 + +#define mmNIC7_QM_ARC_AUX1_BASE 0x1000007FFD7B8000ull +#define NIC7_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC7_QM_ARC_AUX1_SECTION 0xE800 + +#define mmNIC7_QM_ARC_AUX1_SPECIAL_BASE 0x1000007FFD7B8E80ull +#define NIC7_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 + +#define mmNIC7_QM1_BASE 0x1000007FFD7BA000ull +#define NIC7_QM1_MAX_OFFSET 0x1000 +#define NIC7_QM1_SECTION 0x9000 + +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFD7BA900ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFD7BA908ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFD7BA910ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFD7BA918ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFD7BA920ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFD7BA928ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFD7BA930ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFD7BA938ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFD7BA940ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFD7BA948ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFD7BA950ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFD7BA958ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFD7BA960ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFD7BA968ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFD7BA970ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmNIC7_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFD7BA978ull +#define NIC7_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC7_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmNIC7_QM1_AXUSER_SECURED_BASE 0x1000007FFD7BAB00ull +#define NIC7_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC7_QM1_AXUSER_SECURED_SECTION 0x8000 + +#define mmNIC7_QM1_AXUSER_NONSECURED_BASE 0x1000007FFD7BAB80ull +#define NIC7_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC7_QM1_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmNIC7_QM1_DBG_HBW_BASE 0x1000007FFD7BAC00ull +#define NIC7_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC7_QM1_DBG_HBW_SECTION 0x8000 + +#define mmNIC7_QM1_DBG_LBW_BASE 0x1000007FFD7BAC80ull +#define NIC7_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC7_QM1_DBG_LBW_SECTION 0x1000 + +#define mmNIC7_QM1_CGM_BASE 0x1000007FFD7BAD80ull +#define NIC7_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC7_QM1_CGM_SECTION 0x1000 + +#define mmNIC7_QM1_SPECIAL_BASE 0x1000007FFD7BAE80ull +#define NIC7_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_QM1_SPECIAL_SECTION 0x4180 + +#define mmNIC7_QPC1_BASE 0x1000007FFD7BF000ull +#define NIC7_QPC1_MAX_OFFSET 0x1000 +#define NIC7_QPC1_SECTION 0x7200 + +#define mmNIC7_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x1000007FFD7BF720ull +#define NIC7_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x1000007FFD7BF728ull +#define NIC7_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x1000007FFD7BF730ull +#define NIC7_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x1000007FFD7BF738ull +#define NIC7_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x1000007FFD7BF740ull +#define NIC7_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x1000007FFD7BF748ull +#define NIC7_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x1000007FFD7BF750ull +#define NIC7_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x1000007FFD7BF758ull +#define NIC7_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x1000007FFD7BF760ull +#define NIC7_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x1000007FFD7BF768ull +#define NIC7_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x1000007FFD7BF770ull +#define NIC7_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x1000007FFD7BF778ull +#define NIC7_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x1000007FFD7BF780ull +#define NIC7_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x1000007FFD7BF788ull +#define NIC7_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x1000007FFD7BF790ull +#define NIC7_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x1000007FFD7BF798ull +#define NIC7_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x1000007FFD7BF7A0ull +#define NIC7_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x1000007FFD7BF7A8ull +#define NIC7_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x1000007FFD7BF7B0ull +#define NIC7_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x1000007FFD7BF7B8ull +#define NIC7_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x1000007FFD7BF7C0ull +#define NIC7_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x1000007FFD7BF7C8ull +#define NIC7_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x1000007FFD7BF7D0ull +#define NIC7_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x1000007FFD7BF7D8ull +#define NIC7_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x1000007FFD7BF7E0ull +#define NIC7_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x1000007FFD7BF7E8ull +#define NIC7_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x1000007FFD7BF7F0ull +#define NIC7_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x1000007FFD7BF7F8ull +#define NIC7_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x1000007FFD7BF800ull +#define NIC7_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x1000007FFD7BF808ull +#define NIC7_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x1000007FFD7BF810ull +#define NIC7_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC7_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x1000007FFD7BF818ull +#define NIC7_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC7_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 + +#define mmNIC7_QPC1_AXUSER_CONG_QUE_BASE 0x1000007FFD7BFB80ull +#define NIC7_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC7_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 + +#define mmNIC7_QPC1_AXUSER_RXWQE_BASE 0x1000007FFD7BFBE0ull +#define NIC7_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC7_QPC1_AXUSER_RXWQE_SECTION 0x6000 + +#define mmNIC7_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x1000007FFD7BFC40ull +#define NIC7_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC7_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 + +#define mmNIC7_QPC1_AXUSER_DB_FIFO_BASE 0x1000007FFD7BFCA0ull +#define NIC7_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC7_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 + +#define mmNIC7_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x1000007FFD7BFD00ull +#define NIC7_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC7_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 + +#define mmNIC7_QPC1_AXUSER_ERR_FIFO_BASE 0x1000007FFD7BFD60ull +#define NIC7_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC7_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 + +#define mmNIC7_QPC1_AXUSER_QPC_RESP_BASE 0x1000007FFD7BFDC0ull +#define NIC7_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC7_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 + +#define mmNIC7_QPC1_AXUSER_QPC_REQ_BASE 0x1000007FFD7BFE20ull +#define NIC7_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC7_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 + +#define mmNIC7_QPC1_SPECIAL_BASE 0x1000007FFD7BFE80ull +#define NIC7_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_QPC1_SPECIAL_SECTION 0x8180 + +#define mmNIC7_TMR_BASE 0x1000007FFD7C8000ull +#define NIC7_TMR_MAX_OFFSET 0x1000 +#define NIC7_TMR_SECTION 0xD600 + +#define mmNIC7_TMR_AXUSER_TMR_FREE_LIST_BASE 0x1000007FFD7C8D60ull +#define NIC7_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC7_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 + +#define mmNIC7_TMR_AXUSER_TMR_FIFO_BASE 0x1000007FFD7C8DC0ull +#define NIC7_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC7_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 + +#define mmNIC7_TMR_AXUSER_TMR_FSM_BASE 0x1000007FFD7C8E20ull +#define NIC7_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC7_TMR_AXUSER_TMR_FSM_SECTION 0x6000 + +#define mmNIC7_TMR_SPECIAL_BASE 0x1000007FFD7C8E80ull +#define NIC7_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_TMR_SPECIAL_SECTION 0x1800 + +#define mmNIC7_RXB_CORE_BASE 0x1000007FFD7C9000ull +#define NIC7_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC7_RXB_CORE_SECTION 0x6100 + +#define mmNIC7_RXB_CORE_SCT_AWUSER_BASE 0x1000007FFD7C9610ull +#define NIC7_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC7_RXB_CORE_SCT_AWUSER_SECTION 0x8700 + +#define mmNIC7_RXB_CORE_SPECIAL_BASE 0x1000007FFD7C9E80ull +#define NIC7_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_RXB_CORE_SPECIAL_SECTION 0x1800 + +#define mmNIC7_RXE0_BASE 0x1000007FFD7CA000ull +#define NIC7_RXE0_MAX_OFFSET 0x1000 +#define NIC7_RXE0_SECTION 0x9000 + +#define mmNIC7_RXE0_WQE_ARUSER_BASE 0x1000007FFD7CA900ull +#define NIC7_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC7_RXE0_WQE_ARUSER_SECTION 0x5800 + +#define mmNIC7_RXE0_SPECIAL_BASE 0x1000007FFD7CAE80ull +#define NIC7_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_RXE0_SPECIAL_SECTION 0x1800 + +#define mmNIC7_RXE1_BASE 0x1000007FFD7CB000ull +#define NIC7_RXE1_MAX_OFFSET 0x1000 +#define NIC7_RXE1_SECTION 0x9000 + +#define mmNIC7_RXE1_WQE_ARUSER_BASE 0x1000007FFD7CB900ull +#define NIC7_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC7_RXE1_WQE_ARUSER_SECTION 0x5800 + +#define mmNIC7_RXE1_SPECIAL_BASE 0x1000007FFD7CBE80ull +#define NIC7_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_RXE1_SPECIAL_SECTION 0x1800 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ0_BASE 0x1000007FFD7CC000ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ1_BASE 0x1000007FFD7CC050ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ2_BASE 0x1000007FFD7CC0A0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ3_BASE 0x1000007FFD7CC0F0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ4_BASE 0x1000007FFD7CC140ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ5_BASE 0x1000007FFD7CC190ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ6_BASE 0x1000007FFD7CC1E0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ7_BASE 0x1000007FFD7CC230ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ8_BASE 0x1000007FFD7CC280ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ9_BASE 0x1000007FFD7CC2D0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ10_BASE 0x1000007FFD7CC320ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ11_BASE 0x1000007FFD7CC370ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ12_BASE 0x1000007FFD7CC3C0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ13_BASE 0x1000007FFD7CC410ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ14_BASE 0x1000007FFD7CC460ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ15_BASE 0x1000007FFD7CC4B0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ16_BASE 0x1000007FFD7CC500ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ17_BASE 0x1000007FFD7CC550ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ18_BASE 0x1000007FFD7CC5A0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ19_BASE 0x1000007FFD7CC5F0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ20_BASE 0x1000007FFD7CC640ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ21_BASE 0x1000007FFD7CC690ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ22_BASE 0x1000007FFD7CC6E0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ23_BASE 0x1000007FFD7CC730ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ24_BASE 0x1000007FFD7CC780ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ25_BASE 0x1000007FFD7CC7D0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ26_BASE 0x1000007FFD7CC820ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ27_BASE 0x1000007FFD7CC870ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ28_BASE 0x1000007FFD7CC8C0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ29_BASE 0x1000007FFD7CC910ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ30_BASE 0x1000007FFD7CC960ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 + +#define mmNIC7_RXE0_AXUSER_AXUSER_CQ31_BASE 0x1000007FFD7CC9B0ull +#define NIC7_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC7_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 + +#define mmNIC7_RXE0_AXUSER_SPECIAL_BASE 0x1000007FFD7CCE80ull +#define NIC7_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_RXE0_AXUSER_SPECIAL_SECTION 0x1800 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ0_BASE 0x1000007FFD7CD000ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ1_BASE 0x1000007FFD7CD050ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ2_BASE 0x1000007FFD7CD0A0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ3_BASE 0x1000007FFD7CD0F0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ4_BASE 0x1000007FFD7CD140ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ5_BASE 0x1000007FFD7CD190ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ6_BASE 0x1000007FFD7CD1E0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ7_BASE 0x1000007FFD7CD230ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ8_BASE 0x1000007FFD7CD280ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ9_BASE 0x1000007FFD7CD2D0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ10_BASE 0x1000007FFD7CD320ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ11_BASE 0x1000007FFD7CD370ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ12_BASE 0x1000007FFD7CD3C0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ13_BASE 0x1000007FFD7CD410ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ14_BASE 0x1000007FFD7CD460ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ15_BASE 0x1000007FFD7CD4B0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ16_BASE 0x1000007FFD7CD500ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ17_BASE 0x1000007FFD7CD550ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ18_BASE 0x1000007FFD7CD5A0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ19_BASE 0x1000007FFD7CD5F0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ20_BASE 0x1000007FFD7CD640ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ21_BASE 0x1000007FFD7CD690ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ22_BASE 0x1000007FFD7CD6E0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ23_BASE 0x1000007FFD7CD730ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ24_BASE 0x1000007FFD7CD780ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ25_BASE 0x1000007FFD7CD7D0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ26_BASE 0x1000007FFD7CD820ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ27_BASE 0x1000007FFD7CD870ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ28_BASE 0x1000007FFD7CD8C0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ29_BASE 0x1000007FFD7CD910ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ30_BASE 0x1000007FFD7CD960ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 + +#define mmNIC7_RXE1_AXUSER_AXUSER_CQ31_BASE 0x1000007FFD7CD9B0ull +#define NIC7_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC7_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 + +#define mmNIC7_RXE1_AXUSER_SPECIAL_BASE 0x1000007FFD7CDE80ull +#define NIC7_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_RXE1_AXUSER_SPECIAL_SECTION 0x2180 + +#define mmNIC7_TXS0_BASE 0x1000007FFD7D0000ull +#define NIC7_TXS0_MAX_OFFSET 0x1000 +#define NIC7_TXS0_SECTION 0xE800 + +#define mmNIC7_TXS0_SPECIAL_BASE 0x1000007FFD7D0E80ull +#define NIC7_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_TXS0_SPECIAL_SECTION 0x1800 + +#define mmNIC7_TXS1_BASE 0x1000007FFD7D1000ull +#define NIC7_TXS1_MAX_OFFSET 0x1000 +#define NIC7_TXS1_SECTION 0xE800 + +#define mmNIC7_TXS1_SPECIAL_BASE 0x1000007FFD7D1E80ull +#define NIC7_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_TXS1_SPECIAL_SECTION 0x1800 + +#define mmNIC7_TXE0_BASE 0x1000007FFD7D2000ull +#define NIC7_TXE0_MAX_OFFSET 0x1000 +#define NIC7_TXE0_SECTION 0xE800 + +#define mmNIC7_TXE0_SPECIAL_BASE 0x1000007FFD7D2E80ull +#define NIC7_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_TXE0_SPECIAL_SECTION 0x1800 + +#define mmNIC7_TXE1_BASE 0x1000007FFD7D3000ull +#define NIC7_TXE1_MAX_OFFSET 0x1000 +#define NIC7_TXE1_SECTION 0xE800 + +#define mmNIC7_TXE1_SPECIAL_BASE 0x1000007FFD7D3E80ull +#define NIC7_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_TXE1_SPECIAL_SECTION 0x1800 + +#define mmNIC7_TXB_BASE 0x1000007FFD7D4000ull +#define NIC7_TXB_MAX_OFFSET 0x1000 +#define NIC7_TXB_SECTION 0xE800 + +#define mmNIC7_TXB_SPECIAL_BASE 0x1000007FFD7D4E80ull +#define NIC7_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_TXB_SPECIAL_SECTION 0x1800 + +#define mmNIC7_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFD7D5000ull +#define NIC7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmNIC7_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFD7D5200ull +#define NIC7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmNIC7_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFD7D5400ull +#define NIC7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmNIC7_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFD7D5600ull +#define NIC7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmNIC7_MSTR_IF_E2E_CRDT_BASE 0x1000007FFD7D5800ull +#define NIC7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC7_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmNIC7_MSTR_IF_AXUSER_BASE 0x1000007FFD7D5A80ull +#define NIC7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC7_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmNIC7_MSTR_IF_DBG_HBW_BASE 0x1000007FFD7D5B00ull +#define NIC7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC7_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmNIC7_MSTR_IF_DBG_LBW_BASE 0x1000007FFD7D5B80ull +#define NIC7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC7_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmNIC7_MSTR_IF_CORE_HBW_BASE 0x1000007FFD7D5C00ull +#define NIC7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC7_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmNIC7_MSTR_IF_CORE_LBW_BASE 0x1000007FFD7D5D80ull +#define NIC7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC7_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmNIC7_MSTR_IF_SPECIAL_BASE 0x1000007FFD7D5E80ull +#define NIC7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmNIC7_TX_AXUSER_BASE 0x1000007FFD7D6000ull +#define NIC7_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC7_TX_AXUSER_SECTION 0x2000 + +#define mmNIC7_SERDES0_BASE 0x1000007FFD7D8000ull +#define NIC7_SERDES0_MAX_OFFSET 0x3E40 +#define NIC7_SERDES0_SECTION 0x4000 + +#define mmNIC7_SERDES1_BASE 0x1000007FFD7DC000ull +#define NIC7_SERDES1_MAX_OFFSET 0x3E40 +#define NIC7_SERDES1_SECTION 0x4000 + +#define mmNIC7_PHY_BASE 0x1000007FFD7E0000ull +#define NIC7_PHY_MAX_OFFSET 0x1000 +#define NIC7_PHY_SECTION 0xE800 + +#define mmNIC7_PHY_SPECIAL_BASE 0x1000007FFD7E0E80ull +#define NIC7_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC7_PHY_SPECIAL_SECTION 0x7180 + +#define mmPRT7_MAC_AUX_BASE 0x1000007FFD7E8000ull +#define PRT7_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT7_MAC_AUX_SECTION 0xE800 + +#define mmPRT7_MAC_AUX_SPECIAL_BASE 0x1000007FFD7E8E80ull +#define PRT7_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT7_MAC_AUX_SPECIAL_SECTION 0x1800 + +#define mmPRT7_MAC_CORE_BASE 0x1000007FFD7E9000ull +#define PRT7_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT7_MAC_CORE_SECTION 0xE800 + +#define mmPRT7_MAC_CORE_SPECIAL_BASE 0x1000007FFD7E9E80ull +#define PRT7_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT7_MAC_CORE_SPECIAL_SECTION 0x1800 + +#define mmNIC7_MAC_RS_FEC_BASE 0x1000007FFD7EA000ull +#define NIC7_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC7_MAC_RS_FEC_SECTION 0x1000 + +#define mmNIC7_MAC_GLOB_STAT_NIC_MAC_STAT_BASE 0x1000007FFD7EB000ull +#define NIC7_MAC_GLOB_STAT_NIC_MAC_STAT_MAX_OFFSET 0x4D00 +#define NIC7_MAC_GLOB_STAT_NIC_MAC_STAT_SECTION 0x8000 + +#define mmNIC7_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_BASE 0x1000007FFD7EB800ull +#define NIC7_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC7_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_SECTION 0x8000 + +#define mmNIC7_MAC_CH0_MAC_PCS_BASE 0x1000007FFD7EC000ull +#define NIC7_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC7_MAC_CH0_MAC_PCS_SECTION 0x4000 + +#define mmNIC7_MAC_CH0_MAC_128_BASE 0x1000007FFD7EC400ull +#define NIC7_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC7_MAC_CH0_MAC_128_SECTION 0x4000 + +#define mmNIC7_MAC_CH0_MAC_AN_BASE 0x1000007FFD7EC800ull +#define NIC7_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC7_MAC_CH0_MAC_AN_SECTION 0x8000 + +#define mmNIC7_MAC_CH1_MAC_PCS_BASE 0x1000007FFD7ED000ull +#define NIC7_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC7_MAC_CH1_MAC_PCS_SECTION 0x4000 + +#define mmNIC7_MAC_CH1_MAC_128_BASE 0x1000007FFD7ED400ull +#define NIC7_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC7_MAC_CH1_MAC_128_SECTION 0x4000 + +#define mmNIC7_MAC_CH1_MAC_AN_BASE 0x1000007FFD7ED800ull +#define NIC7_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC7_MAC_CH1_MAC_AN_SECTION 0x8000 + +#define mmNIC7_MAC_CH2_MAC_PCS_BASE 0x1000007FFD7EE000ull +#define NIC7_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC7_MAC_CH2_MAC_PCS_SECTION 0x4000 + +#define mmNIC7_MAC_CH2_MAC_128_BASE 0x1000007FFD7EE400ull +#define NIC7_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC7_MAC_CH2_MAC_128_SECTION 0x4000 + +#define mmNIC7_MAC_CH2_MAC_AN_BASE 0x1000007FFD7EE800ull +#define NIC7_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC7_MAC_CH2_MAC_AN_SECTION 0x8000 + +#define mmNIC7_MAC_CH3_MAC_PCS_BASE 0x1000007FFD7EF000ull +#define NIC7_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC7_MAC_CH3_MAC_PCS_SECTION 0x4000 + +#define mmNIC7_MAC_CH3_MAC_128_BASE 0x1000007FFD7EF400ull +#define NIC7_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC7_MAC_CH3_MAC_128_SECTION 0x4000 + +#define mmNIC7_MAC_CH3_MAC_AN_BASE 0x1000007FFD7EF800ull +#define NIC7_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC7_MAC_CH3_MAC_AN_SECTION 0x10800 + +#define mmNIC8_UMR0_0_UNSECURE_DOORBELL0_BASE 0x1000007FFD800000ull +#define NIC8_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR0_0_UNSECURE_DOORBELL1_BASE 0x1000007FFD800080ull +#define NIC8_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD800100ull +#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD800180ull +#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR0_0_SPECIAL_BASE 0x1000007FFD800E80ull +#define NIC8_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_0_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR0_1_UNSECURE_DOORBELL0_BASE 0x1000007FFD801000ull +#define NIC8_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR0_1_UNSECURE_DOORBELL1_BASE 0x1000007FFD801080ull +#define NIC8_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD801100ull +#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD801180ull +#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR0_1_SPECIAL_BASE 0x1000007FFD801E80ull +#define NIC8_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_1_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR0_2_UNSECURE_DOORBELL0_BASE 0x1000007FFD802000ull +#define NIC8_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR0_2_UNSECURE_DOORBELL1_BASE 0x1000007FFD802080ull +#define NIC8_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD802100ull +#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD802180ull +#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR0_2_SPECIAL_BASE 0x1000007FFD802E80ull +#define NIC8_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_2_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR0_3_UNSECURE_DOORBELL0_BASE 0x1000007FFD803000ull +#define NIC8_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR0_3_UNSECURE_DOORBELL1_BASE 0x1000007FFD803080ull +#define NIC8_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD803100ull +#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD803180ull +#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR0_3_SPECIAL_BASE 0x1000007FFD803E80ull +#define NIC8_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_3_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR0_4_UNSECURE_DOORBELL0_BASE 0x1000007FFD804000ull +#define NIC8_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR0_4_UNSECURE_DOORBELL1_BASE 0x1000007FFD804080ull +#define NIC8_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD804100ull +#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD804180ull +#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR0_4_SPECIAL_BASE 0x1000007FFD804E80ull +#define NIC8_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_4_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR0_5_UNSECURE_DOORBELL0_BASE 0x1000007FFD805000ull +#define NIC8_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR0_5_UNSECURE_DOORBELL1_BASE 0x1000007FFD805080ull +#define NIC8_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD805100ull +#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD805180ull +#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR0_5_SPECIAL_BASE 0x1000007FFD805E80ull +#define NIC8_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_5_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR0_6_UNSECURE_DOORBELL0_BASE 0x1000007FFD806000ull +#define NIC8_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR0_6_UNSECURE_DOORBELL1_BASE 0x1000007FFD806080ull +#define NIC8_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD806100ull +#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD806180ull +#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR0_6_SPECIAL_BASE 0x1000007FFD806E80ull +#define NIC8_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_6_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR0_7_UNSECURE_DOORBELL0_BASE 0x1000007FFD807000ull +#define NIC8_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR0_7_UNSECURE_DOORBELL1_BASE 0x1000007FFD807080ull +#define NIC8_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD807100ull +#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD807180ull +#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR0_7_SPECIAL_BASE 0x1000007FFD807E80ull +#define NIC8_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_7_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR0_8_UNSECURE_DOORBELL0_BASE 0x1000007FFD808000ull +#define NIC8_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR0_8_UNSECURE_DOORBELL1_BASE 0x1000007FFD808080ull +#define NIC8_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD808100ull +#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD808180ull +#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR0_8_SPECIAL_BASE 0x1000007FFD808E80ull +#define NIC8_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_8_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR0_9_UNSECURE_DOORBELL0_BASE 0x1000007FFD809000ull +#define NIC8_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR0_9_UNSECURE_DOORBELL1_BASE 0x1000007FFD809080ull +#define NIC8_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD809100ull +#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD809180ull +#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR0_9_SPECIAL_BASE 0x1000007FFD809E80ull +#define NIC8_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_9_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR0_10_UNSECURE_DOORBELL0_BASE 0x1000007FFD80A000ull +#define NIC8_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR0_10_UNSECURE_DOORBELL1_BASE 0x1000007FFD80A080ull +#define NIC8_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD80A100ull +#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD80A180ull +#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR0_10_SPECIAL_BASE 0x1000007FFD80AE80ull +#define NIC8_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_10_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR0_11_UNSECURE_DOORBELL0_BASE 0x1000007FFD80B000ull +#define NIC8_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR0_11_UNSECURE_DOORBELL1_BASE 0x1000007FFD80B080ull +#define NIC8_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD80B100ull +#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD80B180ull +#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR0_11_SPECIAL_BASE 0x1000007FFD80BE80ull +#define NIC8_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_11_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR0_12_UNSECURE_DOORBELL0_BASE 0x1000007FFD80C000ull +#define NIC8_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR0_12_UNSECURE_DOORBELL1_BASE 0x1000007FFD80C080ull +#define NIC8_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD80C100ull +#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD80C180ull +#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR0_12_SPECIAL_BASE 0x1000007FFD80CE80ull +#define NIC8_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_12_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR0_13_UNSECURE_DOORBELL0_BASE 0x1000007FFD80D000ull +#define NIC8_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR0_13_UNSECURE_DOORBELL1_BASE 0x1000007FFD80D080ull +#define NIC8_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD80D100ull +#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD80D180ull +#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR0_13_SPECIAL_BASE 0x1000007FFD80DE80ull +#define NIC8_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_13_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR0_14_UNSECURE_DOORBELL0_BASE 0x1000007FFD80E000ull +#define NIC8_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR0_14_UNSECURE_DOORBELL1_BASE 0x1000007FFD80E080ull +#define NIC8_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD80E100ull +#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD80E180ull +#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR0_14_SPECIAL_BASE 0x1000007FFD80EE80ull +#define NIC8_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR0_14_SPECIAL_SECTION 0x1180 + +#define mmNIC8_QM_DCCM0_BASE 0x1000007FFD810000ull +#define NIC8_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC8_QM_DCCM0_SECTION 0x8000 + +#define mmNIC8_QM_ARC_AUX0_BASE 0x1000007FFD818000ull +#define NIC8_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC8_QM_ARC_AUX0_SECTION 0xE800 + +#define mmNIC8_QM_ARC_AUX0_SPECIAL_BASE 0x1000007FFD818E80ull +#define NIC8_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 + +#define mmNIC8_QM0_BASE 0x1000007FFD81A000ull +#define NIC8_QM0_MAX_OFFSET 0x1000 +#define NIC8_QM0_SECTION 0x9000 + +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFD81A900ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFD81A908ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFD81A910ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFD81A918ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFD81A920ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFD81A928ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFD81A930ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFD81A938ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFD81A940ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFD81A948ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFD81A950ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFD81A958ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFD81A960ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFD81A968ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFD81A970ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmNIC8_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFD81A978ull +#define NIC8_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC8_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmNIC8_QM0_AXUSER_SECURED_BASE 0x1000007FFD81AB00ull +#define NIC8_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC8_QM0_AXUSER_SECURED_SECTION 0x8000 + +#define mmNIC8_QM0_AXUSER_NONSECURED_BASE 0x1000007FFD81AB80ull +#define NIC8_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC8_QM0_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmNIC8_QM0_DBG_HBW_BASE 0x1000007FFD81AC00ull +#define NIC8_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC8_QM0_DBG_HBW_SECTION 0x8000 + +#define mmNIC8_QM0_DBG_LBW_BASE 0x1000007FFD81AC80ull +#define NIC8_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC8_QM0_DBG_LBW_SECTION 0x1000 + +#define mmNIC8_QM0_CGM_BASE 0x1000007FFD81AD80ull +#define NIC8_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC8_QM0_CGM_SECTION 0x1000 + +#define mmNIC8_QM0_SPECIAL_BASE 0x1000007FFD81AE80ull +#define NIC8_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_QM0_SPECIAL_SECTION 0x4180 + +#define mmNIC8_QPC0_BASE 0x1000007FFD81F000ull +#define NIC8_QPC0_MAX_OFFSET 0x1000 +#define NIC8_QPC0_SECTION 0x7200 + +#define mmNIC8_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x1000007FFD81F720ull +#define NIC8_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x1000007FFD81F728ull +#define NIC8_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x1000007FFD81F730ull +#define NIC8_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x1000007FFD81F738ull +#define NIC8_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x1000007FFD81F740ull +#define NIC8_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x1000007FFD81F748ull +#define NIC8_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x1000007FFD81F750ull +#define NIC8_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x1000007FFD81F758ull +#define NIC8_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x1000007FFD81F760ull +#define NIC8_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x1000007FFD81F768ull +#define NIC8_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x1000007FFD81F770ull +#define NIC8_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x1000007FFD81F778ull +#define NIC8_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x1000007FFD81F780ull +#define NIC8_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x1000007FFD81F788ull +#define NIC8_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x1000007FFD81F790ull +#define NIC8_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x1000007FFD81F798ull +#define NIC8_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x1000007FFD81F7A0ull +#define NIC8_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x1000007FFD81F7A8ull +#define NIC8_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x1000007FFD81F7B0ull +#define NIC8_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x1000007FFD81F7B8ull +#define NIC8_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x1000007FFD81F7C0ull +#define NIC8_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x1000007FFD81F7C8ull +#define NIC8_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x1000007FFD81F7D0ull +#define NIC8_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x1000007FFD81F7D8ull +#define NIC8_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x1000007FFD81F7E0ull +#define NIC8_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x1000007FFD81F7E8ull +#define NIC8_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x1000007FFD81F7F0ull +#define NIC8_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x1000007FFD81F7F8ull +#define NIC8_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x1000007FFD81F800ull +#define NIC8_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x1000007FFD81F808ull +#define NIC8_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x1000007FFD81F810ull +#define NIC8_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x1000007FFD81F818ull +#define NIC8_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 + +#define mmNIC8_QPC0_AXUSER_CONG_QUE_BASE 0x1000007FFD81FB80ull +#define NIC8_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC8_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 + +#define mmNIC8_QPC0_AXUSER_RXWQE_BASE 0x1000007FFD81FBE0ull +#define NIC8_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC8_QPC0_AXUSER_RXWQE_SECTION 0x6000 + +#define mmNIC8_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x1000007FFD81FC40ull +#define NIC8_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC8_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 + +#define mmNIC8_QPC0_AXUSER_DB_FIFO_BASE 0x1000007FFD81FCA0ull +#define NIC8_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC8_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 + +#define mmNIC8_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x1000007FFD81FD00ull +#define NIC8_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC8_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 + +#define mmNIC8_QPC0_AXUSER_ERR_FIFO_BASE 0x1000007FFD81FD60ull +#define NIC8_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC8_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 + +#define mmNIC8_QPC0_AXUSER_QPC_RESP_BASE 0x1000007FFD81FDC0ull +#define NIC8_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC8_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 + +#define mmNIC8_QPC0_AXUSER_QPC_REQ_BASE 0x1000007FFD81FE20ull +#define NIC8_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC8_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 + +#define mmNIC8_QPC0_SPECIAL_BASE 0x1000007FFD81FE80ull +#define NIC8_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_QPC0_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR1_0_UNSECURE_DOORBELL0_BASE 0x1000007FFD820000ull +#define NIC8_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR1_0_UNSECURE_DOORBELL1_BASE 0x1000007FFD820080ull +#define NIC8_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD820100ull +#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD820180ull +#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR1_0_SPECIAL_BASE 0x1000007FFD820E80ull +#define NIC8_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_0_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR1_1_UNSECURE_DOORBELL0_BASE 0x1000007FFD821000ull +#define NIC8_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR1_1_UNSECURE_DOORBELL1_BASE 0x1000007FFD821080ull +#define NIC8_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD821100ull +#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD821180ull +#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR1_1_SPECIAL_BASE 0x1000007FFD821E80ull +#define NIC8_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_1_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR1_2_UNSECURE_DOORBELL0_BASE 0x1000007FFD822000ull +#define NIC8_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR1_2_UNSECURE_DOORBELL1_BASE 0x1000007FFD822080ull +#define NIC8_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD822100ull +#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD822180ull +#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR1_2_SPECIAL_BASE 0x1000007FFD822E80ull +#define NIC8_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_2_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR1_3_UNSECURE_DOORBELL0_BASE 0x1000007FFD823000ull +#define NIC8_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR1_3_UNSECURE_DOORBELL1_BASE 0x1000007FFD823080ull +#define NIC8_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD823100ull +#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD823180ull +#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR1_3_SPECIAL_BASE 0x1000007FFD823E80ull +#define NIC8_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_3_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR1_4_UNSECURE_DOORBELL0_BASE 0x1000007FFD824000ull +#define NIC8_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR1_4_UNSECURE_DOORBELL1_BASE 0x1000007FFD824080ull +#define NIC8_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD824100ull +#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD824180ull +#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR1_4_SPECIAL_BASE 0x1000007FFD824E80ull +#define NIC8_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_4_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR1_5_UNSECURE_DOORBELL0_BASE 0x1000007FFD825000ull +#define NIC8_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR1_5_UNSECURE_DOORBELL1_BASE 0x1000007FFD825080ull +#define NIC8_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD825100ull +#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD825180ull +#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR1_5_SPECIAL_BASE 0x1000007FFD825E80ull +#define NIC8_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_5_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR1_6_UNSECURE_DOORBELL0_BASE 0x1000007FFD826000ull +#define NIC8_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR1_6_UNSECURE_DOORBELL1_BASE 0x1000007FFD826080ull +#define NIC8_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD826100ull +#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD826180ull +#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR1_6_SPECIAL_BASE 0x1000007FFD826E80ull +#define NIC8_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_6_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR1_7_UNSECURE_DOORBELL0_BASE 0x1000007FFD827000ull +#define NIC8_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR1_7_UNSECURE_DOORBELL1_BASE 0x1000007FFD827080ull +#define NIC8_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD827100ull +#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD827180ull +#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR1_7_SPECIAL_BASE 0x1000007FFD827E80ull +#define NIC8_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_7_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR1_8_UNSECURE_DOORBELL0_BASE 0x1000007FFD828000ull +#define NIC8_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR1_8_UNSECURE_DOORBELL1_BASE 0x1000007FFD828080ull +#define NIC8_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD828100ull +#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD828180ull +#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR1_8_SPECIAL_BASE 0x1000007FFD828E80ull +#define NIC8_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_8_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR1_9_UNSECURE_DOORBELL0_BASE 0x1000007FFD829000ull +#define NIC8_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR1_9_UNSECURE_DOORBELL1_BASE 0x1000007FFD829080ull +#define NIC8_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD829100ull +#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD829180ull +#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR1_9_SPECIAL_BASE 0x1000007FFD829E80ull +#define NIC8_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_9_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR1_10_UNSECURE_DOORBELL0_BASE 0x1000007FFD82A000ull +#define NIC8_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR1_10_UNSECURE_DOORBELL1_BASE 0x1000007FFD82A080ull +#define NIC8_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD82A100ull +#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD82A180ull +#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR1_10_SPECIAL_BASE 0x1000007FFD82AE80ull +#define NIC8_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_10_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR1_11_UNSECURE_DOORBELL0_BASE 0x1000007FFD82B000ull +#define NIC8_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR1_11_UNSECURE_DOORBELL1_BASE 0x1000007FFD82B080ull +#define NIC8_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD82B100ull +#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD82B180ull +#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR1_11_SPECIAL_BASE 0x1000007FFD82BE80ull +#define NIC8_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_11_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR1_12_UNSECURE_DOORBELL0_BASE 0x1000007FFD82C000ull +#define NIC8_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR1_12_UNSECURE_DOORBELL1_BASE 0x1000007FFD82C080ull +#define NIC8_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD82C100ull +#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD82C180ull +#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR1_12_SPECIAL_BASE 0x1000007FFD82CE80ull +#define NIC8_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_12_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR1_13_UNSECURE_DOORBELL0_BASE 0x1000007FFD82D000ull +#define NIC8_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR1_13_UNSECURE_DOORBELL1_BASE 0x1000007FFD82D080ull +#define NIC8_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD82D100ull +#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD82D180ull +#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR1_13_SPECIAL_BASE 0x1000007FFD82DE80ull +#define NIC8_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_13_SPECIAL_SECTION 0x1800 + +#define mmNIC8_UMR1_14_UNSECURE_DOORBELL0_BASE 0x1000007FFD82E000ull +#define NIC8_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC8_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC8_UMR1_14_UNSECURE_DOORBELL1_BASE 0x1000007FFD82E080ull +#define NIC8_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC8_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC8_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD82E100ull +#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC8_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD82E180ull +#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC8_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC8_UMR1_14_SPECIAL_BASE 0x1000007FFD82EE80ull +#define NIC8_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_UMR1_14_SPECIAL_SECTION 0x1180 + +#define mmNIC8_QM_DCCM1_BASE 0x1000007FFD830000ull +#define NIC8_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC8_QM_DCCM1_SECTION 0x8000 + +#define mmNIC8_QM_ARC_AUX1_BASE 0x1000007FFD838000ull +#define NIC8_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC8_QM_ARC_AUX1_SECTION 0xE800 + +#define mmNIC8_QM_ARC_AUX1_SPECIAL_BASE 0x1000007FFD838E80ull +#define NIC8_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 + +#define mmNIC8_QM1_BASE 0x1000007FFD83A000ull +#define NIC8_QM1_MAX_OFFSET 0x1000 +#define NIC8_QM1_SECTION 0x9000 + +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFD83A900ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFD83A908ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFD83A910ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFD83A918ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFD83A920ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFD83A928ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFD83A930ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFD83A938ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFD83A940ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFD83A948ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFD83A950ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFD83A958ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFD83A960ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFD83A968ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFD83A970ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmNIC8_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFD83A978ull +#define NIC8_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC8_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmNIC8_QM1_AXUSER_SECURED_BASE 0x1000007FFD83AB00ull +#define NIC8_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC8_QM1_AXUSER_SECURED_SECTION 0x8000 + +#define mmNIC8_QM1_AXUSER_NONSECURED_BASE 0x1000007FFD83AB80ull +#define NIC8_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC8_QM1_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmNIC8_QM1_DBG_HBW_BASE 0x1000007FFD83AC00ull +#define NIC8_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC8_QM1_DBG_HBW_SECTION 0x8000 + +#define mmNIC8_QM1_DBG_LBW_BASE 0x1000007FFD83AC80ull +#define NIC8_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC8_QM1_DBG_LBW_SECTION 0x1000 + +#define mmNIC8_QM1_CGM_BASE 0x1000007FFD83AD80ull +#define NIC8_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC8_QM1_CGM_SECTION 0x1000 + +#define mmNIC8_QM1_SPECIAL_BASE 0x1000007FFD83AE80ull +#define NIC8_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_QM1_SPECIAL_SECTION 0x4180 + +#define mmNIC8_QPC1_BASE 0x1000007FFD83F000ull +#define NIC8_QPC1_MAX_OFFSET 0x1000 +#define NIC8_QPC1_SECTION 0x7200 + +#define mmNIC8_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x1000007FFD83F720ull +#define NIC8_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x1000007FFD83F728ull +#define NIC8_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x1000007FFD83F730ull +#define NIC8_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x1000007FFD83F738ull +#define NIC8_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x1000007FFD83F740ull +#define NIC8_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x1000007FFD83F748ull +#define NIC8_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x1000007FFD83F750ull +#define NIC8_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x1000007FFD83F758ull +#define NIC8_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x1000007FFD83F760ull +#define NIC8_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x1000007FFD83F768ull +#define NIC8_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x1000007FFD83F770ull +#define NIC8_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x1000007FFD83F778ull +#define NIC8_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x1000007FFD83F780ull +#define NIC8_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x1000007FFD83F788ull +#define NIC8_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x1000007FFD83F790ull +#define NIC8_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x1000007FFD83F798ull +#define NIC8_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x1000007FFD83F7A0ull +#define NIC8_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x1000007FFD83F7A8ull +#define NIC8_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x1000007FFD83F7B0ull +#define NIC8_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x1000007FFD83F7B8ull +#define NIC8_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x1000007FFD83F7C0ull +#define NIC8_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x1000007FFD83F7C8ull +#define NIC8_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x1000007FFD83F7D0ull +#define NIC8_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x1000007FFD83F7D8ull +#define NIC8_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x1000007FFD83F7E0ull +#define NIC8_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x1000007FFD83F7E8ull +#define NIC8_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x1000007FFD83F7F0ull +#define NIC8_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x1000007FFD83F7F8ull +#define NIC8_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x1000007FFD83F800ull +#define NIC8_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x1000007FFD83F808ull +#define NIC8_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x1000007FFD83F810ull +#define NIC8_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC8_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x1000007FFD83F818ull +#define NIC8_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC8_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 + +#define mmNIC8_QPC1_AXUSER_CONG_QUE_BASE 0x1000007FFD83FB80ull +#define NIC8_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC8_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 + +#define mmNIC8_QPC1_AXUSER_RXWQE_BASE 0x1000007FFD83FBE0ull +#define NIC8_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC8_QPC1_AXUSER_RXWQE_SECTION 0x6000 + +#define mmNIC8_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x1000007FFD83FC40ull +#define NIC8_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC8_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 + +#define mmNIC8_QPC1_AXUSER_DB_FIFO_BASE 0x1000007FFD83FCA0ull +#define NIC8_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC8_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 + +#define mmNIC8_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x1000007FFD83FD00ull +#define NIC8_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC8_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 + +#define mmNIC8_QPC1_AXUSER_ERR_FIFO_BASE 0x1000007FFD83FD60ull +#define NIC8_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC8_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 + +#define mmNIC8_QPC1_AXUSER_QPC_RESP_BASE 0x1000007FFD83FDC0ull +#define NIC8_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC8_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 + +#define mmNIC8_QPC1_AXUSER_QPC_REQ_BASE 0x1000007FFD83FE20ull +#define NIC8_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC8_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 + +#define mmNIC8_QPC1_SPECIAL_BASE 0x1000007FFD83FE80ull +#define NIC8_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_QPC1_SPECIAL_SECTION 0x8180 + +#define mmNIC8_TMR_BASE 0x1000007FFD848000ull +#define NIC8_TMR_MAX_OFFSET 0x1000 +#define NIC8_TMR_SECTION 0xD600 + +#define mmNIC8_TMR_AXUSER_TMR_FREE_LIST_BASE 0x1000007FFD848D60ull +#define NIC8_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC8_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 + +#define mmNIC8_TMR_AXUSER_TMR_FIFO_BASE 0x1000007FFD848DC0ull +#define NIC8_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC8_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 + +#define mmNIC8_TMR_AXUSER_TMR_FSM_BASE 0x1000007FFD848E20ull +#define NIC8_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC8_TMR_AXUSER_TMR_FSM_SECTION 0x6000 + +#define mmNIC8_TMR_SPECIAL_BASE 0x1000007FFD848E80ull +#define NIC8_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_TMR_SPECIAL_SECTION 0x1800 + +#define mmNIC8_RXB_CORE_BASE 0x1000007FFD849000ull +#define NIC8_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC8_RXB_CORE_SECTION 0x6100 + +#define mmNIC8_RXB_CORE_SCT_AWUSER_BASE 0x1000007FFD849610ull +#define NIC8_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC8_RXB_CORE_SCT_AWUSER_SECTION 0x8700 + +#define mmNIC8_RXB_CORE_SPECIAL_BASE 0x1000007FFD849E80ull +#define NIC8_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_RXB_CORE_SPECIAL_SECTION 0x1800 + +#define mmNIC8_RXE0_BASE 0x1000007FFD84A000ull +#define NIC8_RXE0_MAX_OFFSET 0x1000 +#define NIC8_RXE0_SECTION 0x9000 + +#define mmNIC8_RXE0_WQE_ARUSER_BASE 0x1000007FFD84A900ull +#define NIC8_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC8_RXE0_WQE_ARUSER_SECTION 0x5800 + +#define mmNIC8_RXE0_SPECIAL_BASE 0x1000007FFD84AE80ull +#define NIC8_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_RXE0_SPECIAL_SECTION 0x1800 + +#define mmNIC8_RXE1_BASE 0x1000007FFD84B000ull +#define NIC8_RXE1_MAX_OFFSET 0x1000 +#define NIC8_RXE1_SECTION 0x9000 + +#define mmNIC8_RXE1_WQE_ARUSER_BASE 0x1000007FFD84B900ull +#define NIC8_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC8_RXE1_WQE_ARUSER_SECTION 0x5800 + +#define mmNIC8_RXE1_SPECIAL_BASE 0x1000007FFD84BE80ull +#define NIC8_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_RXE1_SPECIAL_SECTION 0x1800 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ0_BASE 0x1000007FFD84C000ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ1_BASE 0x1000007FFD84C050ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ2_BASE 0x1000007FFD84C0A0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ3_BASE 0x1000007FFD84C0F0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ4_BASE 0x1000007FFD84C140ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ5_BASE 0x1000007FFD84C190ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ6_BASE 0x1000007FFD84C1E0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ7_BASE 0x1000007FFD84C230ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ8_BASE 0x1000007FFD84C280ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ9_BASE 0x1000007FFD84C2D0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ10_BASE 0x1000007FFD84C320ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ11_BASE 0x1000007FFD84C370ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ12_BASE 0x1000007FFD84C3C0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ13_BASE 0x1000007FFD84C410ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ14_BASE 0x1000007FFD84C460ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ15_BASE 0x1000007FFD84C4B0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ16_BASE 0x1000007FFD84C500ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ17_BASE 0x1000007FFD84C550ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ18_BASE 0x1000007FFD84C5A0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ19_BASE 0x1000007FFD84C5F0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ20_BASE 0x1000007FFD84C640ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ21_BASE 0x1000007FFD84C690ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ22_BASE 0x1000007FFD84C6E0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ23_BASE 0x1000007FFD84C730ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ24_BASE 0x1000007FFD84C780ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ25_BASE 0x1000007FFD84C7D0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ26_BASE 0x1000007FFD84C820ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ27_BASE 0x1000007FFD84C870ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ28_BASE 0x1000007FFD84C8C0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ29_BASE 0x1000007FFD84C910ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ30_BASE 0x1000007FFD84C960ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 + +#define mmNIC8_RXE0_AXUSER_AXUSER_CQ31_BASE 0x1000007FFD84C9B0ull +#define NIC8_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC8_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 + +#define mmNIC8_RXE0_AXUSER_SPECIAL_BASE 0x1000007FFD84CE80ull +#define NIC8_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_RXE0_AXUSER_SPECIAL_SECTION 0x1800 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ0_BASE 0x1000007FFD84D000ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ1_BASE 0x1000007FFD84D050ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ2_BASE 0x1000007FFD84D0A0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ3_BASE 0x1000007FFD84D0F0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ4_BASE 0x1000007FFD84D140ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ5_BASE 0x1000007FFD84D190ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ6_BASE 0x1000007FFD84D1E0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ7_BASE 0x1000007FFD84D230ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ8_BASE 0x1000007FFD84D280ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ9_BASE 0x1000007FFD84D2D0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ10_BASE 0x1000007FFD84D320ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ11_BASE 0x1000007FFD84D370ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ12_BASE 0x1000007FFD84D3C0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ13_BASE 0x1000007FFD84D410ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ14_BASE 0x1000007FFD84D460ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ15_BASE 0x1000007FFD84D4B0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ16_BASE 0x1000007FFD84D500ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ17_BASE 0x1000007FFD84D550ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ18_BASE 0x1000007FFD84D5A0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ19_BASE 0x1000007FFD84D5F0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ20_BASE 0x1000007FFD84D640ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ21_BASE 0x1000007FFD84D690ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ22_BASE 0x1000007FFD84D6E0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ23_BASE 0x1000007FFD84D730ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ24_BASE 0x1000007FFD84D780ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ25_BASE 0x1000007FFD84D7D0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ26_BASE 0x1000007FFD84D820ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ27_BASE 0x1000007FFD84D870ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ28_BASE 0x1000007FFD84D8C0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ29_BASE 0x1000007FFD84D910ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ30_BASE 0x1000007FFD84D960ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 + +#define mmNIC8_RXE1_AXUSER_AXUSER_CQ31_BASE 0x1000007FFD84D9B0ull +#define NIC8_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC8_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 + +#define mmNIC8_RXE1_AXUSER_SPECIAL_BASE 0x1000007FFD84DE80ull +#define NIC8_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_RXE1_AXUSER_SPECIAL_SECTION 0x2180 + +#define mmNIC8_TXS0_BASE 0x1000007FFD850000ull +#define NIC8_TXS0_MAX_OFFSET 0x1000 +#define NIC8_TXS0_SECTION 0xE800 + +#define mmNIC8_TXS0_SPECIAL_BASE 0x1000007FFD850E80ull +#define NIC8_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_TXS0_SPECIAL_SECTION 0x1800 + +#define mmNIC8_TXS1_BASE 0x1000007FFD851000ull +#define NIC8_TXS1_MAX_OFFSET 0x1000 +#define NIC8_TXS1_SECTION 0xE800 + +#define mmNIC8_TXS1_SPECIAL_BASE 0x1000007FFD851E80ull +#define NIC8_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_TXS1_SPECIAL_SECTION 0x1800 + +#define mmNIC8_TXE0_BASE 0x1000007FFD852000ull +#define NIC8_TXE0_MAX_OFFSET 0x1000 +#define NIC8_TXE0_SECTION 0xE800 + +#define mmNIC8_TXE0_SPECIAL_BASE 0x1000007FFD852E80ull +#define NIC8_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_TXE0_SPECIAL_SECTION 0x1800 + +#define mmNIC8_TXE1_BASE 0x1000007FFD853000ull +#define NIC8_TXE1_MAX_OFFSET 0x1000 +#define NIC8_TXE1_SECTION 0xE800 + +#define mmNIC8_TXE1_SPECIAL_BASE 0x1000007FFD853E80ull +#define NIC8_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_TXE1_SPECIAL_SECTION 0x1800 + +#define mmNIC8_TXB_BASE 0x1000007FFD854000ull +#define NIC8_TXB_MAX_OFFSET 0x1000 +#define NIC8_TXB_SECTION 0xE800 + +#define mmNIC8_TXB_SPECIAL_BASE 0x1000007FFD854E80ull +#define NIC8_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_TXB_SPECIAL_SECTION 0x1800 + +#define mmNIC8_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFD855000ull +#define NIC8_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC8_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmNIC8_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFD855200ull +#define NIC8_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC8_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmNIC8_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFD855400ull +#define NIC8_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC8_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmNIC8_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFD855600ull +#define NIC8_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC8_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmNIC8_MSTR_IF_E2E_CRDT_BASE 0x1000007FFD855800ull +#define NIC8_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC8_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmNIC8_MSTR_IF_AXUSER_BASE 0x1000007FFD855A80ull +#define NIC8_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC8_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmNIC8_MSTR_IF_DBG_HBW_BASE 0x1000007FFD855B00ull +#define NIC8_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC8_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmNIC8_MSTR_IF_DBG_LBW_BASE 0x1000007FFD855B80ull +#define NIC8_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC8_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmNIC8_MSTR_IF_CORE_HBW_BASE 0x1000007FFD855C00ull +#define NIC8_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC8_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmNIC8_MSTR_IF_CORE_LBW_BASE 0x1000007FFD855D80ull +#define NIC8_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC8_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmNIC8_MSTR_IF_SPECIAL_BASE 0x1000007FFD855E80ull +#define NIC8_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmNIC8_TX_AXUSER_BASE 0x1000007FFD856000ull +#define NIC8_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC8_TX_AXUSER_SECTION 0x2000 + +#define mmNIC8_SERDES0_BASE 0x1000007FFD858000ull +#define NIC8_SERDES0_MAX_OFFSET 0x3E40 +#define NIC8_SERDES0_SECTION 0x4000 + +#define mmNIC8_SERDES1_BASE 0x1000007FFD85C000ull +#define NIC8_SERDES1_MAX_OFFSET 0x3E40 +#define NIC8_SERDES1_SECTION 0x4000 + +#define mmNIC8_PHY_BASE 0x1000007FFD860000ull +#define NIC8_PHY_MAX_OFFSET 0x1000 +#define NIC8_PHY_SECTION 0xE800 + +#define mmNIC8_PHY_SPECIAL_BASE 0x1000007FFD860E80ull +#define NIC8_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC8_PHY_SPECIAL_SECTION 0x7180 + +#define mmPRT8_MAC_AUX_BASE 0x1000007FFD868000ull +#define PRT8_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT8_MAC_AUX_SECTION 0xE800 + +#define mmPRT8_MAC_AUX_SPECIAL_BASE 0x1000007FFD868E80ull +#define PRT8_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT8_MAC_AUX_SPECIAL_SECTION 0x1800 + +#define mmPRT8_MAC_CORE_BASE 0x1000007FFD869000ull +#define PRT8_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT8_MAC_CORE_SECTION 0xE800 + +#define mmPRT8_MAC_CORE_SPECIAL_BASE 0x1000007FFD869E80ull +#define PRT8_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT8_MAC_CORE_SPECIAL_SECTION 0x1800 + +#define mmNIC8_MAC_RS_FEC_BASE 0x1000007FFD86A000ull +#define NIC8_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC8_MAC_RS_FEC_SECTION 0x1000 + +#define mmNIC8_MAC_GLOB_STAT_NIC_MAC_STAT_BASE 0x1000007FFD86B000ull +#define NIC8_MAC_GLOB_STAT_NIC_MAC_STAT_MAX_OFFSET 0x4D00 +#define NIC8_MAC_GLOB_STAT_NIC_MAC_STAT_SECTION 0x8000 + +#define mmNIC8_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_BASE 0x1000007FFD86B800ull +#define NIC8_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC8_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_SECTION 0x8000 + +#define mmNIC8_MAC_CH0_MAC_PCS_BASE 0x1000007FFD86C000ull +#define NIC8_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC8_MAC_CH0_MAC_PCS_SECTION 0x4000 + +#define mmNIC8_MAC_CH0_MAC_128_BASE 0x1000007FFD86C400ull +#define NIC8_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC8_MAC_CH0_MAC_128_SECTION 0x4000 + +#define mmNIC8_MAC_CH0_MAC_AN_BASE 0x1000007FFD86C800ull +#define NIC8_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC8_MAC_CH0_MAC_AN_SECTION 0x8000 + +#define mmNIC8_MAC_CH1_MAC_PCS_BASE 0x1000007FFD86D000ull +#define NIC8_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC8_MAC_CH1_MAC_PCS_SECTION 0x4000 + +#define mmNIC8_MAC_CH1_MAC_128_BASE 0x1000007FFD86D400ull +#define NIC8_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC8_MAC_CH1_MAC_128_SECTION 0x4000 + +#define mmNIC8_MAC_CH1_MAC_AN_BASE 0x1000007FFD86D800ull +#define NIC8_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC8_MAC_CH1_MAC_AN_SECTION 0x8000 + +#define mmNIC8_MAC_CH2_MAC_PCS_BASE 0x1000007FFD86E000ull +#define NIC8_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC8_MAC_CH2_MAC_PCS_SECTION 0x4000 + +#define mmNIC8_MAC_CH2_MAC_128_BASE 0x1000007FFD86E400ull +#define NIC8_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC8_MAC_CH2_MAC_128_SECTION 0x4000 + +#define mmNIC8_MAC_CH2_MAC_AN_BASE 0x1000007FFD86E800ull +#define NIC8_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC8_MAC_CH2_MAC_AN_SECTION 0x8000 + +#define mmNIC8_MAC_CH3_MAC_PCS_BASE 0x1000007FFD86F000ull +#define NIC8_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC8_MAC_CH3_MAC_PCS_SECTION 0x4000 + +#define mmNIC8_MAC_CH3_MAC_128_BASE 0x1000007FFD86F400ull +#define NIC8_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC8_MAC_CH3_MAC_128_SECTION 0x4000 + +#define mmNIC8_MAC_CH3_MAC_AN_BASE 0x1000007FFD86F800ull +#define NIC8_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC8_MAC_CH3_MAC_AN_SECTION 0x10800 + +#define mmNIC9_UMR0_0_UNSECURE_DOORBELL0_BASE 0x1000007FFD880000ull +#define NIC9_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR0_0_UNSECURE_DOORBELL1_BASE 0x1000007FFD880080ull +#define NIC9_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD880100ull +#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD880180ull +#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR0_0_SPECIAL_BASE 0x1000007FFD880E80ull +#define NIC9_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_0_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR0_1_UNSECURE_DOORBELL0_BASE 0x1000007FFD881000ull +#define NIC9_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR0_1_UNSECURE_DOORBELL1_BASE 0x1000007FFD881080ull +#define NIC9_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD881100ull +#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD881180ull +#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR0_1_SPECIAL_BASE 0x1000007FFD881E80ull +#define NIC9_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_1_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR0_2_UNSECURE_DOORBELL0_BASE 0x1000007FFD882000ull +#define NIC9_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR0_2_UNSECURE_DOORBELL1_BASE 0x1000007FFD882080ull +#define NIC9_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD882100ull +#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD882180ull +#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR0_2_SPECIAL_BASE 0x1000007FFD882E80ull +#define NIC9_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_2_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR0_3_UNSECURE_DOORBELL0_BASE 0x1000007FFD883000ull +#define NIC9_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR0_3_UNSECURE_DOORBELL1_BASE 0x1000007FFD883080ull +#define NIC9_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD883100ull +#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD883180ull +#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR0_3_SPECIAL_BASE 0x1000007FFD883E80ull +#define NIC9_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_3_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR0_4_UNSECURE_DOORBELL0_BASE 0x1000007FFD884000ull +#define NIC9_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR0_4_UNSECURE_DOORBELL1_BASE 0x1000007FFD884080ull +#define NIC9_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD884100ull +#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD884180ull +#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR0_4_SPECIAL_BASE 0x1000007FFD884E80ull +#define NIC9_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_4_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR0_5_UNSECURE_DOORBELL0_BASE 0x1000007FFD885000ull +#define NIC9_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR0_5_UNSECURE_DOORBELL1_BASE 0x1000007FFD885080ull +#define NIC9_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD885100ull +#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD885180ull +#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR0_5_SPECIAL_BASE 0x1000007FFD885E80ull +#define NIC9_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_5_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR0_6_UNSECURE_DOORBELL0_BASE 0x1000007FFD886000ull +#define NIC9_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR0_6_UNSECURE_DOORBELL1_BASE 0x1000007FFD886080ull +#define NIC9_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD886100ull +#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD886180ull +#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR0_6_SPECIAL_BASE 0x1000007FFD886E80ull +#define NIC9_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_6_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR0_7_UNSECURE_DOORBELL0_BASE 0x1000007FFD887000ull +#define NIC9_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR0_7_UNSECURE_DOORBELL1_BASE 0x1000007FFD887080ull +#define NIC9_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD887100ull +#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD887180ull +#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR0_7_SPECIAL_BASE 0x1000007FFD887E80ull +#define NIC9_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_7_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR0_8_UNSECURE_DOORBELL0_BASE 0x1000007FFD888000ull +#define NIC9_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR0_8_UNSECURE_DOORBELL1_BASE 0x1000007FFD888080ull +#define NIC9_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD888100ull +#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD888180ull +#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR0_8_SPECIAL_BASE 0x1000007FFD888E80ull +#define NIC9_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_8_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR0_9_UNSECURE_DOORBELL0_BASE 0x1000007FFD889000ull +#define NIC9_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR0_9_UNSECURE_DOORBELL1_BASE 0x1000007FFD889080ull +#define NIC9_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD889100ull +#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD889180ull +#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR0_9_SPECIAL_BASE 0x1000007FFD889E80ull +#define NIC9_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_9_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR0_10_UNSECURE_DOORBELL0_BASE 0x1000007FFD88A000ull +#define NIC9_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR0_10_UNSECURE_DOORBELL1_BASE 0x1000007FFD88A080ull +#define NIC9_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD88A100ull +#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD88A180ull +#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR0_10_SPECIAL_BASE 0x1000007FFD88AE80ull +#define NIC9_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_10_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR0_11_UNSECURE_DOORBELL0_BASE 0x1000007FFD88B000ull +#define NIC9_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR0_11_UNSECURE_DOORBELL1_BASE 0x1000007FFD88B080ull +#define NIC9_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD88B100ull +#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD88B180ull +#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR0_11_SPECIAL_BASE 0x1000007FFD88BE80ull +#define NIC9_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_11_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR0_12_UNSECURE_DOORBELL0_BASE 0x1000007FFD88C000ull +#define NIC9_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR0_12_UNSECURE_DOORBELL1_BASE 0x1000007FFD88C080ull +#define NIC9_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD88C100ull +#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD88C180ull +#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR0_12_SPECIAL_BASE 0x1000007FFD88CE80ull +#define NIC9_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_12_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR0_13_UNSECURE_DOORBELL0_BASE 0x1000007FFD88D000ull +#define NIC9_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR0_13_UNSECURE_DOORBELL1_BASE 0x1000007FFD88D080ull +#define NIC9_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD88D100ull +#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD88D180ull +#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR0_13_SPECIAL_BASE 0x1000007FFD88DE80ull +#define NIC9_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_13_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR0_14_UNSECURE_DOORBELL0_BASE 0x1000007FFD88E000ull +#define NIC9_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR0_14_UNSECURE_DOORBELL1_BASE 0x1000007FFD88E080ull +#define NIC9_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD88E100ull +#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD88E180ull +#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR0_14_SPECIAL_BASE 0x1000007FFD88EE80ull +#define NIC9_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR0_14_SPECIAL_SECTION 0x1180 + +#define mmNIC9_QM_DCCM0_BASE 0x1000007FFD890000ull +#define NIC9_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC9_QM_DCCM0_SECTION 0x8000 + +#define mmNIC9_QM_ARC_AUX0_BASE 0x1000007FFD898000ull +#define NIC9_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC9_QM_ARC_AUX0_SECTION 0xE800 + +#define mmNIC9_QM_ARC_AUX0_SPECIAL_BASE 0x1000007FFD898E80ull +#define NIC9_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 + +#define mmNIC9_QM0_BASE 0x1000007FFD89A000ull +#define NIC9_QM0_MAX_OFFSET 0x1000 +#define NIC9_QM0_SECTION 0x9000 + +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFD89A900ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFD89A908ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFD89A910ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFD89A918ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFD89A920ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFD89A928ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFD89A930ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFD89A938ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFD89A940ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFD89A948ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFD89A950ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFD89A958ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFD89A960ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFD89A968ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFD89A970ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmNIC9_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFD89A978ull +#define NIC9_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC9_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmNIC9_QM0_AXUSER_SECURED_BASE 0x1000007FFD89AB00ull +#define NIC9_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC9_QM0_AXUSER_SECURED_SECTION 0x8000 + +#define mmNIC9_QM0_AXUSER_NONSECURED_BASE 0x1000007FFD89AB80ull +#define NIC9_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC9_QM0_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmNIC9_QM0_DBG_HBW_BASE 0x1000007FFD89AC00ull +#define NIC9_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC9_QM0_DBG_HBW_SECTION 0x8000 + +#define mmNIC9_QM0_DBG_LBW_BASE 0x1000007FFD89AC80ull +#define NIC9_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC9_QM0_DBG_LBW_SECTION 0x1000 + +#define mmNIC9_QM0_CGM_BASE 0x1000007FFD89AD80ull +#define NIC9_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC9_QM0_CGM_SECTION 0x1000 + +#define mmNIC9_QM0_SPECIAL_BASE 0x1000007FFD89AE80ull +#define NIC9_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_QM0_SPECIAL_SECTION 0x4180 + +#define mmNIC9_QPC0_BASE 0x1000007FFD89F000ull +#define NIC9_QPC0_MAX_OFFSET 0x1000 +#define NIC9_QPC0_SECTION 0x7200 + +#define mmNIC9_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x1000007FFD89F720ull +#define NIC9_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x1000007FFD89F728ull +#define NIC9_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x1000007FFD89F730ull +#define NIC9_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x1000007FFD89F738ull +#define NIC9_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x1000007FFD89F740ull +#define NIC9_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x1000007FFD89F748ull +#define NIC9_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x1000007FFD89F750ull +#define NIC9_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x1000007FFD89F758ull +#define NIC9_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x1000007FFD89F760ull +#define NIC9_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x1000007FFD89F768ull +#define NIC9_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x1000007FFD89F770ull +#define NIC9_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x1000007FFD89F778ull +#define NIC9_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x1000007FFD89F780ull +#define NIC9_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x1000007FFD89F788ull +#define NIC9_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x1000007FFD89F790ull +#define NIC9_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x1000007FFD89F798ull +#define NIC9_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x1000007FFD89F7A0ull +#define NIC9_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x1000007FFD89F7A8ull +#define NIC9_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x1000007FFD89F7B0ull +#define NIC9_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x1000007FFD89F7B8ull +#define NIC9_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x1000007FFD89F7C0ull +#define NIC9_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x1000007FFD89F7C8ull +#define NIC9_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x1000007FFD89F7D0ull +#define NIC9_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x1000007FFD89F7D8ull +#define NIC9_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x1000007FFD89F7E0ull +#define NIC9_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x1000007FFD89F7E8ull +#define NIC9_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x1000007FFD89F7F0ull +#define NIC9_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x1000007FFD89F7F8ull +#define NIC9_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x1000007FFD89F800ull +#define NIC9_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x1000007FFD89F808ull +#define NIC9_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x1000007FFD89F810ull +#define NIC9_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x1000007FFD89F818ull +#define NIC9_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 + +#define mmNIC9_QPC0_AXUSER_CONG_QUE_BASE 0x1000007FFD89FB80ull +#define NIC9_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC9_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 + +#define mmNIC9_QPC0_AXUSER_RXWQE_BASE 0x1000007FFD89FBE0ull +#define NIC9_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC9_QPC0_AXUSER_RXWQE_SECTION 0x6000 + +#define mmNIC9_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x1000007FFD89FC40ull +#define NIC9_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC9_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 + +#define mmNIC9_QPC0_AXUSER_DB_FIFO_BASE 0x1000007FFD89FCA0ull +#define NIC9_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC9_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 + +#define mmNIC9_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x1000007FFD89FD00ull +#define NIC9_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC9_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 + +#define mmNIC9_QPC0_AXUSER_ERR_FIFO_BASE 0x1000007FFD89FD60ull +#define NIC9_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC9_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 + +#define mmNIC9_QPC0_AXUSER_QPC_RESP_BASE 0x1000007FFD89FDC0ull +#define NIC9_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC9_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 + +#define mmNIC9_QPC0_AXUSER_QPC_REQ_BASE 0x1000007FFD89FE20ull +#define NIC9_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC9_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 + +#define mmNIC9_QPC0_SPECIAL_BASE 0x1000007FFD89FE80ull +#define NIC9_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_QPC0_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR1_0_UNSECURE_DOORBELL0_BASE 0x1000007FFD8A0000ull +#define NIC9_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR1_0_UNSECURE_DOORBELL1_BASE 0x1000007FFD8A0080ull +#define NIC9_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD8A0100ull +#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD8A0180ull +#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR1_0_SPECIAL_BASE 0x1000007FFD8A0E80ull +#define NIC9_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_0_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR1_1_UNSECURE_DOORBELL0_BASE 0x1000007FFD8A1000ull +#define NIC9_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR1_1_UNSECURE_DOORBELL1_BASE 0x1000007FFD8A1080ull +#define NIC9_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD8A1100ull +#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD8A1180ull +#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR1_1_SPECIAL_BASE 0x1000007FFD8A1E80ull +#define NIC9_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_1_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR1_2_UNSECURE_DOORBELL0_BASE 0x1000007FFD8A2000ull +#define NIC9_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR1_2_UNSECURE_DOORBELL1_BASE 0x1000007FFD8A2080ull +#define NIC9_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD8A2100ull +#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD8A2180ull +#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR1_2_SPECIAL_BASE 0x1000007FFD8A2E80ull +#define NIC9_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_2_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR1_3_UNSECURE_DOORBELL0_BASE 0x1000007FFD8A3000ull +#define NIC9_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR1_3_UNSECURE_DOORBELL1_BASE 0x1000007FFD8A3080ull +#define NIC9_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD8A3100ull +#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD8A3180ull +#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR1_3_SPECIAL_BASE 0x1000007FFD8A3E80ull +#define NIC9_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_3_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR1_4_UNSECURE_DOORBELL0_BASE 0x1000007FFD8A4000ull +#define NIC9_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR1_4_UNSECURE_DOORBELL1_BASE 0x1000007FFD8A4080ull +#define NIC9_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD8A4100ull +#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD8A4180ull +#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR1_4_SPECIAL_BASE 0x1000007FFD8A4E80ull +#define NIC9_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_4_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR1_5_UNSECURE_DOORBELL0_BASE 0x1000007FFD8A5000ull +#define NIC9_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR1_5_UNSECURE_DOORBELL1_BASE 0x1000007FFD8A5080ull +#define NIC9_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD8A5100ull +#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD8A5180ull +#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR1_5_SPECIAL_BASE 0x1000007FFD8A5E80ull +#define NIC9_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_5_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR1_6_UNSECURE_DOORBELL0_BASE 0x1000007FFD8A6000ull +#define NIC9_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR1_6_UNSECURE_DOORBELL1_BASE 0x1000007FFD8A6080ull +#define NIC9_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD8A6100ull +#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD8A6180ull +#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR1_6_SPECIAL_BASE 0x1000007FFD8A6E80ull +#define NIC9_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_6_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR1_7_UNSECURE_DOORBELL0_BASE 0x1000007FFD8A7000ull +#define NIC9_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR1_7_UNSECURE_DOORBELL1_BASE 0x1000007FFD8A7080ull +#define NIC9_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD8A7100ull +#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD8A7180ull +#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR1_7_SPECIAL_BASE 0x1000007FFD8A7E80ull +#define NIC9_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_7_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR1_8_UNSECURE_DOORBELL0_BASE 0x1000007FFD8A8000ull +#define NIC9_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR1_8_UNSECURE_DOORBELL1_BASE 0x1000007FFD8A8080ull +#define NIC9_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD8A8100ull +#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD8A8180ull +#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR1_8_SPECIAL_BASE 0x1000007FFD8A8E80ull +#define NIC9_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_8_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR1_9_UNSECURE_DOORBELL0_BASE 0x1000007FFD8A9000ull +#define NIC9_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR1_9_UNSECURE_DOORBELL1_BASE 0x1000007FFD8A9080ull +#define NIC9_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD8A9100ull +#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD8A9180ull +#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR1_9_SPECIAL_BASE 0x1000007FFD8A9E80ull +#define NIC9_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_9_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR1_10_UNSECURE_DOORBELL0_BASE 0x1000007FFD8AA000ull +#define NIC9_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR1_10_UNSECURE_DOORBELL1_BASE 0x1000007FFD8AA080ull +#define NIC9_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD8AA100ull +#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD8AA180ull +#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR1_10_SPECIAL_BASE 0x1000007FFD8AAE80ull +#define NIC9_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_10_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR1_11_UNSECURE_DOORBELL0_BASE 0x1000007FFD8AB000ull +#define NIC9_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR1_11_UNSECURE_DOORBELL1_BASE 0x1000007FFD8AB080ull +#define NIC9_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD8AB100ull +#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD8AB180ull +#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR1_11_SPECIAL_BASE 0x1000007FFD8ABE80ull +#define NIC9_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_11_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR1_12_UNSECURE_DOORBELL0_BASE 0x1000007FFD8AC000ull +#define NIC9_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR1_12_UNSECURE_DOORBELL1_BASE 0x1000007FFD8AC080ull +#define NIC9_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD8AC100ull +#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD8AC180ull +#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR1_12_SPECIAL_BASE 0x1000007FFD8ACE80ull +#define NIC9_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_12_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR1_13_UNSECURE_DOORBELL0_BASE 0x1000007FFD8AD000ull +#define NIC9_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR1_13_UNSECURE_DOORBELL1_BASE 0x1000007FFD8AD080ull +#define NIC9_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD8AD100ull +#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD8AD180ull +#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR1_13_SPECIAL_BASE 0x1000007FFD8ADE80ull +#define NIC9_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_13_SPECIAL_SECTION 0x1800 + +#define mmNIC9_UMR1_14_UNSECURE_DOORBELL0_BASE 0x1000007FFD8AE000ull +#define NIC9_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC9_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC9_UMR1_14_UNSECURE_DOORBELL1_BASE 0x1000007FFD8AE080ull +#define NIC9_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC9_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC9_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD8AE100ull +#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC9_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD8AE180ull +#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC9_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC9_UMR1_14_SPECIAL_BASE 0x1000007FFD8AEE80ull +#define NIC9_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_UMR1_14_SPECIAL_SECTION 0x1180 + +#define mmNIC9_QM_DCCM1_BASE 0x1000007FFD8B0000ull +#define NIC9_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC9_QM_DCCM1_SECTION 0x8000 + +#define mmNIC9_QM_ARC_AUX1_BASE 0x1000007FFD8B8000ull +#define NIC9_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC9_QM_ARC_AUX1_SECTION 0xE800 + +#define mmNIC9_QM_ARC_AUX1_SPECIAL_BASE 0x1000007FFD8B8E80ull +#define NIC9_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 + +#define mmNIC9_QM1_BASE 0x1000007FFD8BA000ull +#define NIC9_QM1_MAX_OFFSET 0x1000 +#define NIC9_QM1_SECTION 0x9000 + +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFD8BA900ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFD8BA908ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFD8BA910ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFD8BA918ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFD8BA920ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFD8BA928ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFD8BA930ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFD8BA938ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFD8BA940ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFD8BA948ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFD8BA950ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFD8BA958ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFD8BA960ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFD8BA968ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFD8BA970ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmNIC9_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFD8BA978ull +#define NIC9_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC9_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmNIC9_QM1_AXUSER_SECURED_BASE 0x1000007FFD8BAB00ull +#define NIC9_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC9_QM1_AXUSER_SECURED_SECTION 0x8000 + +#define mmNIC9_QM1_AXUSER_NONSECURED_BASE 0x1000007FFD8BAB80ull +#define NIC9_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC9_QM1_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmNIC9_QM1_DBG_HBW_BASE 0x1000007FFD8BAC00ull +#define NIC9_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC9_QM1_DBG_HBW_SECTION 0x8000 + +#define mmNIC9_QM1_DBG_LBW_BASE 0x1000007FFD8BAC80ull +#define NIC9_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC9_QM1_DBG_LBW_SECTION 0x1000 + +#define mmNIC9_QM1_CGM_BASE 0x1000007FFD8BAD80ull +#define NIC9_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC9_QM1_CGM_SECTION 0x1000 + +#define mmNIC9_QM1_SPECIAL_BASE 0x1000007FFD8BAE80ull +#define NIC9_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_QM1_SPECIAL_SECTION 0x4180 + +#define mmNIC9_QPC1_BASE 0x1000007FFD8BF000ull +#define NIC9_QPC1_MAX_OFFSET 0x1000 +#define NIC9_QPC1_SECTION 0x7200 + +#define mmNIC9_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x1000007FFD8BF720ull +#define NIC9_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x1000007FFD8BF728ull +#define NIC9_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x1000007FFD8BF730ull +#define NIC9_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x1000007FFD8BF738ull +#define NIC9_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x1000007FFD8BF740ull +#define NIC9_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x1000007FFD8BF748ull +#define NIC9_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x1000007FFD8BF750ull +#define NIC9_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x1000007FFD8BF758ull +#define NIC9_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x1000007FFD8BF760ull +#define NIC9_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x1000007FFD8BF768ull +#define NIC9_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x1000007FFD8BF770ull +#define NIC9_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x1000007FFD8BF778ull +#define NIC9_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x1000007FFD8BF780ull +#define NIC9_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x1000007FFD8BF788ull +#define NIC9_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x1000007FFD8BF790ull +#define NIC9_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x1000007FFD8BF798ull +#define NIC9_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x1000007FFD8BF7A0ull +#define NIC9_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x1000007FFD8BF7A8ull +#define NIC9_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x1000007FFD8BF7B0ull +#define NIC9_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x1000007FFD8BF7B8ull +#define NIC9_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x1000007FFD8BF7C0ull +#define NIC9_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x1000007FFD8BF7C8ull +#define NIC9_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x1000007FFD8BF7D0ull +#define NIC9_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x1000007FFD8BF7D8ull +#define NIC9_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x1000007FFD8BF7E0ull +#define NIC9_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x1000007FFD8BF7E8ull +#define NIC9_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x1000007FFD8BF7F0ull +#define NIC9_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x1000007FFD8BF7F8ull +#define NIC9_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x1000007FFD8BF800ull +#define NIC9_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x1000007FFD8BF808ull +#define NIC9_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x1000007FFD8BF810ull +#define NIC9_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC9_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x1000007FFD8BF818ull +#define NIC9_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC9_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 + +#define mmNIC9_QPC1_AXUSER_CONG_QUE_BASE 0x1000007FFD8BFB80ull +#define NIC9_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC9_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 + +#define mmNIC9_QPC1_AXUSER_RXWQE_BASE 0x1000007FFD8BFBE0ull +#define NIC9_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC9_QPC1_AXUSER_RXWQE_SECTION 0x6000 + +#define mmNIC9_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x1000007FFD8BFC40ull +#define NIC9_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC9_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 + +#define mmNIC9_QPC1_AXUSER_DB_FIFO_BASE 0x1000007FFD8BFCA0ull +#define NIC9_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC9_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 + +#define mmNIC9_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x1000007FFD8BFD00ull +#define NIC9_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC9_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 + +#define mmNIC9_QPC1_AXUSER_ERR_FIFO_BASE 0x1000007FFD8BFD60ull +#define NIC9_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC9_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 + +#define mmNIC9_QPC1_AXUSER_QPC_RESP_BASE 0x1000007FFD8BFDC0ull +#define NIC9_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC9_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 + +#define mmNIC9_QPC1_AXUSER_QPC_REQ_BASE 0x1000007FFD8BFE20ull +#define NIC9_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC9_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 + +#define mmNIC9_QPC1_SPECIAL_BASE 0x1000007FFD8BFE80ull +#define NIC9_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_QPC1_SPECIAL_SECTION 0x8180 + +#define mmNIC9_TMR_BASE 0x1000007FFD8C8000ull +#define NIC9_TMR_MAX_OFFSET 0x1000 +#define NIC9_TMR_SECTION 0xD600 + +#define mmNIC9_TMR_AXUSER_TMR_FREE_LIST_BASE 0x1000007FFD8C8D60ull +#define NIC9_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC9_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 + +#define mmNIC9_TMR_AXUSER_TMR_FIFO_BASE 0x1000007FFD8C8DC0ull +#define NIC9_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC9_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 + +#define mmNIC9_TMR_AXUSER_TMR_FSM_BASE 0x1000007FFD8C8E20ull +#define NIC9_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC9_TMR_AXUSER_TMR_FSM_SECTION 0x6000 + +#define mmNIC9_TMR_SPECIAL_BASE 0x1000007FFD8C8E80ull +#define NIC9_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_TMR_SPECIAL_SECTION 0x1800 + +#define mmNIC9_RXB_CORE_BASE 0x1000007FFD8C9000ull +#define NIC9_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC9_RXB_CORE_SECTION 0x6100 + +#define mmNIC9_RXB_CORE_SCT_AWUSER_BASE 0x1000007FFD8C9610ull +#define NIC9_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC9_RXB_CORE_SCT_AWUSER_SECTION 0x8700 + +#define mmNIC9_RXB_CORE_SPECIAL_BASE 0x1000007FFD8C9E80ull +#define NIC9_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_RXB_CORE_SPECIAL_SECTION 0x1800 + +#define mmNIC9_RXE0_BASE 0x1000007FFD8CA000ull +#define NIC9_RXE0_MAX_OFFSET 0x1000 +#define NIC9_RXE0_SECTION 0x9000 + +#define mmNIC9_RXE0_WQE_ARUSER_BASE 0x1000007FFD8CA900ull +#define NIC9_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC9_RXE0_WQE_ARUSER_SECTION 0x5800 + +#define mmNIC9_RXE0_SPECIAL_BASE 0x1000007FFD8CAE80ull +#define NIC9_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_RXE0_SPECIAL_SECTION 0x1800 + +#define mmNIC9_RXE1_BASE 0x1000007FFD8CB000ull +#define NIC9_RXE1_MAX_OFFSET 0x1000 +#define NIC9_RXE1_SECTION 0x9000 + +#define mmNIC9_RXE1_WQE_ARUSER_BASE 0x1000007FFD8CB900ull +#define NIC9_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC9_RXE1_WQE_ARUSER_SECTION 0x5800 + +#define mmNIC9_RXE1_SPECIAL_BASE 0x1000007FFD8CBE80ull +#define NIC9_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_RXE1_SPECIAL_SECTION 0x1800 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ0_BASE 0x1000007FFD8CC000ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ1_BASE 0x1000007FFD8CC050ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ2_BASE 0x1000007FFD8CC0A0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ3_BASE 0x1000007FFD8CC0F0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ4_BASE 0x1000007FFD8CC140ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ5_BASE 0x1000007FFD8CC190ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ6_BASE 0x1000007FFD8CC1E0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ7_BASE 0x1000007FFD8CC230ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ8_BASE 0x1000007FFD8CC280ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ9_BASE 0x1000007FFD8CC2D0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ10_BASE 0x1000007FFD8CC320ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ11_BASE 0x1000007FFD8CC370ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ12_BASE 0x1000007FFD8CC3C0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ13_BASE 0x1000007FFD8CC410ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ14_BASE 0x1000007FFD8CC460ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ15_BASE 0x1000007FFD8CC4B0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ16_BASE 0x1000007FFD8CC500ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ17_BASE 0x1000007FFD8CC550ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ18_BASE 0x1000007FFD8CC5A0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ19_BASE 0x1000007FFD8CC5F0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ20_BASE 0x1000007FFD8CC640ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ21_BASE 0x1000007FFD8CC690ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ22_BASE 0x1000007FFD8CC6E0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ23_BASE 0x1000007FFD8CC730ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ24_BASE 0x1000007FFD8CC780ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ25_BASE 0x1000007FFD8CC7D0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ26_BASE 0x1000007FFD8CC820ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ27_BASE 0x1000007FFD8CC870ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ28_BASE 0x1000007FFD8CC8C0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ29_BASE 0x1000007FFD8CC910ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ30_BASE 0x1000007FFD8CC960ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 + +#define mmNIC9_RXE0_AXUSER_AXUSER_CQ31_BASE 0x1000007FFD8CC9B0ull +#define NIC9_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC9_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 + +#define mmNIC9_RXE0_AXUSER_SPECIAL_BASE 0x1000007FFD8CCE80ull +#define NIC9_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_RXE0_AXUSER_SPECIAL_SECTION 0x1800 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ0_BASE 0x1000007FFD8CD000ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ1_BASE 0x1000007FFD8CD050ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ2_BASE 0x1000007FFD8CD0A0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ3_BASE 0x1000007FFD8CD0F0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ4_BASE 0x1000007FFD8CD140ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ5_BASE 0x1000007FFD8CD190ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ6_BASE 0x1000007FFD8CD1E0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ7_BASE 0x1000007FFD8CD230ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ8_BASE 0x1000007FFD8CD280ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ9_BASE 0x1000007FFD8CD2D0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ10_BASE 0x1000007FFD8CD320ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ11_BASE 0x1000007FFD8CD370ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ12_BASE 0x1000007FFD8CD3C0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ13_BASE 0x1000007FFD8CD410ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ14_BASE 0x1000007FFD8CD460ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ15_BASE 0x1000007FFD8CD4B0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ16_BASE 0x1000007FFD8CD500ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ17_BASE 0x1000007FFD8CD550ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ18_BASE 0x1000007FFD8CD5A0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ19_BASE 0x1000007FFD8CD5F0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ20_BASE 0x1000007FFD8CD640ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ21_BASE 0x1000007FFD8CD690ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ22_BASE 0x1000007FFD8CD6E0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ23_BASE 0x1000007FFD8CD730ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ24_BASE 0x1000007FFD8CD780ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ25_BASE 0x1000007FFD8CD7D0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ26_BASE 0x1000007FFD8CD820ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ27_BASE 0x1000007FFD8CD870ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ28_BASE 0x1000007FFD8CD8C0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ29_BASE 0x1000007FFD8CD910ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ30_BASE 0x1000007FFD8CD960ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 + +#define mmNIC9_RXE1_AXUSER_AXUSER_CQ31_BASE 0x1000007FFD8CD9B0ull +#define NIC9_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC9_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 + +#define mmNIC9_RXE1_AXUSER_SPECIAL_BASE 0x1000007FFD8CDE80ull +#define NIC9_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_RXE1_AXUSER_SPECIAL_SECTION 0x2180 + +#define mmNIC9_TXS0_BASE 0x1000007FFD8D0000ull +#define NIC9_TXS0_MAX_OFFSET 0x1000 +#define NIC9_TXS0_SECTION 0xE800 + +#define mmNIC9_TXS0_SPECIAL_BASE 0x1000007FFD8D0E80ull +#define NIC9_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_TXS0_SPECIAL_SECTION 0x1800 + +#define mmNIC9_TXS1_BASE 0x1000007FFD8D1000ull +#define NIC9_TXS1_MAX_OFFSET 0x1000 +#define NIC9_TXS1_SECTION 0xE800 + +#define mmNIC9_TXS1_SPECIAL_BASE 0x1000007FFD8D1E80ull +#define NIC9_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_TXS1_SPECIAL_SECTION 0x1800 + +#define mmNIC9_TXE0_BASE 0x1000007FFD8D2000ull +#define NIC9_TXE0_MAX_OFFSET 0x1000 +#define NIC9_TXE0_SECTION 0xE800 + +#define mmNIC9_TXE0_SPECIAL_BASE 0x1000007FFD8D2E80ull +#define NIC9_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_TXE0_SPECIAL_SECTION 0x1800 + +#define mmNIC9_TXE1_BASE 0x1000007FFD8D3000ull +#define NIC9_TXE1_MAX_OFFSET 0x1000 +#define NIC9_TXE1_SECTION 0xE800 + +#define mmNIC9_TXE1_SPECIAL_BASE 0x1000007FFD8D3E80ull +#define NIC9_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_TXE1_SPECIAL_SECTION 0x1800 + +#define mmNIC9_TXB_BASE 0x1000007FFD8D4000ull +#define NIC9_TXB_MAX_OFFSET 0x1000 +#define NIC9_TXB_SECTION 0xE800 + +#define mmNIC9_TXB_SPECIAL_BASE 0x1000007FFD8D4E80ull +#define NIC9_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_TXB_SPECIAL_SECTION 0x1800 + +#define mmNIC9_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFD8D5000ull +#define NIC9_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC9_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmNIC9_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFD8D5200ull +#define NIC9_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC9_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmNIC9_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFD8D5400ull +#define NIC9_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC9_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmNIC9_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFD8D5600ull +#define NIC9_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC9_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmNIC9_MSTR_IF_E2E_CRDT_BASE 0x1000007FFD8D5800ull +#define NIC9_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC9_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmNIC9_MSTR_IF_AXUSER_BASE 0x1000007FFD8D5A80ull +#define NIC9_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC9_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmNIC9_MSTR_IF_DBG_HBW_BASE 0x1000007FFD8D5B00ull +#define NIC9_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC9_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmNIC9_MSTR_IF_DBG_LBW_BASE 0x1000007FFD8D5B80ull +#define NIC9_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC9_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmNIC9_MSTR_IF_CORE_HBW_BASE 0x1000007FFD8D5C00ull +#define NIC9_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC9_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmNIC9_MSTR_IF_CORE_LBW_BASE 0x1000007FFD8D5D80ull +#define NIC9_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC9_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmNIC9_MSTR_IF_SPECIAL_BASE 0x1000007FFD8D5E80ull +#define NIC9_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmNIC9_TX_AXUSER_BASE 0x1000007FFD8D6000ull +#define NIC9_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC9_TX_AXUSER_SECTION 0x2000 + +#define mmNIC9_SERDES0_BASE 0x1000007FFD8D8000ull +#define NIC9_SERDES0_MAX_OFFSET 0x3E40 +#define NIC9_SERDES0_SECTION 0x4000 + +#define mmNIC9_SERDES1_BASE 0x1000007FFD8DC000ull +#define NIC9_SERDES1_MAX_OFFSET 0x3E40 +#define NIC9_SERDES1_SECTION 0x4000 + +#define mmNIC9_PHY_BASE 0x1000007FFD8E0000ull +#define NIC9_PHY_MAX_OFFSET 0x1000 +#define NIC9_PHY_SECTION 0xE800 + +#define mmNIC9_PHY_SPECIAL_BASE 0x1000007FFD8E0E80ull +#define NIC9_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC9_PHY_SPECIAL_SECTION 0x7180 + +#define mmPRT9_MAC_AUX_BASE 0x1000007FFD8E8000ull +#define PRT9_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT9_MAC_AUX_SECTION 0xE800 + +#define mmPRT9_MAC_AUX_SPECIAL_BASE 0x1000007FFD8E8E80ull +#define PRT9_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT9_MAC_AUX_SPECIAL_SECTION 0x1800 + +#define mmPRT9_MAC_CORE_BASE 0x1000007FFD8E9000ull +#define PRT9_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT9_MAC_CORE_SECTION 0xE800 + +#define mmPRT9_MAC_CORE_SPECIAL_BASE 0x1000007FFD8E9E80ull +#define PRT9_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT9_MAC_CORE_SPECIAL_SECTION 0x1800 + +#define mmNIC9_MAC_RS_FEC_BASE 0x1000007FFD8EA000ull +#define NIC9_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC9_MAC_RS_FEC_SECTION 0x1000 + +#define mmNIC9_MAC_GLOB_STAT_NIC_MAC_STAT_BASE 0x1000007FFD8EB000ull +#define NIC9_MAC_GLOB_STAT_NIC_MAC_STAT_MAX_OFFSET 0x4D00 +#define NIC9_MAC_GLOB_STAT_NIC_MAC_STAT_SECTION 0x8000 + +#define mmNIC9_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_BASE 0x1000007FFD8EB800ull +#define NIC9_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC9_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_SECTION 0x8000 + +#define mmNIC9_MAC_CH0_MAC_PCS_BASE 0x1000007FFD8EC000ull +#define NIC9_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC9_MAC_CH0_MAC_PCS_SECTION 0x4000 + +#define mmNIC9_MAC_CH0_MAC_128_BASE 0x1000007FFD8EC400ull +#define NIC9_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC9_MAC_CH0_MAC_128_SECTION 0x4000 + +#define mmNIC9_MAC_CH0_MAC_AN_BASE 0x1000007FFD8EC800ull +#define NIC9_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC9_MAC_CH0_MAC_AN_SECTION 0x8000 + +#define mmNIC9_MAC_CH1_MAC_PCS_BASE 0x1000007FFD8ED000ull +#define NIC9_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC9_MAC_CH1_MAC_PCS_SECTION 0x4000 + +#define mmNIC9_MAC_CH1_MAC_128_BASE 0x1000007FFD8ED400ull +#define NIC9_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC9_MAC_CH1_MAC_128_SECTION 0x4000 + +#define mmNIC9_MAC_CH1_MAC_AN_BASE 0x1000007FFD8ED800ull +#define NIC9_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC9_MAC_CH1_MAC_AN_SECTION 0x8000 + +#define mmNIC9_MAC_CH2_MAC_PCS_BASE 0x1000007FFD8EE000ull +#define NIC9_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC9_MAC_CH2_MAC_PCS_SECTION 0x4000 + +#define mmNIC9_MAC_CH2_MAC_128_BASE 0x1000007FFD8EE400ull +#define NIC9_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC9_MAC_CH2_MAC_128_SECTION 0x4000 + +#define mmNIC9_MAC_CH2_MAC_AN_BASE 0x1000007FFD8EE800ull +#define NIC9_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC9_MAC_CH2_MAC_AN_SECTION 0x8000 + +#define mmNIC9_MAC_CH3_MAC_PCS_BASE 0x1000007FFD8EF000ull +#define NIC9_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC9_MAC_CH3_MAC_PCS_SECTION 0x4000 + +#define mmNIC9_MAC_CH3_MAC_128_BASE 0x1000007FFD8EF400ull +#define NIC9_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC9_MAC_CH3_MAC_128_SECTION 0x4000 + +#define mmNIC9_MAC_CH3_MAC_AN_BASE 0x1000007FFD8EF800ull +#define NIC9_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC9_MAC_CH3_MAC_AN_SECTION 0x10800 + +#define mmNIC10_UMR0_0_UNSECURE_DOORBELL0_BASE 0x1000007FFD900000ull +#define NIC10_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR0_0_UNSECURE_DOORBELL1_BASE 0x1000007FFD900080ull +#define NIC10_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD900100ull +#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD900180ull +#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR0_0_SPECIAL_BASE 0x1000007FFD900E80ull +#define NIC10_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_0_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR0_1_UNSECURE_DOORBELL0_BASE 0x1000007FFD901000ull +#define NIC10_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR0_1_UNSECURE_DOORBELL1_BASE 0x1000007FFD901080ull +#define NIC10_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD901100ull +#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD901180ull +#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR0_1_SPECIAL_BASE 0x1000007FFD901E80ull +#define NIC10_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_1_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR0_2_UNSECURE_DOORBELL0_BASE 0x1000007FFD902000ull +#define NIC10_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR0_2_UNSECURE_DOORBELL1_BASE 0x1000007FFD902080ull +#define NIC10_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD902100ull +#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD902180ull +#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR0_2_SPECIAL_BASE 0x1000007FFD902E80ull +#define NIC10_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_2_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR0_3_UNSECURE_DOORBELL0_BASE 0x1000007FFD903000ull +#define NIC10_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR0_3_UNSECURE_DOORBELL1_BASE 0x1000007FFD903080ull +#define NIC10_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD903100ull +#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD903180ull +#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR0_3_SPECIAL_BASE 0x1000007FFD903E80ull +#define NIC10_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_3_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR0_4_UNSECURE_DOORBELL0_BASE 0x1000007FFD904000ull +#define NIC10_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR0_4_UNSECURE_DOORBELL1_BASE 0x1000007FFD904080ull +#define NIC10_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD904100ull +#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD904180ull +#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR0_4_SPECIAL_BASE 0x1000007FFD904E80ull +#define NIC10_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_4_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR0_5_UNSECURE_DOORBELL0_BASE 0x1000007FFD905000ull +#define NIC10_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR0_5_UNSECURE_DOORBELL1_BASE 0x1000007FFD905080ull +#define NIC10_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD905100ull +#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD905180ull +#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR0_5_SPECIAL_BASE 0x1000007FFD905E80ull +#define NIC10_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_5_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR0_6_UNSECURE_DOORBELL0_BASE 0x1000007FFD906000ull +#define NIC10_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR0_6_UNSECURE_DOORBELL1_BASE 0x1000007FFD906080ull +#define NIC10_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD906100ull +#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD906180ull +#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR0_6_SPECIAL_BASE 0x1000007FFD906E80ull +#define NIC10_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_6_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR0_7_UNSECURE_DOORBELL0_BASE 0x1000007FFD907000ull +#define NIC10_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR0_7_UNSECURE_DOORBELL1_BASE 0x1000007FFD907080ull +#define NIC10_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD907100ull +#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD907180ull +#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR0_7_SPECIAL_BASE 0x1000007FFD907E80ull +#define NIC10_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_7_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR0_8_UNSECURE_DOORBELL0_BASE 0x1000007FFD908000ull +#define NIC10_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR0_8_UNSECURE_DOORBELL1_BASE 0x1000007FFD908080ull +#define NIC10_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD908100ull +#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD908180ull +#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR0_8_SPECIAL_BASE 0x1000007FFD908E80ull +#define NIC10_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_8_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR0_9_UNSECURE_DOORBELL0_BASE 0x1000007FFD909000ull +#define NIC10_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR0_9_UNSECURE_DOORBELL1_BASE 0x1000007FFD909080ull +#define NIC10_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD909100ull +#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD909180ull +#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR0_9_SPECIAL_BASE 0x1000007FFD909E80ull +#define NIC10_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_9_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR0_10_UNSECURE_DOORBELL0_BASE 0x1000007FFD90A000ull +#define NIC10_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR0_10_UNSECURE_DOORBELL1_BASE 0x1000007FFD90A080ull +#define NIC10_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD90A100ull +#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD90A180ull +#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR0_10_SPECIAL_BASE 0x1000007FFD90AE80ull +#define NIC10_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_10_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR0_11_UNSECURE_DOORBELL0_BASE 0x1000007FFD90B000ull +#define NIC10_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR0_11_UNSECURE_DOORBELL1_BASE 0x1000007FFD90B080ull +#define NIC10_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD90B100ull +#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD90B180ull +#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR0_11_SPECIAL_BASE 0x1000007FFD90BE80ull +#define NIC10_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_11_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR0_12_UNSECURE_DOORBELL0_BASE 0x1000007FFD90C000ull +#define NIC10_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR0_12_UNSECURE_DOORBELL1_BASE 0x1000007FFD90C080ull +#define NIC10_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD90C100ull +#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD90C180ull +#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR0_12_SPECIAL_BASE 0x1000007FFD90CE80ull +#define NIC10_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_12_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR0_13_UNSECURE_DOORBELL0_BASE 0x1000007FFD90D000ull +#define NIC10_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR0_13_UNSECURE_DOORBELL1_BASE 0x1000007FFD90D080ull +#define NIC10_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD90D100ull +#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD90D180ull +#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR0_13_SPECIAL_BASE 0x1000007FFD90DE80ull +#define NIC10_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_13_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR0_14_UNSECURE_DOORBELL0_BASE 0x1000007FFD90E000ull +#define NIC10_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR0_14_UNSECURE_DOORBELL1_BASE 0x1000007FFD90E080ull +#define NIC10_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD90E100ull +#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD90E180ull +#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR0_14_SPECIAL_BASE 0x1000007FFD90EE80ull +#define NIC10_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR0_14_SPECIAL_SECTION 0x1180 + +#define mmNIC10_QM_DCCM0_BASE 0x1000007FFD910000ull +#define NIC10_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC10_QM_DCCM0_SECTION 0x8000 + +#define mmNIC10_QM_ARC_AUX0_BASE 0x1000007FFD918000ull +#define NIC10_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC10_QM_ARC_AUX0_SECTION 0xE800 + +#define mmNIC10_QM_ARC_AUX0_SPECIAL_BASE 0x1000007FFD918E80ull +#define NIC10_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 + +#define mmNIC10_QM0_BASE 0x1000007FFD91A000ull +#define NIC10_QM0_MAX_OFFSET 0x1000 +#define NIC10_QM0_SECTION 0x9000 + +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFD91A900ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFD91A908ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFD91A910ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFD91A918ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFD91A920ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFD91A928ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFD91A930ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFD91A938ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFD91A940ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFD91A948ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFD91A950ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFD91A958ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFD91A960ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFD91A968ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFD91A970ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmNIC10_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFD91A978ull +#define NIC10_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC10_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmNIC10_QM0_AXUSER_SECURED_BASE 0x1000007FFD91AB00ull +#define NIC10_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC10_QM0_AXUSER_SECURED_SECTION 0x8000 + +#define mmNIC10_QM0_AXUSER_NONSECURED_BASE 0x1000007FFD91AB80ull +#define NIC10_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC10_QM0_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmNIC10_QM0_DBG_HBW_BASE 0x1000007FFD91AC00ull +#define NIC10_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC10_QM0_DBG_HBW_SECTION 0x8000 + +#define mmNIC10_QM0_DBG_LBW_BASE 0x1000007FFD91AC80ull +#define NIC10_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC10_QM0_DBG_LBW_SECTION 0x1000 + +#define mmNIC10_QM0_CGM_BASE 0x1000007FFD91AD80ull +#define NIC10_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC10_QM0_CGM_SECTION 0x1000 + +#define mmNIC10_QM0_SPECIAL_BASE 0x1000007FFD91AE80ull +#define NIC10_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_QM0_SPECIAL_SECTION 0x4180 + +#define mmNIC10_QPC0_BASE 0x1000007FFD91F000ull +#define NIC10_QPC0_MAX_OFFSET 0x1000 +#define NIC10_QPC0_SECTION 0x7200 + +#define mmNIC10_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x1000007FFD91F720ull +#define NIC10_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x1000007FFD91F728ull +#define NIC10_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x1000007FFD91F730ull +#define NIC10_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x1000007FFD91F738ull +#define NIC10_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x1000007FFD91F740ull +#define NIC10_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x1000007FFD91F748ull +#define NIC10_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x1000007FFD91F750ull +#define NIC10_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x1000007FFD91F758ull +#define NIC10_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x1000007FFD91F760ull +#define NIC10_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x1000007FFD91F768ull +#define NIC10_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x1000007FFD91F770ull +#define NIC10_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x1000007FFD91F778ull +#define NIC10_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x1000007FFD91F780ull +#define NIC10_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x1000007FFD91F788ull +#define NIC10_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x1000007FFD91F790ull +#define NIC10_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x1000007FFD91F798ull +#define NIC10_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x1000007FFD91F7A0ull +#define NIC10_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x1000007FFD91F7A8ull +#define NIC10_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x1000007FFD91F7B0ull +#define NIC10_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x1000007FFD91F7B8ull +#define NIC10_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x1000007FFD91F7C0ull +#define NIC10_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x1000007FFD91F7C8ull +#define NIC10_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x1000007FFD91F7D0ull +#define NIC10_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x1000007FFD91F7D8ull +#define NIC10_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x1000007FFD91F7E0ull +#define NIC10_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x1000007FFD91F7E8ull +#define NIC10_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x1000007FFD91F7F0ull +#define NIC10_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x1000007FFD91F7F8ull +#define NIC10_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x1000007FFD91F800ull +#define NIC10_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x1000007FFD91F808ull +#define NIC10_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x1000007FFD91F810ull +#define NIC10_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x1000007FFD91F818ull +#define NIC10_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 + +#define mmNIC10_QPC0_AXUSER_CONG_QUE_BASE 0x1000007FFD91FB80ull +#define NIC10_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC10_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 + +#define mmNIC10_QPC0_AXUSER_RXWQE_BASE 0x1000007FFD91FBE0ull +#define NIC10_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC10_QPC0_AXUSER_RXWQE_SECTION 0x6000 + +#define mmNIC10_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x1000007FFD91FC40ull +#define NIC10_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC10_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 + +#define mmNIC10_QPC0_AXUSER_DB_FIFO_BASE 0x1000007FFD91FCA0ull +#define NIC10_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC10_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 + +#define mmNIC10_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x1000007FFD91FD00ull +#define NIC10_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC10_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 + +#define mmNIC10_QPC0_AXUSER_ERR_FIFO_BASE 0x1000007FFD91FD60ull +#define NIC10_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC10_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 + +#define mmNIC10_QPC0_AXUSER_QPC_RESP_BASE 0x1000007FFD91FDC0ull +#define NIC10_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC10_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 + +#define mmNIC10_QPC0_AXUSER_QPC_REQ_BASE 0x1000007FFD91FE20ull +#define NIC10_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC10_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 + +#define mmNIC10_QPC0_SPECIAL_BASE 0x1000007FFD91FE80ull +#define NIC10_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_QPC0_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR1_0_UNSECURE_DOORBELL0_BASE 0x1000007FFD920000ull +#define NIC10_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR1_0_UNSECURE_DOORBELL1_BASE 0x1000007FFD920080ull +#define NIC10_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD920100ull +#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD920180ull +#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR1_0_SPECIAL_BASE 0x1000007FFD920E80ull +#define NIC10_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_0_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR1_1_UNSECURE_DOORBELL0_BASE 0x1000007FFD921000ull +#define NIC10_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR1_1_UNSECURE_DOORBELL1_BASE 0x1000007FFD921080ull +#define NIC10_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD921100ull +#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD921180ull +#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR1_1_SPECIAL_BASE 0x1000007FFD921E80ull +#define NIC10_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_1_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR1_2_UNSECURE_DOORBELL0_BASE 0x1000007FFD922000ull +#define NIC10_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR1_2_UNSECURE_DOORBELL1_BASE 0x1000007FFD922080ull +#define NIC10_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD922100ull +#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD922180ull +#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR1_2_SPECIAL_BASE 0x1000007FFD922E80ull +#define NIC10_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_2_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR1_3_UNSECURE_DOORBELL0_BASE 0x1000007FFD923000ull +#define NIC10_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR1_3_UNSECURE_DOORBELL1_BASE 0x1000007FFD923080ull +#define NIC10_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD923100ull +#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD923180ull +#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR1_3_SPECIAL_BASE 0x1000007FFD923E80ull +#define NIC10_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_3_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR1_4_UNSECURE_DOORBELL0_BASE 0x1000007FFD924000ull +#define NIC10_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR1_4_UNSECURE_DOORBELL1_BASE 0x1000007FFD924080ull +#define NIC10_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD924100ull +#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD924180ull +#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR1_4_SPECIAL_BASE 0x1000007FFD924E80ull +#define NIC10_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_4_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR1_5_UNSECURE_DOORBELL0_BASE 0x1000007FFD925000ull +#define NIC10_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR1_5_UNSECURE_DOORBELL1_BASE 0x1000007FFD925080ull +#define NIC10_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD925100ull +#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD925180ull +#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR1_5_SPECIAL_BASE 0x1000007FFD925E80ull +#define NIC10_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_5_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR1_6_UNSECURE_DOORBELL0_BASE 0x1000007FFD926000ull +#define NIC10_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR1_6_UNSECURE_DOORBELL1_BASE 0x1000007FFD926080ull +#define NIC10_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD926100ull +#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD926180ull +#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR1_6_SPECIAL_BASE 0x1000007FFD926E80ull +#define NIC10_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_6_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR1_7_UNSECURE_DOORBELL0_BASE 0x1000007FFD927000ull +#define NIC10_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR1_7_UNSECURE_DOORBELL1_BASE 0x1000007FFD927080ull +#define NIC10_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD927100ull +#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD927180ull +#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR1_7_SPECIAL_BASE 0x1000007FFD927E80ull +#define NIC10_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_7_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR1_8_UNSECURE_DOORBELL0_BASE 0x1000007FFD928000ull +#define NIC10_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR1_8_UNSECURE_DOORBELL1_BASE 0x1000007FFD928080ull +#define NIC10_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD928100ull +#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD928180ull +#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR1_8_SPECIAL_BASE 0x1000007FFD928E80ull +#define NIC10_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_8_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR1_9_UNSECURE_DOORBELL0_BASE 0x1000007FFD929000ull +#define NIC10_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR1_9_UNSECURE_DOORBELL1_BASE 0x1000007FFD929080ull +#define NIC10_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD929100ull +#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD929180ull +#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR1_9_SPECIAL_BASE 0x1000007FFD929E80ull +#define NIC10_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_9_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR1_10_UNSECURE_DOORBELL0_BASE 0x1000007FFD92A000ull +#define NIC10_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR1_10_UNSECURE_DOORBELL1_BASE 0x1000007FFD92A080ull +#define NIC10_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD92A100ull +#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD92A180ull +#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR1_10_SPECIAL_BASE 0x1000007FFD92AE80ull +#define NIC10_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_10_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR1_11_UNSECURE_DOORBELL0_BASE 0x1000007FFD92B000ull +#define NIC10_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR1_11_UNSECURE_DOORBELL1_BASE 0x1000007FFD92B080ull +#define NIC10_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD92B100ull +#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD92B180ull +#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR1_11_SPECIAL_BASE 0x1000007FFD92BE80ull +#define NIC10_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_11_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR1_12_UNSECURE_DOORBELL0_BASE 0x1000007FFD92C000ull +#define NIC10_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR1_12_UNSECURE_DOORBELL1_BASE 0x1000007FFD92C080ull +#define NIC10_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD92C100ull +#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD92C180ull +#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR1_12_SPECIAL_BASE 0x1000007FFD92CE80ull +#define NIC10_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_12_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR1_13_UNSECURE_DOORBELL0_BASE 0x1000007FFD92D000ull +#define NIC10_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR1_13_UNSECURE_DOORBELL1_BASE 0x1000007FFD92D080ull +#define NIC10_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD92D100ull +#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD92D180ull +#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR1_13_SPECIAL_BASE 0x1000007FFD92DE80ull +#define NIC10_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_13_SPECIAL_SECTION 0x1800 + +#define mmNIC10_UMR1_14_UNSECURE_DOORBELL0_BASE 0x1000007FFD92E000ull +#define NIC10_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC10_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC10_UMR1_14_UNSECURE_DOORBELL1_BASE 0x1000007FFD92E080ull +#define NIC10_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC10_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC10_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD92E100ull +#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC10_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD92E180ull +#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC10_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC10_UMR1_14_SPECIAL_BASE 0x1000007FFD92EE80ull +#define NIC10_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_UMR1_14_SPECIAL_SECTION 0x1180 + +#define mmNIC10_QM_DCCM1_BASE 0x1000007FFD930000ull +#define NIC10_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC10_QM_DCCM1_SECTION 0x8000 + +#define mmNIC10_QM_ARC_AUX1_BASE 0x1000007FFD938000ull +#define NIC10_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC10_QM_ARC_AUX1_SECTION 0xE800 + +#define mmNIC10_QM_ARC_AUX1_SPECIAL_BASE 0x1000007FFD938E80ull +#define NIC10_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 + +#define mmNIC10_QM1_BASE 0x1000007FFD93A000ull +#define NIC10_QM1_MAX_OFFSET 0x1000 +#define NIC10_QM1_SECTION 0x9000 + +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFD93A900ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFD93A908ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFD93A910ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFD93A918ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFD93A920ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFD93A928ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFD93A930ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFD93A938ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFD93A940ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFD93A948ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFD93A950ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFD93A958ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFD93A960ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFD93A968ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFD93A970ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmNIC10_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFD93A978ull +#define NIC10_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC10_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmNIC10_QM1_AXUSER_SECURED_BASE 0x1000007FFD93AB00ull +#define NIC10_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC10_QM1_AXUSER_SECURED_SECTION 0x8000 + +#define mmNIC10_QM1_AXUSER_NONSECURED_BASE 0x1000007FFD93AB80ull +#define NIC10_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC10_QM1_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmNIC10_QM1_DBG_HBW_BASE 0x1000007FFD93AC00ull +#define NIC10_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC10_QM1_DBG_HBW_SECTION 0x8000 + +#define mmNIC10_QM1_DBG_LBW_BASE 0x1000007FFD93AC80ull +#define NIC10_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC10_QM1_DBG_LBW_SECTION 0x1000 + +#define mmNIC10_QM1_CGM_BASE 0x1000007FFD93AD80ull +#define NIC10_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC10_QM1_CGM_SECTION 0x1000 + +#define mmNIC10_QM1_SPECIAL_BASE 0x1000007FFD93AE80ull +#define NIC10_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_QM1_SPECIAL_SECTION 0x4180 + +#define mmNIC10_QPC1_BASE 0x1000007FFD93F000ull +#define NIC10_QPC1_MAX_OFFSET 0x1000 +#define NIC10_QPC1_SECTION 0x7200 + +#define mmNIC10_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x1000007FFD93F720ull +#define NIC10_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x1000007FFD93F728ull +#define NIC10_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x1000007FFD93F730ull +#define NIC10_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x1000007FFD93F738ull +#define NIC10_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x1000007FFD93F740ull +#define NIC10_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x1000007FFD93F748ull +#define NIC10_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x1000007FFD93F750ull +#define NIC10_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x1000007FFD93F758ull +#define NIC10_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x1000007FFD93F760ull +#define NIC10_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x1000007FFD93F768ull +#define NIC10_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x1000007FFD93F770ull +#define NIC10_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x1000007FFD93F778ull +#define NIC10_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x1000007FFD93F780ull +#define NIC10_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x1000007FFD93F788ull +#define NIC10_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x1000007FFD93F790ull +#define NIC10_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x1000007FFD93F798ull +#define NIC10_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x1000007FFD93F7A0ull +#define NIC10_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x1000007FFD93F7A8ull +#define NIC10_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x1000007FFD93F7B0ull +#define NIC10_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x1000007FFD93F7B8ull +#define NIC10_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x1000007FFD93F7C0ull +#define NIC10_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x1000007FFD93F7C8ull +#define NIC10_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x1000007FFD93F7D0ull +#define NIC10_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x1000007FFD93F7D8ull +#define NIC10_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x1000007FFD93F7E0ull +#define NIC10_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x1000007FFD93F7E8ull +#define NIC10_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x1000007FFD93F7F0ull +#define NIC10_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x1000007FFD93F7F8ull +#define NIC10_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x1000007FFD93F800ull +#define NIC10_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x1000007FFD93F808ull +#define NIC10_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x1000007FFD93F810ull +#define NIC10_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC10_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x1000007FFD93F818ull +#define NIC10_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC10_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 + +#define mmNIC10_QPC1_AXUSER_CONG_QUE_BASE 0x1000007FFD93FB80ull +#define NIC10_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC10_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 + +#define mmNIC10_QPC1_AXUSER_RXWQE_BASE 0x1000007FFD93FBE0ull +#define NIC10_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC10_QPC1_AXUSER_RXWQE_SECTION 0x6000 + +#define mmNIC10_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x1000007FFD93FC40ull +#define NIC10_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC10_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 + +#define mmNIC10_QPC1_AXUSER_DB_FIFO_BASE 0x1000007FFD93FCA0ull +#define NIC10_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC10_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 + +#define mmNIC10_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x1000007FFD93FD00ull +#define NIC10_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC10_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 + +#define mmNIC10_QPC1_AXUSER_ERR_FIFO_BASE 0x1000007FFD93FD60ull +#define NIC10_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC10_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 + +#define mmNIC10_QPC1_AXUSER_QPC_RESP_BASE 0x1000007FFD93FDC0ull +#define NIC10_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC10_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 + +#define mmNIC10_QPC1_AXUSER_QPC_REQ_BASE 0x1000007FFD93FE20ull +#define NIC10_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC10_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 + +#define mmNIC10_QPC1_SPECIAL_BASE 0x1000007FFD93FE80ull +#define NIC10_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_QPC1_SPECIAL_SECTION 0x8180 + +#define mmNIC10_TMR_BASE 0x1000007FFD948000ull +#define NIC10_TMR_MAX_OFFSET 0x1000 +#define NIC10_TMR_SECTION 0xD600 + +#define mmNIC10_TMR_AXUSER_TMR_FREE_LIST_BASE 0x1000007FFD948D60ull +#define NIC10_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC10_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 + +#define mmNIC10_TMR_AXUSER_TMR_FIFO_BASE 0x1000007FFD948DC0ull +#define NIC10_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC10_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 + +#define mmNIC10_TMR_AXUSER_TMR_FSM_BASE 0x1000007FFD948E20ull +#define NIC10_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC10_TMR_AXUSER_TMR_FSM_SECTION 0x6000 + +#define mmNIC10_TMR_SPECIAL_BASE 0x1000007FFD948E80ull +#define NIC10_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_TMR_SPECIAL_SECTION 0x1800 + +#define mmNIC10_RXB_CORE_BASE 0x1000007FFD949000ull +#define NIC10_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC10_RXB_CORE_SECTION 0x6100 + +#define mmNIC10_RXB_CORE_SCT_AWUSER_BASE 0x1000007FFD949610ull +#define NIC10_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC10_RXB_CORE_SCT_AWUSER_SECTION 0x8700 + +#define mmNIC10_RXB_CORE_SPECIAL_BASE 0x1000007FFD949E80ull +#define NIC10_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_RXB_CORE_SPECIAL_SECTION 0x1800 + +#define mmNIC10_RXE0_BASE 0x1000007FFD94A000ull +#define NIC10_RXE0_MAX_OFFSET 0x1000 +#define NIC10_RXE0_SECTION 0x9000 + +#define mmNIC10_RXE0_WQE_ARUSER_BASE 0x1000007FFD94A900ull +#define NIC10_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC10_RXE0_WQE_ARUSER_SECTION 0x5800 + +#define mmNIC10_RXE0_SPECIAL_BASE 0x1000007FFD94AE80ull +#define NIC10_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_RXE0_SPECIAL_SECTION 0x1800 + +#define mmNIC10_RXE1_BASE 0x1000007FFD94B000ull +#define NIC10_RXE1_MAX_OFFSET 0x1000 +#define NIC10_RXE1_SECTION 0x9000 + +#define mmNIC10_RXE1_WQE_ARUSER_BASE 0x1000007FFD94B900ull +#define NIC10_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC10_RXE1_WQE_ARUSER_SECTION 0x5800 + +#define mmNIC10_RXE1_SPECIAL_BASE 0x1000007FFD94BE80ull +#define NIC10_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_RXE1_SPECIAL_SECTION 0x1800 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ0_BASE 0x1000007FFD94C000ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ1_BASE 0x1000007FFD94C050ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ2_BASE 0x1000007FFD94C0A0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ3_BASE 0x1000007FFD94C0F0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ4_BASE 0x1000007FFD94C140ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ5_BASE 0x1000007FFD94C190ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ6_BASE 0x1000007FFD94C1E0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ7_BASE 0x1000007FFD94C230ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ8_BASE 0x1000007FFD94C280ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ9_BASE 0x1000007FFD94C2D0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ10_BASE 0x1000007FFD94C320ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ11_BASE 0x1000007FFD94C370ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ12_BASE 0x1000007FFD94C3C0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ13_BASE 0x1000007FFD94C410ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ14_BASE 0x1000007FFD94C460ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ15_BASE 0x1000007FFD94C4B0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ16_BASE 0x1000007FFD94C500ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ17_BASE 0x1000007FFD94C550ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ18_BASE 0x1000007FFD94C5A0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ19_BASE 0x1000007FFD94C5F0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ20_BASE 0x1000007FFD94C640ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ21_BASE 0x1000007FFD94C690ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ22_BASE 0x1000007FFD94C6E0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ23_BASE 0x1000007FFD94C730ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ24_BASE 0x1000007FFD94C780ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ25_BASE 0x1000007FFD94C7D0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ26_BASE 0x1000007FFD94C820ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ27_BASE 0x1000007FFD94C870ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ28_BASE 0x1000007FFD94C8C0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ29_BASE 0x1000007FFD94C910ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ30_BASE 0x1000007FFD94C960ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 + +#define mmNIC10_RXE0_AXUSER_AXUSER_CQ31_BASE 0x1000007FFD94C9B0ull +#define NIC10_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC10_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 + +#define mmNIC10_RXE0_AXUSER_SPECIAL_BASE 0x1000007FFD94CE80ull +#define NIC10_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_RXE0_AXUSER_SPECIAL_SECTION 0x1800 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ0_BASE 0x1000007FFD94D000ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ1_BASE 0x1000007FFD94D050ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ2_BASE 0x1000007FFD94D0A0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ3_BASE 0x1000007FFD94D0F0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ4_BASE 0x1000007FFD94D140ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ5_BASE 0x1000007FFD94D190ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ6_BASE 0x1000007FFD94D1E0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ7_BASE 0x1000007FFD94D230ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ8_BASE 0x1000007FFD94D280ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ9_BASE 0x1000007FFD94D2D0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ10_BASE 0x1000007FFD94D320ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ11_BASE 0x1000007FFD94D370ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ12_BASE 0x1000007FFD94D3C0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ13_BASE 0x1000007FFD94D410ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ14_BASE 0x1000007FFD94D460ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ15_BASE 0x1000007FFD94D4B0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ16_BASE 0x1000007FFD94D500ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ17_BASE 0x1000007FFD94D550ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ18_BASE 0x1000007FFD94D5A0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ19_BASE 0x1000007FFD94D5F0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ20_BASE 0x1000007FFD94D640ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ21_BASE 0x1000007FFD94D690ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ22_BASE 0x1000007FFD94D6E0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ23_BASE 0x1000007FFD94D730ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ24_BASE 0x1000007FFD94D780ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ25_BASE 0x1000007FFD94D7D0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ26_BASE 0x1000007FFD94D820ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ27_BASE 0x1000007FFD94D870ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ28_BASE 0x1000007FFD94D8C0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ29_BASE 0x1000007FFD94D910ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ30_BASE 0x1000007FFD94D960ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 + +#define mmNIC10_RXE1_AXUSER_AXUSER_CQ31_BASE 0x1000007FFD94D9B0ull +#define NIC10_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC10_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 + +#define mmNIC10_RXE1_AXUSER_SPECIAL_BASE 0x1000007FFD94DE80ull +#define NIC10_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_RXE1_AXUSER_SPECIAL_SECTION 0x2180 + +#define mmNIC10_TXS0_BASE 0x1000007FFD950000ull +#define NIC10_TXS0_MAX_OFFSET 0x1000 +#define NIC10_TXS0_SECTION 0xE800 + +#define mmNIC10_TXS0_SPECIAL_BASE 0x1000007FFD950E80ull +#define NIC10_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_TXS0_SPECIAL_SECTION 0x1800 + +#define mmNIC10_TXS1_BASE 0x1000007FFD951000ull +#define NIC10_TXS1_MAX_OFFSET 0x1000 +#define NIC10_TXS1_SECTION 0xE800 + +#define mmNIC10_TXS1_SPECIAL_BASE 0x1000007FFD951E80ull +#define NIC10_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_TXS1_SPECIAL_SECTION 0x1800 + +#define mmNIC10_TXE0_BASE 0x1000007FFD952000ull +#define NIC10_TXE0_MAX_OFFSET 0x1000 +#define NIC10_TXE0_SECTION 0xE800 + +#define mmNIC10_TXE0_SPECIAL_BASE 0x1000007FFD952E80ull +#define NIC10_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_TXE0_SPECIAL_SECTION 0x1800 + +#define mmNIC10_TXE1_BASE 0x1000007FFD953000ull +#define NIC10_TXE1_MAX_OFFSET 0x1000 +#define NIC10_TXE1_SECTION 0xE800 + +#define mmNIC10_TXE1_SPECIAL_BASE 0x1000007FFD953E80ull +#define NIC10_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_TXE1_SPECIAL_SECTION 0x1800 + +#define mmNIC10_TXB_BASE 0x1000007FFD954000ull +#define NIC10_TXB_MAX_OFFSET 0x1000 +#define NIC10_TXB_SECTION 0xE800 + +#define mmNIC10_TXB_SPECIAL_BASE 0x1000007FFD954E80ull +#define NIC10_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_TXB_SPECIAL_SECTION 0x1800 + +#define mmNIC10_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFD955000ull +#define NIC10_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC10_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmNIC10_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFD955200ull +#define NIC10_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC10_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmNIC10_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFD955400ull +#define NIC10_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC10_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmNIC10_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFD955600ull +#define NIC10_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC10_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmNIC10_MSTR_IF_E2E_CRDT_BASE 0x1000007FFD955800ull +#define NIC10_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC10_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmNIC10_MSTR_IF_AXUSER_BASE 0x1000007FFD955A80ull +#define NIC10_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC10_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmNIC10_MSTR_IF_DBG_HBW_BASE 0x1000007FFD955B00ull +#define NIC10_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC10_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmNIC10_MSTR_IF_DBG_LBW_BASE 0x1000007FFD955B80ull +#define NIC10_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC10_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmNIC10_MSTR_IF_CORE_HBW_BASE 0x1000007FFD955C00ull +#define NIC10_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC10_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmNIC10_MSTR_IF_CORE_LBW_BASE 0x1000007FFD955D80ull +#define NIC10_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC10_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmNIC10_MSTR_IF_SPECIAL_BASE 0x1000007FFD955E80ull +#define NIC10_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmNIC10_TX_AXUSER_BASE 0x1000007FFD956000ull +#define NIC10_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC10_TX_AXUSER_SECTION 0x2000 + +#define mmNIC10_SERDES0_BASE 0x1000007FFD958000ull +#define NIC10_SERDES0_MAX_OFFSET 0x3E40 +#define NIC10_SERDES0_SECTION 0x4000 + +#define mmNIC10_SERDES1_BASE 0x1000007FFD95C000ull +#define NIC10_SERDES1_MAX_OFFSET 0x3E40 +#define NIC10_SERDES1_SECTION 0x4000 + +#define mmNIC10_PHY_BASE 0x1000007FFD960000ull +#define NIC10_PHY_MAX_OFFSET 0x1000 +#define NIC10_PHY_SECTION 0xE800 + +#define mmNIC10_PHY_SPECIAL_BASE 0x1000007FFD960E80ull +#define NIC10_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC10_PHY_SPECIAL_SECTION 0x7180 + +#define mmPRT10_MAC_AUX_BASE 0x1000007FFD968000ull +#define PRT10_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT10_MAC_AUX_SECTION 0xE800 + +#define mmPRT10_MAC_AUX_SPECIAL_BASE 0x1000007FFD968E80ull +#define PRT10_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT10_MAC_AUX_SPECIAL_SECTION 0x1800 + +#define mmPRT10_MAC_CORE_BASE 0x1000007FFD969000ull +#define PRT10_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT10_MAC_CORE_SECTION 0xE800 + +#define mmPRT10_MAC_CORE_SPECIAL_BASE 0x1000007FFD969E80ull +#define PRT10_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT10_MAC_CORE_SPECIAL_SECTION 0x1800 + +#define mmNIC10_MAC_RS_FEC_BASE 0x1000007FFD96A000ull +#define NIC10_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC10_MAC_RS_FEC_SECTION 0x1000 + +#define mmNIC10_MAC_GLOB_STAT_NIC_MAC_STAT_BASE 0x1000007FFD96B000ull +#define NIC10_MAC_GLOB_STAT_NIC_MAC_STAT_MAX_OFFSET 0x4D00 +#define NIC10_MAC_GLOB_STAT_NIC_MAC_STAT_SECTION 0x8000 + +#define mmNIC10_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_BASE 0x1000007FFD96B800ull +#define NIC10_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC10_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_SECTION 0x8000 + +#define mmNIC10_MAC_CH0_MAC_PCS_BASE 0x1000007FFD96C000ull +#define NIC10_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC10_MAC_CH0_MAC_PCS_SECTION 0x4000 + +#define mmNIC10_MAC_CH0_MAC_128_BASE 0x1000007FFD96C400ull +#define NIC10_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC10_MAC_CH0_MAC_128_SECTION 0x4000 + +#define mmNIC10_MAC_CH0_MAC_AN_BASE 0x1000007FFD96C800ull +#define NIC10_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC10_MAC_CH0_MAC_AN_SECTION 0x8000 + +#define mmNIC10_MAC_CH1_MAC_PCS_BASE 0x1000007FFD96D000ull +#define NIC10_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC10_MAC_CH1_MAC_PCS_SECTION 0x4000 + +#define mmNIC10_MAC_CH1_MAC_128_BASE 0x1000007FFD96D400ull +#define NIC10_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC10_MAC_CH1_MAC_128_SECTION 0x4000 + +#define mmNIC10_MAC_CH1_MAC_AN_BASE 0x1000007FFD96D800ull +#define NIC10_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC10_MAC_CH1_MAC_AN_SECTION 0x8000 + +#define mmNIC10_MAC_CH2_MAC_PCS_BASE 0x1000007FFD96E000ull +#define NIC10_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC10_MAC_CH2_MAC_PCS_SECTION 0x4000 + +#define mmNIC10_MAC_CH2_MAC_128_BASE 0x1000007FFD96E400ull +#define NIC10_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC10_MAC_CH2_MAC_128_SECTION 0x4000 + +#define mmNIC10_MAC_CH2_MAC_AN_BASE 0x1000007FFD96E800ull +#define NIC10_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC10_MAC_CH2_MAC_AN_SECTION 0x8000 + +#define mmNIC10_MAC_CH3_MAC_PCS_BASE 0x1000007FFD96F000ull +#define NIC10_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC10_MAC_CH3_MAC_PCS_SECTION 0x4000 + +#define mmNIC10_MAC_CH3_MAC_128_BASE 0x1000007FFD96F400ull +#define NIC10_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC10_MAC_CH3_MAC_128_SECTION 0x4000 + +#define mmNIC10_MAC_CH3_MAC_AN_BASE 0x1000007FFD96F800ull +#define NIC10_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC10_MAC_CH3_MAC_AN_SECTION 0x10800 + +#define mmNIC11_UMR0_0_UNSECURE_DOORBELL0_BASE 0x1000007FFD980000ull +#define NIC11_UMR0_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_0_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR0_0_UNSECURE_DOORBELL1_BASE 0x1000007FFD980080ull +#define NIC11_UMR0_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_0_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR0_0_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD980100ull +#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR0_0_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD980180ull +#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR0_0_SPECIAL_BASE 0x1000007FFD980E80ull +#define NIC11_UMR0_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_0_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR0_1_UNSECURE_DOORBELL0_BASE 0x1000007FFD981000ull +#define NIC11_UMR0_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_1_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR0_1_UNSECURE_DOORBELL1_BASE 0x1000007FFD981080ull +#define NIC11_UMR0_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_1_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR0_1_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD981100ull +#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR0_1_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD981180ull +#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR0_1_SPECIAL_BASE 0x1000007FFD981E80ull +#define NIC11_UMR0_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_1_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR0_2_UNSECURE_DOORBELL0_BASE 0x1000007FFD982000ull +#define NIC11_UMR0_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_2_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR0_2_UNSECURE_DOORBELL1_BASE 0x1000007FFD982080ull +#define NIC11_UMR0_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_2_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR0_2_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD982100ull +#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR0_2_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD982180ull +#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR0_2_SPECIAL_BASE 0x1000007FFD982E80ull +#define NIC11_UMR0_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_2_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR0_3_UNSECURE_DOORBELL0_BASE 0x1000007FFD983000ull +#define NIC11_UMR0_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_3_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR0_3_UNSECURE_DOORBELL1_BASE 0x1000007FFD983080ull +#define NIC11_UMR0_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_3_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR0_3_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD983100ull +#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR0_3_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD983180ull +#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR0_3_SPECIAL_BASE 0x1000007FFD983E80ull +#define NIC11_UMR0_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_3_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR0_4_UNSECURE_DOORBELL0_BASE 0x1000007FFD984000ull +#define NIC11_UMR0_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_4_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR0_4_UNSECURE_DOORBELL1_BASE 0x1000007FFD984080ull +#define NIC11_UMR0_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_4_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR0_4_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD984100ull +#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR0_4_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD984180ull +#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR0_4_SPECIAL_BASE 0x1000007FFD984E80ull +#define NIC11_UMR0_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_4_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR0_5_UNSECURE_DOORBELL0_BASE 0x1000007FFD985000ull +#define NIC11_UMR0_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_5_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR0_5_UNSECURE_DOORBELL1_BASE 0x1000007FFD985080ull +#define NIC11_UMR0_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_5_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR0_5_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD985100ull +#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR0_5_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD985180ull +#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR0_5_SPECIAL_BASE 0x1000007FFD985E80ull +#define NIC11_UMR0_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_5_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR0_6_UNSECURE_DOORBELL0_BASE 0x1000007FFD986000ull +#define NIC11_UMR0_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_6_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR0_6_UNSECURE_DOORBELL1_BASE 0x1000007FFD986080ull +#define NIC11_UMR0_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_6_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR0_6_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD986100ull +#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR0_6_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD986180ull +#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR0_6_SPECIAL_BASE 0x1000007FFD986E80ull +#define NIC11_UMR0_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_6_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR0_7_UNSECURE_DOORBELL0_BASE 0x1000007FFD987000ull +#define NIC11_UMR0_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_7_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR0_7_UNSECURE_DOORBELL1_BASE 0x1000007FFD987080ull +#define NIC11_UMR0_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_7_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR0_7_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD987100ull +#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR0_7_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD987180ull +#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR0_7_SPECIAL_BASE 0x1000007FFD987E80ull +#define NIC11_UMR0_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_7_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR0_8_UNSECURE_DOORBELL0_BASE 0x1000007FFD988000ull +#define NIC11_UMR0_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_8_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR0_8_UNSECURE_DOORBELL1_BASE 0x1000007FFD988080ull +#define NIC11_UMR0_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_8_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR0_8_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD988100ull +#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR0_8_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD988180ull +#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR0_8_SPECIAL_BASE 0x1000007FFD988E80ull +#define NIC11_UMR0_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_8_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR0_9_UNSECURE_DOORBELL0_BASE 0x1000007FFD989000ull +#define NIC11_UMR0_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_9_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR0_9_UNSECURE_DOORBELL1_BASE 0x1000007FFD989080ull +#define NIC11_UMR0_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_9_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR0_9_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD989100ull +#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR0_9_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD989180ull +#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR0_9_SPECIAL_BASE 0x1000007FFD989E80ull +#define NIC11_UMR0_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_9_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR0_10_UNSECURE_DOORBELL0_BASE 0x1000007FFD98A000ull +#define NIC11_UMR0_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_10_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR0_10_UNSECURE_DOORBELL1_BASE 0x1000007FFD98A080ull +#define NIC11_UMR0_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_10_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR0_10_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD98A100ull +#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR0_10_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD98A180ull +#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR0_10_SPECIAL_BASE 0x1000007FFD98AE80ull +#define NIC11_UMR0_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_10_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR0_11_UNSECURE_DOORBELL0_BASE 0x1000007FFD98B000ull +#define NIC11_UMR0_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_11_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR0_11_UNSECURE_DOORBELL1_BASE 0x1000007FFD98B080ull +#define NIC11_UMR0_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_11_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR0_11_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD98B100ull +#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR0_11_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD98B180ull +#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR0_11_SPECIAL_BASE 0x1000007FFD98BE80ull +#define NIC11_UMR0_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_11_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR0_12_UNSECURE_DOORBELL0_BASE 0x1000007FFD98C000ull +#define NIC11_UMR0_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_12_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR0_12_UNSECURE_DOORBELL1_BASE 0x1000007FFD98C080ull +#define NIC11_UMR0_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_12_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR0_12_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD98C100ull +#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR0_12_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD98C180ull +#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR0_12_SPECIAL_BASE 0x1000007FFD98CE80ull +#define NIC11_UMR0_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_12_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR0_13_UNSECURE_DOORBELL0_BASE 0x1000007FFD98D000ull +#define NIC11_UMR0_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_13_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR0_13_UNSECURE_DOORBELL1_BASE 0x1000007FFD98D080ull +#define NIC11_UMR0_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_13_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR0_13_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD98D100ull +#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR0_13_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD98D180ull +#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR0_13_SPECIAL_BASE 0x1000007FFD98DE80ull +#define NIC11_UMR0_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_13_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR0_14_UNSECURE_DOORBELL0_BASE 0x1000007FFD98E000ull +#define NIC11_UMR0_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR0_14_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR0_14_UNSECURE_DOORBELL1_BASE 0x1000007FFD98E080ull +#define NIC11_UMR0_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR0_14_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR0_14_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD98E100ull +#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR0_14_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD98E180ull +#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR0_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR0_14_SPECIAL_BASE 0x1000007FFD98EE80ull +#define NIC11_UMR0_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR0_14_SPECIAL_SECTION 0x1180 + +#define mmNIC11_QM_DCCM0_BASE 0x1000007FFD990000ull +#define NIC11_QM_DCCM0_MAX_OFFSET 0x4000 +#define NIC11_QM_DCCM0_SECTION 0x8000 + +#define mmNIC11_QM_ARC_AUX0_BASE 0x1000007FFD998000ull +#define NIC11_QM_ARC_AUX0_MAX_OFFSET 0x1000 +#define NIC11_QM_ARC_AUX0_SECTION 0xE800 + +#define mmNIC11_QM_ARC_AUX0_SPECIAL_BASE 0x1000007FFD998E80ull +#define NIC11_QM_ARC_AUX0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_QM_ARC_AUX0_SPECIAL_SECTION 0x1180 + +#define mmNIC11_QM0_BASE 0x1000007FFD99A000ull +#define NIC11_QM0_MAX_OFFSET 0x1000 +#define NIC11_QM0_SECTION 0x9000 + +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFD99A900ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFD99A908ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFD99A910ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFD99A918ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFD99A920ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFD99A928ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFD99A930ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFD99A938ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFD99A940ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFD99A948ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFD99A950ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFD99A958ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFD99A960ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFD99A968ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFD99A970ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmNIC11_QM0_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFD99A978ull +#define NIC11_QM0_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC11_QM0_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmNIC11_QM0_AXUSER_SECURED_BASE 0x1000007FFD99AB00ull +#define NIC11_QM0_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC11_QM0_AXUSER_SECURED_SECTION 0x8000 + +#define mmNIC11_QM0_AXUSER_NONSECURED_BASE 0x1000007FFD99AB80ull +#define NIC11_QM0_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC11_QM0_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmNIC11_QM0_DBG_HBW_BASE 0x1000007FFD99AC00ull +#define NIC11_QM0_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC11_QM0_DBG_HBW_SECTION 0x8000 + +#define mmNIC11_QM0_DBG_LBW_BASE 0x1000007FFD99AC80ull +#define NIC11_QM0_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC11_QM0_DBG_LBW_SECTION 0x1000 + +#define mmNIC11_QM0_CGM_BASE 0x1000007FFD99AD80ull +#define NIC11_QM0_CGM_MAX_OFFSET 0xC000 +#define NIC11_QM0_CGM_SECTION 0x1000 + +#define mmNIC11_QM0_SPECIAL_BASE 0x1000007FFD99AE80ull +#define NIC11_QM0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_QM0_SPECIAL_SECTION 0x4180 + +#define mmNIC11_QPC0_BASE 0x1000007FFD99F000ull +#define NIC11_QPC0_MAX_OFFSET 0x1000 +#define NIC11_QPC0_SECTION 0x7200 + +#define mmNIC11_QPC0_DBFIFO0_CI_UPD_ADDR_BASE 0x1000007FFD99F720ull +#define NIC11_QPC0_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO1_CI_UPD_ADDR_BASE 0x1000007FFD99F728ull +#define NIC11_QPC0_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO2_CI_UPD_ADDR_BASE 0x1000007FFD99F730ull +#define NIC11_QPC0_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO3_CI_UPD_ADDR_BASE 0x1000007FFD99F738ull +#define NIC11_QPC0_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO4_CI_UPD_ADDR_BASE 0x1000007FFD99F740ull +#define NIC11_QPC0_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO5_CI_UPD_ADDR_BASE 0x1000007FFD99F748ull +#define NIC11_QPC0_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO6_CI_UPD_ADDR_BASE 0x1000007FFD99F750ull +#define NIC11_QPC0_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO7_CI_UPD_ADDR_BASE 0x1000007FFD99F758ull +#define NIC11_QPC0_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO8_CI_UPD_ADDR_BASE 0x1000007FFD99F760ull +#define NIC11_QPC0_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO9_CI_UPD_ADDR_BASE 0x1000007FFD99F768ull +#define NIC11_QPC0_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO10_CI_UPD_ADDR_BASE 0x1000007FFD99F770ull +#define NIC11_QPC0_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO11_CI_UPD_ADDR_BASE 0x1000007FFD99F778ull +#define NIC11_QPC0_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO12_CI_UPD_ADDR_BASE 0x1000007FFD99F780ull +#define NIC11_QPC0_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO13_CI_UPD_ADDR_BASE 0x1000007FFD99F788ull +#define NIC11_QPC0_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO14_CI_UPD_ADDR_BASE 0x1000007FFD99F790ull +#define NIC11_QPC0_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO15_CI_UPD_ADDR_BASE 0x1000007FFD99F798ull +#define NIC11_QPC0_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO16_CI_UPD_ADDR_BASE 0x1000007FFD99F7A0ull +#define NIC11_QPC0_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO17_CI_UPD_ADDR_BASE 0x1000007FFD99F7A8ull +#define NIC11_QPC0_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO18_CI_UPD_ADDR_BASE 0x1000007FFD99F7B0ull +#define NIC11_QPC0_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO19_CI_UPD_ADDR_BASE 0x1000007FFD99F7B8ull +#define NIC11_QPC0_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO20_CI_UPD_ADDR_BASE 0x1000007FFD99F7C0ull +#define NIC11_QPC0_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO21_CI_UPD_ADDR_BASE 0x1000007FFD99F7C8ull +#define NIC11_QPC0_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO22_CI_UPD_ADDR_BASE 0x1000007FFD99F7D0ull +#define NIC11_QPC0_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO23_CI_UPD_ADDR_BASE 0x1000007FFD99F7D8ull +#define NIC11_QPC0_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO24_CI_UPD_ADDR_BASE 0x1000007FFD99F7E0ull +#define NIC11_QPC0_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO25_CI_UPD_ADDR_BASE 0x1000007FFD99F7E8ull +#define NIC11_QPC0_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO26_CI_UPD_ADDR_BASE 0x1000007FFD99F7F0ull +#define NIC11_QPC0_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO27_CI_UPD_ADDR_BASE 0x1000007FFD99F7F8ull +#define NIC11_QPC0_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO28_CI_UPD_ADDR_BASE 0x1000007FFD99F800ull +#define NIC11_QPC0_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFO29_CI_UPD_ADDR_BASE 0x1000007FFD99F808ull +#define NIC11_QPC0_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x1000007FFD99F810ull +#define NIC11_QPC0_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x1000007FFD99F818ull +#define NIC11_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC0_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 + +#define mmNIC11_QPC0_AXUSER_CONG_QUE_BASE 0x1000007FFD99FB80ull +#define NIC11_QPC0_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC11_QPC0_AXUSER_CONG_QUE_SECTION 0x6000 + +#define mmNIC11_QPC0_AXUSER_RXWQE_BASE 0x1000007FFD99FBE0ull +#define NIC11_QPC0_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC11_QPC0_AXUSER_RXWQE_SECTION 0x6000 + +#define mmNIC11_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x1000007FFD99FC40ull +#define NIC11_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC11_QPC0_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 + +#define mmNIC11_QPC0_AXUSER_DB_FIFO_BASE 0x1000007FFD99FCA0ull +#define NIC11_QPC0_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC11_QPC0_AXUSER_DB_FIFO_SECTION 0x6000 + +#define mmNIC11_QPC0_AXUSER_EV_QUE_LBW_INTR_BASE 0x1000007FFD99FD00ull +#define NIC11_QPC0_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC11_QPC0_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 + +#define mmNIC11_QPC0_AXUSER_ERR_FIFO_BASE 0x1000007FFD99FD60ull +#define NIC11_QPC0_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC11_QPC0_AXUSER_ERR_FIFO_SECTION 0x6000 + +#define mmNIC11_QPC0_AXUSER_QPC_RESP_BASE 0x1000007FFD99FDC0ull +#define NIC11_QPC0_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC11_QPC0_AXUSER_QPC_RESP_SECTION 0x6000 + +#define mmNIC11_QPC0_AXUSER_QPC_REQ_BASE 0x1000007FFD99FE20ull +#define NIC11_QPC0_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC11_QPC0_AXUSER_QPC_REQ_SECTION 0x6000 + +#define mmNIC11_QPC0_SPECIAL_BASE 0x1000007FFD99FE80ull +#define NIC11_QPC0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_QPC0_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR1_0_UNSECURE_DOORBELL0_BASE 0x1000007FFD9A0000ull +#define NIC11_UMR1_0_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_0_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR1_0_UNSECURE_DOORBELL1_BASE 0x1000007FFD9A0080ull +#define NIC11_UMR1_0_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_0_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR1_0_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD9A0100ull +#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR1_0_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD9A0180ull +#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_0_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR1_0_SPECIAL_BASE 0x1000007FFD9A0E80ull +#define NIC11_UMR1_0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_0_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR1_1_UNSECURE_DOORBELL0_BASE 0x1000007FFD9A1000ull +#define NIC11_UMR1_1_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_1_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR1_1_UNSECURE_DOORBELL1_BASE 0x1000007FFD9A1080ull +#define NIC11_UMR1_1_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_1_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR1_1_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD9A1100ull +#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR1_1_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD9A1180ull +#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_1_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR1_1_SPECIAL_BASE 0x1000007FFD9A1E80ull +#define NIC11_UMR1_1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_1_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR1_2_UNSECURE_DOORBELL0_BASE 0x1000007FFD9A2000ull +#define NIC11_UMR1_2_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_2_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR1_2_UNSECURE_DOORBELL1_BASE 0x1000007FFD9A2080ull +#define NIC11_UMR1_2_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_2_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR1_2_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD9A2100ull +#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR1_2_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD9A2180ull +#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_2_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR1_2_SPECIAL_BASE 0x1000007FFD9A2E80ull +#define NIC11_UMR1_2_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_2_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR1_3_UNSECURE_DOORBELL0_BASE 0x1000007FFD9A3000ull +#define NIC11_UMR1_3_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_3_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR1_3_UNSECURE_DOORBELL1_BASE 0x1000007FFD9A3080ull +#define NIC11_UMR1_3_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_3_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR1_3_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD9A3100ull +#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR1_3_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD9A3180ull +#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_3_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR1_3_SPECIAL_BASE 0x1000007FFD9A3E80ull +#define NIC11_UMR1_3_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_3_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR1_4_UNSECURE_DOORBELL0_BASE 0x1000007FFD9A4000ull +#define NIC11_UMR1_4_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_4_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR1_4_UNSECURE_DOORBELL1_BASE 0x1000007FFD9A4080ull +#define NIC11_UMR1_4_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_4_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR1_4_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD9A4100ull +#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR1_4_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD9A4180ull +#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_4_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR1_4_SPECIAL_BASE 0x1000007FFD9A4E80ull +#define NIC11_UMR1_4_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_4_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR1_5_UNSECURE_DOORBELL0_BASE 0x1000007FFD9A5000ull +#define NIC11_UMR1_5_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_5_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR1_5_UNSECURE_DOORBELL1_BASE 0x1000007FFD9A5080ull +#define NIC11_UMR1_5_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_5_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR1_5_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD9A5100ull +#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR1_5_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD9A5180ull +#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_5_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR1_5_SPECIAL_BASE 0x1000007FFD9A5E80ull +#define NIC11_UMR1_5_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_5_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR1_6_UNSECURE_DOORBELL0_BASE 0x1000007FFD9A6000ull +#define NIC11_UMR1_6_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_6_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR1_6_UNSECURE_DOORBELL1_BASE 0x1000007FFD9A6080ull +#define NIC11_UMR1_6_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_6_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR1_6_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD9A6100ull +#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR1_6_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD9A6180ull +#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_6_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR1_6_SPECIAL_BASE 0x1000007FFD9A6E80ull +#define NIC11_UMR1_6_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_6_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR1_7_UNSECURE_DOORBELL0_BASE 0x1000007FFD9A7000ull +#define NIC11_UMR1_7_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_7_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR1_7_UNSECURE_DOORBELL1_BASE 0x1000007FFD9A7080ull +#define NIC11_UMR1_7_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_7_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR1_7_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD9A7100ull +#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR1_7_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD9A7180ull +#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_7_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR1_7_SPECIAL_BASE 0x1000007FFD9A7E80ull +#define NIC11_UMR1_7_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_7_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR1_8_UNSECURE_DOORBELL0_BASE 0x1000007FFD9A8000ull +#define NIC11_UMR1_8_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_8_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR1_8_UNSECURE_DOORBELL1_BASE 0x1000007FFD9A8080ull +#define NIC11_UMR1_8_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_8_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR1_8_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD9A8100ull +#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR1_8_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD9A8180ull +#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_8_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR1_8_SPECIAL_BASE 0x1000007FFD9A8E80ull +#define NIC11_UMR1_8_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_8_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR1_9_UNSECURE_DOORBELL0_BASE 0x1000007FFD9A9000ull +#define NIC11_UMR1_9_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_9_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR1_9_UNSECURE_DOORBELL1_BASE 0x1000007FFD9A9080ull +#define NIC11_UMR1_9_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_9_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR1_9_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD9A9100ull +#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR1_9_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD9A9180ull +#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_9_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR1_9_SPECIAL_BASE 0x1000007FFD9A9E80ull +#define NIC11_UMR1_9_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_9_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR1_10_UNSECURE_DOORBELL0_BASE 0x1000007FFD9AA000ull +#define NIC11_UMR1_10_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_10_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR1_10_UNSECURE_DOORBELL1_BASE 0x1000007FFD9AA080ull +#define NIC11_UMR1_10_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_10_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR1_10_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD9AA100ull +#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR1_10_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD9AA180ull +#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_10_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR1_10_SPECIAL_BASE 0x1000007FFD9AAE80ull +#define NIC11_UMR1_10_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_10_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR1_11_UNSECURE_DOORBELL0_BASE 0x1000007FFD9AB000ull +#define NIC11_UMR1_11_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_11_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR1_11_UNSECURE_DOORBELL1_BASE 0x1000007FFD9AB080ull +#define NIC11_UMR1_11_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_11_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR1_11_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD9AB100ull +#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR1_11_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD9AB180ull +#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_11_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR1_11_SPECIAL_BASE 0x1000007FFD9ABE80ull +#define NIC11_UMR1_11_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_11_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR1_12_UNSECURE_DOORBELL0_BASE 0x1000007FFD9AC000ull +#define NIC11_UMR1_12_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_12_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR1_12_UNSECURE_DOORBELL1_BASE 0x1000007FFD9AC080ull +#define NIC11_UMR1_12_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_12_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR1_12_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD9AC100ull +#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR1_12_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD9AC180ull +#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_12_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR1_12_SPECIAL_BASE 0x1000007FFD9ACE80ull +#define NIC11_UMR1_12_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_12_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR1_13_UNSECURE_DOORBELL0_BASE 0x1000007FFD9AD000ull +#define NIC11_UMR1_13_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_13_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR1_13_UNSECURE_DOORBELL1_BASE 0x1000007FFD9AD080ull +#define NIC11_UMR1_13_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_13_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR1_13_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD9AD100ull +#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR1_13_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD9AD180ull +#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_13_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR1_13_SPECIAL_BASE 0x1000007FFD9ADE80ull +#define NIC11_UMR1_13_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_13_SPECIAL_SECTION 0x1800 + +#define mmNIC11_UMR1_14_UNSECURE_DOORBELL0_BASE 0x1000007FFD9AE000ull +#define NIC11_UMR1_14_UNSECURE_DOORBELL0_MAX_OFFSET 0x1000 +#define NIC11_UMR1_14_UNSECURE_DOORBELL0_SECTION 0x8000 + +#define mmNIC11_UMR1_14_UNSECURE_DOORBELL1_BASE 0x1000007FFD9AE080ull +#define NIC11_UMR1_14_UNSECURE_DOORBELL1_MAX_OFFSET 0x1000 +#define NIC11_UMR1_14_UNSECURE_DOORBELL1_SECTION 0x8000 + +#define mmNIC11_UMR1_14_COMPLETION_QUEUE_CI_0_BASE 0x1000007FFD9AE100ull +#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_0_MAX_OFFSET 0x8000 +#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_0_SECTION 0x8000 + +#define mmNIC11_UMR1_14_COMPLETION_QUEUE_CI_1_BASE 0x1000007FFD9AE180ull +#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_1_MAX_OFFSET 0x8000 +#define NIC11_UMR1_14_COMPLETION_QUEUE_CI_1_SECTION 0xD000 + +#define mmNIC11_UMR1_14_SPECIAL_BASE 0x1000007FFD9AEE80ull +#define NIC11_UMR1_14_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_UMR1_14_SPECIAL_SECTION 0x1180 + +#define mmNIC11_QM_DCCM1_BASE 0x1000007FFD9B0000ull +#define NIC11_QM_DCCM1_MAX_OFFSET 0x4000 +#define NIC11_QM_DCCM1_SECTION 0x8000 + +#define mmNIC11_QM_ARC_AUX1_BASE 0x1000007FFD9B8000ull +#define NIC11_QM_ARC_AUX1_MAX_OFFSET 0x1000 +#define NIC11_QM_ARC_AUX1_SECTION 0xE800 + +#define mmNIC11_QM_ARC_AUX1_SPECIAL_BASE 0x1000007FFD9B8E80ull +#define NIC11_QM_ARC_AUX1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_QM_ARC_AUX1_SPECIAL_SECTION 0x1180 + +#define mmNIC11_QM1_BASE 0x1000007FFD9BA000ull +#define NIC11_QM1_MAX_OFFSET 0x1000 +#define NIC11_QM1_SECTION 0x9000 + +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR0_BASE 0x1000007FFD9BA900ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 + +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR1_BASE 0x1000007FFD9BA908ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 + +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR2_BASE 0x1000007FFD9BA910ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 + +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR3_BASE 0x1000007FFD9BA918ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 + +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR4_BASE 0x1000007FFD9BA920ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 + +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR5_BASE 0x1000007FFD9BA928ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 + +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR6_BASE 0x1000007FFD9BA930ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 + +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR7_BASE 0x1000007FFD9BA938ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 + +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR8_BASE 0x1000007FFD9BA940ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 + +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR9_BASE 0x1000007FFD9BA948ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 + +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR10_BASE 0x1000007FFD9BA950ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 + +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR11_BASE 0x1000007FFD9BA958ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 + +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR12_BASE 0x1000007FFD9BA960ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 + +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR13_BASE 0x1000007FFD9BA968ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 + +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR14_BASE 0x1000007FFD9BA970ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 + +#define mmNIC11_QM1_QMAN_WR64_BASE_ADDR15_BASE 0x1000007FFD9BA978ull +#define NIC11_QM1_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 +#define NIC11_QM1_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 + +#define mmNIC11_QM1_AXUSER_SECURED_BASE 0x1000007FFD9BAB00ull +#define NIC11_QM1_AXUSER_SECURED_MAX_OFFSET 0x5000 +#define NIC11_QM1_AXUSER_SECURED_SECTION 0x8000 + +#define mmNIC11_QM1_AXUSER_NONSECURED_BASE 0x1000007FFD9BAB80ull +#define NIC11_QM1_AXUSER_NONSECURED_MAX_OFFSET 0x5000 +#define NIC11_QM1_AXUSER_NONSECURED_SECTION 0x8000 + +#define mmNIC11_QM1_DBG_HBW_BASE 0x1000007FFD9BAC00ull +#define NIC11_QM1_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC11_QM1_DBG_HBW_SECTION 0x8000 + +#define mmNIC11_QM1_DBG_LBW_BASE 0x1000007FFD9BAC80ull +#define NIC11_QM1_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC11_QM1_DBG_LBW_SECTION 0x1000 + +#define mmNIC11_QM1_CGM_BASE 0x1000007FFD9BAD80ull +#define NIC11_QM1_CGM_MAX_OFFSET 0xC000 +#define NIC11_QM1_CGM_SECTION 0x1000 + +#define mmNIC11_QM1_SPECIAL_BASE 0x1000007FFD9BAE80ull +#define NIC11_QM1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_QM1_SPECIAL_SECTION 0x4180 + +#define mmNIC11_QPC1_BASE 0x1000007FFD9BF000ull +#define NIC11_QPC1_MAX_OFFSET 0x1000 +#define NIC11_QPC1_SECTION 0x7200 + +#define mmNIC11_QPC1_DBFIFO0_CI_UPD_ADDR_BASE 0x1000007FFD9BF720ull +#define NIC11_QPC1_DBFIFO0_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO0_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO1_CI_UPD_ADDR_BASE 0x1000007FFD9BF728ull +#define NIC11_QPC1_DBFIFO1_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO1_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO2_CI_UPD_ADDR_BASE 0x1000007FFD9BF730ull +#define NIC11_QPC1_DBFIFO2_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO2_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO3_CI_UPD_ADDR_BASE 0x1000007FFD9BF738ull +#define NIC11_QPC1_DBFIFO3_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO3_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO4_CI_UPD_ADDR_BASE 0x1000007FFD9BF740ull +#define NIC11_QPC1_DBFIFO4_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO4_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO5_CI_UPD_ADDR_BASE 0x1000007FFD9BF748ull +#define NIC11_QPC1_DBFIFO5_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO5_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO6_CI_UPD_ADDR_BASE 0x1000007FFD9BF750ull +#define NIC11_QPC1_DBFIFO6_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO6_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO7_CI_UPD_ADDR_BASE 0x1000007FFD9BF758ull +#define NIC11_QPC1_DBFIFO7_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO7_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO8_CI_UPD_ADDR_BASE 0x1000007FFD9BF760ull +#define NIC11_QPC1_DBFIFO8_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO8_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO9_CI_UPD_ADDR_BASE 0x1000007FFD9BF768ull +#define NIC11_QPC1_DBFIFO9_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO9_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO10_CI_UPD_ADDR_BASE 0x1000007FFD9BF770ull +#define NIC11_QPC1_DBFIFO10_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO10_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO11_CI_UPD_ADDR_BASE 0x1000007FFD9BF778ull +#define NIC11_QPC1_DBFIFO11_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO11_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO12_CI_UPD_ADDR_BASE 0x1000007FFD9BF780ull +#define NIC11_QPC1_DBFIFO12_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO12_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO13_CI_UPD_ADDR_BASE 0x1000007FFD9BF788ull +#define NIC11_QPC1_DBFIFO13_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO13_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO14_CI_UPD_ADDR_BASE 0x1000007FFD9BF790ull +#define NIC11_QPC1_DBFIFO14_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO14_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO15_CI_UPD_ADDR_BASE 0x1000007FFD9BF798ull +#define NIC11_QPC1_DBFIFO15_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO15_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO16_CI_UPD_ADDR_BASE 0x1000007FFD9BF7A0ull +#define NIC11_QPC1_DBFIFO16_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO16_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO17_CI_UPD_ADDR_BASE 0x1000007FFD9BF7A8ull +#define NIC11_QPC1_DBFIFO17_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO17_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO18_CI_UPD_ADDR_BASE 0x1000007FFD9BF7B0ull +#define NIC11_QPC1_DBFIFO18_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO18_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO19_CI_UPD_ADDR_BASE 0x1000007FFD9BF7B8ull +#define NIC11_QPC1_DBFIFO19_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO19_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO20_CI_UPD_ADDR_BASE 0x1000007FFD9BF7C0ull +#define NIC11_QPC1_DBFIFO20_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO20_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO21_CI_UPD_ADDR_BASE 0x1000007FFD9BF7C8ull +#define NIC11_QPC1_DBFIFO21_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO21_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO22_CI_UPD_ADDR_BASE 0x1000007FFD9BF7D0ull +#define NIC11_QPC1_DBFIFO22_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO22_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO23_CI_UPD_ADDR_BASE 0x1000007FFD9BF7D8ull +#define NIC11_QPC1_DBFIFO23_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO23_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO24_CI_UPD_ADDR_BASE 0x1000007FFD9BF7E0ull +#define NIC11_QPC1_DBFIFO24_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO24_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO25_CI_UPD_ADDR_BASE 0x1000007FFD9BF7E8ull +#define NIC11_QPC1_DBFIFO25_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO25_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO26_CI_UPD_ADDR_BASE 0x1000007FFD9BF7F0ull +#define NIC11_QPC1_DBFIFO26_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO26_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO27_CI_UPD_ADDR_BASE 0x1000007FFD9BF7F8ull +#define NIC11_QPC1_DBFIFO27_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO27_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO28_CI_UPD_ADDR_BASE 0x1000007FFD9BF800ull +#define NIC11_QPC1_DBFIFO28_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO28_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFO29_CI_UPD_ADDR_BASE 0x1000007FFD9BF808ull +#define NIC11_QPC1_DBFIFO29_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFO29_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFOSECUR_CI_UPD_ADDR_BASE 0x1000007FFD9BF810ull +#define NIC11_QPC1_DBFIFOSECUR_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFOSECUR_CI_UPD_ADDR_SECTION 0x8000 + +#define mmNIC11_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_BASE 0x1000007FFD9BF818ull +#define NIC11_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_MAX_OFFSET 0x8000 +#define NIC11_QPC1_DBFIFOPRIVIL_CI_UPD_ADDR_SECTION 0x3680 + +#define mmNIC11_QPC1_AXUSER_CONG_QUE_BASE 0x1000007FFD9BFB80ull +#define NIC11_QPC1_AXUSER_CONG_QUE_MAX_OFFSET 0x5000 +#define NIC11_QPC1_AXUSER_CONG_QUE_SECTION 0x6000 + +#define mmNIC11_QPC1_AXUSER_RXWQE_BASE 0x1000007FFD9BFBE0ull +#define NIC11_QPC1_AXUSER_RXWQE_MAX_OFFSET 0x5000 +#define NIC11_QPC1_AXUSER_RXWQE_SECTION 0x6000 + +#define mmNIC11_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_BASE 0x1000007FFD9BFC40ull +#define NIC11_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_MAX_OFFSET 0x5000 +#define NIC11_QPC1_AXUSER_TXWQE_LBW_QMAN_BP_SECTION 0x6000 + +#define mmNIC11_QPC1_AXUSER_DB_FIFO_BASE 0x1000007FFD9BFCA0ull +#define NIC11_QPC1_AXUSER_DB_FIFO_MAX_OFFSET 0x5000 +#define NIC11_QPC1_AXUSER_DB_FIFO_SECTION 0x6000 + +#define mmNIC11_QPC1_AXUSER_EV_QUE_LBW_INTR_BASE 0x1000007FFD9BFD00ull +#define NIC11_QPC1_AXUSER_EV_QUE_LBW_INTR_MAX_OFFSET 0x5000 +#define NIC11_QPC1_AXUSER_EV_QUE_LBW_INTR_SECTION 0x6000 + +#define mmNIC11_QPC1_AXUSER_ERR_FIFO_BASE 0x1000007FFD9BFD60ull +#define NIC11_QPC1_AXUSER_ERR_FIFO_MAX_OFFSET 0x5000 +#define NIC11_QPC1_AXUSER_ERR_FIFO_SECTION 0x6000 + +#define mmNIC11_QPC1_AXUSER_QPC_RESP_BASE 0x1000007FFD9BFDC0ull +#define NIC11_QPC1_AXUSER_QPC_RESP_MAX_OFFSET 0x5000 +#define NIC11_QPC1_AXUSER_QPC_RESP_SECTION 0x6000 + +#define mmNIC11_QPC1_AXUSER_QPC_REQ_BASE 0x1000007FFD9BFE20ull +#define NIC11_QPC1_AXUSER_QPC_REQ_MAX_OFFSET 0x5000 +#define NIC11_QPC1_AXUSER_QPC_REQ_SECTION 0x6000 + +#define mmNIC11_QPC1_SPECIAL_BASE 0x1000007FFD9BFE80ull +#define NIC11_QPC1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_QPC1_SPECIAL_SECTION 0x8180 + +#define mmNIC11_TMR_BASE 0x1000007FFD9C8000ull +#define NIC11_TMR_MAX_OFFSET 0x1000 +#define NIC11_TMR_SECTION 0xD600 + +#define mmNIC11_TMR_AXUSER_TMR_FREE_LIST_BASE 0x1000007FFD9C8D60ull +#define NIC11_TMR_AXUSER_TMR_FREE_LIST_MAX_OFFSET 0x5000 +#define NIC11_TMR_AXUSER_TMR_FREE_LIST_SECTION 0x6000 + +#define mmNIC11_TMR_AXUSER_TMR_FIFO_BASE 0x1000007FFD9C8DC0ull +#define NIC11_TMR_AXUSER_TMR_FIFO_MAX_OFFSET 0x5000 +#define NIC11_TMR_AXUSER_TMR_FIFO_SECTION 0x6000 + +#define mmNIC11_TMR_AXUSER_TMR_FSM_BASE 0x1000007FFD9C8E20ull +#define NIC11_TMR_AXUSER_TMR_FSM_MAX_OFFSET 0x5000 +#define NIC11_TMR_AXUSER_TMR_FSM_SECTION 0x6000 + +#define mmNIC11_TMR_SPECIAL_BASE 0x1000007FFD9C8E80ull +#define NIC11_TMR_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_TMR_SPECIAL_SECTION 0x1800 + +#define mmNIC11_RXB_CORE_BASE 0x1000007FFD9C9000ull +#define NIC11_RXB_CORE_MAX_OFFSET 0x1000 +#define NIC11_RXB_CORE_SECTION 0x6100 + +#define mmNIC11_RXB_CORE_SCT_AWUSER_BASE 0x1000007FFD9C9610ull +#define NIC11_RXB_CORE_SCT_AWUSER_MAX_OFFSET 0x5000 +#define NIC11_RXB_CORE_SCT_AWUSER_SECTION 0x8700 + +#define mmNIC11_RXB_CORE_SPECIAL_BASE 0x1000007FFD9C9E80ull +#define NIC11_RXB_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_RXB_CORE_SPECIAL_SECTION 0x1800 + +#define mmNIC11_RXE0_BASE 0x1000007FFD9CA000ull +#define NIC11_RXE0_MAX_OFFSET 0x1000 +#define NIC11_RXE0_SECTION 0x9000 + +#define mmNIC11_RXE0_WQE_ARUSER_BASE 0x1000007FFD9CA900ull +#define NIC11_RXE0_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC11_RXE0_WQE_ARUSER_SECTION 0x5800 + +#define mmNIC11_RXE0_SPECIAL_BASE 0x1000007FFD9CAE80ull +#define NIC11_RXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_RXE0_SPECIAL_SECTION 0x1800 + +#define mmNIC11_RXE1_BASE 0x1000007FFD9CB000ull +#define NIC11_RXE1_MAX_OFFSET 0x1000 +#define NIC11_RXE1_SECTION 0x9000 + +#define mmNIC11_RXE1_WQE_ARUSER_BASE 0x1000007FFD9CB900ull +#define NIC11_RXE1_WQE_ARUSER_MAX_OFFSET 0x5000 +#define NIC11_RXE1_WQE_ARUSER_SECTION 0x5800 + +#define mmNIC11_RXE1_SPECIAL_BASE 0x1000007FFD9CBE80ull +#define NIC11_RXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_RXE1_SPECIAL_SECTION 0x1800 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ0_BASE 0x1000007FFD9CC000ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ0_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ1_BASE 0x1000007FFD9CC050ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ1_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ2_BASE 0x1000007FFD9CC0A0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ2_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ3_BASE 0x1000007FFD9CC0F0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ3_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ4_BASE 0x1000007FFD9CC140ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ4_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ5_BASE 0x1000007FFD9CC190ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ5_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ6_BASE 0x1000007FFD9CC1E0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ6_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ7_BASE 0x1000007FFD9CC230ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ7_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ8_BASE 0x1000007FFD9CC280ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ8_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ9_BASE 0x1000007FFD9CC2D0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ9_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ10_BASE 0x1000007FFD9CC320ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ10_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ11_BASE 0x1000007FFD9CC370ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ11_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ12_BASE 0x1000007FFD9CC3C0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ12_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ13_BASE 0x1000007FFD9CC410ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ13_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ14_BASE 0x1000007FFD9CC460ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ14_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ15_BASE 0x1000007FFD9CC4B0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ15_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ16_BASE 0x1000007FFD9CC500ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ16_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ17_BASE 0x1000007FFD9CC550ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ17_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ18_BASE 0x1000007FFD9CC5A0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ18_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ19_BASE 0x1000007FFD9CC5F0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ19_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ20_BASE 0x1000007FFD9CC640ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ20_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ21_BASE 0x1000007FFD9CC690ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ21_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ22_BASE 0x1000007FFD9CC6E0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ22_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ23_BASE 0x1000007FFD9CC730ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ23_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ24_BASE 0x1000007FFD9CC780ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ24_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ25_BASE 0x1000007FFD9CC7D0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ25_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ26_BASE 0x1000007FFD9CC820ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ26_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ27_BASE 0x1000007FFD9CC870ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ27_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ28_BASE 0x1000007FFD9CC8C0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ28_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ29_BASE 0x1000007FFD9CC910ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ29_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ30_BASE 0x1000007FFD9CC960ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ30_SECTION 0x5000 + +#define mmNIC11_RXE0_AXUSER_AXUSER_CQ31_BASE 0x1000007FFD9CC9B0ull +#define NIC11_RXE0_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC11_RXE0_AXUSER_AXUSER_CQ31_SECTION 0x4D00 + +#define mmNIC11_RXE0_AXUSER_SPECIAL_BASE 0x1000007FFD9CCE80ull +#define NIC11_RXE0_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_RXE0_AXUSER_SPECIAL_SECTION 0x1800 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ0_BASE 0x1000007FFD9CD000ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ0_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ0_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ1_BASE 0x1000007FFD9CD050ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ1_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ1_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ2_BASE 0x1000007FFD9CD0A0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ2_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ2_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ3_BASE 0x1000007FFD9CD0F0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ3_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ3_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ4_BASE 0x1000007FFD9CD140ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ4_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ4_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ5_BASE 0x1000007FFD9CD190ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ5_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ5_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ6_BASE 0x1000007FFD9CD1E0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ6_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ6_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ7_BASE 0x1000007FFD9CD230ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ7_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ7_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ8_BASE 0x1000007FFD9CD280ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ8_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ8_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ9_BASE 0x1000007FFD9CD2D0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ9_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ9_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ10_BASE 0x1000007FFD9CD320ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ10_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ10_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ11_BASE 0x1000007FFD9CD370ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ11_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ11_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ12_BASE 0x1000007FFD9CD3C0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ12_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ12_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ13_BASE 0x1000007FFD9CD410ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ13_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ13_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ14_BASE 0x1000007FFD9CD460ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ14_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ14_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ15_BASE 0x1000007FFD9CD4B0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ15_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ15_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ16_BASE 0x1000007FFD9CD500ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ16_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ16_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ17_BASE 0x1000007FFD9CD550ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ17_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ17_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ18_BASE 0x1000007FFD9CD5A0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ18_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ18_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ19_BASE 0x1000007FFD9CD5F0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ19_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ19_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ20_BASE 0x1000007FFD9CD640ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ20_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ20_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ21_BASE 0x1000007FFD9CD690ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ21_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ21_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ22_BASE 0x1000007FFD9CD6E0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ22_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ22_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ23_BASE 0x1000007FFD9CD730ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ23_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ23_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ24_BASE 0x1000007FFD9CD780ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ24_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ24_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ25_BASE 0x1000007FFD9CD7D0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ25_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ25_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ26_BASE 0x1000007FFD9CD820ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ26_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ26_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ27_BASE 0x1000007FFD9CD870ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ27_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ27_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ28_BASE 0x1000007FFD9CD8C0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ28_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ28_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ29_BASE 0x1000007FFD9CD910ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ29_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ29_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ30_BASE 0x1000007FFD9CD960ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ30_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ30_SECTION 0x5000 + +#define mmNIC11_RXE1_AXUSER_AXUSER_CQ31_BASE 0x1000007FFD9CD9B0ull +#define NIC11_RXE1_AXUSER_AXUSER_CQ31_MAX_OFFSET 0x5000 +#define NIC11_RXE1_AXUSER_AXUSER_CQ31_SECTION 0x4D00 + +#define mmNIC11_RXE1_AXUSER_SPECIAL_BASE 0x1000007FFD9CDE80ull +#define NIC11_RXE1_AXUSER_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_RXE1_AXUSER_SPECIAL_SECTION 0x2180 + +#define mmNIC11_TXS0_BASE 0x1000007FFD9D0000ull +#define NIC11_TXS0_MAX_OFFSET 0x1000 +#define NIC11_TXS0_SECTION 0xE800 + +#define mmNIC11_TXS0_SPECIAL_BASE 0x1000007FFD9D0E80ull +#define NIC11_TXS0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_TXS0_SPECIAL_SECTION 0x1800 + +#define mmNIC11_TXS1_BASE 0x1000007FFD9D1000ull +#define NIC11_TXS1_MAX_OFFSET 0x1000 +#define NIC11_TXS1_SECTION 0xE800 + +#define mmNIC11_TXS1_SPECIAL_BASE 0x1000007FFD9D1E80ull +#define NIC11_TXS1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_TXS1_SPECIAL_SECTION 0x1800 + +#define mmNIC11_TXE0_BASE 0x1000007FFD9D2000ull +#define NIC11_TXE0_MAX_OFFSET 0x1000 +#define NIC11_TXE0_SECTION 0xE800 + +#define mmNIC11_TXE0_SPECIAL_BASE 0x1000007FFD9D2E80ull +#define NIC11_TXE0_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_TXE0_SPECIAL_SECTION 0x1800 + +#define mmNIC11_TXE1_BASE 0x1000007FFD9D3000ull +#define NIC11_TXE1_MAX_OFFSET 0x1000 +#define NIC11_TXE1_SECTION 0xE800 + +#define mmNIC11_TXE1_SPECIAL_BASE 0x1000007FFD9D3E80ull +#define NIC11_TXE1_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_TXE1_SPECIAL_SECTION 0x1800 + +#define mmNIC11_TXB_BASE 0x1000007FFD9D4000ull +#define NIC11_TXB_MAX_OFFSET 0x1000 +#define NIC11_TXB_SECTION 0xE800 + +#define mmNIC11_TXB_SPECIAL_BASE 0x1000007FFD9D4E80ull +#define NIC11_TXB_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_TXB_SPECIAL_SECTION 0x1800 + +#define mmNIC11_MSTR_IF_RR_SHRD_HBW_BASE 0x1000007FFD9D5000ull +#define NIC11_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 +#define NIC11_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 + +#define mmNIC11_MSTR_IF_RR_PRVT_HBW_BASE 0x1000007FFD9D5200ull +#define NIC11_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 +#define NIC11_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 + +#define mmNIC11_MSTR_IF_RR_SHRD_LBW_BASE 0x1000007FFD9D5400ull +#define NIC11_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 +#define NIC11_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 + +#define mmNIC11_MSTR_IF_RR_PRVT_LBW_BASE 0x1000007FFD9D5600ull +#define NIC11_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 +#define NIC11_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 + +#define mmNIC11_MSTR_IF_E2E_CRDT_BASE 0x1000007FFD9D5800ull +#define NIC11_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 +#define NIC11_MSTR_IF_E2E_CRDT_SECTION 0x2800 + +#define mmNIC11_MSTR_IF_AXUSER_BASE 0x1000007FFD9D5A80ull +#define NIC11_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 +#define NIC11_MSTR_IF_AXUSER_SECTION 0x8000 + +#define mmNIC11_MSTR_IF_DBG_HBW_BASE 0x1000007FFD9D5B00ull +#define NIC11_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 +#define NIC11_MSTR_IF_DBG_HBW_SECTION 0x8000 + +#define mmNIC11_MSTR_IF_DBG_LBW_BASE 0x1000007FFD9D5B80ull +#define NIC11_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 +#define NIC11_MSTR_IF_DBG_LBW_SECTION 0x8000 + +#define mmNIC11_MSTR_IF_CORE_HBW_BASE 0x1000007FFD9D5C00ull +#define NIC11_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 +#define NIC11_MSTR_IF_CORE_HBW_SECTION 0x1800 + +#define mmNIC11_MSTR_IF_CORE_LBW_BASE 0x1000007FFD9D5D80ull +#define NIC11_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 +#define NIC11_MSTR_IF_CORE_LBW_SECTION 0x1000 + +#define mmNIC11_MSTR_IF_SPECIAL_BASE 0x1000007FFD9D5E80ull +#define NIC11_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_MSTR_IF_SPECIAL_SECTION 0x1800 + +#define mmNIC11_TX_AXUSER_BASE 0x1000007FFD9D6000ull +#define NIC11_TX_AXUSER_MAX_OFFSET 0x5000 +#define NIC11_TX_AXUSER_SECTION 0x2000 + +#define mmNIC11_SERDES0_BASE 0x1000007FFD9D8000ull +#define NIC11_SERDES0_MAX_OFFSET 0x3E40 +#define NIC11_SERDES0_SECTION 0x4000 + +#define mmNIC11_SERDES1_BASE 0x1000007FFD9DC000ull +#define NIC11_SERDES1_MAX_OFFSET 0x3E40 +#define NIC11_SERDES1_SECTION 0x4000 + +#define mmNIC11_PHY_BASE 0x1000007FFD9E0000ull +#define NIC11_PHY_MAX_OFFSET 0x1000 +#define NIC11_PHY_SECTION 0xE800 + +#define mmNIC11_PHY_SPECIAL_BASE 0x1000007FFD9E0E80ull +#define NIC11_PHY_SPECIAL_MAX_OFFSET 0x1800 +#define NIC11_PHY_SPECIAL_SECTION 0x7180 + +#define mmPRT11_MAC_AUX_BASE 0x1000007FFD9E8000ull +#define PRT11_MAC_AUX_MAX_OFFSET 0x1000 +#define PRT11_MAC_AUX_SECTION 0xE800 + +#define mmPRT11_MAC_AUX_SPECIAL_BASE 0x1000007FFD9E8E80ull +#define PRT11_MAC_AUX_SPECIAL_MAX_OFFSET 0x1800 +#define PRT11_MAC_AUX_SPECIAL_SECTION 0x1800 + +#define mmPRT11_MAC_CORE_BASE 0x1000007FFD9E9000ull +#define PRT11_MAC_CORE_MAX_OFFSET 0x1000 +#define PRT11_MAC_CORE_SECTION 0xE800 + +#define mmPRT11_MAC_CORE_SPECIAL_BASE 0x1000007FFD9E9E80ull +#define PRT11_MAC_CORE_SPECIAL_MAX_OFFSET 0x1800 +#define PRT11_MAC_CORE_SPECIAL_SECTION 0x1800 + +#define mmNIC11_MAC_RS_FEC_BASE 0x1000007FFD9EA000ull +#define NIC11_MAC_RS_FEC_MAX_OFFSET 0x2DC0 +#define NIC11_MAC_RS_FEC_SECTION 0x1000 + +#define mmNIC11_MAC_GLOB_STAT_NIC_MAC_STAT_BASE 0x1000007FFD9EB000ull +#define NIC11_MAC_GLOB_STAT_NIC_MAC_STAT_MAX_OFFSET 0x4D00 +#define NIC11_MAC_GLOB_STAT_NIC_MAC_STAT_SECTION 0x8000 + +#define mmNIC11_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_BASE 0x1000007FFD9EB800ull +#define NIC11_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_MAX_OFFSET 0x1EC0 +#define NIC11_MAC_GLOB_STAT_NIC_MAC_RSFEC_STATS_SECTION 0x8000 + +#define mmNIC11_MAC_CH0_MAC_PCS_BASE 0x1000007FFD9EC000ull +#define NIC11_MAC_CH0_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC11_MAC_CH0_MAC_PCS_SECTION 0x4000 + +#define mmNIC11_MAC_CH0_MAC_128_BASE 0x1000007FFD9EC400ull +#define NIC11_MAC_CH0_MAC_128_MAX_OFFSET 0xA400 +#define NIC11_MAC_CH0_MAC_128_SECTION 0x4000 + +#define mmNIC11_MAC_CH0_MAC_AN_BASE 0x1000007FFD9EC800ull +#define NIC11_MAC_CH0_MAC_AN_MAX_OFFSET 0x4400 +#define NIC11_MAC_CH0_MAC_AN_SECTION 0x8000 + +#define mmNIC11_MAC_CH1_MAC_PCS_BASE 0x1000007FFD9ED000ull +#define NIC11_MAC_CH1_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC11_MAC_CH1_MAC_PCS_SECTION 0x4000 + +#define mmNIC11_MAC_CH1_MAC_128_BASE 0x1000007FFD9ED400ull +#define NIC11_MAC_CH1_MAC_128_MAX_OFFSET 0xA400 +#define NIC11_MAC_CH1_MAC_128_SECTION 0x4000 + +#define mmNIC11_MAC_CH1_MAC_AN_BASE 0x1000007FFD9ED800ull +#define NIC11_MAC_CH1_MAC_AN_MAX_OFFSET 0x4400 +#define NIC11_MAC_CH1_MAC_AN_SECTION 0x8000 + +#define mmNIC11_MAC_CH2_MAC_PCS_BASE 0x1000007FFD9EE000ull +#define NIC11_MAC_CH2_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC11_MAC_CH2_MAC_PCS_SECTION 0x4000 + +#define mmNIC11_MAC_CH2_MAC_128_BASE 0x1000007FFD9EE400ull +#define NIC11_MAC_CH2_MAC_128_MAX_OFFSET 0xA400 +#define NIC11_MAC_CH2_MAC_128_SECTION 0x4000 + +#define mmNIC11_MAC_CH2_MAC_AN_BASE 0x1000007FFD9EE800ull +#define NIC11_MAC_CH2_MAC_AN_MAX_OFFSET 0x4400 +#define NIC11_MAC_CH2_MAC_AN_SECTION 0x8000 + +#define mmNIC11_MAC_CH3_MAC_PCS_BASE 0x1000007FFD9EF000ull +#define NIC11_MAC_CH3_MAC_PCS_MAX_OFFSET 0x31C0 +#define NIC11_MAC_CH3_MAC_PCS_SECTION 0x4000 + +#define mmNIC11_MAC_CH3_MAC_128_BASE 0x1000007FFD9EF400ull +#define NIC11_MAC_CH3_MAC_128_MAX_OFFSET 0xA400 +#define NIC11_MAC_CH3_MAC_128_SECTION 0x4000 + +#define mmNIC11_MAC_CH3_MAC_AN_BASE 0x1000007FFD9EF800ull +#define NIC11_MAC_CH3_MAC_AN_MAX_OFFSET 0x4400 +#define NIC11_MAC_CH3_MAC_AN_SECTION 0x610800 + +#define mmDCORE0_ROM_TABLE_L_BASE 0x1000007FFE000000ull +#define DCORE0_ROM_TABLE_L_MAX_OFFSET 0x1000 +#define DCORE0_ROM_TABLE_L_SECTION 0x80000 + +#define mmDCORE0_HMMU0_CS_ROM_TBL_BASE 0x1000007FFE080000ull +#define DCORE0_HMMU0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE0_HMMU0_CS_STM_BASE 0x1000007FFE081000ull +#define DCORE0_HMMU0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_CS_STM_SECTION 0x1000 + +#define mmDCORE0_HMMU0_CS_CTI_BASE 0x1000007FFE082000ull +#define DCORE0_HMMU0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_CS_CTI_SECTION 0x1000 + +#define mmDCORE0_HMMU0_CS_ETF_BASE 0x1000007FFE083000ull +#define DCORE0_HMMU0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_CS_ETF_SECTION 0x1000 + +#define mmDCORE0_HMMU0_CS_SPMU_BASE 0x1000007FFE084000ull +#define DCORE0_HMMU0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_CS_SPMU_SECTION 0x1000 + +#define mmDCORE0_HMMU0_BMON_CTI_BASE 0x1000007FFE085000ull +#define DCORE0_HMMU0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_BMON_CTI_SECTION 0x1000 + +#define mmDCORE0_HMMU0_USER_CTI_BASE 0x1000007FFE086000ull +#define DCORE0_HMMU0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_USER_CTI_SECTION 0x1000 + +#define mmDCORE0_HMMU0_BMON_0_BASE 0x1000007FFE087000ull +#define DCORE0_HMMU0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_BMON_0_SECTION 0x1000 + +#define mmDCORE0_HMMU0_BMON_1_BASE 0x1000007FFE088000ull +#define DCORE0_HMMU0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_BMON_1_SECTION 0x1000 + +#define mmDCORE0_HMMU0_BMON_3_BASE 0x1000007FFE089000ull +#define DCORE0_HMMU0_BMON_3_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_BMON_3_SECTION 0x1000 + +#define mmDCORE0_HMMU0_BMON_2_BASE 0x1000007FFE08A000ull +#define DCORE0_HMMU0_BMON_2_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_BMON_2_SECTION 0x1000 + +#define mmDCORE0_HMMU0_BMON_4_BASE 0x1000007FFE08B000ull +#define DCORE0_HMMU0_BMON_4_MAX_OFFSET 0x1000 +#define DCORE0_HMMU0_BMON_4_SECTION 0x5000 + +#define mmDCORE0_HMMU1_CS_ROM_TBL_BASE 0x1000007FFE090000ull +#define DCORE0_HMMU1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE0_HMMU1_CS_STM_BASE 0x1000007FFE091000ull +#define DCORE0_HMMU1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_CS_STM_SECTION 0x1000 + +#define mmDCORE0_HMMU1_CS_CTI_BASE 0x1000007FFE092000ull +#define DCORE0_HMMU1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_CS_CTI_SECTION 0x1000 + +#define mmDCORE0_HMMU1_CS_ETF_BASE 0x1000007FFE093000ull +#define DCORE0_HMMU1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_CS_ETF_SECTION 0x1000 + +#define mmDCORE0_HMMU1_CS_SPMU_BASE 0x1000007FFE094000ull +#define DCORE0_HMMU1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_CS_SPMU_SECTION 0x1000 + +#define mmDCORE0_HMMU1_BMON_CTI_BASE 0x1000007FFE095000ull +#define DCORE0_HMMU1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_BMON_CTI_SECTION 0x1000 + +#define mmDCORE0_HMMU1_USER_CTI_BASE 0x1000007FFE096000ull +#define DCORE0_HMMU1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_USER_CTI_SECTION 0x1000 + +#define mmDCORE0_HMMU1_BMON_0_BASE 0x1000007FFE097000ull +#define DCORE0_HMMU1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_BMON_0_SECTION 0x1000 + +#define mmDCORE0_HMMU1_BMON_1_BASE 0x1000007FFE098000ull +#define DCORE0_HMMU1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_BMON_1_SECTION 0x1000 + +#define mmDCORE0_HMMU1_BMON_3_BASE 0x1000007FFE099000ull +#define DCORE0_HMMU1_BMON_3_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_BMON_3_SECTION 0x1000 + +#define mmDCORE0_HMMU1_BMON_2_BASE 0x1000007FFE09A000ull +#define DCORE0_HMMU1_BMON_2_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_BMON_2_SECTION 0x1000 + +#define mmDCORE0_HMMU1_BMON_4_BASE 0x1000007FFE09B000ull +#define DCORE0_HMMU1_BMON_4_MAX_OFFSET 0x1000 +#define DCORE0_HMMU1_BMON_4_SECTION 0x5000 + +#define mmDCORE0_HMMU2_CS_ROM_TBL_BASE 0x1000007FFE0A0000ull +#define DCORE0_HMMU2_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE0_HMMU2_CS_STM_BASE 0x1000007FFE0A1000ull +#define DCORE0_HMMU2_CS_STM_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_CS_STM_SECTION 0x1000 + +#define mmDCORE0_HMMU2_CS_CTI_BASE 0x1000007FFE0A2000ull +#define DCORE0_HMMU2_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_CS_CTI_SECTION 0x1000 + +#define mmDCORE0_HMMU2_CS_ETF_BASE 0x1000007FFE0A3000ull +#define DCORE0_HMMU2_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_CS_ETF_SECTION 0x1000 + +#define mmDCORE0_HMMU2_CS_SPMU_BASE 0x1000007FFE0A4000ull +#define DCORE0_HMMU2_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_CS_SPMU_SECTION 0x1000 + +#define mmDCORE0_HMMU2_BMON_CTI_BASE 0x1000007FFE0A5000ull +#define DCORE0_HMMU2_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_BMON_CTI_SECTION 0x1000 + +#define mmDCORE0_HMMU2_USER_CTI_BASE 0x1000007FFE0A6000ull +#define DCORE0_HMMU2_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_USER_CTI_SECTION 0x1000 + +#define mmDCORE0_HMMU2_BMON_0_BASE 0x1000007FFE0A7000ull +#define DCORE0_HMMU2_BMON_0_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_BMON_0_SECTION 0x1000 + +#define mmDCORE0_HMMU2_BMON_1_BASE 0x1000007FFE0A8000ull +#define DCORE0_HMMU2_BMON_1_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_BMON_1_SECTION 0x1000 + +#define mmDCORE0_HMMU2_BMON_3_BASE 0x1000007FFE0A9000ull +#define DCORE0_HMMU2_BMON_3_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_BMON_3_SECTION 0x1000 + +#define mmDCORE0_HMMU2_BMON_2_BASE 0x1000007FFE0AA000ull +#define DCORE0_HMMU2_BMON_2_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_BMON_2_SECTION 0x1000 + +#define mmDCORE0_HMMU2_BMON_4_BASE 0x1000007FFE0AB000ull +#define DCORE0_HMMU2_BMON_4_MAX_OFFSET 0x1000 +#define DCORE0_HMMU2_BMON_4_SECTION 0x5000 + +#define mmDCORE0_HMMU3_CS_ROM_TBL_BASE 0x1000007FFE0B0000ull +#define DCORE0_HMMU3_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE0_HMMU3_CS_STM_BASE 0x1000007FFE0B1000ull +#define DCORE0_HMMU3_CS_STM_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_CS_STM_SECTION 0x1000 + +#define mmDCORE0_HMMU3_CS_CTI_BASE 0x1000007FFE0B2000ull +#define DCORE0_HMMU3_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_CS_CTI_SECTION 0x1000 + +#define mmDCORE0_HMMU3_CS_ETF_BASE 0x1000007FFE0B3000ull +#define DCORE0_HMMU3_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_CS_ETF_SECTION 0x1000 + +#define mmDCORE0_HMMU3_CS_SPMU_BASE 0x1000007FFE0B4000ull +#define DCORE0_HMMU3_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_CS_SPMU_SECTION 0x1000 + +#define mmDCORE0_HMMU3_BMON_CTI_BASE 0x1000007FFE0B5000ull +#define DCORE0_HMMU3_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_BMON_CTI_SECTION 0x1000 + +#define mmDCORE0_HMMU3_USER_CTI_BASE 0x1000007FFE0B6000ull +#define DCORE0_HMMU3_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_USER_CTI_SECTION 0x1000 + +#define mmDCORE0_HMMU3_BMON_0_BASE 0x1000007FFE0B7000ull +#define DCORE0_HMMU3_BMON_0_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_BMON_0_SECTION 0x1000 + +#define mmDCORE0_HMMU3_BMON_1_BASE 0x1000007FFE0B8000ull +#define DCORE0_HMMU3_BMON_1_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_BMON_1_SECTION 0x1000 + +#define mmDCORE0_HMMU3_BMON_3_BASE 0x1000007FFE0B9000ull +#define DCORE0_HMMU3_BMON_3_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_BMON_3_SECTION 0x1000 + +#define mmDCORE0_HMMU3_BMON_2_BASE 0x1000007FFE0BA000ull +#define DCORE0_HMMU3_BMON_2_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_BMON_2_SECTION 0x1000 + +#define mmDCORE0_HMMU3_BMON_4_BASE 0x1000007FFE0BB000ull +#define DCORE0_HMMU3_BMON_4_MAX_OFFSET 0x1000 +#define DCORE0_HMMU3_BMON_4_SECTION 0x5000 + +#define mmDCORE0_SM_CS_DBG_ROM_TBL_BASE 0x1000007FFE110000ull +#define DCORE0_SM_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_SM_CS_DBG_ROM_TBL_SECTION 0x1000 + +#define mmDCORE0_SM_STM_BASE 0x1000007FFE111000ull +#define DCORE0_SM_STM_MAX_OFFSET 0x1000 +#define DCORE0_SM_STM_SECTION 0x1000 + +#define mmDCORE0_SM_CTI_BASE 0x1000007FFE112000ull +#define DCORE0_SM_CTI_MAX_OFFSET 0x1000 +#define DCORE0_SM_CTI_SECTION 0x1000 + +#define mmDCORE0_SM_ETF_BASE 0x1000007FFE113000ull +#define DCORE0_SM_ETF_MAX_OFFSET 0x1000 +#define DCORE0_SM_ETF_SECTION 0x1000 + +#define mmDCORE0_SM_SPMU_BASE 0x1000007FFE114000ull +#define DCORE0_SM_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_SM_SPMU_SECTION 0x1000 + +#define mmDCORE0_SM_BMON_CTI_BASE 0x1000007FFE115000ull +#define DCORE0_SM_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_SM_BMON_CTI_SECTION 0x1000 + +#define mmDCORE0_SM_USER_CTI_BASE 0x1000007FFE116000ull +#define DCORE0_SM_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_SM_USER_CTI_SECTION 0x1000 + +#define mmDCORE0_SM_BMON_BASE 0x1000007FFE117000ull +#define DCORE0_SM_BMON_MAX_OFFSET 0x1000 +#define DCORE0_SM_BMON_SECTION 0x1000 + +#define mmDCORE0_SM_BMON1_BASE 0x1000007FFE118000ull +#define DCORE0_SM_BMON1_MAX_OFFSET 0x1000 +#define DCORE0_SM_BMON1_SECTION 0x18000 + +#define mmDCORE0_XFT_FUNNEL_BASE 0x1000007FFE130000ull +#define DCORE0_XFT_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_XFT_FUNNEL_SECTION 0x8000 + +#define mmDCORE0_TFT0_FUNNEL_BASE 0x1000007FFE138000ull +#define DCORE0_TFT0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TFT0_FUNNEL_SECTION 0x1000 + +#define mmDCORE0_TFT1_FUNNEL_BASE 0x1000007FFE139000ull +#define DCORE0_TFT1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TFT1_FUNNEL_SECTION 0x1000 + +#define mmDCORE0_TFT2_FUNNEL_BASE 0x1000007FFE13A000ull +#define DCORE0_TFT2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_TFT2_FUNNEL_SECTION 0x7000 + +#define mmDCORE0_RTR0_FUNNEL_BASE 0x1000007FFE141000ull +#define DCORE0_RTR0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_RTR0_FUNNEL_SECTION 0x8000 + +#define mmDCORE0_RTR1_FUNNEL_BASE 0x1000007FFE149000ull +#define DCORE0_RTR1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_RTR1_FUNNEL_SECTION 0x8000 + +#define mmDCORE0_RTR2_FUNNEL_BASE 0x1000007FFE151000ull +#define DCORE0_RTR2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_RTR2_FUNNEL_SECTION 0x8000 + +#define mmDCORE0_RTR3_FUNNEL_BASE 0x1000007FFE159000ull +#define DCORE0_RTR3_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_RTR3_FUNNEL_SECTION 0x8000 + +#define mmDCORE0_RTR4_FUNNEL_BASE 0x1000007FFE161000ull +#define DCORE0_RTR4_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_RTR4_FUNNEL_SECTION 0x4000 + +#define mmDCORE0_MIF0_FUNNEL_BASE 0x1000007FFE165000ull +#define DCORE0_MIF0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_MIF0_FUNNEL_SECTION 0x4000 + +#define mmDCORE0_RTR5_FUNNEL_BASE 0x1000007FFE169000ull +#define DCORE0_RTR5_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_RTR5_FUNNEL_SECTION 0x4000 + +#define mmDCORE0_MIF1_FUNNEL_BASE 0x1000007FFE16D000ull +#define DCORE0_MIF1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_MIF1_FUNNEL_SECTION 0x4000 + +#define mmDCORE0_RTR6_FUNNEL_BASE 0x1000007FFE171000ull +#define DCORE0_RTR6_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_RTR6_FUNNEL_SECTION 0x4000 + +#define mmDCORE0_MIF2_FUNNEL_BASE 0x1000007FFE175000ull +#define DCORE0_MIF2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_MIF2_FUNNEL_SECTION 0x4000 + +#define mmDCORE0_RTR7_FUNNEL_BASE 0x1000007FFE179000ull +#define DCORE0_RTR7_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_RTR7_FUNNEL_SECTION 0x4000 + +#define mmDCORE0_MIF3_FUNNEL_BASE 0x1000007FFE17D000ull +#define DCORE0_MIF3_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_MIF3_FUNNEL_SECTION 0x43000 + +#define mmDCORE0_EDMA0_CS_ROM_TBL_BASE 0x1000007FFE1C0000ull +#define DCORE0_EDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE0_EDMA0_CS_STM_BASE 0x1000007FFE1C1000ull +#define DCORE0_EDMA0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_CS_STM_SECTION 0x1000 + +#define mmDCORE0_EDMA0_CS_CTI_BASE 0x1000007FFE1C2000ull +#define DCORE0_EDMA0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_CS_CTI_SECTION 0x1000 + +#define mmDCORE0_EDMA0_CS_ETF_BASE 0x1000007FFE1C3000ull +#define DCORE0_EDMA0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_CS_ETF_SECTION 0x1000 + +#define mmDCORE0_EDMA0_CS_SPMU_BASE 0x1000007FFE1C4000ull +#define DCORE0_EDMA0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_CS_SPMU_SECTION 0x1000 + +#define mmDCORE0_EDMA0_BMON_CTI_BASE 0x1000007FFE1C5000ull +#define DCORE0_EDMA0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_BMON_CTI_SECTION 0x1000 + +#define mmDCORE0_EDMA0_USER_CTI_BASE 0x1000007FFE1C6000ull +#define DCORE0_EDMA0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_USER_CTI_SECTION 0x1000 + +#define mmDCORE0_EDMA0_BMON_0_BASE 0x1000007FFE1C7000ull +#define DCORE0_EDMA0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_BMON_0_SECTION 0x1000 + +#define mmDCORE0_EDMA0_BMON_1_BASE 0x1000007FFE1C8000ull +#define DCORE0_EDMA0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE0_EDMA0_BMON_1_SECTION 0x1000 + +#define mmDCORE0_EDMA0_QM_ARC_RTT_BASE 0x1000007FFE1C9000ull +#define DCORE0_EDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_EDMA0_QM_ARC_RTT_SECTION 0x7000 + +#define mmDCORE0_EDMA1_CS_ROM_TBL_BASE 0x1000007FFE1D0000ull +#define DCORE0_EDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE0_EDMA1_CS_STM_BASE 0x1000007FFE1D1000ull +#define DCORE0_EDMA1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_CS_STM_SECTION 0x1000 + +#define mmDCORE0_EDMA1_CS_CTI_BASE 0x1000007FFE1D2000ull +#define DCORE0_EDMA1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_CS_CTI_SECTION 0x1000 + +#define mmDCORE0_EDMA1_CS_ETF_BASE 0x1000007FFE1D3000ull +#define DCORE0_EDMA1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_CS_ETF_SECTION 0x1000 + +#define mmDCORE0_EDMA1_CS_SPMU_BASE 0x1000007FFE1D4000ull +#define DCORE0_EDMA1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_CS_SPMU_SECTION 0x1000 + +#define mmDCORE0_EDMA1_BMON_CTI_BASE 0x1000007FFE1D5000ull +#define DCORE0_EDMA1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_BMON_CTI_SECTION 0x1000 + +#define mmDCORE0_EDMA1_USER_CTI_BASE 0x1000007FFE1D6000ull +#define DCORE0_EDMA1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_USER_CTI_SECTION 0x1000 + +#define mmDCORE0_EDMA1_BMON_0_BASE 0x1000007FFE1D7000ull +#define DCORE0_EDMA1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_BMON_0_SECTION 0x1000 + +#define mmDCORE0_EDMA1_BMON_1_BASE 0x1000007FFE1D8000ull +#define DCORE0_EDMA1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE0_EDMA1_BMON_1_SECTION 0x1000 + +#define mmDCORE0_EDMA1_QM_ARC_RTT_BASE 0x1000007FFE1D9000ull +#define DCORE0_EDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE0_EDMA1_QM_ARC_RTT_SECTION 0x7000 + +#define mmDCORE0_VDEC0_CS_ROM_TBL_BASE 0x1000007FFE1E0000ull +#define DCORE0_VDEC0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE0_VDEC0_CS_STM_BASE 0x1000007FFE1E1000ull +#define DCORE0_VDEC0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_CS_STM_SECTION 0x1000 + +#define mmDCORE0_VDEC0_CS_CTI_BASE 0x1000007FFE1E2000ull +#define DCORE0_VDEC0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_CS_CTI_SECTION 0x1000 + +#define mmDCORE0_VDEC0_CS_ETF_BASE 0x1000007FFE1E3000ull +#define DCORE0_VDEC0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_CS_ETF_SECTION 0x1000 + +#define mmDCORE0_VDEC0_CS_SPMU_BASE 0x1000007FFE1E4000ull +#define DCORE0_VDEC0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_CS_SPMU_SECTION 0x1000 + +#define mmDCORE0_VDEC0_BMON_CTI_BASE 0x1000007FFE1E5000ull +#define DCORE0_VDEC0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_BMON_CTI_SECTION 0x1000 + +#define mmDCORE0_VDEC0_USER_CTI_BASE 0x1000007FFE1E6000ull +#define DCORE0_VDEC0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_USER_CTI_SECTION 0x1000 + +#define mmDCORE0_VDEC0_BMON_0_BASE 0x1000007FFE1E7000ull +#define DCORE0_VDEC0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_BMON_0_SECTION 0x1000 + +#define mmDCORE0_VDEC0_BMON_1_BASE 0x1000007FFE1E8000ull +#define DCORE0_VDEC0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_BMON_1_SECTION 0x1000 + +#define mmDCORE0_VDEC0_BMON_2_BASE 0x1000007FFE1E9000ull +#define DCORE0_VDEC0_BMON_2_MAX_OFFSET 0x1000 +#define DCORE0_VDEC0_BMON_2_SECTION 0x7000 + +#define mmDCORE0_VDEC1_CS_ROM_TBL_BASE 0x1000007FFE1F0000ull +#define DCORE0_VDEC1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE0_VDEC1_CS_STM_BASE 0x1000007FFE1F1000ull +#define DCORE0_VDEC1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_CS_STM_SECTION 0x1000 + +#define mmDCORE0_VDEC1_CS_CTI_BASE 0x1000007FFE1F2000ull +#define DCORE0_VDEC1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_CS_CTI_SECTION 0x1000 + +#define mmDCORE0_VDEC1_CS_ETF_BASE 0x1000007FFE1F3000ull +#define DCORE0_VDEC1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_CS_ETF_SECTION 0x1000 + +#define mmDCORE0_VDEC1_CS_SPMU_BASE 0x1000007FFE1F4000ull +#define DCORE0_VDEC1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_CS_SPMU_SECTION 0x1000 + +#define mmDCORE0_VDEC1_BMON_CTI_BASE 0x1000007FFE1F5000ull +#define DCORE0_VDEC1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_BMON_CTI_SECTION 0x1000 + +#define mmDCORE0_VDEC1_USER_CTI_BASE 0x1000007FFE1F6000ull +#define DCORE0_VDEC1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_USER_CTI_SECTION 0x1000 + +#define mmDCORE0_VDEC1_BMON_0_BASE 0x1000007FFE1F7000ull +#define DCORE0_VDEC1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_BMON_0_SECTION 0x1000 + +#define mmDCORE0_VDEC1_BMON_1_BASE 0x1000007FFE1F8000ull +#define DCORE0_VDEC1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_BMON_1_SECTION 0x1000 + +#define mmDCORE0_VDEC1_BMON_2_BASE 0x1000007FFE1F9000ull +#define DCORE0_VDEC1_BMON_2_MAX_OFFSET 0x1000 +#define DCORE0_VDEC1_BMON_2_SECTION 0x7000 + +#define mmDCORE1_ROM_TABLE_L_BASE 0x1000007FFE200000ull +#define DCORE1_ROM_TABLE_L_MAX_OFFSET 0x1000 +#define DCORE1_ROM_TABLE_L_SECTION 0x80000 + +#define mmDCORE1_HMMU0_CS_ROM_TBL_BASE 0x1000007FFE280000ull +#define DCORE1_HMMU0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE1_HMMU0_CS_STM_BASE 0x1000007FFE281000ull +#define DCORE1_HMMU0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_CS_STM_SECTION 0x1000 + +#define mmDCORE1_HMMU0_CS_CTI_BASE 0x1000007FFE282000ull +#define DCORE1_HMMU0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_CS_CTI_SECTION 0x1000 + +#define mmDCORE1_HMMU0_CS_ETF_BASE 0x1000007FFE283000ull +#define DCORE1_HMMU0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_CS_ETF_SECTION 0x1000 + +#define mmDCORE1_HMMU0_CS_SPMU_BASE 0x1000007FFE284000ull +#define DCORE1_HMMU0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_CS_SPMU_SECTION 0x1000 + +#define mmDCORE1_HMMU0_BMON_CTI_BASE 0x1000007FFE285000ull +#define DCORE1_HMMU0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_BMON_CTI_SECTION 0x1000 + +#define mmDCORE1_HMMU0_USER_CTI_BASE 0x1000007FFE286000ull +#define DCORE1_HMMU0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_USER_CTI_SECTION 0x1000 + +#define mmDCORE1_HMMU0_BMON_0_BASE 0x1000007FFE287000ull +#define DCORE1_HMMU0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_BMON_0_SECTION 0x1000 + +#define mmDCORE1_HMMU0_BMON_1_BASE 0x1000007FFE288000ull +#define DCORE1_HMMU0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_BMON_1_SECTION 0x1000 + +#define mmDCORE1_HMMU0_BMON_3_BASE 0x1000007FFE289000ull +#define DCORE1_HMMU0_BMON_3_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_BMON_3_SECTION 0x1000 + +#define mmDCORE1_HMMU0_BMON_2_BASE 0x1000007FFE28A000ull +#define DCORE1_HMMU0_BMON_2_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_BMON_2_SECTION 0x1000 + +#define mmDCORE1_HMMU0_BMON_4_BASE 0x1000007FFE28B000ull +#define DCORE1_HMMU0_BMON_4_MAX_OFFSET 0x1000 +#define DCORE1_HMMU0_BMON_4_SECTION 0x5000 + +#define mmDCORE1_HMMU1_CS_ROM_TBL_BASE 0x1000007FFE290000ull +#define DCORE1_HMMU1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE1_HMMU1_CS_STM_BASE 0x1000007FFE291000ull +#define DCORE1_HMMU1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_CS_STM_SECTION 0x1000 + +#define mmDCORE1_HMMU1_CS_CTI_BASE 0x1000007FFE292000ull +#define DCORE1_HMMU1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_CS_CTI_SECTION 0x1000 + +#define mmDCORE1_HMMU1_CS_ETF_BASE 0x1000007FFE293000ull +#define DCORE1_HMMU1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_CS_ETF_SECTION 0x1000 + +#define mmDCORE1_HMMU1_CS_SPMU_BASE 0x1000007FFE294000ull +#define DCORE1_HMMU1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_CS_SPMU_SECTION 0x1000 + +#define mmDCORE1_HMMU1_BMON_CTI_BASE 0x1000007FFE295000ull +#define DCORE1_HMMU1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_BMON_CTI_SECTION 0x1000 + +#define mmDCORE1_HMMU1_USER_CTI_BASE 0x1000007FFE296000ull +#define DCORE1_HMMU1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_USER_CTI_SECTION 0x1000 + +#define mmDCORE1_HMMU1_BMON_0_BASE 0x1000007FFE297000ull +#define DCORE1_HMMU1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_BMON_0_SECTION 0x1000 + +#define mmDCORE1_HMMU1_BMON_1_BASE 0x1000007FFE298000ull +#define DCORE1_HMMU1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_BMON_1_SECTION 0x1000 + +#define mmDCORE1_HMMU1_BMON_3_BASE 0x1000007FFE299000ull +#define DCORE1_HMMU1_BMON_3_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_BMON_3_SECTION 0x1000 + +#define mmDCORE1_HMMU1_BMON_2_BASE 0x1000007FFE29A000ull +#define DCORE1_HMMU1_BMON_2_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_BMON_2_SECTION 0x1000 + +#define mmDCORE1_HMMU1_BMON_4_BASE 0x1000007FFE29B000ull +#define DCORE1_HMMU1_BMON_4_MAX_OFFSET 0x1000 +#define DCORE1_HMMU1_BMON_4_SECTION 0x5000 + +#define mmDCORE1_HMMU2_CS_ROM_TBL_BASE 0x1000007FFE2A0000ull +#define DCORE1_HMMU2_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE1_HMMU2_CS_STM_BASE 0x1000007FFE2A1000ull +#define DCORE1_HMMU2_CS_STM_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_CS_STM_SECTION 0x1000 + +#define mmDCORE1_HMMU2_CS_CTI_BASE 0x1000007FFE2A2000ull +#define DCORE1_HMMU2_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_CS_CTI_SECTION 0x1000 + +#define mmDCORE1_HMMU2_CS_ETF_BASE 0x1000007FFE2A3000ull +#define DCORE1_HMMU2_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_CS_ETF_SECTION 0x1000 + +#define mmDCORE1_HMMU2_CS_SPMU_BASE 0x1000007FFE2A4000ull +#define DCORE1_HMMU2_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_CS_SPMU_SECTION 0x1000 + +#define mmDCORE1_HMMU2_BMON_CTI_BASE 0x1000007FFE2A5000ull +#define DCORE1_HMMU2_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_BMON_CTI_SECTION 0x1000 + +#define mmDCORE1_HMMU2_USER_CTI_BASE 0x1000007FFE2A6000ull +#define DCORE1_HMMU2_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_USER_CTI_SECTION 0x1000 + +#define mmDCORE1_HMMU2_BMON_0_BASE 0x1000007FFE2A7000ull +#define DCORE1_HMMU2_BMON_0_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_BMON_0_SECTION 0x1000 + +#define mmDCORE1_HMMU2_BMON_1_BASE 0x1000007FFE2A8000ull +#define DCORE1_HMMU2_BMON_1_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_BMON_1_SECTION 0x1000 + +#define mmDCORE1_HMMU2_BMON_3_BASE 0x1000007FFE2A9000ull +#define DCORE1_HMMU2_BMON_3_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_BMON_3_SECTION 0x1000 + +#define mmDCORE1_HMMU2_BMON_2_BASE 0x1000007FFE2AA000ull +#define DCORE1_HMMU2_BMON_2_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_BMON_2_SECTION 0x1000 + +#define mmDCORE1_HMMU2_BMON_4_BASE 0x1000007FFE2AB000ull +#define DCORE1_HMMU2_BMON_4_MAX_OFFSET 0x1000 +#define DCORE1_HMMU2_BMON_4_SECTION 0x5000 + +#define mmDCORE1_HMMU3_CS_ROM_TBL_BASE 0x1000007FFE2B0000ull +#define DCORE1_HMMU3_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE1_HMMU3_CS_STM_BASE 0x1000007FFE2B1000ull +#define DCORE1_HMMU3_CS_STM_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_CS_STM_SECTION 0x1000 + +#define mmDCORE1_HMMU3_CS_CTI_BASE 0x1000007FFE2B2000ull +#define DCORE1_HMMU3_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_CS_CTI_SECTION 0x1000 + +#define mmDCORE1_HMMU3_CS_ETF_BASE 0x1000007FFE2B3000ull +#define DCORE1_HMMU3_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_CS_ETF_SECTION 0x1000 + +#define mmDCORE1_HMMU3_CS_SPMU_BASE 0x1000007FFE2B4000ull +#define DCORE1_HMMU3_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_CS_SPMU_SECTION 0x1000 + +#define mmDCORE1_HMMU3_BMON_CTI_BASE 0x1000007FFE2B5000ull +#define DCORE1_HMMU3_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_BMON_CTI_SECTION 0x1000 + +#define mmDCORE1_HMMU3_USER_CTI_BASE 0x1000007FFE2B6000ull +#define DCORE1_HMMU3_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_USER_CTI_SECTION 0x1000 + +#define mmDCORE1_HMMU3_BMON_0_BASE 0x1000007FFE2B7000ull +#define DCORE1_HMMU3_BMON_0_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_BMON_0_SECTION 0x1000 + +#define mmDCORE1_HMMU3_BMON_1_BASE 0x1000007FFE2B8000ull +#define DCORE1_HMMU3_BMON_1_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_BMON_1_SECTION 0x1000 + +#define mmDCORE1_HMMU3_BMON_3_BASE 0x1000007FFE2B9000ull +#define DCORE1_HMMU3_BMON_3_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_BMON_3_SECTION 0x1000 + +#define mmDCORE1_HMMU3_BMON_2_BASE 0x1000007FFE2BA000ull +#define DCORE1_HMMU3_BMON_2_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_BMON_2_SECTION 0x1000 + +#define mmDCORE1_HMMU3_BMON_4_BASE 0x1000007FFE2BB000ull +#define DCORE1_HMMU3_BMON_4_MAX_OFFSET 0x1000 +#define DCORE1_HMMU3_BMON_4_SECTION 0x5000 + +#define mmDCORE1_SM_CS_DBG_ROM_TBL_BASE 0x1000007FFE310000ull +#define DCORE1_SM_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_SM_CS_DBG_ROM_TBL_SECTION 0x1000 + +#define mmDCORE1_SM_STM_BASE 0x1000007FFE311000ull +#define DCORE1_SM_STM_MAX_OFFSET 0x1000 +#define DCORE1_SM_STM_SECTION 0x1000 + +#define mmDCORE1_SM_CTI_BASE 0x1000007FFE312000ull +#define DCORE1_SM_CTI_MAX_OFFSET 0x1000 +#define DCORE1_SM_CTI_SECTION 0x1000 + +#define mmDCORE1_SM_ETF_BASE 0x1000007FFE313000ull +#define DCORE1_SM_ETF_MAX_OFFSET 0x1000 +#define DCORE1_SM_ETF_SECTION 0x1000 + +#define mmDCORE1_SM_SPMU_BASE 0x1000007FFE314000ull +#define DCORE1_SM_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_SM_SPMU_SECTION 0x1000 + +#define mmDCORE1_SM_BMON_CTI_BASE 0x1000007FFE315000ull +#define DCORE1_SM_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_SM_BMON_CTI_SECTION 0x1000 + +#define mmDCORE1_SM_USER_CTI_BASE 0x1000007FFE316000ull +#define DCORE1_SM_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_SM_USER_CTI_SECTION 0x1000 + +#define mmDCORE1_SM_BMON_BASE 0x1000007FFE317000ull +#define DCORE1_SM_BMON_MAX_OFFSET 0x1000 +#define DCORE1_SM_BMON_SECTION 0x1000 + +#define mmDCORE1_SM_BMON1_BASE 0x1000007FFE318000ull +#define DCORE1_SM_BMON1_MAX_OFFSET 0x1000 +#define DCORE1_SM_BMON1_SECTION 0x18000 + +#define mmDCORE1_XFT_FUNNEL_BASE 0x1000007FFE330000ull +#define DCORE1_XFT_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_XFT_FUNNEL_SECTION 0x8000 + +#define mmDCORE1_TFT0_FUNNEL_BASE 0x1000007FFE338000ull +#define DCORE1_TFT0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TFT0_FUNNEL_SECTION 0x1000 + +#define mmDCORE1_TFT1_FUNNEL_BASE 0x1000007FFE339000ull +#define DCORE1_TFT1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TFT1_FUNNEL_SECTION 0x1000 + +#define mmDCORE1_TFT2_FUNNEL_BASE 0x1000007FFE33A000ull +#define DCORE1_TFT2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_TFT2_FUNNEL_SECTION 0x7000 + +#define mmDCORE1_RTR0_FUNNEL_BASE 0x1000007FFE341000ull +#define DCORE1_RTR0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_RTR0_FUNNEL_SECTION 0x4000 + +#define mmDCORE1_MIF0_FUNNEL_BASE 0x1000007FFE345000ull +#define DCORE1_MIF0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_MIF0_FUNNEL_SECTION 0x4000 + +#define mmDCORE1_RTR1_FUNNEL_BASE 0x1000007FFE349000ull +#define DCORE1_RTR1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_RTR1_FUNNEL_SECTION 0x4000 + +#define mmDCORE1_MIF1_FUNNEL_BASE 0x1000007FFE34D000ull +#define DCORE1_MIF1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_MIF1_FUNNEL_SECTION 0x4000 + +#define mmDCORE1_RTR2_FUNNEL_BASE 0x1000007FFE351000ull +#define DCORE1_RTR2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_RTR2_FUNNEL_SECTION 0x4000 + +#define mmDCORE1_MIF2_FUNNEL_BASE 0x1000007FFE355000ull +#define DCORE1_MIF2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_MIF2_FUNNEL_SECTION 0x4000 + +#define mmDCORE1_RTR3_FUNNEL_BASE 0x1000007FFE359000ull +#define DCORE1_RTR3_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_RTR3_FUNNEL_SECTION 0x4000 + +#define mmDCORE1_MIF3_FUNNEL_BASE 0x1000007FFE35D000ull +#define DCORE1_MIF3_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_MIF3_FUNNEL_SECTION 0x4000 + +#define mmDCORE1_RTR4_FUNNEL_BASE 0x1000007FFE361000ull +#define DCORE1_RTR4_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_RTR4_FUNNEL_SECTION 0x8000 + +#define mmDCORE1_RTR5_FUNNEL_BASE 0x1000007FFE369000ull +#define DCORE1_RTR5_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_RTR5_FUNNEL_SECTION 0x8000 + +#define mmDCORE1_RTR6_FUNNEL_BASE 0x1000007FFE371000ull +#define DCORE1_RTR6_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_RTR6_FUNNEL_SECTION 0x8000 + +#define mmDCORE1_RTR7_FUNNEL_BASE 0x1000007FFE379000ull +#define DCORE1_RTR7_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_RTR7_FUNNEL_SECTION 0x47000 + +#define mmDCORE1_EDMA0_CS_ROM_TBL_BASE 0x1000007FFE3C0000ull +#define DCORE1_EDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE1_EDMA0_CS_STM_BASE 0x1000007FFE3C1000ull +#define DCORE1_EDMA0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_CS_STM_SECTION 0x1000 + +#define mmDCORE1_EDMA0_CS_CTI_BASE 0x1000007FFE3C2000ull +#define DCORE1_EDMA0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_CS_CTI_SECTION 0x1000 + +#define mmDCORE1_EDMA0_CS_ETF_BASE 0x1000007FFE3C3000ull +#define DCORE1_EDMA0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_CS_ETF_SECTION 0x1000 + +#define mmDCORE1_EDMA0_CS_SPMU_BASE 0x1000007FFE3C4000ull +#define DCORE1_EDMA0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_CS_SPMU_SECTION 0x1000 + +#define mmDCORE1_EDMA0_BMON_CTI_BASE 0x1000007FFE3C5000ull +#define DCORE1_EDMA0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_BMON_CTI_SECTION 0x1000 + +#define mmDCORE1_EDMA0_USER_CTI_BASE 0x1000007FFE3C6000ull +#define DCORE1_EDMA0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_USER_CTI_SECTION 0x1000 + +#define mmDCORE1_EDMA0_BMON_0_BASE 0x1000007FFE3C7000ull +#define DCORE1_EDMA0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_BMON_0_SECTION 0x1000 + +#define mmDCORE1_EDMA0_BMON_1_BASE 0x1000007FFE3C8000ull +#define DCORE1_EDMA0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE1_EDMA0_BMON_1_SECTION 0x1000 + +#define mmDCORE1_EDMA0_QM_ARC_RTT_BASE 0x1000007FFE3C9000ull +#define DCORE1_EDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_EDMA0_QM_ARC_RTT_SECTION 0x7000 + +#define mmDCORE1_EDMA1_CS_ROM_TBL_BASE 0x1000007FFE3D0000ull +#define DCORE1_EDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE1_EDMA1_CS_STM_BASE 0x1000007FFE3D1000ull +#define DCORE1_EDMA1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_CS_STM_SECTION 0x1000 + +#define mmDCORE1_EDMA1_CS_CTI_BASE 0x1000007FFE3D2000ull +#define DCORE1_EDMA1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_CS_CTI_SECTION 0x1000 + +#define mmDCORE1_EDMA1_CS_ETF_BASE 0x1000007FFE3D3000ull +#define DCORE1_EDMA1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_CS_ETF_SECTION 0x1000 + +#define mmDCORE1_EDMA1_CS_SPMU_BASE 0x1000007FFE3D4000ull +#define DCORE1_EDMA1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_CS_SPMU_SECTION 0x1000 + +#define mmDCORE1_EDMA1_BMON_CTI_BASE 0x1000007FFE3D5000ull +#define DCORE1_EDMA1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_BMON_CTI_SECTION 0x1000 + +#define mmDCORE1_EDMA1_USER_CTI_BASE 0x1000007FFE3D6000ull +#define DCORE1_EDMA1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_USER_CTI_SECTION 0x1000 + +#define mmDCORE1_EDMA1_BMON_0_BASE 0x1000007FFE3D7000ull +#define DCORE1_EDMA1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_BMON_0_SECTION 0x1000 + +#define mmDCORE1_EDMA1_BMON_1_BASE 0x1000007FFE3D8000ull +#define DCORE1_EDMA1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE1_EDMA1_BMON_1_SECTION 0x1000 + +#define mmDCORE1_EDMA1_QM_ARC_RTT_BASE 0x1000007FFE3D9000ull +#define DCORE1_EDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE1_EDMA1_QM_ARC_RTT_SECTION 0x7000 + +#define mmDCORE1_VDEC0_CS_ROM_TBL_BASE 0x1000007FFE3E0000ull +#define DCORE1_VDEC0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE1_VDEC0_CS_STM_BASE 0x1000007FFE3E1000ull +#define DCORE1_VDEC0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_CS_STM_SECTION 0x1000 + +#define mmDCORE1_VDEC0_CS_CTI_BASE 0x1000007FFE3E2000ull +#define DCORE1_VDEC0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_CS_CTI_SECTION 0x1000 + +#define mmDCORE1_VDEC0_CS_ETF_BASE 0x1000007FFE3E3000ull +#define DCORE1_VDEC0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_CS_ETF_SECTION 0x1000 + +#define mmDCORE1_VDEC0_CS_SPMU_BASE 0x1000007FFE3E4000ull +#define DCORE1_VDEC0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_CS_SPMU_SECTION 0x1000 + +#define mmDCORE1_VDEC0_BMON_CTI_BASE 0x1000007FFE3E5000ull +#define DCORE1_VDEC0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_BMON_CTI_SECTION 0x1000 + +#define mmDCORE1_VDEC0_USER_CTI_BASE 0x1000007FFE3E6000ull +#define DCORE1_VDEC0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_USER_CTI_SECTION 0x1000 + +#define mmDCORE1_VDEC0_BMON_0_BASE 0x1000007FFE3E7000ull +#define DCORE1_VDEC0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_BMON_0_SECTION 0x1000 + +#define mmDCORE1_VDEC0_BMON_1_BASE 0x1000007FFE3E8000ull +#define DCORE1_VDEC0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_BMON_1_SECTION 0x1000 + +#define mmDCORE1_VDEC0_BMON_2_BASE 0x1000007FFE3E9000ull +#define DCORE1_VDEC0_BMON_2_MAX_OFFSET 0x1000 +#define DCORE1_VDEC0_BMON_2_SECTION 0x7000 + +#define mmDCORE1_VDEC1_CS_ROM_TBL_BASE 0x1000007FFE3F0000ull +#define DCORE1_VDEC1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE1_VDEC1_CS_STM_BASE 0x1000007FFE3F1000ull +#define DCORE1_VDEC1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_CS_STM_SECTION 0x1000 + +#define mmDCORE1_VDEC1_CS_CTI_BASE 0x1000007FFE3F2000ull +#define DCORE1_VDEC1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_CS_CTI_SECTION 0x1000 + +#define mmDCORE1_VDEC1_CS_ETF_BASE 0x1000007FFE3F3000ull +#define DCORE1_VDEC1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_CS_ETF_SECTION 0x1000 + +#define mmDCORE1_VDEC1_CS_SPMU_BASE 0x1000007FFE3F4000ull +#define DCORE1_VDEC1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_CS_SPMU_SECTION 0x1000 + +#define mmDCORE1_VDEC1_BMON_CTI_BASE 0x1000007FFE3F5000ull +#define DCORE1_VDEC1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_BMON_CTI_SECTION 0x1000 + +#define mmDCORE1_VDEC1_USER_CTI_BASE 0x1000007FFE3F6000ull +#define DCORE1_VDEC1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_USER_CTI_SECTION 0x1000 + +#define mmDCORE1_VDEC1_BMON_0_BASE 0x1000007FFE3F7000ull +#define DCORE1_VDEC1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_BMON_0_SECTION 0x1000 + +#define mmDCORE1_VDEC1_BMON_1_BASE 0x1000007FFE3F8000ull +#define DCORE1_VDEC1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_BMON_1_SECTION 0x1000 + +#define mmDCORE1_VDEC1_BMON_2_BASE 0x1000007FFE3F9000ull +#define DCORE1_VDEC1_BMON_2_MAX_OFFSET 0x1000 +#define DCORE1_VDEC1_BMON_2_SECTION 0x7000 + +#define mmDCORE2_ROM_TABLE_L_BASE 0x1000007FFE400000ull +#define DCORE2_ROM_TABLE_L_MAX_OFFSET 0x1000 +#define DCORE2_ROM_TABLE_L_SECTION 0x80000 + +#define mmDCORE2_HMMU0_CS_ROM_TBL_BASE 0x1000007FFE480000ull +#define DCORE2_HMMU0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE2_HMMU0_CS_STM_BASE 0x1000007FFE481000ull +#define DCORE2_HMMU0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_CS_STM_SECTION 0x1000 + +#define mmDCORE2_HMMU0_CS_CTI_BASE 0x1000007FFE482000ull +#define DCORE2_HMMU0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_CS_CTI_SECTION 0x1000 + +#define mmDCORE2_HMMU0_CS_ETF_BASE 0x1000007FFE483000ull +#define DCORE2_HMMU0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_CS_ETF_SECTION 0x1000 + +#define mmDCORE2_HMMU0_CS_SPMU_BASE 0x1000007FFE484000ull +#define DCORE2_HMMU0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_CS_SPMU_SECTION 0x1000 + +#define mmDCORE2_HMMU0_BMON_CTI_BASE 0x1000007FFE485000ull +#define DCORE2_HMMU0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_BMON_CTI_SECTION 0x1000 + +#define mmDCORE2_HMMU0_USER_CTI_BASE 0x1000007FFE486000ull +#define DCORE2_HMMU0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_USER_CTI_SECTION 0x1000 + +#define mmDCORE2_HMMU0_BMON_0_BASE 0x1000007FFE487000ull +#define DCORE2_HMMU0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_BMON_0_SECTION 0x1000 + +#define mmDCORE2_HMMU0_BMON_1_BASE 0x1000007FFE488000ull +#define DCORE2_HMMU0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_BMON_1_SECTION 0x1000 + +#define mmDCORE2_HMMU0_BMON_3_BASE 0x1000007FFE489000ull +#define DCORE2_HMMU0_BMON_3_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_BMON_3_SECTION 0x1000 + +#define mmDCORE2_HMMU0_BMON_2_BASE 0x1000007FFE48A000ull +#define DCORE2_HMMU0_BMON_2_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_BMON_2_SECTION 0x1000 + +#define mmDCORE2_HMMU0_BMON_4_BASE 0x1000007FFE48B000ull +#define DCORE2_HMMU0_BMON_4_MAX_OFFSET 0x1000 +#define DCORE2_HMMU0_BMON_4_SECTION 0x5000 + +#define mmDCORE2_HMMU1_CS_ROM_TBL_BASE 0x1000007FFE490000ull +#define DCORE2_HMMU1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE2_HMMU1_CS_STM_BASE 0x1000007FFE491000ull +#define DCORE2_HMMU1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_CS_STM_SECTION 0x1000 + +#define mmDCORE2_HMMU1_CS_CTI_BASE 0x1000007FFE492000ull +#define DCORE2_HMMU1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_CS_CTI_SECTION 0x1000 + +#define mmDCORE2_HMMU1_CS_ETF_BASE 0x1000007FFE493000ull +#define DCORE2_HMMU1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_CS_ETF_SECTION 0x1000 + +#define mmDCORE2_HMMU1_CS_SPMU_BASE 0x1000007FFE494000ull +#define DCORE2_HMMU1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_CS_SPMU_SECTION 0x1000 + +#define mmDCORE2_HMMU1_BMON_CTI_BASE 0x1000007FFE495000ull +#define DCORE2_HMMU1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_BMON_CTI_SECTION 0x1000 + +#define mmDCORE2_HMMU1_USER_CTI_BASE 0x1000007FFE496000ull +#define DCORE2_HMMU1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_USER_CTI_SECTION 0x1000 + +#define mmDCORE2_HMMU1_BMON_0_BASE 0x1000007FFE497000ull +#define DCORE2_HMMU1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_BMON_0_SECTION 0x1000 + +#define mmDCORE2_HMMU1_BMON_1_BASE 0x1000007FFE498000ull +#define DCORE2_HMMU1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_BMON_1_SECTION 0x1000 + +#define mmDCORE2_HMMU1_BMON_3_BASE 0x1000007FFE499000ull +#define DCORE2_HMMU1_BMON_3_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_BMON_3_SECTION 0x1000 + +#define mmDCORE2_HMMU1_BMON_2_BASE 0x1000007FFE49A000ull +#define DCORE2_HMMU1_BMON_2_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_BMON_2_SECTION 0x1000 + +#define mmDCORE2_HMMU1_BMON_4_BASE 0x1000007FFE49B000ull +#define DCORE2_HMMU1_BMON_4_MAX_OFFSET 0x1000 +#define DCORE2_HMMU1_BMON_4_SECTION 0x5000 + +#define mmDCORE2_HMMU2_CS_ROM_TBL_BASE 0x1000007FFE4A0000ull +#define DCORE2_HMMU2_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE2_HMMU2_CS_STM_BASE 0x1000007FFE4A1000ull +#define DCORE2_HMMU2_CS_STM_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_CS_STM_SECTION 0x1000 + +#define mmDCORE2_HMMU2_CS_CTI_BASE 0x1000007FFE4A2000ull +#define DCORE2_HMMU2_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_CS_CTI_SECTION 0x1000 + +#define mmDCORE2_HMMU2_CS_ETF_BASE 0x1000007FFE4A3000ull +#define DCORE2_HMMU2_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_CS_ETF_SECTION 0x1000 + +#define mmDCORE2_HMMU2_CS_SPMU_BASE 0x1000007FFE4A4000ull +#define DCORE2_HMMU2_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_CS_SPMU_SECTION 0x1000 + +#define mmDCORE2_HMMU2_BMON_CTI_BASE 0x1000007FFE4A5000ull +#define DCORE2_HMMU2_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_BMON_CTI_SECTION 0x1000 + +#define mmDCORE2_HMMU2_USER_CTI_BASE 0x1000007FFE4A6000ull +#define DCORE2_HMMU2_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_USER_CTI_SECTION 0x1000 + +#define mmDCORE2_HMMU2_BMON_0_BASE 0x1000007FFE4A7000ull +#define DCORE2_HMMU2_BMON_0_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_BMON_0_SECTION 0x1000 + +#define mmDCORE2_HMMU2_BMON_1_BASE 0x1000007FFE4A8000ull +#define DCORE2_HMMU2_BMON_1_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_BMON_1_SECTION 0x1000 + +#define mmDCORE2_HMMU2_BMON_3_BASE 0x1000007FFE4A9000ull +#define DCORE2_HMMU2_BMON_3_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_BMON_3_SECTION 0x1000 + +#define mmDCORE2_HMMU2_BMON_2_BASE 0x1000007FFE4AA000ull +#define DCORE2_HMMU2_BMON_2_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_BMON_2_SECTION 0x1000 + +#define mmDCORE2_HMMU2_BMON_4_BASE 0x1000007FFE4AB000ull +#define DCORE2_HMMU2_BMON_4_MAX_OFFSET 0x1000 +#define DCORE2_HMMU2_BMON_4_SECTION 0x5000 + +#define mmDCORE2_HMMU3_CS_ROM_TBL_BASE 0x1000007FFE4B0000ull +#define DCORE2_HMMU3_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE2_HMMU3_CS_STM_BASE 0x1000007FFE4B1000ull +#define DCORE2_HMMU3_CS_STM_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_CS_STM_SECTION 0x1000 + +#define mmDCORE2_HMMU3_CS_CTI_BASE 0x1000007FFE4B2000ull +#define DCORE2_HMMU3_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_CS_CTI_SECTION 0x1000 + +#define mmDCORE2_HMMU3_CS_ETF_BASE 0x1000007FFE4B3000ull +#define DCORE2_HMMU3_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_CS_ETF_SECTION 0x1000 + +#define mmDCORE2_HMMU3_CS_SPMU_BASE 0x1000007FFE4B4000ull +#define DCORE2_HMMU3_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_CS_SPMU_SECTION 0x1000 + +#define mmDCORE2_HMMU3_BMON_CTI_BASE 0x1000007FFE4B5000ull +#define DCORE2_HMMU3_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_BMON_CTI_SECTION 0x1000 + +#define mmDCORE2_HMMU3_USER_CTI_BASE 0x1000007FFE4B6000ull +#define DCORE2_HMMU3_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_USER_CTI_SECTION 0x1000 + +#define mmDCORE2_HMMU3_BMON_0_BASE 0x1000007FFE4B7000ull +#define DCORE2_HMMU3_BMON_0_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_BMON_0_SECTION 0x1000 + +#define mmDCORE2_HMMU3_BMON_1_BASE 0x1000007FFE4B8000ull +#define DCORE2_HMMU3_BMON_1_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_BMON_1_SECTION 0x1000 + +#define mmDCORE2_HMMU3_BMON_3_BASE 0x1000007FFE4B9000ull +#define DCORE2_HMMU3_BMON_3_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_BMON_3_SECTION 0x1000 + +#define mmDCORE2_HMMU3_BMON_2_BASE 0x1000007FFE4BA000ull +#define DCORE2_HMMU3_BMON_2_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_BMON_2_SECTION 0x1000 + +#define mmDCORE2_HMMU3_BMON_4_BASE 0x1000007FFE4BB000ull +#define DCORE2_HMMU3_BMON_4_MAX_OFFSET 0x1000 +#define DCORE2_HMMU3_BMON_4_SECTION 0x5000 + +#define mmDCORE2_SM_CS_DBG_ROM_TBL_BASE 0x1000007FFE510000ull +#define DCORE2_SM_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_SM_CS_DBG_ROM_TBL_SECTION 0x1000 + +#define mmDCORE2_SM_STM_BASE 0x1000007FFE511000ull +#define DCORE2_SM_STM_MAX_OFFSET 0x1000 +#define DCORE2_SM_STM_SECTION 0x1000 + +#define mmDCORE2_SM_CTI_BASE 0x1000007FFE512000ull +#define DCORE2_SM_CTI_MAX_OFFSET 0x1000 +#define DCORE2_SM_CTI_SECTION 0x1000 + +#define mmDCORE2_SM_ETF_BASE 0x1000007FFE513000ull +#define DCORE2_SM_ETF_MAX_OFFSET 0x1000 +#define DCORE2_SM_ETF_SECTION 0x1000 + +#define mmDCORE2_SM_SPMU_BASE 0x1000007FFE514000ull +#define DCORE2_SM_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_SM_SPMU_SECTION 0x1000 + +#define mmDCORE2_SM_BMON_CTI_BASE 0x1000007FFE515000ull +#define DCORE2_SM_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_SM_BMON_CTI_SECTION 0x1000 + +#define mmDCORE2_SM_USER_CTI_BASE 0x1000007FFE516000ull +#define DCORE2_SM_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_SM_USER_CTI_SECTION 0x1000 + +#define mmDCORE2_SM_BMON_BASE 0x1000007FFE517000ull +#define DCORE2_SM_BMON_MAX_OFFSET 0x1000 +#define DCORE2_SM_BMON_SECTION 0x1000 + +#define mmDCORE2_SM_BMON1_BASE 0x1000007FFE518000ull +#define DCORE2_SM_BMON1_MAX_OFFSET 0x1000 +#define DCORE2_SM_BMON1_SECTION 0x18000 + +#define mmDCORE2_XFT_FUNNEL_BASE 0x1000007FFE530000ull +#define DCORE2_XFT_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_XFT_FUNNEL_SECTION 0x8000 + +#define mmDCORE2_TFT0_FUNNEL_BASE 0x1000007FFE538000ull +#define DCORE2_TFT0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TFT0_FUNNEL_SECTION 0x1000 + +#define mmDCORE2_TFT1_FUNNEL_BASE 0x1000007FFE539000ull +#define DCORE2_TFT1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TFT1_FUNNEL_SECTION 0x1000 + +#define mmDCORE2_TFT2_FUNNEL_BASE 0x1000007FFE53A000ull +#define DCORE2_TFT2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_TFT2_FUNNEL_SECTION 0x7000 + +#define mmDCORE2_RTR0_FUNNEL_BASE 0x1000007FFE541000ull +#define DCORE2_RTR0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_RTR0_FUNNEL_SECTION 0x8000 + +#define mmDCORE2_RTR1_FUNNEL_BASE 0x1000007FFE549000ull +#define DCORE2_RTR1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_RTR1_FUNNEL_SECTION 0x8000 + +#define mmDCORE2_RTR2_FUNNEL_BASE 0x1000007FFE551000ull +#define DCORE2_RTR2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_RTR2_FUNNEL_SECTION 0x8000 + +#define mmDCORE2_RTR3_FUNNEL_BASE 0x1000007FFE559000ull +#define DCORE2_RTR3_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_RTR3_FUNNEL_SECTION 0x8000 + +#define mmDCORE2_RTR4_FUNNEL_BASE 0x1000007FFE561000ull +#define DCORE2_RTR4_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_RTR4_FUNNEL_SECTION 0x4000 + +#define mmDCORE2_MIF0_FUNNEL_BASE 0x1000007FFE565000ull +#define DCORE2_MIF0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_MIF0_FUNNEL_SECTION 0x4000 + +#define mmDCORE2_RTR5_FUNNEL_BASE 0x1000007FFE569000ull +#define DCORE2_RTR5_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_RTR5_FUNNEL_SECTION 0x4000 + +#define mmDCORE2_MIF1_FUNNEL_BASE 0x1000007FFE56D000ull +#define DCORE2_MIF1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_MIF1_FUNNEL_SECTION 0x4000 + +#define mmDCORE2_RTR6_FUNNEL_BASE 0x1000007FFE571000ull +#define DCORE2_RTR6_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_RTR6_FUNNEL_SECTION 0x4000 + +#define mmDCORE2_MIF2_FUNNEL_BASE 0x1000007FFE575000ull +#define DCORE2_MIF2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_MIF2_FUNNEL_SECTION 0x4000 + +#define mmDCORE2_RTR7_FUNNEL_BASE 0x1000007FFE579000ull +#define DCORE2_RTR7_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_RTR7_FUNNEL_SECTION 0x4000 + +#define mmDCORE2_MIF3_FUNNEL_BASE 0x1000007FFE57D000ull +#define DCORE2_MIF3_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_MIF3_FUNNEL_SECTION 0x43000 + +#define mmDCORE2_EDMA0_CS_ROM_TBL_BASE 0x1000007FFE5C0000ull +#define DCORE2_EDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE2_EDMA0_CS_STM_BASE 0x1000007FFE5C1000ull +#define DCORE2_EDMA0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_CS_STM_SECTION 0x1000 + +#define mmDCORE2_EDMA0_CS_CTI_BASE 0x1000007FFE5C2000ull +#define DCORE2_EDMA0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_CS_CTI_SECTION 0x1000 + +#define mmDCORE2_EDMA0_CS_ETF_BASE 0x1000007FFE5C3000ull +#define DCORE2_EDMA0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_CS_ETF_SECTION 0x1000 + +#define mmDCORE2_EDMA0_CS_SPMU_BASE 0x1000007FFE5C4000ull +#define DCORE2_EDMA0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_CS_SPMU_SECTION 0x1000 + +#define mmDCORE2_EDMA0_BMON_CTI_BASE 0x1000007FFE5C5000ull +#define DCORE2_EDMA0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_BMON_CTI_SECTION 0x1000 + +#define mmDCORE2_EDMA0_USER_CTI_BASE 0x1000007FFE5C6000ull +#define DCORE2_EDMA0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_USER_CTI_SECTION 0x1000 + +#define mmDCORE2_EDMA0_BMON_0_BASE 0x1000007FFE5C7000ull +#define DCORE2_EDMA0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_BMON_0_SECTION 0x1000 + +#define mmDCORE2_EDMA0_BMON_1_BASE 0x1000007FFE5C8000ull +#define DCORE2_EDMA0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE2_EDMA0_BMON_1_SECTION 0x1000 + +#define mmDCORE2_EDMA0_QM_ARC_RTT_BASE 0x1000007FFE5C9000ull +#define DCORE2_EDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_EDMA0_QM_ARC_RTT_SECTION 0x7000 + +#define mmDCORE2_EDMA1_CS_ROM_TBL_BASE 0x1000007FFE5D0000ull +#define DCORE2_EDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE2_EDMA1_CS_STM_BASE 0x1000007FFE5D1000ull +#define DCORE2_EDMA1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_CS_STM_SECTION 0x1000 + +#define mmDCORE2_EDMA1_CS_CTI_BASE 0x1000007FFE5D2000ull +#define DCORE2_EDMA1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_CS_CTI_SECTION 0x1000 + +#define mmDCORE2_EDMA1_CS_ETF_BASE 0x1000007FFE5D3000ull +#define DCORE2_EDMA1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_CS_ETF_SECTION 0x1000 + +#define mmDCORE2_EDMA1_CS_SPMU_BASE 0x1000007FFE5D4000ull +#define DCORE2_EDMA1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_CS_SPMU_SECTION 0x1000 + +#define mmDCORE2_EDMA1_BMON_CTI_BASE 0x1000007FFE5D5000ull +#define DCORE2_EDMA1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_BMON_CTI_SECTION 0x1000 + +#define mmDCORE2_EDMA1_USER_CTI_BASE 0x1000007FFE5D6000ull +#define DCORE2_EDMA1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_USER_CTI_SECTION 0x1000 + +#define mmDCORE2_EDMA1_BMON_0_BASE 0x1000007FFE5D7000ull +#define DCORE2_EDMA1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_BMON_0_SECTION 0x1000 + +#define mmDCORE2_EDMA1_BMON_1_BASE 0x1000007FFE5D8000ull +#define DCORE2_EDMA1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE2_EDMA1_BMON_1_SECTION 0x1000 + +#define mmDCORE2_EDMA1_QM_ARC_RTT_BASE 0x1000007FFE5D9000ull +#define DCORE2_EDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE2_EDMA1_QM_ARC_RTT_SECTION 0x7000 + +#define mmDCORE2_VDEC0_CS_ROM_TBL_BASE 0x1000007FFE5E0000ull +#define DCORE2_VDEC0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE2_VDEC0_CS_STM_BASE 0x1000007FFE5E1000ull +#define DCORE2_VDEC0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_CS_STM_SECTION 0x1000 + +#define mmDCORE2_VDEC0_CS_CTI_BASE 0x1000007FFE5E2000ull +#define DCORE2_VDEC0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_CS_CTI_SECTION 0x1000 + +#define mmDCORE2_VDEC0_CS_ETF_BASE 0x1000007FFE5E3000ull +#define DCORE2_VDEC0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_CS_ETF_SECTION 0x1000 + +#define mmDCORE2_VDEC0_CS_SPMU_BASE 0x1000007FFE5E4000ull +#define DCORE2_VDEC0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_CS_SPMU_SECTION 0x1000 + +#define mmDCORE2_VDEC0_BMON_CTI_BASE 0x1000007FFE5E5000ull +#define DCORE2_VDEC0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_BMON_CTI_SECTION 0x1000 + +#define mmDCORE2_VDEC0_USER_CTI_BASE 0x1000007FFE5E6000ull +#define DCORE2_VDEC0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_USER_CTI_SECTION 0x1000 + +#define mmDCORE2_VDEC0_BMON_0_BASE 0x1000007FFE5E7000ull +#define DCORE2_VDEC0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_BMON_0_SECTION 0x1000 + +#define mmDCORE2_VDEC0_BMON_1_BASE 0x1000007FFE5E8000ull +#define DCORE2_VDEC0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_BMON_1_SECTION 0x1000 + +#define mmDCORE2_VDEC0_BMON_2_BASE 0x1000007FFE5E9000ull +#define DCORE2_VDEC0_BMON_2_MAX_OFFSET 0x1000 +#define DCORE2_VDEC0_BMON_2_SECTION 0x7000 + +#define mmDCORE2_VDEC1_CS_ROM_TBL_BASE 0x1000007FFE5F0000ull +#define DCORE2_VDEC1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE2_VDEC1_CS_STM_BASE 0x1000007FFE5F1000ull +#define DCORE2_VDEC1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_CS_STM_SECTION 0x1000 + +#define mmDCORE2_VDEC1_CS_CTI_BASE 0x1000007FFE5F2000ull +#define DCORE2_VDEC1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_CS_CTI_SECTION 0x1000 + +#define mmDCORE2_VDEC1_CS_ETF_BASE 0x1000007FFE5F3000ull +#define DCORE2_VDEC1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_CS_ETF_SECTION 0x1000 + +#define mmDCORE2_VDEC1_CS_SPMU_BASE 0x1000007FFE5F4000ull +#define DCORE2_VDEC1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_CS_SPMU_SECTION 0x1000 + +#define mmDCORE2_VDEC1_BMON_CTI_BASE 0x1000007FFE5F5000ull +#define DCORE2_VDEC1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_BMON_CTI_SECTION 0x1000 + +#define mmDCORE2_VDEC1_USER_CTI_BASE 0x1000007FFE5F6000ull +#define DCORE2_VDEC1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_USER_CTI_SECTION 0x1000 + +#define mmDCORE2_VDEC1_BMON_0_BASE 0x1000007FFE5F7000ull +#define DCORE2_VDEC1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_BMON_0_SECTION 0x1000 + +#define mmDCORE2_VDEC1_BMON_1_BASE 0x1000007FFE5F8000ull +#define DCORE2_VDEC1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_BMON_1_SECTION 0x1000 + +#define mmDCORE2_VDEC1_BMON_2_BASE 0x1000007FFE5F9000ull +#define DCORE2_VDEC1_BMON_2_MAX_OFFSET 0x1000 +#define DCORE2_VDEC1_BMON_2_SECTION 0x7000 + +#define mmDCORE3_ROM_TABLE_L_BASE 0x1000007FFE600000ull +#define DCORE3_ROM_TABLE_L_MAX_OFFSET 0x1000 +#define DCORE3_ROM_TABLE_L_SECTION 0x80000 + +#define mmDCORE3_HMMU0_CS_ROM_TBL_BASE 0x1000007FFE680000ull +#define DCORE3_HMMU0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE3_HMMU0_CS_STM_BASE 0x1000007FFE681000ull +#define DCORE3_HMMU0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_CS_STM_SECTION 0x1000 + +#define mmDCORE3_HMMU0_CS_CTI_BASE 0x1000007FFE682000ull +#define DCORE3_HMMU0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_CS_CTI_SECTION 0x1000 + +#define mmDCORE3_HMMU0_CS_ETF_BASE 0x1000007FFE683000ull +#define DCORE3_HMMU0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_CS_ETF_SECTION 0x1000 + +#define mmDCORE3_HMMU0_CS_SPMU_BASE 0x1000007FFE684000ull +#define DCORE3_HMMU0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_CS_SPMU_SECTION 0x1000 + +#define mmDCORE3_HMMU0_BMON_CTI_BASE 0x1000007FFE685000ull +#define DCORE3_HMMU0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_BMON_CTI_SECTION 0x1000 + +#define mmDCORE3_HMMU0_USER_CTI_BASE 0x1000007FFE686000ull +#define DCORE3_HMMU0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_USER_CTI_SECTION 0x1000 + +#define mmDCORE3_HMMU0_BMON_0_BASE 0x1000007FFE687000ull +#define DCORE3_HMMU0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_BMON_0_SECTION 0x1000 + +#define mmDCORE3_HMMU0_BMON_1_BASE 0x1000007FFE688000ull +#define DCORE3_HMMU0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_BMON_1_SECTION 0x1000 + +#define mmDCORE3_HMMU0_BMON_3_BASE 0x1000007FFE689000ull +#define DCORE3_HMMU0_BMON_3_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_BMON_3_SECTION 0x1000 + +#define mmDCORE3_HMMU0_BMON_2_BASE 0x1000007FFE68A000ull +#define DCORE3_HMMU0_BMON_2_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_BMON_2_SECTION 0x1000 + +#define mmDCORE3_HMMU0_BMON_4_BASE 0x1000007FFE68B000ull +#define DCORE3_HMMU0_BMON_4_MAX_OFFSET 0x1000 +#define DCORE3_HMMU0_BMON_4_SECTION 0x5000 + +#define mmDCORE3_HMMU1_CS_ROM_TBL_BASE 0x1000007FFE690000ull +#define DCORE3_HMMU1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE3_HMMU1_CS_STM_BASE 0x1000007FFE691000ull +#define DCORE3_HMMU1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_CS_STM_SECTION 0x1000 + +#define mmDCORE3_HMMU1_CS_CTI_BASE 0x1000007FFE692000ull +#define DCORE3_HMMU1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_CS_CTI_SECTION 0x1000 + +#define mmDCORE3_HMMU1_CS_ETF_BASE 0x1000007FFE693000ull +#define DCORE3_HMMU1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_CS_ETF_SECTION 0x1000 + +#define mmDCORE3_HMMU1_CS_SPMU_BASE 0x1000007FFE694000ull +#define DCORE3_HMMU1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_CS_SPMU_SECTION 0x1000 + +#define mmDCORE3_HMMU1_BMON_CTI_BASE 0x1000007FFE695000ull +#define DCORE3_HMMU1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_BMON_CTI_SECTION 0x1000 + +#define mmDCORE3_HMMU1_USER_CTI_BASE 0x1000007FFE696000ull +#define DCORE3_HMMU1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_USER_CTI_SECTION 0x1000 + +#define mmDCORE3_HMMU1_BMON_0_BASE 0x1000007FFE697000ull +#define DCORE3_HMMU1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_BMON_0_SECTION 0x1000 + +#define mmDCORE3_HMMU1_BMON_1_BASE 0x1000007FFE698000ull +#define DCORE3_HMMU1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_BMON_1_SECTION 0x1000 + +#define mmDCORE3_HMMU1_BMON_3_BASE 0x1000007FFE699000ull +#define DCORE3_HMMU1_BMON_3_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_BMON_3_SECTION 0x1000 + +#define mmDCORE3_HMMU1_BMON_2_BASE 0x1000007FFE69A000ull +#define DCORE3_HMMU1_BMON_2_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_BMON_2_SECTION 0x1000 + +#define mmDCORE3_HMMU1_BMON_4_BASE 0x1000007FFE69B000ull +#define DCORE3_HMMU1_BMON_4_MAX_OFFSET 0x1000 +#define DCORE3_HMMU1_BMON_4_SECTION 0x5000 + +#define mmDCORE3_HMMU2_CS_ROM_TBL_BASE 0x1000007FFE6A0000ull +#define DCORE3_HMMU2_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE3_HMMU2_CS_STM_BASE 0x1000007FFE6A1000ull +#define DCORE3_HMMU2_CS_STM_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_CS_STM_SECTION 0x1000 + +#define mmDCORE3_HMMU2_CS_CTI_BASE 0x1000007FFE6A2000ull +#define DCORE3_HMMU2_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_CS_CTI_SECTION 0x1000 + +#define mmDCORE3_HMMU2_CS_ETF_BASE 0x1000007FFE6A3000ull +#define DCORE3_HMMU2_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_CS_ETF_SECTION 0x1000 + +#define mmDCORE3_HMMU2_CS_SPMU_BASE 0x1000007FFE6A4000ull +#define DCORE3_HMMU2_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_CS_SPMU_SECTION 0x1000 + +#define mmDCORE3_HMMU2_BMON_CTI_BASE 0x1000007FFE6A5000ull +#define DCORE3_HMMU2_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_BMON_CTI_SECTION 0x1000 + +#define mmDCORE3_HMMU2_USER_CTI_BASE 0x1000007FFE6A6000ull +#define DCORE3_HMMU2_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_USER_CTI_SECTION 0x1000 + +#define mmDCORE3_HMMU2_BMON_0_BASE 0x1000007FFE6A7000ull +#define DCORE3_HMMU2_BMON_0_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_BMON_0_SECTION 0x1000 + +#define mmDCORE3_HMMU2_BMON_1_BASE 0x1000007FFE6A8000ull +#define DCORE3_HMMU2_BMON_1_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_BMON_1_SECTION 0x1000 + +#define mmDCORE3_HMMU2_BMON_3_BASE 0x1000007FFE6A9000ull +#define DCORE3_HMMU2_BMON_3_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_BMON_3_SECTION 0x1000 + +#define mmDCORE3_HMMU2_BMON_2_BASE 0x1000007FFE6AA000ull +#define DCORE3_HMMU2_BMON_2_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_BMON_2_SECTION 0x1000 + +#define mmDCORE3_HMMU2_BMON_4_BASE 0x1000007FFE6AB000ull +#define DCORE3_HMMU2_BMON_4_MAX_OFFSET 0x1000 +#define DCORE3_HMMU2_BMON_4_SECTION 0x5000 + +#define mmDCORE3_HMMU3_CS_ROM_TBL_BASE 0x1000007FFE6B0000ull +#define DCORE3_HMMU3_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE3_HMMU3_CS_STM_BASE 0x1000007FFE6B1000ull +#define DCORE3_HMMU3_CS_STM_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_CS_STM_SECTION 0x1000 + +#define mmDCORE3_HMMU3_CS_CTI_BASE 0x1000007FFE6B2000ull +#define DCORE3_HMMU3_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_CS_CTI_SECTION 0x1000 + +#define mmDCORE3_HMMU3_CS_ETF_BASE 0x1000007FFE6B3000ull +#define DCORE3_HMMU3_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_CS_ETF_SECTION 0x1000 + +#define mmDCORE3_HMMU3_CS_SPMU_BASE 0x1000007FFE6B4000ull +#define DCORE3_HMMU3_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_CS_SPMU_SECTION 0x1000 + +#define mmDCORE3_HMMU3_BMON_CTI_BASE 0x1000007FFE6B5000ull +#define DCORE3_HMMU3_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_BMON_CTI_SECTION 0x1000 + +#define mmDCORE3_HMMU3_USER_CTI_BASE 0x1000007FFE6B6000ull +#define DCORE3_HMMU3_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_USER_CTI_SECTION 0x1000 + +#define mmDCORE3_HMMU3_BMON_0_BASE 0x1000007FFE6B7000ull +#define DCORE3_HMMU3_BMON_0_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_BMON_0_SECTION 0x1000 + +#define mmDCORE3_HMMU3_BMON_1_BASE 0x1000007FFE6B8000ull +#define DCORE3_HMMU3_BMON_1_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_BMON_1_SECTION 0x1000 + +#define mmDCORE3_HMMU3_BMON_3_BASE 0x1000007FFE6B9000ull +#define DCORE3_HMMU3_BMON_3_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_BMON_3_SECTION 0x1000 + +#define mmDCORE3_HMMU3_BMON_2_BASE 0x1000007FFE6BA000ull +#define DCORE3_HMMU3_BMON_2_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_BMON_2_SECTION 0x1000 + +#define mmDCORE3_HMMU3_BMON_4_BASE 0x1000007FFE6BB000ull +#define DCORE3_HMMU3_BMON_4_MAX_OFFSET 0x1000 +#define DCORE3_HMMU3_BMON_4_SECTION 0x5000 + +#define mmDCORE3_SM_CS_DBG_ROM_TBL_BASE 0x1000007FFE710000ull +#define DCORE3_SM_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_SM_CS_DBG_ROM_TBL_SECTION 0x1000 + +#define mmDCORE3_SM_STM_BASE 0x1000007FFE711000ull +#define DCORE3_SM_STM_MAX_OFFSET 0x1000 +#define DCORE3_SM_STM_SECTION 0x1000 + +#define mmDCORE3_SM_CTI_BASE 0x1000007FFE712000ull +#define DCORE3_SM_CTI_MAX_OFFSET 0x1000 +#define DCORE3_SM_CTI_SECTION 0x1000 + +#define mmDCORE3_SM_ETF_BASE 0x1000007FFE713000ull +#define DCORE3_SM_ETF_MAX_OFFSET 0x1000 +#define DCORE3_SM_ETF_SECTION 0x1000 + +#define mmDCORE3_SM_SPMU_BASE 0x1000007FFE714000ull +#define DCORE3_SM_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_SM_SPMU_SECTION 0x1000 + +#define mmDCORE3_SM_BMON_CTI_BASE 0x1000007FFE715000ull +#define DCORE3_SM_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_SM_BMON_CTI_SECTION 0x1000 + +#define mmDCORE3_SM_USER_CTI_BASE 0x1000007FFE716000ull +#define DCORE3_SM_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_SM_USER_CTI_SECTION 0x1000 + +#define mmDCORE3_SM_BMON_BASE 0x1000007FFE717000ull +#define DCORE3_SM_BMON_MAX_OFFSET 0x1000 +#define DCORE3_SM_BMON_SECTION 0x1000 + +#define mmDCORE3_SM_BMON1_BASE 0x1000007FFE718000ull +#define DCORE3_SM_BMON1_MAX_OFFSET 0x1000 +#define DCORE3_SM_BMON1_SECTION 0x18000 + +#define mmDCORE3_XFT_FUNNEL_BASE 0x1000007FFE730000ull +#define DCORE3_XFT_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_XFT_FUNNEL_SECTION 0x8000 + +#define mmDCORE3_TFT0_FUNNEL_BASE 0x1000007FFE738000ull +#define DCORE3_TFT0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TFT0_FUNNEL_SECTION 0x1000 + +#define mmDCORE3_TFT1_FUNNEL_BASE 0x1000007FFE739000ull +#define DCORE3_TFT1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TFT1_FUNNEL_SECTION 0x1000 + +#define mmDCORE3_TFT2_FUNNEL_BASE 0x1000007FFE73A000ull +#define DCORE3_TFT2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_TFT2_FUNNEL_SECTION 0x7000 + +#define mmDCORE3_RTR0_FUNNEL_BASE 0x1000007FFE741000ull +#define DCORE3_RTR0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_RTR0_FUNNEL_SECTION 0x4000 + +#define mmDCORE3_MIF0_FUNNEL_BASE 0x1000007FFE745000ull +#define DCORE3_MIF0_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_MIF0_FUNNEL_SECTION 0x4000 + +#define mmDCORE3_RTR1_FUNNEL_BASE 0x1000007FFE749000ull +#define DCORE3_RTR1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_RTR1_FUNNEL_SECTION 0x4000 + +#define mmDCORE3_MIF1_FUNNEL_BASE 0x1000007FFE74D000ull +#define DCORE3_MIF1_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_MIF1_FUNNEL_SECTION 0x4000 + +#define mmDCORE3_RTR2_FUNNEL_BASE 0x1000007FFE751000ull +#define DCORE3_RTR2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_RTR2_FUNNEL_SECTION 0x4000 + +#define mmDCORE3_MIF2_FUNNEL_BASE 0x1000007FFE755000ull +#define DCORE3_MIF2_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_MIF2_FUNNEL_SECTION 0x4000 + +#define mmDCORE3_RTR3_FUNNEL_BASE 0x1000007FFE759000ull +#define DCORE3_RTR3_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_RTR3_FUNNEL_SECTION 0x4000 + +#define mmDCORE3_MIF3_FUNNEL_BASE 0x1000007FFE75D000ull +#define DCORE3_MIF3_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_MIF3_FUNNEL_SECTION 0x4000 + +#define mmDCORE3_RTR4_FUNNEL_BASE 0x1000007FFE761000ull +#define DCORE3_RTR4_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_RTR4_FUNNEL_SECTION 0x8000 + +#define mmDCORE3_RTR5_FUNNEL_BASE 0x1000007FFE769000ull +#define DCORE3_RTR5_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_RTR5_FUNNEL_SECTION 0x8000 + +#define mmDCORE3_RTR6_FUNNEL_BASE 0x1000007FFE771000ull +#define DCORE3_RTR6_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_RTR6_FUNNEL_SECTION 0x8000 + +#define mmDCORE3_RTR7_FUNNEL_BASE 0x1000007FFE779000ull +#define DCORE3_RTR7_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_RTR7_FUNNEL_SECTION 0x47000 + +#define mmDCORE3_EDMA0_CS_ROM_TBL_BASE 0x1000007FFE7C0000ull +#define DCORE3_EDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE3_EDMA0_CS_STM_BASE 0x1000007FFE7C1000ull +#define DCORE3_EDMA0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_CS_STM_SECTION 0x1000 + +#define mmDCORE3_EDMA0_CS_CTI_BASE 0x1000007FFE7C2000ull +#define DCORE3_EDMA0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_CS_CTI_SECTION 0x1000 + +#define mmDCORE3_EDMA0_CS_ETF_BASE 0x1000007FFE7C3000ull +#define DCORE3_EDMA0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_CS_ETF_SECTION 0x1000 + +#define mmDCORE3_EDMA0_CS_SPMU_BASE 0x1000007FFE7C4000ull +#define DCORE3_EDMA0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_CS_SPMU_SECTION 0x1000 + +#define mmDCORE3_EDMA0_BMON_CTI_BASE 0x1000007FFE7C5000ull +#define DCORE3_EDMA0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_BMON_CTI_SECTION 0x1000 + +#define mmDCORE3_EDMA0_USER_CTI_BASE 0x1000007FFE7C6000ull +#define DCORE3_EDMA0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_USER_CTI_SECTION 0x1000 + +#define mmDCORE3_EDMA0_BMON_0_BASE 0x1000007FFE7C7000ull +#define DCORE3_EDMA0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_BMON_0_SECTION 0x1000 + +#define mmDCORE3_EDMA0_BMON_1_BASE 0x1000007FFE7C8000ull +#define DCORE3_EDMA0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE3_EDMA0_BMON_1_SECTION 0x1000 + +#define mmDCORE3_EDMA0_QM_ARC_RTT_BASE 0x1000007FFE7C9000ull +#define DCORE3_EDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_EDMA0_QM_ARC_RTT_SECTION 0x7000 + +#define mmDCORE3_EDMA1_CS_ROM_TBL_BASE 0x1000007FFE7D0000ull +#define DCORE3_EDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE3_EDMA1_CS_STM_BASE 0x1000007FFE7D1000ull +#define DCORE3_EDMA1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_CS_STM_SECTION 0x1000 + +#define mmDCORE3_EDMA1_CS_CTI_BASE 0x1000007FFE7D2000ull +#define DCORE3_EDMA1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_CS_CTI_SECTION 0x1000 + +#define mmDCORE3_EDMA1_CS_ETF_BASE 0x1000007FFE7D3000ull +#define DCORE3_EDMA1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_CS_ETF_SECTION 0x1000 + +#define mmDCORE3_EDMA1_CS_SPMU_BASE 0x1000007FFE7D4000ull +#define DCORE3_EDMA1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_CS_SPMU_SECTION 0x1000 + +#define mmDCORE3_EDMA1_BMON_CTI_BASE 0x1000007FFE7D5000ull +#define DCORE3_EDMA1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_BMON_CTI_SECTION 0x1000 + +#define mmDCORE3_EDMA1_USER_CTI_BASE 0x1000007FFE7D6000ull +#define DCORE3_EDMA1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_USER_CTI_SECTION 0x1000 + +#define mmDCORE3_EDMA1_BMON_0_BASE 0x1000007FFE7D7000ull +#define DCORE3_EDMA1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_BMON_0_SECTION 0x1000 + +#define mmDCORE3_EDMA1_BMON_1_BASE 0x1000007FFE7D8000ull +#define DCORE3_EDMA1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE3_EDMA1_BMON_1_SECTION 0x1000 + +#define mmDCORE3_EDMA1_QM_ARC_RTT_BASE 0x1000007FFE7D9000ull +#define DCORE3_EDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define DCORE3_EDMA1_QM_ARC_RTT_SECTION 0x7000 + +#define mmDCORE3_VDEC0_CS_ROM_TBL_BASE 0x1000007FFE7E0000ull +#define DCORE3_VDEC0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE3_VDEC0_CS_STM_BASE 0x1000007FFE7E1000ull +#define DCORE3_VDEC0_CS_STM_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_CS_STM_SECTION 0x1000 + +#define mmDCORE3_VDEC0_CS_CTI_BASE 0x1000007FFE7E2000ull +#define DCORE3_VDEC0_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_CS_CTI_SECTION 0x1000 + +#define mmDCORE3_VDEC0_CS_ETF_BASE 0x1000007FFE7E3000ull +#define DCORE3_VDEC0_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_CS_ETF_SECTION 0x1000 + +#define mmDCORE3_VDEC0_CS_SPMU_BASE 0x1000007FFE7E4000ull +#define DCORE3_VDEC0_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_CS_SPMU_SECTION 0x1000 + +#define mmDCORE3_VDEC0_BMON_CTI_BASE 0x1000007FFE7E5000ull +#define DCORE3_VDEC0_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_BMON_CTI_SECTION 0x1000 + +#define mmDCORE3_VDEC0_USER_CTI_BASE 0x1000007FFE7E6000ull +#define DCORE3_VDEC0_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_USER_CTI_SECTION 0x1000 + +#define mmDCORE3_VDEC0_BMON_0_BASE 0x1000007FFE7E7000ull +#define DCORE3_VDEC0_BMON_0_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_BMON_0_SECTION 0x1000 + +#define mmDCORE3_VDEC0_BMON_1_BASE 0x1000007FFE7E8000ull +#define DCORE3_VDEC0_BMON_1_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_BMON_1_SECTION 0x1000 + +#define mmDCORE3_VDEC0_BMON_2_BASE 0x1000007FFE7E9000ull +#define DCORE3_VDEC0_BMON_2_MAX_OFFSET 0x1000 +#define DCORE3_VDEC0_BMON_2_SECTION 0x7000 + +#define mmDCORE3_VDEC1_CS_ROM_TBL_BASE 0x1000007FFE7F0000ull +#define DCORE3_VDEC1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_CS_ROM_TBL_SECTION 0x1000 + +#define mmDCORE3_VDEC1_CS_STM_BASE 0x1000007FFE7F1000ull +#define DCORE3_VDEC1_CS_STM_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_CS_STM_SECTION 0x1000 + +#define mmDCORE3_VDEC1_CS_CTI_BASE 0x1000007FFE7F2000ull +#define DCORE3_VDEC1_CS_CTI_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_CS_CTI_SECTION 0x1000 + +#define mmDCORE3_VDEC1_CS_ETF_BASE 0x1000007FFE7F3000ull +#define DCORE3_VDEC1_CS_ETF_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_CS_ETF_SECTION 0x1000 + +#define mmDCORE3_VDEC1_CS_SPMU_BASE 0x1000007FFE7F4000ull +#define DCORE3_VDEC1_CS_SPMU_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_CS_SPMU_SECTION 0x1000 + +#define mmDCORE3_VDEC1_BMON_CTI_BASE 0x1000007FFE7F5000ull +#define DCORE3_VDEC1_BMON_CTI_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_BMON_CTI_SECTION 0x1000 + +#define mmDCORE3_VDEC1_USER_CTI_BASE 0x1000007FFE7F6000ull +#define DCORE3_VDEC1_USER_CTI_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_USER_CTI_SECTION 0x1000 + +#define mmDCORE3_VDEC1_BMON_0_BASE 0x1000007FFE7F7000ull +#define DCORE3_VDEC1_BMON_0_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_BMON_0_SECTION 0x1000 + +#define mmDCORE3_VDEC1_BMON_1_BASE 0x1000007FFE7F8000ull +#define DCORE3_VDEC1_BMON_1_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_BMON_1_SECTION 0x1000 + +#define mmDCORE3_VDEC1_BMON_2_BASE 0x1000007FFE7F9000ull +#define DCORE3_VDEC1_BMON_2_MAX_OFFSET 0x1000 +#define DCORE3_VDEC1_BMON_2_SECTION 0x7000 + +#define mmCA53_BASE 0x1000007FFE800000ull +#define CA53_MAX_OFFSET 0x141000 +#define CA53_SECTION 0x400000 + +#define mmPCI_ROM_TABLE_BASE 0x1000007FFEC00000ull +#define PCI_ROM_TABLE_MAX_OFFSET 0x1000 +#define PCI_ROM_TABLE_SECTION 0x1000 + +#define mmPCIE_STM_BASE 0x1000007FFEC01000ull +#define PCIE_STM_MAX_OFFSET 0x1000 +#define PCIE_STM_SECTION 0x1000 + +#define mmPCIE_ETF_BASE 0x1000007FFEC02000ull +#define PCIE_ETF_MAX_OFFSET 0x1000 +#define PCIE_ETF_SECTION 0x1000 + +#define mmPCIE_CTI_0_BASE 0x1000007FFEC03000ull +#define PCIE_CTI_0_MAX_OFFSET 0x1000 +#define PCIE_CTI_0_SECTION 0x1000 + +#define mmPCIE_SPMU_BASE 0x1000007FFEC04000ull +#define PCIE_SPMU_MAX_OFFSET 0x1000 +#define PCIE_SPMU_SECTION 0x1000 + +#define mmPCIE_CTI_1_BASE 0x1000007FFEC05000ull +#define PCIE_CTI_1_MAX_OFFSET 0x1000 +#define PCIE_CTI_1_SECTION 0x2000 + +#define mmPCIE_BMON_MSTR_WR_BASE 0x1000007FFEC07000ull +#define PCIE_BMON_MSTR_WR_MAX_OFFSET 0x1000 +#define PCIE_BMON_MSTR_WR_SECTION 0x1000 + +#define mmPCIE_BMON_MSTR_RD_BASE 0x1000007FFEC08000ull +#define PCIE_BMON_MSTR_RD_MAX_OFFSET 0x1000 +#define PCIE_BMON_MSTR_RD_SECTION 0x1000 + +#define mmPCIE_BMON_SLV_WR_BASE 0x1000007FFEC09000ull +#define PCIE_BMON_SLV_WR_MAX_OFFSET 0x1000 +#define PCIE_BMON_SLV_WR_SECTION 0x1000 + +#define mmPCIE_BMON_SLV_RD_BASE 0x1000007FFEC0A000ull +#define PCIE_BMON_SLV_RD_MAX_OFFSET 0x1000 +#define PCIE_BMON_SLV_RD_SECTION 0x36000 + +#define mmTOP_ROM_TABLE_BASE 0x1000007FFEC40000ull +#define TOP_ROM_TABLE_MAX_OFFSET 0x1000 +#define TOP_ROM_TABLE_SECTION 0x1000 + +#define mmPSOC_CTI_BASE 0x1000007FFEC41000ull +#define PSOC_CTI_MAX_OFFSET 0x1000 +#define PSOC_CTI_SECTION 0x1000 + +#define mmPSOC_STM_BASE 0x1000007FFEC42000ull +#define PSOC_STM_MAX_OFFSET 0x1000 +#define PSOC_STM_SECTION 0x1000 + +#define mmPSOC_FUNNEL_BASE 0x1000007FFEC43000ull +#define PSOC_FUNNEL_MAX_OFFSET 0x1000 +#define PSOC_FUNNEL_SECTION 0x1000 + +#define mmPSOC_ETR_BASE 0x1000007FFEC44000ull +#define PSOC_ETR_MAX_OFFSET 0x1000 +#define PSOC_ETR_SECTION 0x1000 + +#define mmPSOC_ETF_BASE 0x1000007FFEC45000ull +#define PSOC_ETF_MAX_OFFSET 0x1000 +#define PSOC_ETF_SECTION 0x1000 + +#define mmPSOC_TS_CTI_BASE 0x1000007FFEC46000ull +#define PSOC_TS_CTI_MAX_OFFSET 0x1000 +#define PSOC_TS_CTI_SECTION 0xA000 + +#define mmPSOC_ARC0_CS_DBG_ROM_TBL_BASE 0x1000007FFEC50000ull +#define PSOC_ARC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CS_DBG_ROM_TBL_SECTION 0x1000 + +#define mmPSOC_ARC0_CS_STM_BASE 0x1000007FFEC51000ull +#define PSOC_ARC0_CS_STM_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CS_STM_SECTION 0x1000 + +#define mmPSOC_ARC0_CS_CTI_BASE 0x1000007FFEC52000ull +#define PSOC_ARC0_CS_CTI_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CS_CTI_SECTION 0x1000 + +#define mmPSOC_ARC0_CS_ETF_BASE 0x1000007FFEC53000ull +#define PSOC_ARC0_CS_ETF_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CS_ETF_SECTION 0x1000 + +#define mmPSOC_ARC0_CS_SPMU_BASE 0x1000007FFEC54000ull +#define PSOC_ARC0_CS_SPMU_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CS_SPMU_SECTION 0x1000 + +#define mmPSOC_ARC0_BMON_CTI_BASE 0x1000007FFEC55000ull +#define PSOC_ARC0_BMON_CTI_MAX_OFFSET 0x1000 +#define PSOC_ARC0_BMON_CTI_SECTION 0x1000 + +#define mmPSOC_ARC0_USER_CTI_BASE 0x1000007FFEC56000ull +#define PSOC_ARC0_USER_CTI_MAX_OFFSET 0x1000 +#define PSOC_ARC0_USER_CTI_SECTION 0x1000 + +#define mmPSOC_ARC0_BMON_0_BASE 0x1000007FFEC57000ull +#define PSOC_ARC0_BMON_0_MAX_OFFSET 0x1000 +#define PSOC_ARC0_BMON_0_SECTION 0x1000 + +#define mmPSOC_ARC0_BMON_1_BASE 0x1000007FFEC58000ull +#define PSOC_ARC0_BMON_1_MAX_OFFSET 0x1000 +#define PSOC_ARC0_BMON_1_SECTION 0x6000 + +#define mmPSOC_ARC0_RTT_BASE 0x1000007FFEC5E000ull +#define PSOC_ARC0_RTT_MAX_OFFSET 0x1400 +#define PSOC_ARC0_RTT_SECTION 0x1000 + +#define mmPSOC_ARC0_FUNNEL_BASE 0x1000007FFEC5F000ull +#define PSOC_ARC0_FUNNEL_MAX_OFFSET 0x1000 +#define PSOC_ARC0_FUNNEL_SECTION 0x1000 + +#define mmPSOC_ARC1_CS_DBG_ROM_TBL_BASE 0x1000007FFEC60000ull +#define PSOC_ARC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CS_DBG_ROM_TBL_SECTION 0x1000 + +#define mmPSOC_ARC1_CS_STM_BASE 0x1000007FFEC61000ull +#define PSOC_ARC1_CS_STM_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CS_STM_SECTION 0x1000 + +#define mmPSOC_ARC1_CS_CTI_BASE 0x1000007FFEC62000ull +#define PSOC_ARC1_CS_CTI_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CS_CTI_SECTION 0x1000 + +#define mmPSOC_ARC1_CS_ETF_BASE 0x1000007FFEC63000ull +#define PSOC_ARC1_CS_ETF_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CS_ETF_SECTION 0x1000 + +#define mmPSOC_ARC1_CS_SPMU_BASE 0x1000007FFEC64000ull +#define PSOC_ARC1_CS_SPMU_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CS_SPMU_SECTION 0x1000 + +#define mmPSOC_ARC1_BMON_CTI_BASE 0x1000007FFEC65000ull +#define PSOC_ARC1_BMON_CTI_MAX_OFFSET 0x1000 +#define PSOC_ARC1_BMON_CTI_SECTION 0x1000 + +#define mmPSOC_ARC1_USER_CTI_BASE 0x1000007FFEC66000ull +#define PSOC_ARC1_USER_CTI_MAX_OFFSET 0x1000 +#define PSOC_ARC1_USER_CTI_SECTION 0x1000 + +#define mmPSOC_ARC1_BMON_0_BASE 0x1000007FFEC67000ull +#define PSOC_ARC1_BMON_0_MAX_OFFSET 0x1000 +#define PSOC_ARC1_BMON_0_SECTION 0x1000 + +#define mmPSOC_ARC1_BMON_1_BASE 0x1000007FFEC68000ull +#define PSOC_ARC1_BMON_1_MAX_OFFSET 0x1000 +#define PSOC_ARC1_BMON_1_SECTION 0x6000 + +#define mmPSOC_ARC1_RTT_BASE 0x1000007FFEC6E000ull +#define PSOC_ARC1_RTT_MAX_OFFSET 0x1400 +#define PSOC_ARC1_RTT_SECTION 0x1000 + +#define mmPSOC_ARC1_FUNNEL_BASE 0x1000007FFEC6F000ull +#define PSOC_ARC1_FUNNEL_MAX_OFFSET 0x1000 +#define PSOC_ARC1_FUNNEL_SECTION 0x1000 + +#define mmPSOC_ARC0_CTI0_BASE 0x1000007FFEC70000ull +#define PSOC_ARC0_CTI0_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CTI0_SECTION 0x1000 + +#define mmPSOC_ARC0_CTI1_BASE 0x1000007FFEC71000ull +#define PSOC_ARC0_CTI1_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CTI1_SECTION 0x1000 + +#define mmPSOC_ARC0_CTI2_BASE 0x1000007FFEC72000ull +#define PSOC_ARC0_CTI2_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CTI2_SECTION 0x1000 + +#define mmPSOC_ARC0_CTI3_BASE 0x1000007FFEC73000ull +#define PSOC_ARC0_CTI3_MAX_OFFSET 0x1000 +#define PSOC_ARC0_CTI3_SECTION 0x1000 + +#define mmPSOC_ARC1_CTI0_BASE 0x1000007FFEC74000ull +#define PSOC_ARC1_CTI0_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CTI0_SECTION 0x1000 + +#define mmPSOC_ARC1_CTI1_BASE 0x1000007FFEC75000ull +#define PSOC_ARC1_CTI1_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CTI1_SECTION 0x1000 + +#define mmPSOC_ARC1_CTI2_BASE 0x1000007FFEC76000ull +#define PSOC_ARC1_CTI2_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CTI2_SECTION 0x1000 + +#define mmPSOC_ARC1_CTI3_BASE 0x1000007FFEC77000ull +#define PSOC_ARC1_CTI3_MAX_OFFSET 0x1000 +#define PSOC_ARC1_CTI3_SECTION 0x9000 + +#define mmPDMA0_CS_ROM_TBL_BASE 0x1000007FFEC80000ull +#define PDMA0_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define PDMA0_CS_ROM_TBL_SECTION 0x1000 + +#define mmPDMA0_CS_STM_BASE 0x1000007FFEC81000ull +#define PDMA0_CS_STM_MAX_OFFSET 0x1000 +#define PDMA0_CS_STM_SECTION 0x1000 + +#define mmPDMA0_CS_CTI_BASE 0x1000007FFEC82000ull +#define PDMA0_CS_CTI_MAX_OFFSET 0x1000 +#define PDMA0_CS_CTI_SECTION 0x1000 + +#define mmPDMA0_CS_ETF_BASE 0x1000007FFEC83000ull +#define PDMA0_CS_ETF_MAX_OFFSET 0x1000 +#define PDMA0_CS_ETF_SECTION 0x1000 + +#define mmPDMA0_CS_SPMU_BASE 0x1000007FFEC84000ull +#define PDMA0_CS_SPMU_MAX_OFFSET 0x1000 +#define PDMA0_CS_SPMU_SECTION 0x1000 + +#define mmPDMA0_BMON_CTI_BASE 0x1000007FFEC85000ull +#define PDMA0_BMON_CTI_MAX_OFFSET 0x1000 +#define PDMA0_BMON_CTI_SECTION 0x1000 + +#define mmPDMA0_USER_CTI_BASE 0x1000007FFEC86000ull +#define PDMA0_USER_CTI_MAX_OFFSET 0x1000 +#define PDMA0_USER_CTI_SECTION 0x1000 + +#define mmPDMA0_BMON_0_BASE 0x1000007FFEC87000ull +#define PDMA0_BMON_0_MAX_OFFSET 0x1000 +#define PDMA0_BMON_0_SECTION 0x1000 + +#define mmPDMA0_BMON_1_BASE 0x1000007FFEC88000ull +#define PDMA0_BMON_1_MAX_OFFSET 0x1000 +#define PDMA0_BMON_1_SECTION 0x1000 + +#define mmPDMA0_QM_ARC_RTT_BASE 0x1000007FFEC89000ull +#define PDMA0_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define PDMA0_QM_ARC_RTT_SECTION 0x7000 + +#define mmPDMA1_CS_ROM_TBL_BASE 0x1000007FFEC90000ull +#define PDMA1_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define PDMA1_CS_ROM_TBL_SECTION 0x1000 + +#define mmPDMA1_CS_STM_BASE 0x1000007FFEC91000ull +#define PDMA1_CS_STM_MAX_OFFSET 0x1000 +#define PDMA1_CS_STM_SECTION 0x1000 + +#define mmPDMA1_CS_CTI_BASE 0x1000007FFEC92000ull +#define PDMA1_CS_CTI_MAX_OFFSET 0x1000 +#define PDMA1_CS_CTI_SECTION 0x1000 + +#define mmPDMA1_CS_ETF_BASE 0x1000007FFEC93000ull +#define PDMA1_CS_ETF_MAX_OFFSET 0x1000 +#define PDMA1_CS_ETF_SECTION 0x1000 + +#define mmPDMA1_CS_SPMU_BASE 0x1000007FFEC94000ull +#define PDMA1_CS_SPMU_MAX_OFFSET 0x1000 +#define PDMA1_CS_SPMU_SECTION 0x1000 + +#define mmPDMA1_BMON_CTI_BASE 0x1000007FFEC95000ull +#define PDMA1_BMON_CTI_MAX_OFFSET 0x1000 +#define PDMA1_BMON_CTI_SECTION 0x1000 + +#define mmPDMA1_USER_CTI_BASE 0x1000007FFEC96000ull +#define PDMA1_USER_CTI_MAX_OFFSET 0x1000 +#define PDMA1_USER_CTI_SECTION 0x1000 + +#define mmPDMA1_BMON_0_BASE 0x1000007FFEC97000ull +#define PDMA1_BMON_0_MAX_OFFSET 0x1000 +#define PDMA1_BMON_0_SECTION 0x1000 + +#define mmPDMA1_BMON_1_BASE 0x1000007FFEC98000ull +#define PDMA1_BMON_1_MAX_OFFSET 0x1000 +#define PDMA1_BMON_1_SECTION 0x1000 + +#define mmPDMA1_QM_ARC_RTT_BASE 0x1000007FFEC99000ull +#define PDMA1_QM_ARC_RTT_MAX_OFFSET 0x1400 +#define PDMA1_QM_ARC_RTT_SECTION 0x7000 + +#define mmXDMA_FUNNEL_BASE 0x1000007FFECA0000ull +#define XDMA_FUNNEL_MAX_OFFSET 0x1000 +#define XDMA_FUNNEL_SECTION 0x21000 + +#define mmCPU_ETF_0_BASE 0x1000007FFECC1000ull +#define CPU_ETF_0_MAX_OFFSET 0x1000 +#define CPU_ETF_0_SECTION 0x1000 + +#define mmCPU_ETF_1_BASE 0x1000007FFECC2000ull +#define CPU_ETF_1_MAX_OFFSET 0x1000 +#define CPU_ETF_1_SECTION 0x2000 + +#define mmCPU_CTI_BASE 0x1000007FFECC4000ull +#define CPU_CTI_MAX_OFFSET 0x1000 +#define CPU_CTI_SECTION 0x1000 + +#define mmCPU_FUNNEL_BASE 0x1000007FFECC5000ull +#define CPU_FUNNEL_MAX_OFFSET 0x1000 +#define CPU_FUNNEL_SECTION 0x1000 + +#define mmCPU_STM_BASE 0x1000007FFECC6000ull +#define CPU_STM_MAX_OFFSET 0x1000 +#define CPU_STM_SECTION 0x1000 + +#define mmCPU_CTI_TRACE_BASE 0x1000007FFECC7000ull +#define CPU_CTI_TRACE_MAX_OFFSET 0x1000 +#define CPU_CTI_TRACE_SECTION 0x1000 + +#define mmCPU_ETF_TRACE_BASE 0x1000007FFECC8000ull +#define CPU_ETF_TRACE_MAX_OFFSET 0x1000 +#define CPU_ETF_TRACE_SECTION 0x1000 + +#define mmCPU_WR_BMON_BASE 0x1000007FFECC9000ull +#define CPU_WR_BMON_MAX_OFFSET 0x1000 +#define CPU_WR_BMON_SECTION 0x1000 + +#define mmCPU_RD_BMON_BASE 0x1000007FFECCA000ull +#define CPU_RD_BMON_MAX_OFFSET 0x1000 +#define CPU_RD_BMON_SECTION 0x36000 + +#define mmPMMU_CS_DBG_ROM_TBL_BASE 0x1000007FFED00000ull +#define PMMU_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define PMMU_CS_DBG_ROM_TBL_SECTION 0x1000 + +#define mmPMMU_CS_STM_BASE 0x1000007FFED01000ull +#define PMMU_CS_STM_MAX_OFFSET 0x1000 +#define PMMU_CS_STM_SECTION 0x1000 + +#define mmPMMU_CS_CTI_BASE 0x1000007FFED02000ull +#define PMMU_CS_CTI_MAX_OFFSET 0x1000 +#define PMMU_CS_CTI_SECTION 0x1000 + +#define mmPMMU_CS_ETF_BASE 0x1000007FFED03000ull +#define PMMU_CS_ETF_MAX_OFFSET 0x1000 +#define PMMU_CS_ETF_SECTION 0x1000 + +#define mmPMMU_CS_SPMU_BASE 0x1000007FFED04000ull +#define PMMU_CS_SPMU_MAX_OFFSET 0x1000 +#define PMMU_CS_SPMU_SECTION 0x1000 + +#define mmPMMU_BMON_CTI_BASE 0x1000007FFED05000ull +#define PMMU_BMON_CTI_MAX_OFFSET 0x1000 +#define PMMU_BMON_CTI_SECTION 0x1000 + +#define mmPMMU_USER_CTI_BASE 0x1000007FFED06000ull +#define PMMU_USER_CTI_MAX_OFFSET 0x1000 +#define PMMU_USER_CTI_SECTION 0x1000 + +#define mmPMMU_BMON_0_BASE 0x1000007FFED07000ull +#define PMMU_BMON_0_MAX_OFFSET 0x1000 +#define PMMU_BMON_0_SECTION 0x1000 + +#define mmPMMU_BMON_1_BASE 0x1000007FFED08000ull +#define PMMU_BMON_1_MAX_OFFSET 0x1000 +#define PMMU_BMON_1_SECTION 0x1000 + +#define mmPMMU_BMON_2_BASE 0x1000007FFED09000ull +#define PMMU_BMON_2_MAX_OFFSET 0x1000 +#define PMMU_BMON_2_SECTION 0x1000 + +#define mmPMMU_BMON_3_BASE 0x1000007FFED0A000ull +#define PMMU_BMON_3_MAX_OFFSET 0x1000 +#define PMMU_BMON_3_SECTION 0x1000 + +#define mmPMMU_BMON_4_BASE 0x1000007FFED0B000ull +#define PMMU_BMON_4_MAX_OFFSET 0x1000 +#define PMMU_BMON_4_SECTION 0x1000 + +#define mmPMMU_FUNNEL_BASE 0x1000007FFED0C000ull +#define PMMU_FUNNEL_MAX_OFFSET 0x1000 +#define PMMU_FUNNEL_SECTION 0x1000 + +#define mmPMMU_FUNNEL_DEC_BASE 0x1000007FFED0D000ull +#define PMMU_FUNNEL_DEC_MAX_OFFSET 0x1000 +#define PMMU_FUNNEL_DEC_SECTION 0x33000 + +#define mmDCORE0_XBAR_MID_FUNNEL_BASE 0x1000007FFED40000ull +#define DCORE0_XBAR_MID_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_XBAR_MID_FUNNEL_SECTION 0x8000 + +#define mmDCORE0_XBAR_EDGE_FUNNEL_BASE 0x1000007FFED48000ull +#define DCORE0_XBAR_EDGE_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE0_XBAR_EDGE_FUNNEL_SECTION 0x8000 + +#define mmDCORE1_XBAR_MID_FUNNEL_BASE 0x1000007FFED50000ull +#define DCORE1_XBAR_MID_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_XBAR_MID_FUNNEL_SECTION 0x8000 + +#define mmDCORE1_XBAR_EDGE_FUNNEL_BASE 0x1000007FFED58000ull +#define DCORE1_XBAR_EDGE_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE1_XBAR_EDGE_FUNNEL_SECTION 0x8000 + +#define mmDCORE2_XBAR_MID_FUNNEL_BASE 0x1000007FFED60000ull +#define DCORE2_XBAR_MID_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_XBAR_MID_FUNNEL_SECTION 0x8000 + +#define mmDCORE2_XBAR_EDGE_FUNNEL_BASE 0x1000007FFED68000ull +#define DCORE2_XBAR_EDGE_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE2_XBAR_EDGE_FUNNEL_SECTION 0x8000 + +#define mmDCORE3_XBAR_MID_FUNNEL_BASE 0x1000007FFED70000ull +#define DCORE3_XBAR_MID_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_XBAR_MID_FUNNEL_SECTION 0x8000 + +#define mmDCORE3_XBAR_EDGE_FUNNEL_BASE 0x1000007FFED78000ull +#define DCORE3_XBAR_EDGE_FUNNEL_MAX_OFFSET 0x1000 +#define DCORE3_XBAR_EDGE_FUNNEL_SECTION 0x88000 + +#define mmARC_FARM_ARC0_RTT_BASE 0x1000007FFEE80000ull +#define ARC_FARM_ARC0_RTT_MAX_OFFSET 0x1400 +#define ARC_FARM_ARC0_RTT_SECTION 0x1000 + +#define mmARC_FARM_ARC1_RTT_BASE 0x1000007FFEE81000ull +#define ARC_FARM_ARC1_RTT_MAX_OFFSET 0x1400 +#define ARC_FARM_ARC1_RTT_SECTION 0x1000 + +#define mmARC_FARM_ARC2_RTT_BASE 0x1000007FFEE82000ull +#define ARC_FARM_ARC2_RTT_MAX_OFFSET 0x1400 +#define ARC_FARM_ARC2_RTT_SECTION 0x1000 + +#define mmARC_FARM_ARC3_RTT_BASE 0x1000007FFEE83000ull +#define ARC_FARM_ARC3_RTT_MAX_OFFSET 0x1400 +#define ARC_FARM_ARC3_RTT_SECTION 0xD000 + +#define mmARC_FARM_CS_ROM_TBL_BASE 0x1000007FFEE90000ull +#define ARC_FARM_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define ARC_FARM_CS_ROM_TBL_SECTION 0x1000 + +#define mmARC_FARM_CS_STM_BASE 0x1000007FFEE91000ull +#define ARC_FARM_CS_STM_MAX_OFFSET 0x1000 +#define ARC_FARM_CS_STM_SECTION 0x1000 + +#define mmARC_FARM_CS_CTI_BASE 0x1000007FFEE92000ull +#define ARC_FARM_CS_CTI_MAX_OFFSET 0x1000 +#define ARC_FARM_CS_CTI_SECTION 0x1000 + +#define mmARC_FARM_CS_ETF_BASE 0x1000007FFEE93000ull +#define ARC_FARM_CS_ETF_MAX_OFFSET 0x1000 +#define ARC_FARM_CS_ETF_SECTION 0x1000 + +#define mmARC_FARM_CS_SPMU_BASE 0x1000007FFEE94000ull +#define ARC_FARM_CS_SPMU_MAX_OFFSET 0x1000 +#define ARC_FARM_CS_SPMU_SECTION 0x1000 + +#define mmARC_FARM_BMON_CTI_BASE 0x1000007FFEE95000ull +#define ARC_FARM_BMON_CTI_MAX_OFFSET 0x1000 +#define ARC_FARM_BMON_CTI_SECTION 0x1000 + +#define mmARC_FARM_USER_CTI_BASE 0x1000007FFEE96000ull +#define ARC_FARM_USER_CTI_MAX_OFFSET 0x1000 +#define ARC_FARM_USER_CTI_SECTION 0x1000 + +#define mmARC_FARM_BMON_0_BASE 0x1000007FFEE97000ull +#define ARC_FARM_BMON_0_MAX_OFFSET 0x1000 +#define ARC_FARM_BMON_0_SECTION 0x1000 + +#define mmARC_FARM_BMON_1_BASE 0x1000007FFEE98000ull +#define ARC_FARM_BMON_1_MAX_OFFSET 0x1000 +#define ARC_FARM_BMON_1_SECTION 0x1000 + +#define mmARC_FARM_BMON_2_BASE 0x1000007FFEE99000ull +#define ARC_FARM_BMON_2_MAX_OFFSET 0x1000 +#define ARC_FARM_BMON_2_SECTION 0x1000 + +#define mmARC_FARM_BMON_3_BASE 0x1000007FFEE9A000ull +#define ARC_FARM_BMON_3_MAX_OFFSET 0x1000 +#define ARC_FARM_BMON_3_SECTION 0x1000 + +#define mmARC_FARM_CTI_BASE 0x1000007FFEE9B000ull +#define ARC_FARM_CTI_MAX_OFFSET 0x1000 +#define ARC_FARM_CTI_SECTION 0x1000 + +#define mmARC_FARM_FUNNEL_BASE 0x1000007FFEE9C000ull +#define ARC_FARM_FUNNEL_MAX_OFFSET 0x1000 +#define ARC_FARM_FUNNEL_SECTION 0x4000 + +#define mmKDMA_CS_ROM_TBL_BASE 0x1000007FFEEA0000ull +#define KDMA_CS_ROM_TBL_MAX_OFFSET 0x1000 +#define KDMA_CS_ROM_TBL_SECTION 0x1000 + +#define mmKDMA_CS_STM_BASE 0x1000007FFEEA1000ull +#define KDMA_CS_STM_MAX_OFFSET 0x1000 +#define KDMA_CS_STM_SECTION 0x1000 + +#define mmKDMA_CS_CTI_BASE 0x1000007FFEEA2000ull +#define KDMA_CS_CTI_MAX_OFFSET 0x1000 +#define KDMA_CS_CTI_SECTION 0x1000 + +#define mmKDMA_CS_ETF_BASE 0x1000007FFEEA3000ull +#define KDMA_CS_ETF_MAX_OFFSET 0x1000 +#define KDMA_CS_ETF_SECTION 0x1000 + +#define mmKDMA_CS_SPMU_BASE 0x1000007FFEEA4000ull +#define KDMA_CS_SPMU_MAX_OFFSET 0x1000 +#define KDMA_CS_SPMU_SECTION 0x1000 + +#define mmKDMA_BMON_CTI_BASE 0x1000007FFEEA5000ull +#define KDMA_BMON_CTI_MAX_OFFSET 0x1000 +#define KDMA_BMON_CTI_SECTION 0x1000 + +#define mmKDMA_USER_CTI_BASE 0x1000007FFEEA6000ull +#define KDMA_USER_CTI_MAX_OFFSET 0x1000 +#define KDMA_USER_CTI_SECTION 0x1000 + +#define mmKDMA_BMON_0_BASE 0x1000007FFEEA7000ull +#define KDMA_BMON_0_MAX_OFFSET 0x1000 +#define KDMA_BMON_0_SECTION 0x1000 + +#define mmKDMA_BMON_1_BASE 0x1000007FFEEA8000ull +#define KDMA_BMON_1_MAX_OFFSET 0x1000 +#define KDMA_BMON_1_SECTION 0x1000 + +#define mmKDMA_BMON_2_BASE 0x1000007FFEEA9000ull +#define KDMA_BMON_2_MAX_OFFSET 0x1000 +#define KDMA_BMON_2_SECTION 0x1000 + +#define mmKDMA_BMON_3_BASE 0x1000007FFEEAA000ull +#define KDMA_BMON_3_MAX_OFFSET 0x1000 +#define KDMA_BMON_3_SECTION 0x56000 + +#define mmPCIE_VDEC0_CS_DBG_ROM_TBL_BASE 0x1000007FFEF00000ull +#define PCIE_VDEC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_CS_DBG_ROM_TBL_SECTION 0x1000 + +#define mmPCIE_VDEC0_CS_STM_BASE 0x1000007FFEF01000ull +#define PCIE_VDEC0_CS_STM_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_CS_STM_SECTION 0x1000 + +#define mmPCIE_VDEC0_CS_CTI_BASE 0x1000007FFEF02000ull +#define PCIE_VDEC0_CS_CTI_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_CS_CTI_SECTION 0x1000 + +#define mmPCIE_VDEC0_CS_ETF_BASE 0x1000007FFEF03000ull +#define PCIE_VDEC0_CS_ETF_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_CS_ETF_SECTION 0x1000 + +#define mmPCIE_VDEC0_CS_SPMU_BASE 0x1000007FFEF04000ull +#define PCIE_VDEC0_CS_SPMU_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_CS_SPMU_SECTION 0x1000 + +#define mmPCIE_VDEC0_BMON_CTI_BASE 0x1000007FFEF05000ull +#define PCIE_VDEC0_BMON_CTI_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_BMON_CTI_SECTION 0x1000 + +#define mmPCIE_VDEC0_USER_CTI_BASE 0x1000007FFEF06000ull +#define PCIE_VDEC0_USER_CTI_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_USER_CTI_SECTION 0x1000 + +#define mmPCIE_VDEC0_BMON_0_BASE 0x1000007FFEF07000ull +#define PCIE_VDEC0_BMON_0_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_BMON_0_SECTION 0x1000 + +#define mmPCIE_VDEC0_BMON_1_BASE 0x1000007FFEF08000ull +#define PCIE_VDEC0_BMON_1_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_BMON_1_SECTION 0x1000 + +#define mmPCIE_VDEC0_BMON_2_BASE 0x1000007FFEF09000ull +#define PCIE_VDEC0_BMON_2_MAX_OFFSET 0x1000 +#define PCIE_VDEC0_BMON_2_SECTION 0x7000 + +#define mmPCIE_VDEC1_CS_DBG_ROM_TBL_BASE 0x1000007FFEF10000ull +#define PCIE_VDEC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_CS_DBG_ROM_TBL_SECTION 0x1000 + +#define mmPCIE_VDEC1_CS_STM_BASE 0x1000007FFEF11000ull +#define PCIE_VDEC1_CS_STM_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_CS_STM_SECTION 0x1000 + +#define mmPCIE_VDEC1_CS_CTI_BASE 0x1000007FFEF12000ull +#define PCIE_VDEC1_CS_CTI_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_CS_CTI_SECTION 0x1000 + +#define mmPCIE_VDEC1_CS_ETF_BASE 0x1000007FFEF13000ull +#define PCIE_VDEC1_CS_ETF_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_CS_ETF_SECTION 0x1000 + +#define mmPCIE_VDEC1_CS_SPMU_BASE 0x1000007FFEF14000ull +#define PCIE_VDEC1_CS_SPMU_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_CS_SPMU_SECTION 0x1000 + +#define mmPCIE_VDEC1_BMON_CTI_BASE 0x1000007FFEF15000ull +#define PCIE_VDEC1_BMON_CTI_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_BMON_CTI_SECTION 0x1000 + +#define mmPCIE_VDEC1_USER_CTI_BASE 0x1000007FFEF16000ull +#define PCIE_VDEC1_USER_CTI_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_USER_CTI_SECTION 0x1000 + +#define mmPCIE_VDEC1_BMON_0_BASE 0x1000007FFEF17000ull +#define PCIE_VDEC1_BMON_0_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_BMON_0_SECTION 0x1000 + +#define mmPCIE_VDEC1_BMON_1_BASE 0x1000007FFEF18000ull +#define PCIE_VDEC1_BMON_1_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_BMON_1_SECTION 0x1000 + +#define mmPCIE_VDEC1_BMON_2_BASE 0x1000007FFEF19000ull +#define PCIE_VDEC1_BMON_2_MAX_OFFSET 0x1000 +#define PCIE_VDEC1_BMON_2_SECTION 0xF7000 + +#define mmHBM0_MC0_CS_DBG_ROM_TBL_BASE 0x1000007FFF010000ull +#define HBM0_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM0_MC0_CS_DBG_ROM_TBL_SECTION 0x1000 + +#define mmHBM0_MC0_CS_STM_BASE 0x1000007FFF011000ull +#define HBM0_MC0_CS_STM_MAX_OFFSET 0x1000 +#define HBM0_MC0_CS_STM_SECTION 0x1000 + +#define mmHBM0_MC0_CS_CTI_BASE 0x1000007FFF012000ull +#define HBM0_MC0_CS_CTI_MAX_OFFSET 0x1000 +#define HBM0_MC0_CS_CTI_SECTION 0x1000 + +#define mmHBM0_MC0_CS_ETF_BASE 0x1000007FFF013000ull +#define HBM0_MC0_CS_ETF_MAX_OFFSET 0x1000 +#define HBM0_MC0_CS_ETF_SECTION 0x1000 + +#define mmHBM0_MC0_CS_SPMU_BASE 0x1000007FFF014000ull +#define HBM0_MC0_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM0_MC0_CS_SPMU_SECTION 0x1000 + +#define mmHBM0_MC0_BMON_CTI_BASE 0x1000007FFF015000ull +#define HBM0_MC0_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM0_MC0_BMON_CTI_SECTION 0x1000 + +#define mmHBM0_MC0_USER_CTI_BASE 0x1000007FFF016000ull +#define HBM0_MC0_USER_CTI_MAX_OFFSET 0x1000 +#define HBM0_MC0_USER_CTI_SECTION 0xA000 + +#define mmHBM0_MC0_FUNNEL_BASE 0x1000007FFF020000ull +#define HBM0_MC0_FUNNEL_MAX_OFFSET 0x1000 +#define HBM0_MC0_FUNNEL_SECTION 0x30000 + +#define mmHBM0_MC1_CS_DBG_ROM_TBL_BASE 0x1000007FFF050000ull +#define HBM0_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM0_MC1_CS_DBG_ROM_TBL_SECTION 0x1000 + +#define mmHBM0_MC1_CS_STM_BASE 0x1000007FFF051000ull +#define HBM0_MC1_CS_STM_MAX_OFFSET 0x1000 +#define HBM0_MC1_CS_STM_SECTION 0x1000 + +#define mmHBM0_MC1_CS_CTI_BASE 0x1000007FFF052000ull +#define HBM0_MC1_CS_CTI_MAX_OFFSET 0x1000 +#define HBM0_MC1_CS_CTI_SECTION 0x1000 + +#define mmHBM0_MC1_CS_ETF_BASE 0x1000007FFF053000ull +#define HBM0_MC1_CS_ETF_MAX_OFFSET 0x1000 +#define HBM0_MC1_CS_ETF_SECTION 0x1000 + +#define mmHBM0_MC1_CS_SPMU_BASE 0x1000007FFF054000ull +#define HBM0_MC1_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM0_MC1_CS_SPMU_SECTION 0x1000 + +#define mmHBM0_MC1_BMON_CTI_BASE 0x1000007FFF055000ull +#define HBM0_MC1_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM0_MC1_BMON_CTI_SECTION 0x1000 + +#define mmHBM0_MC1_USER_CTI_BASE 0x1000007FFF056000ull +#define HBM0_MC1_USER_CTI_MAX_OFFSET 0x1000 +#define HBM0_MC1_USER_CTI_SECTION 0xA000 + +#define mmHBM0_MC1_FUNNEL_BASE 0x1000007FFF060000ull +#define HBM0_MC1_FUNNEL_MAX_OFFSET 0x1000 +#define HBM0_MC1_FUNNEL_SECTION 0x30000 + +#define mmHBM1_MC0_CS_DBG_ROM_TBL_BASE 0x1000007FFF090000ull +#define HBM1_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM1_MC0_CS_DBG_ROM_TBL_SECTION 0x1000 + +#define mmHBM1_MC0_CS_STM_BASE 0x1000007FFF091000ull +#define HBM1_MC0_CS_STM_MAX_OFFSET 0x1000 +#define HBM1_MC0_CS_STM_SECTION 0x1000 + +#define mmHBM1_MC0_CS_CTI_BASE 0x1000007FFF092000ull +#define HBM1_MC0_CS_CTI_MAX_OFFSET 0x1000 +#define HBM1_MC0_CS_CTI_SECTION 0x1000 + +#define mmHBM1_MC0_CS_ETF_BASE 0x1000007FFF093000ull +#define HBM1_MC0_CS_ETF_MAX_OFFSET 0x1000 +#define HBM1_MC0_CS_ETF_SECTION 0x1000 + +#define mmHBM1_MC0_CS_SPMU_BASE 0x1000007FFF094000ull +#define HBM1_MC0_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM1_MC0_CS_SPMU_SECTION 0x1000 + +#define mmHBM1_MC0_BMON_CTI_BASE 0x1000007FFF095000ull +#define HBM1_MC0_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM1_MC0_BMON_CTI_SECTION 0x1000 + +#define mmHBM1_MC0_USER_CTI_BASE 0x1000007FFF096000ull +#define HBM1_MC0_USER_CTI_MAX_OFFSET 0x1000 +#define HBM1_MC0_USER_CTI_SECTION 0xA000 + +#define mmHBM1_MC0_FUNNEL_BASE 0x1000007FFF0A0000ull +#define HBM1_MC0_FUNNEL_MAX_OFFSET 0x1000 +#define HBM1_MC0_FUNNEL_SECTION 0x30000 + +#define mmHBM1_MC1_CS_DBG_ROM_TBL_BASE 0x1000007FFF0D0000ull +#define HBM1_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM1_MC1_CS_DBG_ROM_TBL_SECTION 0x1000 + +#define mmHBM1_MC1_CS_STM_BASE 0x1000007FFF0D1000ull +#define HBM1_MC1_CS_STM_MAX_OFFSET 0x1000 +#define HBM1_MC1_CS_STM_SECTION 0x1000 + +#define mmHBM1_MC1_CS_CTI_BASE 0x1000007FFF0D2000ull +#define HBM1_MC1_CS_CTI_MAX_OFFSET 0x1000 +#define HBM1_MC1_CS_CTI_SECTION 0x1000 + +#define mmHBM1_MC1_CS_ETF_BASE 0x1000007FFF0D3000ull +#define HBM1_MC1_CS_ETF_MAX_OFFSET 0x1000 +#define HBM1_MC1_CS_ETF_SECTION 0x1000 + +#define mmHBM1_MC1_CS_SPMU_BASE 0x1000007FFF0D4000ull +#define HBM1_MC1_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM1_MC1_CS_SPMU_SECTION 0x1000 + +#define mmHBM1_MC1_BMON_CTI_BASE 0x1000007FFF0D5000ull +#define HBM1_MC1_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM1_MC1_BMON_CTI_SECTION 0x1000 + +#define mmHBM1_MC1_USER_CTI_BASE 0x1000007FFF0D6000ull +#define HBM1_MC1_USER_CTI_MAX_OFFSET 0x1000 +#define HBM1_MC1_USER_CTI_SECTION 0xA000 + +#define mmHBM1_MC1_FUNNEL_BASE 0x1000007FFF0E0000ull +#define HBM1_MC1_FUNNEL_MAX_OFFSET 0x1000 +#define HBM1_MC1_FUNNEL_SECTION 0x30000 + +#define mmHBM2_MC0_CS_DBG_ROM_TBL_BASE 0x1000007FFF110000ull +#define HBM2_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM2_MC0_CS_DBG_ROM_TBL_SECTION 0x1000 + +#define mmHBM2_MC0_CS_STM_BASE 0x1000007FFF111000ull +#define HBM2_MC0_CS_STM_MAX_OFFSET 0x1000 +#define HBM2_MC0_CS_STM_SECTION 0x1000 + +#define mmHBM2_MC0_CS_CTI_BASE 0x1000007FFF112000ull +#define HBM2_MC0_CS_CTI_MAX_OFFSET 0x1000 +#define HBM2_MC0_CS_CTI_SECTION 0x1000 + +#define mmHBM2_MC0_CS_ETF_BASE 0x1000007FFF113000ull +#define HBM2_MC0_CS_ETF_MAX_OFFSET 0x1000 +#define HBM2_MC0_CS_ETF_SECTION 0x1000 + +#define mmHBM2_MC0_CS_SPMU_BASE 0x1000007FFF114000ull +#define HBM2_MC0_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM2_MC0_CS_SPMU_SECTION 0x1000 + +#define mmHBM2_MC0_BMON_CTI_BASE 0x1000007FFF115000ull +#define HBM2_MC0_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM2_MC0_BMON_CTI_SECTION 0x1000 + +#define mmHBM2_MC0_USER_CTI_BASE 0x1000007FFF116000ull +#define HBM2_MC0_USER_CTI_MAX_OFFSET 0x1000 +#define HBM2_MC0_USER_CTI_SECTION 0xA000 + +#define mmHBM2_MC0_FUNNEL_BASE 0x1000007FFF120000ull +#define HBM2_MC0_FUNNEL_MAX_OFFSET 0x1000 +#define HBM2_MC0_FUNNEL_SECTION 0x30000 + +#define mmHBM2_MC1_CS_DBG_ROM_TBL_BASE 0x1000007FFF150000ull +#define HBM2_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM2_MC1_CS_DBG_ROM_TBL_SECTION 0x1000 + +#define mmHBM2_MC1_CS_STM_BASE 0x1000007FFF151000ull +#define HBM2_MC1_CS_STM_MAX_OFFSET 0x1000 +#define HBM2_MC1_CS_STM_SECTION 0x1000 + +#define mmHBM2_MC1_CS_CTI_BASE 0x1000007FFF152000ull +#define HBM2_MC1_CS_CTI_MAX_OFFSET 0x1000 +#define HBM2_MC1_CS_CTI_SECTION 0x1000 + +#define mmHBM2_MC1_CS_ETF_BASE 0x1000007FFF153000ull +#define HBM2_MC1_CS_ETF_MAX_OFFSET 0x1000 +#define HBM2_MC1_CS_ETF_SECTION 0x1000 + +#define mmHBM2_MC1_CS_SPMU_BASE 0x1000007FFF154000ull +#define HBM2_MC1_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM2_MC1_CS_SPMU_SECTION 0x1000 + +#define mmHBM2_MC1_BMON_CTI_BASE 0x1000007FFF155000ull +#define HBM2_MC1_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM2_MC1_BMON_CTI_SECTION 0x1000 + +#define mmHBM2_MC1_USER_CTI_BASE 0x1000007FFF156000ull +#define HBM2_MC1_USER_CTI_MAX_OFFSET 0x1000 +#define HBM2_MC1_USER_CTI_SECTION 0xA000 + +#define mmHBM2_MC1_FUNNEL_BASE 0x1000007FFF160000ull +#define HBM2_MC1_FUNNEL_MAX_OFFSET 0x1000 +#define HBM2_MC1_FUNNEL_SECTION 0x30000 + +#define mmHBM3_MC0_CS_DBG_ROM_TBL_BASE 0x1000007FFF190000ull +#define HBM3_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM3_MC0_CS_DBG_ROM_TBL_SECTION 0x1000 + +#define mmHBM3_MC0_CS_STM_BASE 0x1000007FFF191000ull +#define HBM3_MC0_CS_STM_MAX_OFFSET 0x1000 +#define HBM3_MC0_CS_STM_SECTION 0x1000 + +#define mmHBM3_MC0_CS_CTI_BASE 0x1000007FFF192000ull +#define HBM3_MC0_CS_CTI_MAX_OFFSET 0x1000 +#define HBM3_MC0_CS_CTI_SECTION 0x1000 + +#define mmHBM3_MC0_CS_ETF_BASE 0x1000007FFF193000ull +#define HBM3_MC0_CS_ETF_MAX_OFFSET 0x1000 +#define HBM3_MC0_CS_ETF_SECTION 0x1000 + +#define mmHBM3_MC0_CS_SPMU_BASE 0x1000007FFF194000ull +#define HBM3_MC0_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM3_MC0_CS_SPMU_SECTION 0x1000 + +#define mmHBM3_MC0_BMON_CTI_BASE 0x1000007FFF195000ull +#define HBM3_MC0_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM3_MC0_BMON_CTI_SECTION 0x1000 + +#define mmHBM3_MC0_USER_CTI_BASE 0x1000007FFF196000ull +#define HBM3_MC0_USER_CTI_MAX_OFFSET 0x1000 +#define HBM3_MC0_USER_CTI_SECTION 0xA000 + +#define mmHBM3_MC0_FUNNEL_BASE 0x1000007FFF1A0000ull +#define HBM3_MC0_FUNNEL_MAX_OFFSET 0x1000 +#define HBM3_MC0_FUNNEL_SECTION 0x30000 + +#define mmHBM3_MC1_CS_DBG_ROM_TBL_BASE 0x1000007FFF1D0000ull +#define HBM3_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM3_MC1_CS_DBG_ROM_TBL_SECTION 0x1000 + +#define mmHBM3_MC1_CS_STM_BASE 0x1000007FFF1D1000ull +#define HBM3_MC1_CS_STM_MAX_OFFSET 0x1000 +#define HBM3_MC1_CS_STM_SECTION 0x1000 + +#define mmHBM3_MC1_CS_CTI_BASE 0x1000007FFF1D2000ull +#define HBM3_MC1_CS_CTI_MAX_OFFSET 0x1000 +#define HBM3_MC1_CS_CTI_SECTION 0x1000 + +#define mmHBM3_MC1_CS_ETF_BASE 0x1000007FFF1D3000ull +#define HBM3_MC1_CS_ETF_MAX_OFFSET 0x1000 +#define HBM3_MC1_CS_ETF_SECTION 0x1000 + +#define mmHBM3_MC1_CS_SPMU_BASE 0x1000007FFF1D4000ull +#define HBM3_MC1_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM3_MC1_CS_SPMU_SECTION 0x1000 + +#define mmHBM3_MC1_BMON_CTI_BASE 0x1000007FFF1D5000ull +#define HBM3_MC1_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM3_MC1_BMON_CTI_SECTION 0x1000 + +#define mmHBM3_MC1_USER_CTI_BASE 0x1000007FFF1D6000ull +#define HBM3_MC1_USER_CTI_MAX_OFFSET 0x1000 +#define HBM3_MC1_USER_CTI_SECTION 0xA000 + +#define mmHBM3_MC1_FUNNEL_BASE 0x1000007FFF1E0000ull +#define HBM3_MC1_FUNNEL_MAX_OFFSET 0x1000 +#define HBM3_MC1_FUNNEL_SECTION 0x30000 + +#define mmHBM4_MC0_CS_DBG_ROM_TBL_BASE 0x1000007FFF210000ull +#define HBM4_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM4_MC0_CS_DBG_ROM_TBL_SECTION 0x1000 + +#define mmHBM4_MC0_CS_STM_BASE 0x1000007FFF211000ull +#define HBM4_MC0_CS_STM_MAX_OFFSET 0x1000 +#define HBM4_MC0_CS_STM_SECTION 0x1000 + +#define mmHBM4_MC0_CS_CTI_BASE 0x1000007FFF212000ull +#define HBM4_MC0_CS_CTI_MAX_OFFSET 0x1000 +#define HBM4_MC0_CS_CTI_SECTION 0x1000 + +#define mmHBM4_MC0_CS_ETF_BASE 0x1000007FFF213000ull +#define HBM4_MC0_CS_ETF_MAX_OFFSET 0x1000 +#define HBM4_MC0_CS_ETF_SECTION 0x1000 + +#define mmHBM4_MC0_CS_SPMU_BASE 0x1000007FFF214000ull +#define HBM4_MC0_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM4_MC0_CS_SPMU_SECTION 0x1000 + +#define mmHBM4_MC0_BMON_CTI_BASE 0x1000007FFF215000ull +#define HBM4_MC0_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM4_MC0_BMON_CTI_SECTION 0x1000 + +#define mmHBM4_MC0_USER_CTI_BASE 0x1000007FFF216000ull +#define HBM4_MC0_USER_CTI_MAX_OFFSET 0x1000 +#define HBM4_MC0_USER_CTI_SECTION 0xA000 + +#define mmHBM4_MC0_FUNNEL_BASE 0x1000007FFF220000ull +#define HBM4_MC0_FUNNEL_MAX_OFFSET 0x1000 +#define HBM4_MC0_FUNNEL_SECTION 0x30000 + +#define mmHBM4_MC1_CS_DBG_ROM_TBL_BASE 0x1000007FFF250000ull +#define HBM4_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM4_MC1_CS_DBG_ROM_TBL_SECTION 0x1000 + +#define mmHBM4_MC1_CS_STM_BASE 0x1000007FFF251000ull +#define HBM4_MC1_CS_STM_MAX_OFFSET 0x1000 +#define HBM4_MC1_CS_STM_SECTION 0x1000 + +#define mmHBM4_MC1_CS_CTI_BASE 0x1000007FFF252000ull +#define HBM4_MC1_CS_CTI_MAX_OFFSET 0x1000 +#define HBM4_MC1_CS_CTI_SECTION 0x1000 + +#define mmHBM4_MC1_CS_ETF_BASE 0x1000007FFF253000ull +#define HBM4_MC1_CS_ETF_MAX_OFFSET 0x1000 +#define HBM4_MC1_CS_ETF_SECTION 0x1000 + +#define mmHBM4_MC1_CS_SPMU_BASE 0x1000007FFF254000ull +#define HBM4_MC1_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM4_MC1_CS_SPMU_SECTION 0x1000 + +#define mmHBM4_MC1_BMON_CTI_BASE 0x1000007FFF255000ull +#define HBM4_MC1_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM4_MC1_BMON_CTI_SECTION 0x1000 + +#define mmHBM4_MC1_USER_CTI_BASE 0x1000007FFF256000ull +#define HBM4_MC1_USER_CTI_MAX_OFFSET 0x1000 +#define HBM4_MC1_USER_CTI_SECTION 0xA000 + +#define mmHBM4_MC1_FUNNEL_BASE 0x1000007FFF260000ull +#define HBM4_MC1_FUNNEL_MAX_OFFSET 0x1000 +#define HBM4_MC1_FUNNEL_SECTION 0x30000 + +#define mmHBM5_MC0_CS_DBG_ROM_TBL_BASE 0x1000007FFF290000ull +#define HBM5_MC0_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM5_MC0_CS_DBG_ROM_TBL_SECTION 0x1000 + +#define mmHBM5_MC0_CS_STM_BASE 0x1000007FFF291000ull +#define HBM5_MC0_CS_STM_MAX_OFFSET 0x1000 +#define HBM5_MC0_CS_STM_SECTION 0x1000 + +#define mmHBM5_MC0_CS_CTI_BASE 0x1000007FFF292000ull +#define HBM5_MC0_CS_CTI_MAX_OFFSET 0x1000 +#define HBM5_MC0_CS_CTI_SECTION 0x1000 + +#define mmHBM5_MC0_CS_ETF_BASE 0x1000007FFF293000ull +#define HBM5_MC0_CS_ETF_MAX_OFFSET 0x1000 +#define HBM5_MC0_CS_ETF_SECTION 0x1000 + +#define mmHBM5_MC0_CS_SPMU_BASE 0x1000007FFF294000ull +#define HBM5_MC0_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM5_MC0_CS_SPMU_SECTION 0x1000 + +#define mmHBM5_MC0_BMON_CTI_BASE 0x1000007FFF295000ull +#define HBM5_MC0_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM5_MC0_BMON_CTI_SECTION 0x1000 + +#define mmHBM5_MC0_USER_CTI_BASE 0x1000007FFF296000ull +#define HBM5_MC0_USER_CTI_MAX_OFFSET 0x1000 +#define HBM5_MC0_USER_CTI_SECTION 0xA000 + +#define mmHBM5_MC0_FUNNEL_BASE 0x1000007FFF2A0000ull +#define HBM5_MC0_FUNNEL_MAX_OFFSET 0x1000 +#define HBM5_MC0_FUNNEL_SECTION 0x30000 + +#define mmHBM5_MC1_CS_DBG_ROM_TBL_BASE 0x1000007FFF2D0000ull +#define HBM5_MC1_CS_DBG_ROM_TBL_MAX_OFFSET 0x1000 +#define HBM5_MC1_CS_DBG_ROM_TBL_SECTION 0x1000 + +#define mmHBM5_MC1_CS_STM_BASE 0x1000007FFF2D1000ull +#define HBM5_MC1_CS_STM_MAX_OFFSET 0x1000 +#define HBM5_MC1_CS_STM_SECTION 0x1000 + +#define mmHBM5_MC1_CS_CTI_BASE 0x1000007FFF2D2000ull +#define HBM5_MC1_CS_CTI_MAX_OFFSET 0x1000 +#define HBM5_MC1_CS_CTI_SECTION 0x1000 + +#define mmHBM5_MC1_CS_ETF_BASE 0x1000007FFF2D3000ull +#define HBM5_MC1_CS_ETF_MAX_OFFSET 0x1000 +#define HBM5_MC1_CS_ETF_SECTION 0x1000 + +#define mmHBM5_MC1_CS_SPMU_BASE 0x1000007FFF2D4000ull +#define HBM5_MC1_CS_SPMU_MAX_OFFSET 0x1000 +#define HBM5_MC1_CS_SPMU_SECTION 0x1000 + +#define mmHBM5_MC1_BMON_CTI_BASE 0x1000007FFF2D5000ull +#define HBM5_MC1_BMON_CTI_MAX_OFFSET 0x1000 +#define HBM5_MC1_BMON_CTI_SECTION 0x1000 + +#define mmHBM5_MC1_USER_CTI_BASE 0x1000007FFF2D6000ull +#define HBM5_MC1_USER_CTI_MAX_OFFSET 0x1000 +#define HBM5_MC1_USER_CTI_SECTION 0xA000 + +#define mmHBM5_MC1_FUNNEL_BASE 0x1000007FFF2E0000ull +#define HBM5_MC1_FUNNEL_MAX_OFFSET 0x1000 +#define HBM5_MC1_FUNNEL_SECTION 0x20000 + +#define mmNIC0_DBG_CS_DBG_ROM_TABLE_0_BASE 0x1000007FFF300000ull +#define NIC0_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 + +#define mmNIC0_DBG_STM_0_BASE 0x1000007FFF301000ull +#define NIC0_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_STM_0_SECTION 0x1000 + +#define mmNIC0_DBG_CTI_0_BASE 0x1000007FFF302000ull +#define NIC0_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_CTI_0_SECTION 0x1000 + +#define mmNIC0_DBG_ETF_0_BASE 0x1000007FFF303000ull +#define NIC0_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_ETF_0_SECTION 0x1000 + +#define mmNIC0_DBG_SPMU_0_BASE 0x1000007FFF304000ull +#define NIC0_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_SPMU_0_SECTION 0x1000 + +#define mmNIC0_DBG_USER_CTI_0_BASE 0x1000007FFF305000ull +#define NIC0_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_USER_CTI_0_SECTION 0x1000 + +#define mmNIC0_DBG_BMON_CTI_0_BASE 0x1000007FFF306000ull +#define NIC0_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_BMON_CTI_0_SECTION 0x1000 + +#define mmNIC0_DBG_BMON0_0_BASE 0x1000007FFF307000ull +#define NIC0_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_BMON0_0_SECTION 0x1000 + +#define mmNIC0_DBG_BMON1_0_BASE 0x1000007FFF308000ull +#define NIC0_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_BMON1_0_SECTION 0x1000 + +#define mmNIC0_DBG_BMON2_0_BASE 0x1000007FFF309000ull +#define NIC0_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC0_DBG_BMON2_0_SECTION 0x7000 + +#define mmNIC0_DBG_ARC_RTT0_BASE 0x1000007FFF310000ull +#define NIC0_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC0_DBG_ARC_RTT0_SECTION 0x10000 + +#define mmNIC0_DBG_CS_DBG_ROM_TABLE_1_BASE 0x1000007FFF320000ull +#define NIC0_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 + +#define mmNIC0_DBG_STM_1_BASE 0x1000007FFF321000ull +#define NIC0_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_STM_1_SECTION 0x1000 + +#define mmNIC0_DBG_CTI_1_BASE 0x1000007FFF322000ull +#define NIC0_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_CTI_1_SECTION 0x1000 + +#define mmNIC0_DBG_ETF_1_BASE 0x1000007FFF323000ull +#define NIC0_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_ETF_1_SECTION 0x1000 + +#define mmNIC0_DBG_SPMU_1_BASE 0x1000007FFF324000ull +#define NIC0_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_SPMU_1_SECTION 0x1000 + +#define mmNIC0_DBG_USER_CTI_1_BASE 0x1000007FFF325000ull +#define NIC0_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_USER_CTI_1_SECTION 0x1000 + +#define mmNIC0_DBG_BMON_CTI_1_BASE 0x1000007FFF326000ull +#define NIC0_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_BMON_CTI_1_SECTION 0x1000 + +#define mmNIC0_DBG_BMON0_1_BASE 0x1000007FFF327000ull +#define NIC0_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_BMON0_1_SECTION 0x1000 + +#define mmNIC0_DBG_BMON1_1_BASE 0x1000007FFF328000ull +#define NIC0_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_BMON1_1_SECTION 0x1000 + +#define mmNIC0_DBG_BMON2_1_BASE 0x1000007FFF329000ull +#define NIC0_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC0_DBG_BMON2_1_SECTION 0x7000 + +#define mmNIC0_DBG_ARC_RTT1_BASE 0x1000007FFF330000ull +#define NIC0_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC0_DBG_ARC_RTT1_SECTION 0x8000 + +#define mmNIC0_DBG_FUNNEL_TX_BASE 0x1000007FFF338000ull +#define NIC0_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC0_DBG_FUNNEL_TX_SECTION 0x1000 + +#define mmNIC0_DBG_FUNNEL_NCH_BASE 0x1000007FFF339000ull +#define NIC0_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC0_DBG_FUNNEL_NCH_SECTION 0x7000 + +#define mmNIC1_DBG_CS_DBG_ROM_TABLE_0_BASE 0x1000007FFF340000ull +#define NIC1_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 + +#define mmNIC1_DBG_STM_0_BASE 0x1000007FFF341000ull +#define NIC1_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_STM_0_SECTION 0x1000 + +#define mmNIC1_DBG_CTI_0_BASE 0x1000007FFF342000ull +#define NIC1_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_CTI_0_SECTION 0x1000 + +#define mmNIC1_DBG_ETF_0_BASE 0x1000007FFF343000ull +#define NIC1_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_ETF_0_SECTION 0x1000 + +#define mmNIC1_DBG_SPMU_0_BASE 0x1000007FFF344000ull +#define NIC1_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_SPMU_0_SECTION 0x1000 + +#define mmNIC1_DBG_USER_CTI_0_BASE 0x1000007FFF345000ull +#define NIC1_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_USER_CTI_0_SECTION 0x1000 + +#define mmNIC1_DBG_BMON_CTI_0_BASE 0x1000007FFF346000ull +#define NIC1_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_BMON_CTI_0_SECTION 0x1000 + +#define mmNIC1_DBG_BMON0_0_BASE 0x1000007FFF347000ull +#define NIC1_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_BMON0_0_SECTION 0x1000 + +#define mmNIC1_DBG_BMON1_0_BASE 0x1000007FFF348000ull +#define NIC1_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_BMON1_0_SECTION 0x1000 + +#define mmNIC1_DBG_BMON2_0_BASE 0x1000007FFF349000ull +#define NIC1_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC1_DBG_BMON2_0_SECTION 0x7000 + +#define mmNIC1_DBG_ARC_RTT0_BASE 0x1000007FFF350000ull +#define NIC1_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC1_DBG_ARC_RTT0_SECTION 0x10000 + +#define mmNIC1_DBG_CS_DBG_ROM_TABLE_1_BASE 0x1000007FFF360000ull +#define NIC1_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 + +#define mmNIC1_DBG_STM_1_BASE 0x1000007FFF361000ull +#define NIC1_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_STM_1_SECTION 0x1000 + +#define mmNIC1_DBG_CTI_1_BASE 0x1000007FFF362000ull +#define NIC1_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_CTI_1_SECTION 0x1000 + +#define mmNIC1_DBG_ETF_1_BASE 0x1000007FFF363000ull +#define NIC1_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_ETF_1_SECTION 0x1000 + +#define mmNIC1_DBG_SPMU_1_BASE 0x1000007FFF364000ull +#define NIC1_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_SPMU_1_SECTION 0x1000 + +#define mmNIC1_DBG_USER_CTI_1_BASE 0x1000007FFF365000ull +#define NIC1_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_USER_CTI_1_SECTION 0x1000 + +#define mmNIC1_DBG_BMON_CTI_1_BASE 0x1000007FFF366000ull +#define NIC1_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_BMON_CTI_1_SECTION 0x1000 + +#define mmNIC1_DBG_BMON0_1_BASE 0x1000007FFF367000ull +#define NIC1_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_BMON0_1_SECTION 0x1000 + +#define mmNIC1_DBG_BMON1_1_BASE 0x1000007FFF368000ull +#define NIC1_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_BMON1_1_SECTION 0x1000 + +#define mmNIC1_DBG_BMON2_1_BASE 0x1000007FFF369000ull +#define NIC1_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC1_DBG_BMON2_1_SECTION 0x7000 + +#define mmNIC1_DBG_ARC_RTT1_BASE 0x1000007FFF370000ull +#define NIC1_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC1_DBG_ARC_RTT1_SECTION 0x8000 + +#define mmNIC1_DBG_FUNNEL_TX_BASE 0x1000007FFF378000ull +#define NIC1_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC1_DBG_FUNNEL_TX_SECTION 0x1000 + +#define mmNIC1_DBG_FUNNEL_NCH_BASE 0x1000007FFF379000ull +#define NIC1_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC1_DBG_FUNNEL_NCH_SECTION 0x7000 + +#define mmNIC2_DBG_CS_DBG_ROM_TABLE_0_BASE 0x1000007FFF380000ull +#define NIC2_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 + +#define mmNIC2_DBG_STM_0_BASE 0x1000007FFF381000ull +#define NIC2_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_STM_0_SECTION 0x1000 + +#define mmNIC2_DBG_CTI_0_BASE 0x1000007FFF382000ull +#define NIC2_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_CTI_0_SECTION 0x1000 + +#define mmNIC2_DBG_ETF_0_BASE 0x1000007FFF383000ull +#define NIC2_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_ETF_0_SECTION 0x1000 + +#define mmNIC2_DBG_SPMU_0_BASE 0x1000007FFF384000ull +#define NIC2_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_SPMU_0_SECTION 0x1000 + +#define mmNIC2_DBG_USER_CTI_0_BASE 0x1000007FFF385000ull +#define NIC2_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_USER_CTI_0_SECTION 0x1000 + +#define mmNIC2_DBG_BMON_CTI_0_BASE 0x1000007FFF386000ull +#define NIC2_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_BMON_CTI_0_SECTION 0x1000 + +#define mmNIC2_DBG_BMON0_0_BASE 0x1000007FFF387000ull +#define NIC2_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_BMON0_0_SECTION 0x1000 + +#define mmNIC2_DBG_BMON1_0_BASE 0x1000007FFF388000ull +#define NIC2_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_BMON1_0_SECTION 0x1000 + +#define mmNIC2_DBG_BMON2_0_BASE 0x1000007FFF389000ull +#define NIC2_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC2_DBG_BMON2_0_SECTION 0x7000 + +#define mmNIC2_DBG_ARC_RTT0_BASE 0x1000007FFF390000ull +#define NIC2_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC2_DBG_ARC_RTT0_SECTION 0x10000 + +#define mmNIC2_DBG_CS_DBG_ROM_TABLE_1_BASE 0x1000007FFF3A0000ull +#define NIC2_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 + +#define mmNIC2_DBG_STM_1_BASE 0x1000007FFF3A1000ull +#define NIC2_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_STM_1_SECTION 0x1000 + +#define mmNIC2_DBG_CTI_1_BASE 0x1000007FFF3A2000ull +#define NIC2_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_CTI_1_SECTION 0x1000 + +#define mmNIC2_DBG_ETF_1_BASE 0x1000007FFF3A3000ull +#define NIC2_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_ETF_1_SECTION 0x1000 + +#define mmNIC2_DBG_SPMU_1_BASE 0x1000007FFF3A4000ull +#define NIC2_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_SPMU_1_SECTION 0x1000 + +#define mmNIC2_DBG_USER_CTI_1_BASE 0x1000007FFF3A5000ull +#define NIC2_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_USER_CTI_1_SECTION 0x1000 + +#define mmNIC2_DBG_BMON_CTI_1_BASE 0x1000007FFF3A6000ull +#define NIC2_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_BMON_CTI_1_SECTION 0x1000 + +#define mmNIC2_DBG_BMON0_1_BASE 0x1000007FFF3A7000ull +#define NIC2_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_BMON0_1_SECTION 0x1000 + +#define mmNIC2_DBG_BMON1_1_BASE 0x1000007FFF3A8000ull +#define NIC2_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_BMON1_1_SECTION 0x1000 + +#define mmNIC2_DBG_BMON2_1_BASE 0x1000007FFF3A9000ull +#define NIC2_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC2_DBG_BMON2_1_SECTION 0x7000 + +#define mmNIC2_DBG_ARC_RTT1_BASE 0x1000007FFF3B0000ull +#define NIC2_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC2_DBG_ARC_RTT1_SECTION 0x8000 + +#define mmNIC2_DBG_FUNNEL_TX_BASE 0x1000007FFF3B8000ull +#define NIC2_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC2_DBG_FUNNEL_TX_SECTION 0x1000 + +#define mmNIC2_DBG_FUNNEL_NCH_BASE 0x1000007FFF3B9000ull +#define NIC2_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC2_DBG_FUNNEL_NCH_SECTION 0x7000 + +#define mmNIC3_DBG_CS_DBG_ROM_TABLE_0_BASE 0x1000007FFF3C0000ull +#define NIC3_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 + +#define mmNIC3_DBG_STM_0_BASE 0x1000007FFF3C1000ull +#define NIC3_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_STM_0_SECTION 0x1000 + +#define mmNIC3_DBG_CTI_0_BASE 0x1000007FFF3C2000ull +#define NIC3_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_CTI_0_SECTION 0x1000 + +#define mmNIC3_DBG_ETF_0_BASE 0x1000007FFF3C3000ull +#define NIC3_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_ETF_0_SECTION 0x1000 + +#define mmNIC3_DBG_SPMU_0_BASE 0x1000007FFF3C4000ull +#define NIC3_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_SPMU_0_SECTION 0x1000 + +#define mmNIC3_DBG_USER_CTI_0_BASE 0x1000007FFF3C5000ull +#define NIC3_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_USER_CTI_0_SECTION 0x1000 + +#define mmNIC3_DBG_BMON_CTI_0_BASE 0x1000007FFF3C6000ull +#define NIC3_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_BMON_CTI_0_SECTION 0x1000 + +#define mmNIC3_DBG_BMON0_0_BASE 0x1000007FFF3C7000ull +#define NIC3_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_BMON0_0_SECTION 0x1000 + +#define mmNIC3_DBG_BMON1_0_BASE 0x1000007FFF3C8000ull +#define NIC3_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_BMON1_0_SECTION 0x1000 + +#define mmNIC3_DBG_BMON2_0_BASE 0x1000007FFF3C9000ull +#define NIC3_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC3_DBG_BMON2_0_SECTION 0x7000 + +#define mmNIC3_DBG_ARC_RTT0_BASE 0x1000007FFF3D0000ull +#define NIC3_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC3_DBG_ARC_RTT0_SECTION 0x10000 + +#define mmNIC3_DBG_CS_DBG_ROM_TABLE_1_BASE 0x1000007FFF3E0000ull +#define NIC3_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 + +#define mmNIC3_DBG_STM_1_BASE 0x1000007FFF3E1000ull +#define NIC3_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_STM_1_SECTION 0x1000 + +#define mmNIC3_DBG_CTI_1_BASE 0x1000007FFF3E2000ull +#define NIC3_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_CTI_1_SECTION 0x1000 + +#define mmNIC3_DBG_ETF_1_BASE 0x1000007FFF3E3000ull +#define NIC3_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_ETF_1_SECTION 0x1000 + +#define mmNIC3_DBG_SPMU_1_BASE 0x1000007FFF3E4000ull +#define NIC3_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_SPMU_1_SECTION 0x1000 + +#define mmNIC3_DBG_USER_CTI_1_BASE 0x1000007FFF3E5000ull +#define NIC3_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_USER_CTI_1_SECTION 0x1000 + +#define mmNIC3_DBG_BMON_CTI_1_BASE 0x1000007FFF3E6000ull +#define NIC3_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_BMON_CTI_1_SECTION 0x1000 + +#define mmNIC3_DBG_BMON0_1_BASE 0x1000007FFF3E7000ull +#define NIC3_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_BMON0_1_SECTION 0x1000 + +#define mmNIC3_DBG_BMON1_1_BASE 0x1000007FFF3E8000ull +#define NIC3_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_BMON1_1_SECTION 0x1000 + +#define mmNIC3_DBG_BMON2_1_BASE 0x1000007FFF3E9000ull +#define NIC3_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC3_DBG_BMON2_1_SECTION 0x7000 + +#define mmNIC3_DBG_ARC_RTT1_BASE 0x1000007FFF3F0000ull +#define NIC3_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC3_DBG_ARC_RTT1_SECTION 0x8000 + +#define mmNIC3_DBG_FUNNEL_TX_BASE 0x1000007FFF3F8000ull +#define NIC3_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC3_DBG_FUNNEL_TX_SECTION 0x1000 + +#define mmNIC3_DBG_FUNNEL_NCH_BASE 0x1000007FFF3F9000ull +#define NIC3_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC3_DBG_FUNNEL_NCH_SECTION 0x7000 + +#define mmNIC4_DBG_CS_DBG_ROM_TABLE_0_BASE 0x1000007FFF400000ull +#define NIC4_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 + +#define mmNIC4_DBG_STM_0_BASE 0x1000007FFF401000ull +#define NIC4_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_STM_0_SECTION 0x1000 + +#define mmNIC4_DBG_CTI_0_BASE 0x1000007FFF402000ull +#define NIC4_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_CTI_0_SECTION 0x1000 + +#define mmNIC4_DBG_ETF_0_BASE 0x1000007FFF403000ull +#define NIC4_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_ETF_0_SECTION 0x1000 + +#define mmNIC4_DBG_SPMU_0_BASE 0x1000007FFF404000ull +#define NIC4_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_SPMU_0_SECTION 0x1000 + +#define mmNIC4_DBG_USER_CTI_0_BASE 0x1000007FFF405000ull +#define NIC4_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_USER_CTI_0_SECTION 0x1000 + +#define mmNIC4_DBG_BMON_CTI_0_BASE 0x1000007FFF406000ull +#define NIC4_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_BMON_CTI_0_SECTION 0x1000 + +#define mmNIC4_DBG_BMON0_0_BASE 0x1000007FFF407000ull +#define NIC4_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_BMON0_0_SECTION 0x1000 + +#define mmNIC4_DBG_BMON1_0_BASE 0x1000007FFF408000ull +#define NIC4_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_BMON1_0_SECTION 0x1000 + +#define mmNIC4_DBG_BMON2_0_BASE 0x1000007FFF409000ull +#define NIC4_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC4_DBG_BMON2_0_SECTION 0x7000 + +#define mmNIC4_DBG_ARC_RTT0_BASE 0x1000007FFF410000ull +#define NIC4_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC4_DBG_ARC_RTT0_SECTION 0x10000 + +#define mmNIC4_DBG_CS_DBG_ROM_TABLE_1_BASE 0x1000007FFF420000ull +#define NIC4_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 + +#define mmNIC4_DBG_STM_1_BASE 0x1000007FFF421000ull +#define NIC4_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_STM_1_SECTION 0x1000 + +#define mmNIC4_DBG_CTI_1_BASE 0x1000007FFF422000ull +#define NIC4_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_CTI_1_SECTION 0x1000 + +#define mmNIC4_DBG_ETF_1_BASE 0x1000007FFF423000ull +#define NIC4_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_ETF_1_SECTION 0x1000 + +#define mmNIC4_DBG_SPMU_1_BASE 0x1000007FFF424000ull +#define NIC4_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_SPMU_1_SECTION 0x1000 + +#define mmNIC4_DBG_USER_CTI_1_BASE 0x1000007FFF425000ull +#define NIC4_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_USER_CTI_1_SECTION 0x1000 + +#define mmNIC4_DBG_BMON_CTI_1_BASE 0x1000007FFF426000ull +#define NIC4_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_BMON_CTI_1_SECTION 0x1000 + +#define mmNIC4_DBG_BMON0_1_BASE 0x1000007FFF427000ull +#define NIC4_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_BMON0_1_SECTION 0x1000 + +#define mmNIC4_DBG_BMON1_1_BASE 0x1000007FFF428000ull +#define NIC4_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_BMON1_1_SECTION 0x1000 + +#define mmNIC4_DBG_BMON2_1_BASE 0x1000007FFF429000ull +#define NIC4_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC4_DBG_BMON2_1_SECTION 0x7000 + +#define mmNIC4_DBG_ARC_RTT1_BASE 0x1000007FFF430000ull +#define NIC4_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC4_DBG_ARC_RTT1_SECTION 0x8000 + +#define mmNIC4_DBG_FUNNEL_TX_BASE 0x1000007FFF438000ull +#define NIC4_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC4_DBG_FUNNEL_TX_SECTION 0x1000 + +#define mmNIC4_DBG_FUNNEL_NCH_BASE 0x1000007FFF439000ull +#define NIC4_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC4_DBG_FUNNEL_NCH_SECTION 0x7000 + +#define mmNIC5_DBG_CS_DBG_ROM_TABLE_0_BASE 0x1000007FFF440000ull +#define NIC5_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 + +#define mmNIC5_DBG_STM_0_BASE 0x1000007FFF441000ull +#define NIC5_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_STM_0_SECTION 0x1000 + +#define mmNIC5_DBG_CTI_0_BASE 0x1000007FFF442000ull +#define NIC5_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_CTI_0_SECTION 0x1000 + +#define mmNIC5_DBG_ETF_0_BASE 0x1000007FFF443000ull +#define NIC5_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_ETF_0_SECTION 0x1000 + +#define mmNIC5_DBG_SPMU_0_BASE 0x1000007FFF444000ull +#define NIC5_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_SPMU_0_SECTION 0x1000 + +#define mmNIC5_DBG_USER_CTI_0_BASE 0x1000007FFF445000ull +#define NIC5_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_USER_CTI_0_SECTION 0x1000 + +#define mmNIC5_DBG_BMON_CTI_0_BASE 0x1000007FFF446000ull +#define NIC5_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_BMON_CTI_0_SECTION 0x1000 + +#define mmNIC5_DBG_BMON0_0_BASE 0x1000007FFF447000ull +#define NIC5_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_BMON0_0_SECTION 0x1000 + +#define mmNIC5_DBG_BMON1_0_BASE 0x1000007FFF448000ull +#define NIC5_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_BMON1_0_SECTION 0x1000 + +#define mmNIC5_DBG_BMON2_0_BASE 0x1000007FFF449000ull +#define NIC5_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC5_DBG_BMON2_0_SECTION 0x7000 + +#define mmNIC5_DBG_ARC_RTT0_BASE 0x1000007FFF450000ull +#define NIC5_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC5_DBG_ARC_RTT0_SECTION 0x10000 + +#define mmNIC5_DBG_CS_DBG_ROM_TABLE_1_BASE 0x1000007FFF460000ull +#define NIC5_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 + +#define mmNIC5_DBG_STM_1_BASE 0x1000007FFF461000ull +#define NIC5_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_STM_1_SECTION 0x1000 + +#define mmNIC5_DBG_CTI_1_BASE 0x1000007FFF462000ull +#define NIC5_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_CTI_1_SECTION 0x1000 + +#define mmNIC5_DBG_ETF_1_BASE 0x1000007FFF463000ull +#define NIC5_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_ETF_1_SECTION 0x1000 + +#define mmNIC5_DBG_SPMU_1_BASE 0x1000007FFF464000ull +#define NIC5_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_SPMU_1_SECTION 0x1000 + +#define mmNIC5_DBG_USER_CTI_1_BASE 0x1000007FFF465000ull +#define NIC5_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_USER_CTI_1_SECTION 0x1000 + +#define mmNIC5_DBG_BMON_CTI_1_BASE 0x1000007FFF466000ull +#define NIC5_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_BMON_CTI_1_SECTION 0x1000 + +#define mmNIC5_DBG_BMON0_1_BASE 0x1000007FFF467000ull +#define NIC5_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_BMON0_1_SECTION 0x1000 + +#define mmNIC5_DBG_BMON1_1_BASE 0x1000007FFF468000ull +#define NIC5_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_BMON1_1_SECTION 0x1000 + +#define mmNIC5_DBG_BMON2_1_BASE 0x1000007FFF469000ull +#define NIC5_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC5_DBG_BMON2_1_SECTION 0x7000 + +#define mmNIC5_DBG_ARC_RTT1_BASE 0x1000007FFF470000ull +#define NIC5_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC5_DBG_ARC_RTT1_SECTION 0x8000 + +#define mmNIC5_DBG_FUNNEL_TX_BASE 0x1000007FFF478000ull +#define NIC5_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC5_DBG_FUNNEL_TX_SECTION 0x1000 + +#define mmNIC5_DBG_FUNNEL_NCH_BASE 0x1000007FFF479000ull +#define NIC5_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC5_DBG_FUNNEL_NCH_SECTION 0x7000 + +#define mmNIC6_DBG_CS_DBG_ROM_TABLE_0_BASE 0x1000007FFF480000ull +#define NIC6_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 + +#define mmNIC6_DBG_STM_0_BASE 0x1000007FFF481000ull +#define NIC6_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_STM_0_SECTION 0x1000 + +#define mmNIC6_DBG_CTI_0_BASE 0x1000007FFF482000ull +#define NIC6_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_CTI_0_SECTION 0x1000 + +#define mmNIC6_DBG_ETF_0_BASE 0x1000007FFF483000ull +#define NIC6_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_ETF_0_SECTION 0x1000 + +#define mmNIC6_DBG_SPMU_0_BASE 0x1000007FFF484000ull +#define NIC6_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_SPMU_0_SECTION 0x1000 + +#define mmNIC6_DBG_USER_CTI_0_BASE 0x1000007FFF485000ull +#define NIC6_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_USER_CTI_0_SECTION 0x1000 + +#define mmNIC6_DBG_BMON_CTI_0_BASE 0x1000007FFF486000ull +#define NIC6_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_BMON_CTI_0_SECTION 0x1000 + +#define mmNIC6_DBG_BMON0_0_BASE 0x1000007FFF487000ull +#define NIC6_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_BMON0_0_SECTION 0x1000 + +#define mmNIC6_DBG_BMON1_0_BASE 0x1000007FFF488000ull +#define NIC6_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_BMON1_0_SECTION 0x1000 + +#define mmNIC6_DBG_BMON2_0_BASE 0x1000007FFF489000ull +#define NIC6_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC6_DBG_BMON2_0_SECTION 0x7000 + +#define mmNIC6_DBG_ARC_RTT0_BASE 0x1000007FFF490000ull +#define NIC6_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC6_DBG_ARC_RTT0_SECTION 0x10000 + +#define mmNIC6_DBG_CS_DBG_ROM_TABLE_1_BASE 0x1000007FFF4A0000ull +#define NIC6_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 + +#define mmNIC6_DBG_STM_1_BASE 0x1000007FFF4A1000ull +#define NIC6_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_STM_1_SECTION 0x1000 + +#define mmNIC6_DBG_CTI_1_BASE 0x1000007FFF4A2000ull +#define NIC6_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_CTI_1_SECTION 0x1000 + +#define mmNIC6_DBG_ETF_1_BASE 0x1000007FFF4A3000ull +#define NIC6_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_ETF_1_SECTION 0x1000 + +#define mmNIC6_DBG_SPMU_1_BASE 0x1000007FFF4A4000ull +#define NIC6_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_SPMU_1_SECTION 0x1000 + +#define mmNIC6_DBG_USER_CTI_1_BASE 0x1000007FFF4A5000ull +#define NIC6_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_USER_CTI_1_SECTION 0x1000 + +#define mmNIC6_DBG_BMON_CTI_1_BASE 0x1000007FFF4A6000ull +#define NIC6_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_BMON_CTI_1_SECTION 0x1000 + +#define mmNIC6_DBG_BMON0_1_BASE 0x1000007FFF4A7000ull +#define NIC6_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_BMON0_1_SECTION 0x1000 + +#define mmNIC6_DBG_BMON1_1_BASE 0x1000007FFF4A8000ull +#define NIC6_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_BMON1_1_SECTION 0x1000 + +#define mmNIC6_DBG_BMON2_1_BASE 0x1000007FFF4A9000ull +#define NIC6_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC6_DBG_BMON2_1_SECTION 0x7000 + +#define mmNIC6_DBG_ARC_RTT1_BASE 0x1000007FFF4B0000ull +#define NIC6_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC6_DBG_ARC_RTT1_SECTION 0x8000 + +#define mmNIC6_DBG_FUNNEL_TX_BASE 0x1000007FFF4B8000ull +#define NIC6_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC6_DBG_FUNNEL_TX_SECTION 0x1000 + +#define mmNIC6_DBG_FUNNEL_NCH_BASE 0x1000007FFF4B9000ull +#define NIC6_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC6_DBG_FUNNEL_NCH_SECTION 0x7000 + +#define mmNIC7_DBG_CS_DBG_ROM_TABLE_0_BASE 0x1000007FFF4C0000ull +#define NIC7_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 + +#define mmNIC7_DBG_STM_0_BASE 0x1000007FFF4C1000ull +#define NIC7_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_STM_0_SECTION 0x1000 + +#define mmNIC7_DBG_CTI_0_BASE 0x1000007FFF4C2000ull +#define NIC7_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_CTI_0_SECTION 0x1000 + +#define mmNIC7_DBG_ETF_0_BASE 0x1000007FFF4C3000ull +#define NIC7_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_ETF_0_SECTION 0x1000 + +#define mmNIC7_DBG_SPMU_0_BASE 0x1000007FFF4C4000ull +#define NIC7_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_SPMU_0_SECTION 0x1000 + +#define mmNIC7_DBG_USER_CTI_0_BASE 0x1000007FFF4C5000ull +#define NIC7_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_USER_CTI_0_SECTION 0x1000 + +#define mmNIC7_DBG_BMON_CTI_0_BASE 0x1000007FFF4C6000ull +#define NIC7_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_BMON_CTI_0_SECTION 0x1000 + +#define mmNIC7_DBG_BMON0_0_BASE 0x1000007FFF4C7000ull +#define NIC7_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_BMON0_0_SECTION 0x1000 + +#define mmNIC7_DBG_BMON1_0_BASE 0x1000007FFF4C8000ull +#define NIC7_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_BMON1_0_SECTION 0x1000 + +#define mmNIC7_DBG_BMON2_0_BASE 0x1000007FFF4C9000ull +#define NIC7_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC7_DBG_BMON2_0_SECTION 0x7000 + +#define mmNIC7_DBG_ARC_RTT0_BASE 0x1000007FFF4D0000ull +#define NIC7_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC7_DBG_ARC_RTT0_SECTION 0x10000 + +#define mmNIC7_DBG_CS_DBG_ROM_TABLE_1_BASE 0x1000007FFF4E0000ull +#define NIC7_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 + +#define mmNIC7_DBG_STM_1_BASE 0x1000007FFF4E1000ull +#define NIC7_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_STM_1_SECTION 0x1000 + +#define mmNIC7_DBG_CTI_1_BASE 0x1000007FFF4E2000ull +#define NIC7_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_CTI_1_SECTION 0x1000 + +#define mmNIC7_DBG_ETF_1_BASE 0x1000007FFF4E3000ull +#define NIC7_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_ETF_1_SECTION 0x1000 + +#define mmNIC7_DBG_SPMU_1_BASE 0x1000007FFF4E4000ull +#define NIC7_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_SPMU_1_SECTION 0x1000 + +#define mmNIC7_DBG_USER_CTI_1_BASE 0x1000007FFF4E5000ull +#define NIC7_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_USER_CTI_1_SECTION 0x1000 + +#define mmNIC7_DBG_BMON_CTI_1_BASE 0x1000007FFF4E6000ull +#define NIC7_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_BMON_CTI_1_SECTION 0x1000 + +#define mmNIC7_DBG_BMON0_1_BASE 0x1000007FFF4E7000ull +#define NIC7_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_BMON0_1_SECTION 0x1000 + +#define mmNIC7_DBG_BMON1_1_BASE 0x1000007FFF4E8000ull +#define NIC7_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_BMON1_1_SECTION 0x1000 + +#define mmNIC7_DBG_BMON2_1_BASE 0x1000007FFF4E9000ull +#define NIC7_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC7_DBG_BMON2_1_SECTION 0x7000 + +#define mmNIC7_DBG_ARC_RTT1_BASE 0x1000007FFF4F0000ull +#define NIC7_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC7_DBG_ARC_RTT1_SECTION 0x8000 + +#define mmNIC7_DBG_FUNNEL_TX_BASE 0x1000007FFF4F8000ull +#define NIC7_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC7_DBG_FUNNEL_TX_SECTION 0x1000 + +#define mmNIC7_DBG_FUNNEL_NCH_BASE 0x1000007FFF4F9000ull +#define NIC7_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC7_DBG_FUNNEL_NCH_SECTION 0x7000 + +#define mmNIC8_DBG_CS_DBG_ROM_TABLE_0_BASE 0x1000007FFF500000ull +#define NIC8_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 + +#define mmNIC8_DBG_STM_0_BASE 0x1000007FFF501000ull +#define NIC8_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_STM_0_SECTION 0x1000 + +#define mmNIC8_DBG_CTI_0_BASE 0x1000007FFF502000ull +#define NIC8_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_CTI_0_SECTION 0x1000 + +#define mmNIC8_DBG_ETF_0_BASE 0x1000007FFF503000ull +#define NIC8_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_ETF_0_SECTION 0x1000 + +#define mmNIC8_DBG_SPMU_0_BASE 0x1000007FFF504000ull +#define NIC8_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_SPMU_0_SECTION 0x1000 + +#define mmNIC8_DBG_USER_CTI_0_BASE 0x1000007FFF505000ull +#define NIC8_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_USER_CTI_0_SECTION 0x1000 + +#define mmNIC8_DBG_BMON_CTI_0_BASE 0x1000007FFF506000ull +#define NIC8_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_BMON_CTI_0_SECTION 0x1000 + +#define mmNIC8_DBG_BMON0_0_BASE 0x1000007FFF507000ull +#define NIC8_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_BMON0_0_SECTION 0x1000 + +#define mmNIC8_DBG_BMON1_0_BASE 0x1000007FFF508000ull +#define NIC8_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_BMON1_0_SECTION 0x1000 + +#define mmNIC8_DBG_BMON2_0_BASE 0x1000007FFF509000ull +#define NIC8_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC8_DBG_BMON2_0_SECTION 0x7000 + +#define mmNIC8_DBG_ARC_RTT0_BASE 0x1000007FFF510000ull +#define NIC8_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC8_DBG_ARC_RTT0_SECTION 0x10000 + +#define mmNIC8_DBG_CS_DBG_ROM_TABLE_1_BASE 0x1000007FFF520000ull +#define NIC8_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 + +#define mmNIC8_DBG_STM_1_BASE 0x1000007FFF521000ull +#define NIC8_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_STM_1_SECTION 0x1000 + +#define mmNIC8_DBG_CTI_1_BASE 0x1000007FFF522000ull +#define NIC8_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_CTI_1_SECTION 0x1000 + +#define mmNIC8_DBG_ETF_1_BASE 0x1000007FFF523000ull +#define NIC8_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_ETF_1_SECTION 0x1000 + +#define mmNIC8_DBG_SPMU_1_BASE 0x1000007FFF524000ull +#define NIC8_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_SPMU_1_SECTION 0x1000 + +#define mmNIC8_DBG_USER_CTI_1_BASE 0x1000007FFF525000ull +#define NIC8_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_USER_CTI_1_SECTION 0x1000 + +#define mmNIC8_DBG_BMON_CTI_1_BASE 0x1000007FFF526000ull +#define NIC8_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_BMON_CTI_1_SECTION 0x1000 + +#define mmNIC8_DBG_BMON0_1_BASE 0x1000007FFF527000ull +#define NIC8_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_BMON0_1_SECTION 0x1000 + +#define mmNIC8_DBG_BMON1_1_BASE 0x1000007FFF528000ull +#define NIC8_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_BMON1_1_SECTION 0x1000 + +#define mmNIC8_DBG_BMON2_1_BASE 0x1000007FFF529000ull +#define NIC8_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC8_DBG_BMON2_1_SECTION 0x7000 + +#define mmNIC8_DBG_ARC_RTT1_BASE 0x1000007FFF530000ull +#define NIC8_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC8_DBG_ARC_RTT1_SECTION 0x8000 + +#define mmNIC8_DBG_FUNNEL_TX_BASE 0x1000007FFF538000ull +#define NIC8_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC8_DBG_FUNNEL_TX_SECTION 0x1000 + +#define mmNIC8_DBG_FUNNEL_NCH_BASE 0x1000007FFF539000ull +#define NIC8_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC8_DBG_FUNNEL_NCH_SECTION 0x7000 + +#define mmNIC9_DBG_CS_DBG_ROM_TABLE_0_BASE 0x1000007FFF540000ull +#define NIC9_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 + +#define mmNIC9_DBG_STM_0_BASE 0x1000007FFF541000ull +#define NIC9_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_STM_0_SECTION 0x1000 + +#define mmNIC9_DBG_CTI_0_BASE 0x1000007FFF542000ull +#define NIC9_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_CTI_0_SECTION 0x1000 + +#define mmNIC9_DBG_ETF_0_BASE 0x1000007FFF543000ull +#define NIC9_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_ETF_0_SECTION 0x1000 + +#define mmNIC9_DBG_SPMU_0_BASE 0x1000007FFF544000ull +#define NIC9_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_SPMU_0_SECTION 0x1000 + +#define mmNIC9_DBG_USER_CTI_0_BASE 0x1000007FFF545000ull +#define NIC9_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_USER_CTI_0_SECTION 0x1000 + +#define mmNIC9_DBG_BMON_CTI_0_BASE 0x1000007FFF546000ull +#define NIC9_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_BMON_CTI_0_SECTION 0x1000 + +#define mmNIC9_DBG_BMON0_0_BASE 0x1000007FFF547000ull +#define NIC9_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_BMON0_0_SECTION 0x1000 + +#define mmNIC9_DBG_BMON1_0_BASE 0x1000007FFF548000ull +#define NIC9_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_BMON1_0_SECTION 0x1000 + +#define mmNIC9_DBG_BMON2_0_BASE 0x1000007FFF549000ull +#define NIC9_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC9_DBG_BMON2_0_SECTION 0x7000 + +#define mmNIC9_DBG_ARC_RTT0_BASE 0x1000007FFF550000ull +#define NIC9_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC9_DBG_ARC_RTT0_SECTION 0x10000 + +#define mmNIC9_DBG_CS_DBG_ROM_TABLE_1_BASE 0x1000007FFF560000ull +#define NIC9_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 + +#define mmNIC9_DBG_STM_1_BASE 0x1000007FFF561000ull +#define NIC9_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_STM_1_SECTION 0x1000 + +#define mmNIC9_DBG_CTI_1_BASE 0x1000007FFF562000ull +#define NIC9_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_CTI_1_SECTION 0x1000 + +#define mmNIC9_DBG_ETF_1_BASE 0x1000007FFF563000ull +#define NIC9_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_ETF_1_SECTION 0x1000 + +#define mmNIC9_DBG_SPMU_1_BASE 0x1000007FFF564000ull +#define NIC9_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_SPMU_1_SECTION 0x1000 + +#define mmNIC9_DBG_USER_CTI_1_BASE 0x1000007FFF565000ull +#define NIC9_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_USER_CTI_1_SECTION 0x1000 + +#define mmNIC9_DBG_BMON_CTI_1_BASE 0x1000007FFF566000ull +#define NIC9_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_BMON_CTI_1_SECTION 0x1000 + +#define mmNIC9_DBG_BMON0_1_BASE 0x1000007FFF567000ull +#define NIC9_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_BMON0_1_SECTION 0x1000 + +#define mmNIC9_DBG_BMON1_1_BASE 0x1000007FFF568000ull +#define NIC9_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_BMON1_1_SECTION 0x1000 + +#define mmNIC9_DBG_BMON2_1_BASE 0x1000007FFF569000ull +#define NIC9_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC9_DBG_BMON2_1_SECTION 0x7000 + +#define mmNIC9_DBG_ARC_RTT1_BASE 0x1000007FFF570000ull +#define NIC9_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC9_DBG_ARC_RTT1_SECTION 0x8000 + +#define mmNIC9_DBG_FUNNEL_TX_BASE 0x1000007FFF578000ull +#define NIC9_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC9_DBG_FUNNEL_TX_SECTION 0x1000 + +#define mmNIC9_DBG_FUNNEL_NCH_BASE 0x1000007FFF579000ull +#define NIC9_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC9_DBG_FUNNEL_NCH_SECTION 0x7000 + +#define mmNIC10_DBG_CS_DBG_ROM_TABLE_0_BASE 0x1000007FFF580000ull +#define NIC10_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 + +#define mmNIC10_DBG_STM_0_BASE 0x1000007FFF581000ull +#define NIC10_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_STM_0_SECTION 0x1000 + +#define mmNIC10_DBG_CTI_0_BASE 0x1000007FFF582000ull +#define NIC10_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_CTI_0_SECTION 0x1000 + +#define mmNIC10_DBG_ETF_0_BASE 0x1000007FFF583000ull +#define NIC10_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_ETF_0_SECTION 0x1000 + +#define mmNIC10_DBG_SPMU_0_BASE 0x1000007FFF584000ull +#define NIC10_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_SPMU_0_SECTION 0x1000 + +#define mmNIC10_DBG_USER_CTI_0_BASE 0x1000007FFF585000ull +#define NIC10_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_USER_CTI_0_SECTION 0x1000 + +#define mmNIC10_DBG_BMON_CTI_0_BASE 0x1000007FFF586000ull +#define NIC10_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_BMON_CTI_0_SECTION 0x1000 + +#define mmNIC10_DBG_BMON0_0_BASE 0x1000007FFF587000ull +#define NIC10_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_BMON0_0_SECTION 0x1000 + +#define mmNIC10_DBG_BMON1_0_BASE 0x1000007FFF588000ull +#define NIC10_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_BMON1_0_SECTION 0x1000 + +#define mmNIC10_DBG_BMON2_0_BASE 0x1000007FFF589000ull +#define NIC10_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC10_DBG_BMON2_0_SECTION 0x7000 + +#define mmNIC10_DBG_ARC_RTT0_BASE 0x1000007FFF590000ull +#define NIC10_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC10_DBG_ARC_RTT0_SECTION 0x10000 + +#define mmNIC10_DBG_CS_DBG_ROM_TABLE_1_BASE 0x1000007FFF5A0000ull +#define NIC10_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 + +#define mmNIC10_DBG_STM_1_BASE 0x1000007FFF5A1000ull +#define NIC10_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_STM_1_SECTION 0x1000 + +#define mmNIC10_DBG_CTI_1_BASE 0x1000007FFF5A2000ull +#define NIC10_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_CTI_1_SECTION 0x1000 + +#define mmNIC10_DBG_ETF_1_BASE 0x1000007FFF5A3000ull +#define NIC10_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_ETF_1_SECTION 0x1000 + +#define mmNIC10_DBG_SPMU_1_BASE 0x1000007FFF5A4000ull +#define NIC10_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_SPMU_1_SECTION 0x1000 + +#define mmNIC10_DBG_USER_CTI_1_BASE 0x1000007FFF5A5000ull +#define NIC10_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_USER_CTI_1_SECTION 0x1000 + +#define mmNIC10_DBG_BMON_CTI_1_BASE 0x1000007FFF5A6000ull +#define NIC10_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_BMON_CTI_1_SECTION 0x1000 + +#define mmNIC10_DBG_BMON0_1_BASE 0x1000007FFF5A7000ull +#define NIC10_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_BMON0_1_SECTION 0x1000 + +#define mmNIC10_DBG_BMON1_1_BASE 0x1000007FFF5A8000ull +#define NIC10_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_BMON1_1_SECTION 0x1000 + +#define mmNIC10_DBG_BMON2_1_BASE 0x1000007FFF5A9000ull +#define NIC10_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC10_DBG_BMON2_1_SECTION 0x7000 + +#define mmNIC10_DBG_ARC_RTT1_BASE 0x1000007FFF5B0000ull +#define NIC10_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC10_DBG_ARC_RTT1_SECTION 0x8000 + +#define mmNIC10_DBG_FUNNEL_TX_BASE 0x1000007FFF5B8000ull +#define NIC10_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC10_DBG_FUNNEL_TX_SECTION 0x1000 + +#define mmNIC10_DBG_FUNNEL_NCH_BASE 0x1000007FFF5B9000ull +#define NIC10_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 +#define NIC10_DBG_FUNNEL_NCH_SECTION 0x7000 + +#define mmNIC11_DBG_CS_DBG_ROM_TABLE_0_BASE 0x1000007FFF5C0000ull +#define NIC11_DBG_CS_DBG_ROM_TABLE_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_CS_DBG_ROM_TABLE_0_SECTION 0x1000 + +#define mmNIC11_DBG_STM_0_BASE 0x1000007FFF5C1000ull +#define NIC11_DBG_STM_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_STM_0_SECTION 0x1000 + +#define mmNIC11_DBG_CTI_0_BASE 0x1000007FFF5C2000ull +#define NIC11_DBG_CTI_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_CTI_0_SECTION 0x1000 + +#define mmNIC11_DBG_ETF_0_BASE 0x1000007FFF5C3000ull +#define NIC11_DBG_ETF_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_ETF_0_SECTION 0x1000 + +#define mmNIC11_DBG_SPMU_0_BASE 0x1000007FFF5C4000ull +#define NIC11_DBG_SPMU_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_SPMU_0_SECTION 0x1000 + +#define mmNIC11_DBG_USER_CTI_0_BASE 0x1000007FFF5C5000ull +#define NIC11_DBG_USER_CTI_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_USER_CTI_0_SECTION 0x1000 + +#define mmNIC11_DBG_BMON_CTI_0_BASE 0x1000007FFF5C6000ull +#define NIC11_DBG_BMON_CTI_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_BMON_CTI_0_SECTION 0x1000 + +#define mmNIC11_DBG_BMON0_0_BASE 0x1000007FFF5C7000ull +#define NIC11_DBG_BMON0_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_BMON0_0_SECTION 0x1000 + +#define mmNIC11_DBG_BMON1_0_BASE 0x1000007FFF5C8000ull +#define NIC11_DBG_BMON1_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_BMON1_0_SECTION 0x1000 + +#define mmNIC11_DBG_BMON2_0_BASE 0x1000007FFF5C9000ull +#define NIC11_DBG_BMON2_0_MAX_OFFSET 0x1000 +#define NIC11_DBG_BMON2_0_SECTION 0x7000 + +#define mmNIC11_DBG_ARC_RTT0_BASE 0x1000007FFF5D0000ull +#define NIC11_DBG_ARC_RTT0_MAX_OFFSET 0x1400 +#define NIC11_DBG_ARC_RTT0_SECTION 0x10000 + +#define mmNIC11_DBG_CS_DBG_ROM_TABLE_1_BASE 0x1000007FFF5E0000ull +#define NIC11_DBG_CS_DBG_ROM_TABLE_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_CS_DBG_ROM_TABLE_1_SECTION 0x1000 + +#define mmNIC11_DBG_STM_1_BASE 0x1000007FFF5E1000ull +#define NIC11_DBG_STM_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_STM_1_SECTION 0x1000 + +#define mmNIC11_DBG_CTI_1_BASE 0x1000007FFF5E2000ull +#define NIC11_DBG_CTI_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_CTI_1_SECTION 0x1000 + +#define mmNIC11_DBG_ETF_1_BASE 0x1000007FFF5E3000ull +#define NIC11_DBG_ETF_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_ETF_1_SECTION 0x1000 + +#define mmNIC11_DBG_SPMU_1_BASE 0x1000007FFF5E4000ull +#define NIC11_DBG_SPMU_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_SPMU_1_SECTION 0x1000 + +#define mmNIC11_DBG_USER_CTI_1_BASE 0x1000007FFF5E5000ull +#define NIC11_DBG_USER_CTI_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_USER_CTI_1_SECTION 0x1000 + +#define mmNIC11_DBG_BMON_CTI_1_BASE 0x1000007FFF5E6000ull +#define NIC11_DBG_BMON_CTI_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_BMON_CTI_1_SECTION 0x1000 + +#define mmNIC11_DBG_BMON0_1_BASE 0x1000007FFF5E7000ull +#define NIC11_DBG_BMON0_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_BMON0_1_SECTION 0x1000 + +#define mmNIC11_DBG_BMON1_1_BASE 0x1000007FFF5E8000ull +#define NIC11_DBG_BMON1_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_BMON1_1_SECTION 0x1000 + +#define mmNIC11_DBG_BMON2_1_BASE 0x1000007FFF5E9000ull +#define NIC11_DBG_BMON2_1_MAX_OFFSET 0x1000 +#define NIC11_DBG_BMON2_1_SECTION 0x7000 + +#define mmNIC11_DBG_ARC_RTT1_BASE 0x1000007FFF5F0000ull +#define NIC11_DBG_ARC_RTT1_MAX_OFFSET 0x1400 +#define NIC11_DBG_ARC_RTT1_SECTION 0x8000 + +#define mmNIC11_DBG_FUNNEL_TX_BASE 0x1000007FFF5F8000ull +#define NIC11_DBG_FUNNEL_TX_MAX_OFFSET 0x1000 +#define NIC11_DBG_FUNNEL_TX_SECTION 0x1000 + +#define mmNIC11_DBG_FUNNEL_NCH_BASE 0x1000007FFF5F9000ull +#define NIC11_DBG_FUNNEL_NCH_MAX_OFFSET 0x1000 + +#endif /* GAUDI2_BLOCKS_H_ */ diff --git a/external_includes/gaudi2/asic_reg_structs/axuser_regs.h b/external_includes/gaudi2/asic_reg_structs/axuser_regs.h new file mode 100644 index 0000000..53d7867 --- /dev/null +++ b/external_includes/gaudi2/asic_reg_structs/axuser_regs.h @@ -0,0 +1,397 @@ +/*********************************** +** This is an auto-generated file ** +** DO NOT EDIT BELOW ** +************************************/ + +#ifndef ASIC_REG_STRUCTS_AXUSER_H_ +#define ASIC_REG_STRUCTS_AXUSER_H_ + +#include +#include "gaudi2_types.h" + +#pragma pack(push, 1) + +#ifdef __cplusplus +namespace gaudi2 { +namespace axuser { +#else +# ifndef static_assert +# if defined( __STDC__ ) && defined( __STDC_VERSION__ ) && __STDC_VERSION__ >= 201112L +# define static_assert(...) _Static_assert(__VA_ARGS__) +# else +# define static_assert(...) +# endif +# endif +#endif + +/* + HB_ASID + b'HBW ASID' +*/ +typedef struct reg_hb_asid { + union { + struct { + uint32_t wr : 10, + _reserved16 : 6, + rd : 10, + _reserved26 : 6; + }; + uint32_t _raw; + }; +} reg_hb_asid; +static_assert((sizeof(struct reg_hb_asid) == 4), "reg_hb_asid size is not 32-bit"); +/* + HB_MMU_BP + b'HBW MMU bypass' +*/ +typedef struct reg_hb_mmu_bp { + union { + struct { + uint32_t wr : 1, + _reserved4 : 3, + rd : 1, + _reserved5 : 27; + }; + uint32_t _raw; + }; +} reg_hb_mmu_bp; +static_assert((sizeof(struct reg_hb_mmu_bp) == 4), "reg_hb_mmu_bp size is not 32-bit"); +/* + HB_STRONG_ORDER + b'HBW Strong Order' +*/ +typedef struct reg_hb_strong_order { + union { + struct { + uint32_t wr : 1, + _reserved4 : 3, + rd : 1, + _reserved5 : 27; + }; + uint32_t _raw; + }; +} reg_hb_strong_order; +static_assert((sizeof(struct reg_hb_strong_order) == 4), "reg_hb_strong_order size is not 32-bit"); +/* + HB_NO_SNOOP + b'HBW NO_SNOOP' +*/ +typedef struct reg_hb_no_snoop { + union { + struct { + uint32_t wr : 1, + _reserved4 : 3, + rd : 1, + _reserved5 : 27; + }; + uint32_t _raw; + }; +} reg_hb_no_snoop; +static_assert((sizeof(struct reg_hb_no_snoop) == 4), "reg_hb_no_snoop size is not 32-bit"); +/* + HB_WR_REDUCTION + b'HBW Reduction operators' +*/ +typedef struct reg_hb_wr_reduction { + union { + struct { + uint32_t ind : 1, + _reserved4 : 3, + dtype : 4, + op : 2, + _reserved12 : 2, + round : 2, + _reserved16 : 2, + max : 1, + _reserved17 : 15; + }; + uint32_t _raw; + }; +} reg_hb_wr_reduction; +static_assert((sizeof(struct reg_hb_wr_reduction) == 4), "reg_hb_wr_reduction size is not 32-bit"); +/* + HB_RD_ATOMIC + b'HBW Read atomic' +*/ +typedef struct reg_hb_rd_atomic { + union { + struct { + uint32_t ind : 2, + _reserved4 : 2, + addition_size : 8, + msb_mask : 5, + _reserved17 : 15; + }; + uint32_t _raw; + }; +} reg_hb_rd_atomic; +static_assert((sizeof(struct reg_hb_rd_atomic) == 4), "reg_hb_rd_atomic size is not 32-bit"); +/* + HB_QOS + b'HBW Quality of service for HBM' +*/ +typedef struct reg_hb_qos { + union { + struct { + uint32_t wr : 4, + rd : 3, + _reserved7 : 25; + }; + uint32_t _raw; + }; +} reg_hb_qos; +static_assert((sizeof(struct reg_hb_qos) == 4), "reg_hb_qos size is not 32-bit"); +/* + HB_RSVD + b'HBW reserved fields of user bus' +*/ +typedef struct reg_hb_rsvd { + union { + struct { + uint32_t wr_bit_27 : 1, + wr_bit_28 : 1, + wr_bit_30 : 1, + wr_bit_31 : 1, + _reserved4 : 28; + }; + uint32_t _raw; + }; +} reg_hb_rsvd; +static_assert((sizeof(struct reg_hb_rsvd) == 4), "reg_hb_rsvd size is not 32-bit"); +/* + HB_EMEM_CPAGE + b'HBW HBM Mode close page' +*/ +typedef struct reg_hb_emem_cpage { + union { + struct { + uint32_t wr : 1, + _reserved4 : 3, + rd : 1, + _reserved5 : 27; + }; + uint32_t _raw; + }; +} reg_hb_emem_cpage; +static_assert((sizeof(struct reg_hb_emem_cpage) == 4), "reg_hb_emem_cpage size is not 32-bit"); +/* + HB_CORE + b'HBW Coreherency load lock (or store unlock)' +*/ +typedef struct reg_hb_core { + union { + struct { + uint32_t wr : 1, + _reserved4 : 3, + rd : 1, + _reserved5 : 27; + }; + uint32_t _raw; + }; +} reg_hb_core; +static_assert((sizeof(struct reg_hb_core) == 4), "reg_hb_core size is not 32-bit"); +/* + E2E_COORD + b'HBW and LBW E2E coordinates' +*/ +typedef struct reg_e2e_coord { + union { + struct { + uint32_t x : 5, + _reserved8 : 3, + y : 4, + _reserved12 : 20; + }; + uint32_t _raw; + }; +} reg_e2e_coord; +static_assert((sizeof(struct reg_e2e_coord) == 4), "reg_e2e_coord size is not 32-bit"); +/* + HB_WR_OVRD_LO + b'HBM AWUSER override config[31:0]' +*/ +typedef struct reg_hb_wr_ovrd_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_hb_wr_ovrd_lo; +static_assert((sizeof(struct reg_hb_wr_ovrd_lo) == 4), "reg_hb_wr_ovrd_lo size is not 32-bit"); +/* + HB_WR_OVRD_HI + b'HBM AWUSER override config[41:32]' +*/ +typedef struct reg_hb_wr_ovrd_hi { + union { + struct { + uint32_t val : 10, + _reserved10 : 22; + }; + uint32_t _raw; + }; +} reg_hb_wr_ovrd_hi; +static_assert((sizeof(struct reg_hb_wr_ovrd_hi) == 4), "reg_hb_wr_ovrd_hi size is not 32-bit"); +/* + HB_RD_OVRD_LO + b'HBM ARUSER override config[31:0]' +*/ +typedef struct reg_hb_rd_ovrd_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_hb_rd_ovrd_lo; +static_assert((sizeof(struct reg_hb_rd_ovrd_lo) == 4), "reg_hb_rd_ovrd_lo size is not 32-bit"); +/* + HB_RD_OVRD_HI + b'HBM ARUSER override config[41:32]' +*/ +typedef struct reg_hb_rd_ovrd_hi { + union { + struct { + uint32_t val : 10, + _reserved10 : 22; + }; + uint32_t _raw; + }; +} reg_hb_rd_ovrd_hi; +static_assert((sizeof(struct reg_hb_rd_ovrd_hi) == 4), "reg_hb_rd_ovrd_hi size is not 32-bit"); +/* + LB_COORD + b'LBW RAZWI coordinates' +*/ +typedef struct reg_lb_coord { + union { + struct { + uint32_t val : 10, + _reserved10 : 22; + }; + uint32_t _raw; + }; +} reg_lb_coord; +static_assert((sizeof(struct reg_lb_coord) == 4), "reg_lb_coord size is not 32-bit"); +/* + LB_LOCK + b'LBW TPC Lock indication' +*/ +typedef struct reg_lb_lock { + union { + struct { + uint32_t val : 1, + _reserved1 : 31; + }; + uint32_t _raw; + }; +} reg_lb_lock; +static_assert((sizeof(struct reg_lb_lock) == 4), "reg_lb_lock size is not 32-bit"); +/* + LB_RSVD + b'LBW Reserved' +*/ +typedef struct reg_lb_rsvd { + union { + struct { + uint32_t bit_21_11 : 11, + _reserved12 : 1, + bit_22 : 1, + _reserved13 : 19; + }; + uint32_t _raw; + }; +} reg_lb_rsvd; +static_assert((sizeof(struct reg_lb_rsvd) == 4), "reg_lb_rsvd size is not 32-bit"); +/* + LB_OVRD + b'LBW AxUSER override config' +*/ +typedef struct reg_lb_ovrd { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_lb_ovrd; +static_assert((sizeof(struct reg_lb_ovrd) == 4), "reg_lb_ovrd size is not 32-bit"); + +#ifdef __cplusplus +} /* axuser namespace */ +#endif + +/* + AXUSER block +*/ + +#ifdef __cplusplus + +struct block_axuser { + struct axuser::reg_hb_asid hb_asid; + struct axuser::reg_hb_mmu_bp hb_mmu_bp; + struct axuser::reg_hb_strong_order hb_strong_order; + struct axuser::reg_hb_no_snoop hb_no_snoop; + struct axuser::reg_hb_wr_reduction hb_wr_reduction; + struct axuser::reg_hb_rd_atomic hb_rd_atomic; + struct axuser::reg_hb_qos hb_qos; + struct axuser::reg_hb_rsvd hb_rsvd; + struct axuser::reg_hb_emem_cpage hb_emem_cpage; + struct axuser::reg_hb_core hb_core; + struct axuser::reg_e2e_coord e2e_coord; + uint32_t _pad44[1]; + struct axuser::reg_hb_wr_ovrd_lo hb_wr_ovrd_lo; + struct axuser::reg_hb_wr_ovrd_hi hb_wr_ovrd_hi; + struct axuser::reg_hb_rd_ovrd_lo hb_rd_ovrd_lo; + struct axuser::reg_hb_rd_ovrd_hi hb_rd_ovrd_hi; + struct axuser::reg_lb_coord lb_coord; + struct axuser::reg_lb_lock lb_lock; + struct axuser::reg_lb_rsvd lb_rsvd; + struct axuser::reg_lb_ovrd lb_ovrd; +}; +#else + +typedef struct block_axuser { + reg_hb_asid hb_asid; + reg_hb_mmu_bp hb_mmu_bp; + reg_hb_strong_order hb_strong_order; + reg_hb_no_snoop hb_no_snoop; + reg_hb_wr_reduction hb_wr_reduction; + reg_hb_rd_atomic hb_rd_atomic; + reg_hb_qos hb_qos; + reg_hb_rsvd hb_rsvd; + reg_hb_emem_cpage hb_emem_cpage; + reg_hb_core hb_core; + reg_e2e_coord e2e_coord; + uint32_t _pad44[1]; + reg_hb_wr_ovrd_lo hb_wr_ovrd_lo; + reg_hb_wr_ovrd_hi hb_wr_ovrd_hi; + reg_hb_rd_ovrd_lo hb_rd_ovrd_lo; + reg_hb_rd_ovrd_hi hb_rd_ovrd_hi; + reg_lb_coord lb_coord; + reg_lb_lock lb_lock; + reg_lb_rsvd lb_rsvd; + reg_lb_ovrd lb_ovrd; +} block_axuser; +#endif + +const offsetVal block_axuser_defaults[] = +{ + // offset // value + { 0x4 , 0x11 , 1 }, // hb_mmu_bp + { 0x8 , 0x11 , 1 }, // hb_strong_order + { 0x20 , 0x11 , 1 }, // hb_emem_cpage + { 0x30 , 0xffffffff , 1 }, // hb_wr_ovrd_lo + { 0x34 , 0x3ff , 1 }, // hb_wr_ovrd_hi + { 0x38 , 0xffffffff , 1 }, // hb_rd_ovrd_lo + { 0x3c , 0x3ff , 1 }, // hb_rd_ovrd_hi + { 0x4c , 0xffffffff , 1 }, // lb_ovrd +}; + +#ifdef __cplusplus +} /* gaudi2 namespace */ +#endif + +#pragma pack(pop) +#endif /* ASIC_REG_STRUCTS_AXUSER_H_ */ diff --git a/external_includes/gaudi2/asic_reg_structs/dma_core_ctx_regs.h b/external_includes/gaudi2/asic_reg_structs/dma_core_ctx_regs.h new file mode 100644 index 0000000..5a5bae2 --- /dev/null +++ b/external_includes/gaudi2/asic_reg_structs/dma_core_ctx_regs.h @@ -0,0 +1,636 @@ +/*********************************** +** This is an auto-generated file ** +** DO NOT EDIT BELOW ** +************************************/ + +#ifndef ASIC_REG_STRUCTS_DMA_CORE_CTX_H_ +#define ASIC_REG_STRUCTS_DMA_CORE_CTX_H_ + +#include +#include "gaudi2_types.h" + +#pragma pack(push, 1) + +#ifdef __cplusplus +namespace gaudi2 { +namespace dma_core_ctx { +#else +# ifndef static_assert +# if defined( __STDC__ ) && defined( __STDC_VERSION__ ) && __STDC_VERSION__ >= 201112L +# define static_assert(...) _Static_assert(__VA_ARGS__) +# else +# define static_assert(...) +# endif +# endif +#endif + +/* + RATE_LIM_TKN + b'Rate limiters Tokens' +*/ +typedef struct reg_rate_lim_tkn { + union { + struct { + uint32_t rd : 8, + _reserved16 : 8, + wr : 8, + _reserved24 : 8; + }; + uint32_t _raw; + }; +} reg_rate_lim_tkn; +static_assert((sizeof(struct reg_rate_lim_tkn) == 4), "reg_rate_lim_tkn size is not 32-bit"); +/* + PWRLP + b'power loop data and control' +*/ +typedef struct reg_pwrlp { + union { + struct { + uint32_t data : 8, + en : 1, + _reserved9 : 23; + }; + uint32_t _raw; + }; +} reg_pwrlp; +static_assert((sizeof(struct reg_pwrlp) == 4), "reg_pwrlp size is not 32-bit"); +/* + TE_NUMROWS + b'Total rows num per descriptor. ignored if transpose not set' +*/ +typedef struct reg_te_numrows { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_te_numrows; +static_assert((sizeof(struct reg_te_numrows) == 4), "reg_te_numrows size is not 32-bit"); +/* + IDX + b'context ID' +*/ +typedef struct reg_idx { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_idx; +static_assert((sizeof(struct reg_idx) == 4), "reg_idx size is not 32-bit"); +/* + IDX_INC + b'context index inc signed value' +*/ +typedef struct reg_idx_inc { + union { + struct { + uint32_t val : 8, + _reserved8 : 24; + }; + uint32_t _raw; + }; +} reg_idx_inc; +static_assert((sizeof(struct reg_idx_inc) == 4), "reg_idx_inc size is not 32-bit"); +/* + CTRL + b'Control bits. TE, compress etc.' +*/ +typedef struct reg_ctrl { + union { + struct { + uint32_t transpose : 1, + _reserved4 : 3, + dtype : 2, + _reserved8 : 2, + compress : 1, + decompress : 1, + _reserved12 : 2, + rd_uncacheable : 1, + _reserved13 : 19; + }; + uint32_t _raw; + }; +} reg_ctrl; +static_assert((sizeof(struct reg_ctrl) == 4), "reg_ctrl size is not 32-bit"); +/* + SRC_TSIZE_0 + b'Size in bytes of dim 0 transfer' +*/ +typedef struct reg_src_tsize_0 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_src_tsize_0; +static_assert((sizeof(struct reg_src_tsize_0) == 4), "reg_src_tsize_0 size is not 32-bit"); +/* + SRC_TSIZE_1 + b'Size in elements of Dim1' +*/ +typedef struct reg_src_tsize_1 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_src_tsize_1; +static_assert((sizeof(struct reg_src_tsize_1) == 4), "reg_src_tsize_1 size is not 32-bit"); +/* + SRC_STRIDE_1 + b'Src strides dim1' +*/ +typedef struct reg_src_stride_1 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_src_stride_1; +static_assert((sizeof(struct reg_src_stride_1) == 4), "reg_src_stride_1 size is not 32-bit"); +/* + SRC_TSIZE_2 + b'Source size in elements of Dim2' +*/ +typedef struct reg_src_tsize_2 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_src_tsize_2; +static_assert((sizeof(struct reg_src_tsize_2) == 4), "reg_src_tsize_2 size is not 32-bit"); +/* + SRC_STRIDE_2 + b'Source stride dim2' +*/ +typedef struct reg_src_stride_2 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_src_stride_2; +static_assert((sizeof(struct reg_src_stride_2) == 4), "reg_src_stride_2 size is not 32-bit"); +/* + SRC_TSIZE_3 + b'Source size in elements of Dim3' +*/ +typedef struct reg_src_tsize_3 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_src_tsize_3; +static_assert((sizeof(struct reg_src_tsize_3) == 4), "reg_src_tsize_3 size is not 32-bit"); +/* + SRC_STRIDE_3 + b'Source stride dim3' +*/ +typedef struct reg_src_stride_3 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_src_stride_3; +static_assert((sizeof(struct reg_src_stride_3) == 4), "reg_src_stride_3 size is not 32-bit"); +/* + SRC_TSIZE_4 + b'Source size in elements of Dim4' +*/ +typedef struct reg_src_tsize_4 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_src_tsize_4; +static_assert((sizeof(struct reg_src_tsize_4) == 4), "reg_src_tsize_4 size is not 32-bit"); +/* + SRC_STRIDE_4 + b'Source stride dim4' +*/ +typedef struct reg_src_stride_4 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_src_stride_4; +static_assert((sizeof(struct reg_src_stride_4) == 4), "reg_src_stride_4 size is not 32-bit"); +/* + DST_TSIZE_1 + b'Dest size in elements Dim1' +*/ +typedef struct reg_dst_tsize_1 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_dst_tsize_1; +static_assert((sizeof(struct reg_dst_tsize_1) == 4), "reg_dst_tsize_1 size is not 32-bit"); +/* + DST_STRIDE_1 + b'Dest stride dim1' +*/ +typedef struct reg_dst_stride_1 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_dst_stride_1; +static_assert((sizeof(struct reg_dst_stride_1) == 4), "reg_dst_stride_1 size is not 32-bit"); +/* + DST_TSIZE_2 + b'Dest size in elements Dim2' +*/ +typedef struct reg_dst_tsize_2 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_dst_tsize_2; +static_assert((sizeof(struct reg_dst_tsize_2) == 4), "reg_dst_tsize_2 size is not 32-bit"); +/* + DST_STRIDE_2 + b'Dest stride Dim2' +*/ +typedef struct reg_dst_stride_2 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_dst_stride_2; +static_assert((sizeof(struct reg_dst_stride_2) == 4), "reg_dst_stride_2 size is not 32-bit"); +/* + DST_TSIZE_3 + b'Dest size in elements Dim3' +*/ +typedef struct reg_dst_tsize_3 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_dst_tsize_3; +static_assert((sizeof(struct reg_dst_tsize_3) == 4), "reg_dst_tsize_3 size is not 32-bit"); +/* + DST_STRIDE_3 + b'Dest stride dim3' +*/ +typedef struct reg_dst_stride_3 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_dst_stride_3; +static_assert((sizeof(struct reg_dst_stride_3) == 4), "reg_dst_stride_3 size is not 32-bit"); +/* + DST_TSIZE_4 + b'Dest size in elements Dim4' +*/ +typedef struct reg_dst_tsize_4 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_dst_tsize_4; +static_assert((sizeof(struct reg_dst_tsize_4) == 4), "reg_dst_tsize_4 size is not 32-bit"); +/* + DST_STRIDE_4 + b'Dest stride dim4' +*/ +typedef struct reg_dst_stride_4 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_dst_stride_4; +static_assert((sizeof(struct reg_dst_stride_4) == 4), "reg_dst_stride_4 size is not 32-bit"); +/* + WR_COMP_ADDR_HI + b'Wr completion msg address byte 7-4' +*/ +typedef struct reg_wr_comp_addr_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_wr_comp_addr_hi; +static_assert((sizeof(struct reg_wr_comp_addr_hi) == 4), "reg_wr_comp_addr_hi size is not 32-bit"); +/* + WR_COMP_ADDR_LO + b'Wr completion msg address byte 3-0' +*/ +typedef struct reg_wr_comp_addr_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_wr_comp_addr_lo; +static_assert((sizeof(struct reg_wr_comp_addr_lo) == 4), "reg_wr_comp_addr_lo size is not 32-bit"); +/* + WR_COMP_WDATA + b'Wr completion msg wdata to send' +*/ +typedef struct reg_wr_comp_wdata { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_wr_comp_wdata; +static_assert((sizeof(struct reg_wr_comp_wdata) == 4), "reg_wr_comp_wdata size is not 32-bit"); +/* + SRC_OFFSET_LO + b'Source base address offset byte 3-0' +*/ +typedef struct reg_src_offset_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_src_offset_lo; +static_assert((sizeof(struct reg_src_offset_lo) == 4), "reg_src_offset_lo size is not 32-bit"); +/* + SRC_OFFSET_HI + b'Source base address offset byte 7-4' +*/ +typedef struct reg_src_offset_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_src_offset_hi; +static_assert((sizeof(struct reg_src_offset_hi) == 4), "reg_src_offset_hi size is not 32-bit"); +/* + DST_OFFSET_LO + b'destination base address offset byte 3-0' +*/ +typedef struct reg_dst_offset_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_dst_offset_lo; +static_assert((sizeof(struct reg_dst_offset_lo) == 4), "reg_dst_offset_lo size is not 32-bit"); +/* + DST_OFFSET_HI + b'destination base address byte 7-4' +*/ +typedef struct reg_dst_offset_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_dst_offset_hi; +static_assert((sizeof(struct reg_dst_offset_hi) == 4), "reg_dst_offset_hi size is not 32-bit"); +/* + SRC_BASE_LO + b'Source base address byte 3-0' +*/ +typedef struct reg_src_base_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_src_base_lo; +static_assert((sizeof(struct reg_src_base_lo) == 4), "reg_src_base_lo size is not 32-bit"); +/* + SRC_BASE_HI + b'Source base address byte 7-4' +*/ +typedef struct reg_src_base_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_src_base_hi; +static_assert((sizeof(struct reg_src_base_hi) == 4), "reg_src_base_hi size is not 32-bit"); +/* + DST_BASE_LO + b'Destination base address byte 3-0' +*/ +typedef struct reg_dst_base_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_dst_base_lo; +static_assert((sizeof(struct reg_dst_base_lo) == 4), "reg_dst_base_lo size is not 32-bit"); +/* + DST_BASE_HI + b'Destination base address byte 7-4' +*/ +typedef struct reg_dst_base_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_dst_base_hi; +static_assert((sizeof(struct reg_dst_base_hi) == 4), "reg_dst_base_hi size is not 32-bit"); +/* + DST_TSIZE_0 + b'Size in bytes of dim0. QMAN CP LDMA uses this as size' +*/ +typedef struct reg_dst_tsize_0 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_dst_tsize_0; +static_assert((sizeof(struct reg_dst_tsize_0) == 4), "reg_dst_tsize_0 size is not 32-bit"); +/* + COMMIT + b'Controls. writing to this reg initiates transfer' +*/ +typedef struct reg_commit { + union { + struct { + uint32_t wr_comp_en : 1, + endian_swap : 2, + _reserved4 : 1, + mem_set : 1, + _reserved6 : 1, + bf16 : 1, + fp16 : 1, + ctx_id_inc : 1, + add_offset_0 : 1, + src_size0_from_dst_size0 : 1, + src_ofst_from_dst_ofst : 1, + disable_dim1 : 1, + disable_dim2 : 1, + disable_dim3 : 1, + disable_dim4 : 1, + src_size1_from_dst_size1 : 1, + src_size2_from_dst_size2 : 1, + src_size3_from_dst_size3 : 1, + src_size4_from_dst_size4 : 1, + src_strd1_from_dst_strd1 : 1, + src_strd2_from_dst_strd2 : 1, + src_strd3_from_dst_strd3 : 1, + src_strd4_from_dst_strd4 : 1, + _reserved31 : 7, + lin : 1; + }; + uint32_t _raw; + }; +} reg_commit; +static_assert((sizeof(struct reg_commit) == 4), "reg_commit size is not 32-bit"); + +#ifdef __cplusplus +} /* dma_core_ctx namespace */ +#endif + +/* + DMA_CORE_CTX block +*/ + +#ifdef __cplusplus + +struct block_dma_core_ctx { + struct dma_core_ctx::reg_rate_lim_tkn rate_lim_tkn; + struct dma_core_ctx::reg_pwrlp pwrlp; + struct dma_core_ctx::reg_te_numrows te_numrows; + struct dma_core_ctx::reg_idx idx; + struct dma_core_ctx::reg_idx_inc idx_inc; + struct dma_core_ctx::reg_ctrl ctrl; + struct dma_core_ctx::reg_src_tsize_0 src_tsize_0; + struct dma_core_ctx::reg_src_tsize_1 src_tsize_1; + struct dma_core_ctx::reg_src_stride_1 src_stride_1; + struct dma_core_ctx::reg_src_tsize_2 src_tsize_2; + struct dma_core_ctx::reg_src_stride_2 src_stride_2; + struct dma_core_ctx::reg_src_tsize_3 src_tsize_3; + struct dma_core_ctx::reg_src_stride_3 src_stride_3; + struct dma_core_ctx::reg_src_tsize_4 src_tsize_4; + struct dma_core_ctx::reg_src_stride_4 src_stride_4; + struct dma_core_ctx::reg_dst_tsize_1 dst_tsize_1; + struct dma_core_ctx::reg_dst_stride_1 dst_stride_1; + struct dma_core_ctx::reg_dst_tsize_2 dst_tsize_2; + struct dma_core_ctx::reg_dst_stride_2 dst_stride_2; + struct dma_core_ctx::reg_dst_tsize_3 dst_tsize_3; + struct dma_core_ctx::reg_dst_stride_3 dst_stride_3; + struct dma_core_ctx::reg_dst_tsize_4 dst_tsize_4; + struct dma_core_ctx::reg_dst_stride_4 dst_stride_4; + struct dma_core_ctx::reg_wr_comp_addr_hi wr_comp_addr_hi; + struct dma_core_ctx::reg_wr_comp_addr_lo wr_comp_addr_lo; + struct dma_core_ctx::reg_wr_comp_wdata wr_comp_wdata; + struct dma_core_ctx::reg_src_offset_lo src_offset_lo; + struct dma_core_ctx::reg_src_offset_hi src_offset_hi; + struct dma_core_ctx::reg_dst_offset_lo dst_offset_lo; + struct dma_core_ctx::reg_dst_offset_hi dst_offset_hi; + struct dma_core_ctx::reg_src_base_lo src_base_lo; + struct dma_core_ctx::reg_src_base_hi src_base_hi; + struct dma_core_ctx::reg_dst_base_lo dst_base_lo; + struct dma_core_ctx::reg_dst_base_hi dst_base_hi; + struct dma_core_ctx::reg_dst_tsize_0 dst_tsize_0; + struct dma_core_ctx::reg_commit commit; +}; +#else + +typedef struct block_dma_core_ctx { + reg_rate_lim_tkn rate_lim_tkn; + reg_pwrlp pwrlp; + reg_te_numrows te_numrows; + reg_idx idx; + reg_idx_inc idx_inc; + reg_ctrl ctrl; + reg_src_tsize_0 src_tsize_0; + reg_src_tsize_1 src_tsize_1; + reg_src_stride_1 src_stride_1; + reg_src_tsize_2 src_tsize_2; + reg_src_stride_2 src_stride_2; + reg_src_tsize_3 src_tsize_3; + reg_src_stride_3 src_stride_3; + reg_src_tsize_4 src_tsize_4; + reg_src_stride_4 src_stride_4; + reg_dst_tsize_1 dst_tsize_1; + reg_dst_stride_1 dst_stride_1; + reg_dst_tsize_2 dst_tsize_2; + reg_dst_stride_2 dst_stride_2; + reg_dst_tsize_3 dst_tsize_3; + reg_dst_stride_3 dst_stride_3; + reg_dst_tsize_4 dst_tsize_4; + reg_dst_stride_4 dst_stride_4; + reg_wr_comp_addr_hi wr_comp_addr_hi; + reg_wr_comp_addr_lo wr_comp_addr_lo; + reg_wr_comp_wdata wr_comp_wdata; + reg_src_offset_lo src_offset_lo; + reg_src_offset_hi src_offset_hi; + reg_dst_offset_lo dst_offset_lo; + reg_dst_offset_hi dst_offset_hi; + reg_src_base_lo src_base_lo; + reg_src_base_hi src_base_hi; + reg_dst_base_lo dst_base_lo; + reg_dst_base_hi dst_base_hi; + reg_dst_tsize_0 dst_tsize_0; + reg_commit commit; +} block_dma_core_ctx; +#endif + +const offsetVal block_dma_core_ctx_defaults[] = +{ + // offset // value + { 0x0 , 0x40004 , 1 }, // rate_lim_tkn +}; + +#ifdef __cplusplus +} /* gaudi2 namespace */ +#endif + +#pragma pack(pop) +#endif /* ASIC_REG_STRUCTS_DMA_CORE_CTX_H_ */ diff --git a/external_includes/gaudi2/asic_reg_structs/dma_core_regs.h b/external_includes/gaudi2/asic_reg_structs/dma_core_regs.h new file mode 100644 index 0000000..d7670a1 --- /dev/null +++ b/external_includes/gaudi2/asic_reg_structs/dma_core_regs.h @@ -0,0 +1,1265 @@ +/*********************************** +** This is an auto-generated file ** +** DO NOT EDIT BELOW ** +************************************/ + +#ifndef ASIC_REG_STRUCTS_DMA_CORE_H_ +#define ASIC_REG_STRUCTS_DMA_CORE_H_ + +#include +#include "gaudi2_types.h" +#include "axuser_regs.h" +#include "dma_core_ctx_regs.h" +#include "qman_cgm_regs.h" +#include "special_regs_regs.h" + +#pragma pack(push, 1) + +#ifdef __cplusplus +namespace gaudi2 { +namespace dma_core { +#else +# ifndef static_assert +# if defined( __STDC__ ) && defined( __STDC_VERSION__ ) && __STDC_VERSION__ >= 201112L +# define static_assert(...) _Static_assert(__VA_ARGS__) +# else +# define static_assert(...) +# endif +# endif +#endif + +/* + CFG_0 + b'DMA enable' +*/ +typedef struct reg_cfg_0 { + union { + struct { + uint32_t en : 1, + _reserved1 : 31; + }; + uint32_t _raw; + }; +} reg_cfg_0; +static_assert((sizeof(struct reg_cfg_0) == 4), "reg_cfg_0 size is not 32-bit"); +/* + CFG_1 + b'Halt(stop), flush,force-miss' +*/ +typedef struct reg_cfg_1 { + union { + struct { + uint32_t halt : 1, + flush : 1, + _reserved2 : 30; + }; + uint32_t _raw; + }; +} reg_cfg_1; +static_assert((sizeof(struct reg_cfg_1) == 4), "reg_cfg_1 size is not 32-bit"); +/* + PROT + b'Secure or non Secure master' +*/ +typedef struct reg_prot { + union { + struct { + uint32_t val : 1, + err_val : 1, + _reserved2 : 30; + }; + uint32_t _raw; + }; +} reg_prot; +static_assert((sizeof(struct reg_prot) == 4), "reg_prot size is not 32-bit"); +/* + CKG + b'clock gating config' +*/ +typedef struct reg_ckg { + union { + struct { + uint32_t hbw_rbuf : 1, + lbw_rbuf_kdma : 1, + te : 1, + _reserved3 : 29; + }; + uint32_t _raw; + }; +} reg_ckg; +static_assert((sizeof(struct reg_ckg) == 4), "reg_ckg size is not 32-bit"); +/* + RD_GLBL + b'global RD config' +*/ +typedef struct reg_rd_glbl { + union { + struct { + uint32_t lbw_via_hbw : 1, + _reserved4 : 3, + hbw_force_miss : 1, + lbw_force_miss : 1, + _reserved6 : 26; + }; + uint32_t _raw; + }; +} reg_rd_glbl; +static_assert((sizeof(struct reg_rd_glbl) == 4), "reg_rd_glbl size is not 32-bit"); +/* + RD_HBW_MAX_OUTSTAND + b'Max Read open AXI transactions.0 means max possible' +*/ +typedef struct reg_rd_hbw_max_outstand { + union { + struct { + uint32_t val : 12, + _reserved12 : 20; + }; + uint32_t _raw; + }; +} reg_rd_hbw_max_outstand; +static_assert((sizeof(struct reg_rd_hbw_max_outstand) == 4), "reg_rd_hbw_max_outstand size is not 32-bit"); +/* + RD_HBW_MAX_SIZE + b'Max buffers size to use. 0 means max possible' +*/ +typedef struct reg_rd_hbw_max_size { + union { + struct { + uint32_t data : 12, + _reserved16 : 4, + md : 12, + _reserved28 : 4; + }; + uint32_t _raw; + }; +} reg_rd_hbw_max_size; +static_assert((sizeof(struct reg_rd_hbw_max_size) == 4), "reg_rd_hbw_max_size size is not 32-bit"); +/* + RD_HBW_ARCACHE + b'AXI ARCACHE' +*/ +typedef struct reg_rd_hbw_arcache { + union { + struct { + uint32_t val : 4, + _reserved4 : 28; + }; + uint32_t _raw; + }; +} reg_rd_hbw_arcache; +static_assert((sizeof(struct reg_rd_hbw_arcache) == 4), "reg_rd_hbw_arcache size is not 32-bit"); +/* + RD_HBW_INFLIGHTS + b'Read buffer open requests counter' +*/ +typedef struct reg_rd_hbw_inflights { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_rd_hbw_inflights; +static_assert((sizeof(struct reg_rd_hbw_inflights) == 4), "reg_rd_hbw_inflights size is not 32-bit"); +/* + RD_HBW_RATE_LIM_CFG + b'Read rate limiter timeout,saturation,enable' +*/ +typedef struct reg_rd_hbw_rate_lim_cfg { + union { + struct { + uint32_t tout : 8, + _reserved16 : 8, + sat : 8, + _reserved31 : 7, + en : 1; + }; + uint32_t _raw; + }; +} reg_rd_hbw_rate_lim_cfg; +static_assert((sizeof(struct reg_rd_hbw_rate_lim_cfg) == 4), "reg_rd_hbw_rate_lim_cfg size is not 32-bit"); +/* + RD_LBW_MAX_OUTSTAND + b'Max Read open AXI transactions.0 means max possible' +*/ +typedef struct reg_rd_lbw_max_outstand { + union { + struct { + uint32_t val : 12, + _reserved12 : 20; + }; + uint32_t _raw; + }; +} reg_rd_lbw_max_outstand; +static_assert((sizeof(struct reg_rd_lbw_max_outstand) == 4), "reg_rd_lbw_max_outstand size is not 32-bit"); +/* + RD_LBW_MAX_SIZE + b'Max buffers size to use. 0 means max possible' +*/ +typedef struct reg_rd_lbw_max_size { + union { + struct { + uint32_t data : 12, + _reserved16 : 4, + md : 12, + _reserved28 : 4; + }; + uint32_t _raw; + }; +} reg_rd_lbw_max_size; +static_assert((sizeof(struct reg_rd_lbw_max_size) == 4), "reg_rd_lbw_max_size size is not 32-bit"); +/* + RD_LBW_ARCACHE + b'AXI ARCACHE' +*/ +typedef struct reg_rd_lbw_arcache { + union { + struct { + uint32_t val : 4, + _reserved4 : 28; + }; + uint32_t _raw; + }; +} reg_rd_lbw_arcache; +static_assert((sizeof(struct reg_rd_lbw_arcache) == 4), "reg_rd_lbw_arcache size is not 32-bit"); +/* + RD_LBW_INFLIGHTS + b'Read buffer open requests counter' +*/ +typedef struct reg_rd_lbw_inflights { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_rd_lbw_inflights; +static_assert((sizeof(struct reg_rd_lbw_inflights) == 4), "reg_rd_lbw_inflights size is not 32-bit"); +/* + RD_LBW_RATE_LIM_CFG + b'Read rate limiter timeout,saturation,enable' +*/ +typedef struct reg_rd_lbw_rate_lim_cfg { + union { + struct { + uint32_t tout : 8, + _reserved16 : 8, + sat : 8, + _reserved31 : 7, + en : 1; + }; + uint32_t _raw; + }; +} reg_rd_lbw_rate_lim_cfg; +static_assert((sizeof(struct reg_rd_lbw_rate_lim_cfg) == 4), "reg_rd_lbw_rate_lim_cfg size is not 32-bit"); +/* + WR_HBW_MAX_OUTSTAND + b'Max open AXI-WR transactions. val of 0 means max possible' +*/ +typedef struct reg_wr_hbw_max_outstand { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_wr_hbw_max_outstand; +static_assert((sizeof(struct reg_wr_hbw_max_outstand) == 4), "reg_wr_hbw_max_outstand size is not 32-bit"); +/* + WR_HBW_MAX_AWID + b'MAX ID value for Wr buffer for debug' +*/ +typedef struct reg_wr_hbw_max_awid { + union { + struct { + uint32_t val : 14, + _reserved14 : 18; + }; + uint32_t _raw; + }; +} reg_wr_hbw_max_awid; +static_assert((sizeof(struct reg_wr_hbw_max_awid) == 4), "reg_wr_hbw_max_awid size is not 32-bit"); +/* + WR_HBW_AWCACHE + b'AXI AWCACHE' +*/ +typedef struct reg_wr_hbw_awcache { + union { + struct { + uint32_t val : 4, + _reserved4 : 28; + }; + uint32_t _raw; + }; +} reg_wr_hbw_awcache; +static_assert((sizeof(struct reg_wr_hbw_awcache) == 4), "reg_wr_hbw_awcache size is not 32-bit"); +/* + WR_HBW_INFLIGHTS + b'AXI INFLIGHT Writes COUNTER' +*/ +typedef struct reg_wr_hbw_inflights { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_wr_hbw_inflights; +static_assert((sizeof(struct reg_wr_hbw_inflights) == 4), "reg_wr_hbw_inflights size is not 32-bit"); +/* + WR_HBW_RATE_LIM_CFG + b'Write rate limiter timeout,saturation,enable' +*/ +typedef struct reg_wr_hbw_rate_lim_cfg { + union { + struct { + uint32_t tout : 8, + _reserved16 : 8, + sat : 8, + _reserved31 : 7, + en : 1; + }; + uint32_t _raw; + }; +} reg_wr_hbw_rate_lim_cfg; +static_assert((sizeof(struct reg_wr_hbw_rate_lim_cfg) == 4), "reg_wr_hbw_rate_lim_cfg size is not 32-bit"); +/* + WR_LBW_MAX_OUTSTAND + b'Max open AXI-WR transactions. val of 0 means max possible' +*/ +typedef struct reg_wr_lbw_max_outstand { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_wr_lbw_max_outstand; +static_assert((sizeof(struct reg_wr_lbw_max_outstand) == 4), "reg_wr_lbw_max_outstand size is not 32-bit"); +/* + WR_LBW_MAX_AWID + b'MAX ID value for Wr buffer for debug' +*/ +typedef struct reg_wr_lbw_max_awid { + union { + struct { + uint32_t val : 7, + _reserved7 : 25; + }; + uint32_t _raw; + }; +} reg_wr_lbw_max_awid; +static_assert((sizeof(struct reg_wr_lbw_max_awid) == 4), "reg_wr_lbw_max_awid size is not 32-bit"); +/* + WR_LBW_AWCACHE + b'AXI AWCACHE' +*/ +typedef struct reg_wr_lbw_awcache { + union { + struct { + uint32_t val : 4, + _reserved4 : 28; + }; + uint32_t _raw; + }; +} reg_wr_lbw_awcache; +static_assert((sizeof(struct reg_wr_lbw_awcache) == 4), "reg_wr_lbw_awcache size is not 32-bit"); +/* + WR_LBW_INFLIGHTS + b'AXI INFLIGHT Writes COUNTER' +*/ +typedef struct reg_wr_lbw_inflights { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_wr_lbw_inflights; +static_assert((sizeof(struct reg_wr_lbw_inflights) == 4), "reg_wr_lbw_inflights size is not 32-bit"); +/* + WR_LBW_RATE_LIM_CFG + b'Write rate limiter timeout,saturation,enable' +*/ +typedef struct reg_wr_lbw_rate_lim_cfg { + union { + struct { + uint32_t tout : 8, + _reserved16 : 8, + sat : 8, + _reserved31 : 7, + en : 1; + }; + uint32_t _raw; + }; +} reg_wr_lbw_rate_lim_cfg; +static_assert((sizeof(struct reg_wr_lbw_rate_lim_cfg) == 4), "reg_wr_lbw_rate_lim_cfg size is not 32-bit"); +/* + WR_COMP_MAX_OUTSTAND + b'MAX LBW AXI transactions' +*/ +typedef struct reg_wr_comp_max_outstand { + union { + struct { + uint32_t val : 5, + _reserved5 : 27; + }; + uint32_t _raw; + }; +} reg_wr_comp_max_outstand; +static_assert((sizeof(struct reg_wr_comp_max_outstand) == 4), "reg_wr_comp_max_outstand size is not 32-bit"); +/* + WR_COMP_AWUSER + b'AWUSER bits for completion message' +*/ +typedef struct reg_wr_comp_awuser { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_wr_comp_awuser; +static_assert((sizeof(struct reg_wr_comp_awuser) == 4), "reg_wr_comp_awuser size is not 32-bit"); +/* + ERR_CFG + b'Err msg en, stop on error' +*/ +typedef struct reg_err_cfg { + union { + struct { + uint32_t err_msg_en : 1, + stop_on_err : 1, + _reserved2 : 30; + }; + uint32_t _raw; + }; +} reg_err_cfg; +static_assert((sizeof(struct reg_err_cfg) == 4), "reg_err_cfg size is not 32-bit"); +/* + ERR_CAUSE + b'Error cause' +*/ +typedef struct reg_err_cause { + union { + struct { + uint32_t hbw_rd_err : 1, + hbw_wr_err : 1, + lbw_msg_wr_err : 1, + desc_ovf : 1, + lbw_rd_err : 1, + lbw_wr_err : 1, + te_desc_fifo_ovfl : 1, + lin_dma_commit_cfg_err : 1, + _reserved8 : 24; + }; + uint32_t _raw; + }; +} reg_err_cause; +static_assert((sizeof(struct reg_err_cause) == 4), "reg_err_cause size is not 32-bit"); +/* + ERRMSG_ADDR_LO + b'Error message address byte 3-0' +*/ +typedef struct reg_errmsg_addr_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_errmsg_addr_lo; +static_assert((sizeof(struct reg_errmsg_addr_lo) == 4), "reg_errmsg_addr_lo size is not 32-bit"); +/* + ERRMSG_ADDR_HI + b'Error message address byte 7-4' +*/ +typedef struct reg_errmsg_addr_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_errmsg_addr_hi; +static_assert((sizeof(struct reg_errmsg_addr_hi) == 4), "reg_errmsg_addr_hi size is not 32-bit"); +/* + ERRMSG_WDATA + b'Error message wdata to send' +*/ +typedef struct reg_errmsg_wdata { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_errmsg_wdata; +static_assert((sizeof(struct reg_errmsg_wdata) == 4), "reg_errmsg_wdata size is not 32-bit"); +/* + STS0 + b'BUSY and counters' +*/ +typedef struct reg_sts0 { + union { + struct { + uint32_t rd_req_cnt : 15, + _reserved16 : 1, + wr_req_cnt : 15, + busy : 1; + }; + uint32_t _raw; + }; +} reg_sts0; +static_assert((sizeof(struct reg_sts0) == 4), "reg_sts0 size is not 32-bit"); +/* + STS1 + b'IS_STOP' +*/ +typedef struct reg_sts1 { + union { + struct { + uint32_t is_halt : 1, + _reserved1 : 31; + }; + uint32_t _raw; + }; +} reg_sts1; +static_assert((sizeof(struct reg_sts1) == 4), "reg_sts1 size is not 32-bit"); +/* + STS_RD_CTX_SEL + b'Current descriptor in process. select dim size sts' +*/ +typedef struct reg_sts_rd_ctx_sel { + union { + struct { + uint32_t val : 3, + _reserved8 : 5, + stride : 1, + _reserved9 : 23; + }; + uint32_t _raw; + }; +} reg_sts_rd_ctx_sel; +static_assert((sizeof(struct reg_sts_rd_ctx_sel) == 4), "reg_sts_rd_ctx_sel size is not 32-bit"); +/* + STS_RD_CTX_SIZE + b'Current desc. in process. dim size selected by sel' +*/ +typedef struct reg_sts_rd_ctx_size { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_sts_rd_ctx_size; +static_assert((sizeof(struct reg_sts_rd_ctx_size) == 4), "reg_sts_rd_ctx_size size is not 32-bit"); +/* + STS_RD_CTX_BASE_LO + b'Current descriptor in process. base address 31:0' +*/ +typedef struct reg_sts_rd_ctx_base_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_sts_rd_ctx_base_lo; +static_assert((sizeof(struct reg_sts_rd_ctx_base_lo) == 4), "reg_sts_rd_ctx_base_lo size is not 32-bit"); +/* + STS_RD_CTX_BASE_HI + b'Current descriptor in process. base address 63:0' +*/ +typedef struct reg_sts_rd_ctx_base_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_sts_rd_ctx_base_hi; +static_assert((sizeof(struct reg_sts_rd_ctx_base_hi) == 4), "reg_sts_rd_ctx_base_hi size is not 32-bit"); +/* + STS_RD_CTX_ID + b'Current descriptor in process. Context ID' +*/ +typedef struct reg_sts_rd_ctx_id { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_sts_rd_ctx_id; +static_assert((sizeof(struct reg_sts_rd_ctx_id) == 4), "reg_sts_rd_ctx_id size is not 32-bit"); +/* + STS_RD_HB_AXI_ADDR_LO + b'Current AXI address 31:0' +*/ +typedef struct reg_sts_rd_hb_axi_addr_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_sts_rd_hb_axi_addr_lo; +static_assert((sizeof(struct reg_sts_rd_hb_axi_addr_lo) == 4), "reg_sts_rd_hb_axi_addr_lo size is not 32-bit"); +/* + STS_RD_HB_AXI_ADDR_HI + b'Current AXI address 49:32, valid,ready' +*/ +typedef struct reg_sts_rd_hb_axi_addr_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_sts_rd_hb_axi_addr_hi; +static_assert((sizeof(struct reg_sts_rd_hb_axi_addr_hi) == 4), "reg_sts_rd_hb_axi_addr_hi size is not 32-bit"); +/* + STS_RD_LB_AXI_ADDR + b'Current AXI address 25:0, valid,ready' +*/ +typedef struct reg_sts_rd_lb_axi_addr { + union { + struct { + uint32_t val : 26, + _reserved30 : 4, + rdy : 1, + vld : 1; + }; + uint32_t _raw; + }; +} reg_sts_rd_lb_axi_addr; +static_assert((sizeof(struct reg_sts_rd_lb_axi_addr) == 4), "reg_sts_rd_lb_axi_addr size is not 32-bit"); +/* + STS_WR_CTX_SEL + b'Current descriptor in process. select dim size sts' +*/ +typedef struct reg_sts_wr_ctx_sel { + union { + struct { + uint32_t val : 3, + _reserved8 : 5, + stride : 1, + _reserved9 : 23; + }; + uint32_t _raw; + }; +} reg_sts_wr_ctx_sel; +static_assert((sizeof(struct reg_sts_wr_ctx_sel) == 4), "reg_sts_wr_ctx_sel size is not 32-bit"); +/* + STS_WR_CTX_SIZE + b'Current desc. in process. dim size selected by sel' +*/ +typedef struct reg_sts_wr_ctx_size { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_sts_wr_ctx_size; +static_assert((sizeof(struct reg_sts_wr_ctx_size) == 4), "reg_sts_wr_ctx_size size is not 32-bit"); +/* + STS_WR_CTX_BASE_LO + b'Current descriptor in process. base address 31:0' +*/ +typedef struct reg_sts_wr_ctx_base_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_sts_wr_ctx_base_lo; +static_assert((sizeof(struct reg_sts_wr_ctx_base_lo) == 4), "reg_sts_wr_ctx_base_lo size is not 32-bit"); +/* + STS_WR_CTX_BASE_HI + b'Current descriptor in process. base address 63:0' +*/ +typedef struct reg_sts_wr_ctx_base_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_sts_wr_ctx_base_hi; +static_assert((sizeof(struct reg_sts_wr_ctx_base_hi) == 4), "reg_sts_wr_ctx_base_hi size is not 32-bit"); +/* + STS_WR_CTX_ID + b'Current descriptor in process. Context ID' +*/ +typedef struct reg_sts_wr_ctx_id { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_sts_wr_ctx_id; +static_assert((sizeof(struct reg_sts_wr_ctx_id) == 4), "reg_sts_wr_ctx_id size is not 32-bit"); +/* + STS_WR_HB_AXI_ADDR_LO + b'Current AXI address 31:0' +*/ +typedef struct reg_sts_wr_hb_axi_addr_lo { + union { + struct { + uint32_t val : 18, + _reserved30 : 12, + rdy : 1, + vld : 1; + }; + uint32_t _raw; + }; +} reg_sts_wr_hb_axi_addr_lo; +static_assert((sizeof(struct reg_sts_wr_hb_axi_addr_lo) == 4), "reg_sts_wr_hb_axi_addr_lo size is not 32-bit"); +/* + STS_WR_HB_AXI_ADDR_HI + b'Current AXI address 49:32, valid,ready' +*/ +typedef struct reg_sts_wr_hb_axi_addr_hi { + union { + struct { + uint32_t val : 18, + _reserved30 : 12, + rdy : 1, + vld : 1; + }; + uint32_t _raw; + }; +} reg_sts_wr_hb_axi_addr_hi; +static_assert((sizeof(struct reg_sts_wr_hb_axi_addr_hi) == 4), "reg_sts_wr_hb_axi_addr_hi size is not 32-bit"); +/* + STS_WR_LB_AXI_ADDR + b'Current AXI address 25:0, valid,ready' +*/ +typedef struct reg_sts_wr_lb_axi_addr { + union { + struct { + uint32_t val : 26, + _reserved30 : 4, + rdy : 1, + vld : 1; + }; + uint32_t _raw; + }; +} reg_sts_wr_lb_axi_addr; +static_assert((sizeof(struct reg_sts_wr_lb_axi_addr) == 4), "reg_sts_wr_lb_axi_addr size is not 32-bit"); +/* + PWRLP_CFG + b'power loop static config' +*/ +typedef struct reg_pwrlp_cfg { + union { + struct { + uint32_t glbl_en : 1, + _reserved4 : 3, + clr : 1, + _reserved5 : 27; + }; + uint32_t _raw; + }; +} reg_pwrlp_cfg; +static_assert((sizeof(struct reg_pwrlp_cfg) == 4), "reg_pwrlp_cfg size is not 32-bit"); +/* + PWRLP_STS + b'power loop status - fifos, counters' +*/ +typedef struct reg_pwrlp_sts { + union { + struct { + uint32_t rlvl : 7, + _reserved8 : 1, + wlvl : 7, + _reserved16 : 1, + rcnt : 7, + wcnt : 7, + rfull : 1, + wfull : 1; + }; + uint32_t _raw; + }; +} reg_pwrlp_sts; +static_assert((sizeof(struct reg_pwrlp_sts) == 4), "reg_pwrlp_sts size is not 32-bit"); +/* + DBG_DESC_CNT + b'Global cyclic read descriptor count for debug' +*/ +typedef struct reg_dbg_desc_cnt { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_dbg_desc_cnt; +static_assert((sizeof(struct reg_dbg_desc_cnt) == 4), "reg_dbg_desc_cnt size is not 32-bit"); +/* + DBG_STS + b'FIFOs status etc' +*/ +typedef struct reg_dbg_sts { + union { + struct { + uint32_t rd_ctx_full : 1, + wr_ctx_full : 1, + wr_comp_full : 1, + rd_ctx_empty : 1, + wr_ctx_empty : 1, + wr_comp_empty : 1, + te_empty : 1, + te_busy : 1, + gskt_empty : 1, + gskt_full : 1, + rd_agu_cs : 1, + wr_agu_cs : 1, + _reserved12 : 20; + }; + uint32_t _raw; + }; +} reg_dbg_sts; +static_assert((sizeof(struct reg_dbg_sts) == 4), "reg_dbg_sts size is not 32-bit"); +/* + DBG_BUF_STS + b'Buffer fullness' +*/ +typedef struct reg_dbg_buf_sts { + union { + struct { + uint32_t hbw_fullness : 12, + _reserved16 : 4, + lbw_fullness : 12, + _reserved28 : 4; + }; + uint32_t _raw; + }; +} reg_dbg_buf_sts; +static_assert((sizeof(struct reg_dbg_buf_sts) == 4), "reg_dbg_buf_sts size is not 32-bit"); +/* + DBG_RD_DESC_ID + b'Current RD descriptor ID' +*/ +typedef struct reg_dbg_rd_desc_id { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_dbg_rd_desc_id; +static_assert((sizeof(struct reg_dbg_rd_desc_id) == 4), "reg_dbg_rd_desc_id size is not 32-bit"); +/* + DBG_WR_DESC_ID + b'Current WR descriptor ID' +*/ +typedef struct reg_dbg_wr_desc_id { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_dbg_wr_desc_id; +static_assert((sizeof(struct reg_dbg_wr_desc_id) == 4), "reg_dbg_wr_desc_id size is not 32-bit"); +/* + APB_DMA_LBW_BASE + b'dma cfg base address used for apb forking' +*/ +typedef struct reg_apb_dma_lbw_base { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_apb_dma_lbw_base; +static_assert((sizeof(struct reg_apb_dma_lbw_base) == 4), "reg_apb_dma_lbw_base size is not 32-bit"); +/* + APB_MSTR_IF_LBW_BASE + b'mstr if cfg base address used for apb forking' +*/ +typedef struct reg_apb_mstr_if_lbw_base { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_apb_mstr_if_lbw_base; +static_assert((sizeof(struct reg_apb_mstr_if_lbw_base) == 4), "reg_apb_mstr_if_lbw_base size is not 32-bit"); +/* + E2E_CRED_ASYNC_CFG + b'e2e cred top async_cfg ports' +*/ +typedef struct reg_e2e_cred_async_cfg { + union { + struct { + uint32_t y_x_force : 9, + force_en : 1, + _reserved10 : 22; + }; + uint32_t _raw; + }; +} reg_e2e_cred_async_cfg; +static_assert((sizeof(struct reg_e2e_cred_async_cfg) == 4), "reg_e2e_cred_async_cfg size is not 32-bit"); +/* + DBG_APB_ENABLER + b'Force DBG APB auto clock opener to always on' +*/ +typedef struct reg_dbg_apb_enabler { + union { + struct { + uint32_t dis : 1, + _reserved1 : 31; + }; + uint32_t _raw; + }; +} reg_dbg_apb_enabler; +static_assert((sizeof(struct reg_dbg_apb_enabler) == 4), "reg_dbg_apb_enabler size is not 32-bit"); +/* + L2H_CMPR_LO + b'L2H Addr mask bit 31 to 0 to selecet HBW over LBW' +*/ +typedef struct reg_l2h_cmpr_lo { + union { + struct { + uint32_t _reserved20 : 20, +val : 12; + }; + uint32_t _raw; + }; +} reg_l2h_cmpr_lo; +static_assert((sizeof(struct reg_l2h_cmpr_lo) == 4), "reg_l2h_cmpr_lo size is not 32-bit"); +/* + L2H_CMPR_HI + b'L2H Addr mask bit 63 to 32 to selecet HBW over LBW' +*/ +typedef struct reg_l2h_cmpr_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_l2h_cmpr_hi; +static_assert((sizeof(struct reg_l2h_cmpr_hi) == 4), "reg_l2h_cmpr_hi size is not 32-bit"); +/* + L2H_MASK_LO + b'L2H Addr compare bit 31 to 0 to selecet HBW over L' +*/ +typedef struct reg_l2h_mask_lo { + union { + struct { + uint32_t _reserved20 : 20, +val : 12; + }; + uint32_t _raw; + }; +} reg_l2h_mask_lo; +static_assert((sizeof(struct reg_l2h_mask_lo) == 4), "reg_l2h_mask_lo size is not 32-bit"); +/* + L2H_MASK_HI + b'L2H Addr compare bit 63 to 32 to selecet HBW over' +*/ +typedef struct reg_l2h_mask_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_l2h_mask_hi; +static_assert((sizeof(struct reg_l2h_mask_hi) == 4), "reg_l2h_mask_hi size is not 32-bit"); +/* + IDLE_IND_MASK + b'option to mask idle indications' +*/ +typedef struct reg_idle_ind_mask { + union { + struct { + uint32_t desc : 1, + comp : 1, + instage : 1, + core : 1, + _reserved8 : 4, + desc_cnt_sts : 5, + _reserved16 : 3, + comp_cnt_sts : 5, + _reserved24 : 3, + instage_empty : 1, + core_idle_sts : 1, + _reserved26 : 6; + }; + uint32_t _raw; + }; +} reg_idle_ind_mask; +static_assert((sizeof(struct reg_idle_ind_mask) == 4), "reg_idle_ind_mask size is not 32-bit"); +/* + APB_ENABLER + b'Force APB auto clock opener to always on' +*/ +typedef struct reg_apb_enabler { + union { + struct { + uint32_t dis : 1, + _reserved1 : 31; + }; + uint32_t _raw; + }; +} reg_apb_enabler; +static_assert((sizeof(struct reg_apb_enabler) == 4), "reg_apb_enabler size is not 32-bit"); + +#ifdef __cplusplus +} /* dma_core namespace */ +#endif + +/* + DMA_CORE block +*/ + +#ifdef __cplusplus + +struct block_dma_core { + struct dma_core::reg_cfg_0 cfg_0; + struct dma_core::reg_cfg_1 cfg_1; + struct dma_core::reg_prot prot; + struct dma_core::reg_ckg ckg; + uint32_t _pad16[27]; + struct dma_core::reg_rd_glbl rd_glbl; + struct dma_core::reg_rd_hbw_max_outstand rd_hbw_max_outstand; + struct dma_core::reg_rd_hbw_max_size rd_hbw_max_size; + struct dma_core::reg_rd_hbw_arcache rd_hbw_arcache; + uint32_t _pad140[1]; + struct dma_core::reg_rd_hbw_inflights rd_hbw_inflights; + struct dma_core::reg_rd_hbw_rate_lim_cfg rd_hbw_rate_lim_cfg; + uint32_t _pad152[10]; + struct dma_core::reg_rd_lbw_max_outstand rd_lbw_max_outstand; + struct dma_core::reg_rd_lbw_max_size rd_lbw_max_size; + struct dma_core::reg_rd_lbw_arcache rd_lbw_arcache; + uint32_t _pad204[1]; + struct dma_core::reg_rd_lbw_inflights rd_lbw_inflights; + struct dma_core::reg_rd_lbw_rate_lim_cfg rd_lbw_rate_lim_cfg; + uint32_t _pad216[10]; + struct dma_core::reg_wr_hbw_max_outstand wr_hbw_max_outstand; + struct dma_core::reg_wr_hbw_max_awid wr_hbw_max_awid; + struct dma_core::reg_wr_hbw_awcache wr_hbw_awcache; + struct dma_core::reg_wr_hbw_inflights wr_hbw_inflights; + struct dma_core::reg_wr_hbw_rate_lim_cfg wr_hbw_rate_lim_cfg; + uint32_t _pad276[11]; + struct dma_core::reg_wr_lbw_max_outstand wr_lbw_max_outstand; + struct dma_core::reg_wr_lbw_max_awid wr_lbw_max_awid; + struct dma_core::reg_wr_lbw_awcache wr_lbw_awcache; + struct dma_core::reg_wr_lbw_inflights wr_lbw_inflights; + struct dma_core::reg_wr_lbw_rate_lim_cfg wr_lbw_rate_lim_cfg; + uint32_t _pad340[11]; + struct dma_core::reg_wr_comp_max_outstand wr_comp_max_outstand; + struct dma_core::reg_wr_comp_awuser wr_comp_awuser; + uint32_t _pad392[94]; + struct dma_core::reg_err_cfg err_cfg; + struct dma_core::reg_err_cause err_cause; + struct dma_core::reg_errmsg_addr_lo errmsg_addr_lo; + struct dma_core::reg_errmsg_addr_hi errmsg_addr_hi; + struct dma_core::reg_errmsg_wdata errmsg_wdata; + uint32_t _pad788[27]; + struct dma_core::reg_sts0 sts0; + struct dma_core::reg_sts1 sts1; + uint32_t _pad904[30]; + struct dma_core::reg_sts_rd_ctx_sel sts_rd_ctx_sel; + struct dma_core::reg_sts_rd_ctx_size sts_rd_ctx_size; + struct dma_core::reg_sts_rd_ctx_base_lo sts_rd_ctx_base_lo; + struct dma_core::reg_sts_rd_ctx_base_hi sts_rd_ctx_base_hi; + struct dma_core::reg_sts_rd_ctx_id sts_rd_ctx_id; + struct dma_core::reg_sts_rd_hb_axi_addr_lo sts_rd_hb_axi_addr_lo; + struct dma_core::reg_sts_rd_hb_axi_addr_hi sts_rd_hb_axi_addr_hi; + struct dma_core::reg_sts_rd_lb_axi_addr sts_rd_lb_axi_addr; + struct dma_core::reg_sts_wr_ctx_sel sts_wr_ctx_sel; + struct dma_core::reg_sts_wr_ctx_size sts_wr_ctx_size; + struct dma_core::reg_sts_wr_ctx_base_lo sts_wr_ctx_base_lo; + struct dma_core::reg_sts_wr_ctx_base_hi sts_wr_ctx_base_hi; + struct dma_core::reg_sts_wr_ctx_id sts_wr_ctx_id; + struct dma_core::reg_sts_wr_hb_axi_addr_lo sts_wr_hb_axi_addr_lo; + struct dma_core::reg_sts_wr_hb_axi_addr_hi sts_wr_hb_axi_addr_hi; + struct dma_core::reg_sts_wr_lb_axi_addr sts_wr_lb_axi_addr; + uint32_t _pad1088[176]; + struct dma_core::reg_pwrlp_cfg pwrlp_cfg; + struct dma_core::reg_pwrlp_sts pwrlp_sts; + uint32_t _pad1800[2]; + struct dma_core::reg_dbg_desc_cnt dbg_desc_cnt; + struct dma_core::reg_dbg_sts dbg_sts; + struct dma_core::reg_dbg_buf_sts dbg_buf_sts; + uint32_t _pad1820[1]; + struct dma_core::reg_dbg_rd_desc_id dbg_rd_desc_id; + struct dma_core::reg_dbg_wr_desc_id dbg_wr_desc_id; + struct dma_core::reg_apb_dma_lbw_base apb_dma_lbw_base; + struct dma_core::reg_apb_mstr_if_lbw_base apb_mstr_if_lbw_base; + struct dma_core::reg_e2e_cred_async_cfg e2e_cred_async_cfg; + uint32_t _pad1844[51]; + struct block_axuser ctx_axuser; + uint32_t _pad2128[4]; + struct block_dma_core_ctx ctx; + uint32_t _pad2288[324]; + struct block_qman_cgm kdma_cgm; + uint32_t _pad3596[4]; + struct dma_core::reg_dbg_apb_enabler dbg_apb_enabler; + struct dma_core::reg_l2h_cmpr_lo l2h_cmpr_lo; + struct dma_core::reg_l2h_cmpr_hi l2h_cmpr_hi; + struct dma_core::reg_l2h_mask_lo l2h_mask_lo; + struct dma_core::reg_l2h_mask_hi l2h_mask_hi; + struct dma_core::reg_idle_ind_mask idle_ind_mask; + struct dma_core::reg_apb_enabler apb_enabler; + uint32_t _pad3640[18]; + struct block_special_regs special; +}; +#else + +typedef struct block_dma_core { + reg_cfg_0 cfg_0; + reg_cfg_1 cfg_1; + reg_prot prot; + reg_ckg ckg; + uint32_t _pad16[27]; + reg_rd_glbl rd_glbl; + reg_rd_hbw_max_outstand rd_hbw_max_outstand; + reg_rd_hbw_max_size rd_hbw_max_size; + reg_rd_hbw_arcache rd_hbw_arcache; + uint32_t _pad140[1]; + reg_rd_hbw_inflights rd_hbw_inflights; + reg_rd_hbw_rate_lim_cfg rd_hbw_rate_lim_cfg; + uint32_t _pad152[10]; + reg_rd_lbw_max_outstand rd_lbw_max_outstand; + reg_rd_lbw_max_size rd_lbw_max_size; + reg_rd_lbw_arcache rd_lbw_arcache; + uint32_t _pad204[1]; + reg_rd_lbw_inflights rd_lbw_inflights; + reg_rd_lbw_rate_lim_cfg rd_lbw_rate_lim_cfg; + uint32_t _pad216[10]; + reg_wr_hbw_max_outstand wr_hbw_max_outstand; + reg_wr_hbw_max_awid wr_hbw_max_awid; + reg_wr_hbw_awcache wr_hbw_awcache; + reg_wr_hbw_inflights wr_hbw_inflights; + reg_wr_hbw_rate_lim_cfg wr_hbw_rate_lim_cfg; + uint32_t _pad276[11]; + reg_wr_lbw_max_outstand wr_lbw_max_outstand; + reg_wr_lbw_max_awid wr_lbw_max_awid; + reg_wr_lbw_awcache wr_lbw_awcache; + reg_wr_lbw_inflights wr_lbw_inflights; + reg_wr_lbw_rate_lim_cfg wr_lbw_rate_lim_cfg; + uint32_t _pad340[11]; + reg_wr_comp_max_outstand wr_comp_max_outstand; + reg_wr_comp_awuser wr_comp_awuser; + uint32_t _pad392[94]; + reg_err_cfg err_cfg; + reg_err_cause err_cause; + reg_errmsg_addr_lo errmsg_addr_lo; + reg_errmsg_addr_hi errmsg_addr_hi; + reg_errmsg_wdata errmsg_wdata; + uint32_t _pad788[27]; + reg_sts0 sts0; + reg_sts1 sts1; + uint32_t _pad904[30]; + reg_sts_rd_ctx_sel sts_rd_ctx_sel; + reg_sts_rd_ctx_size sts_rd_ctx_size; + reg_sts_rd_ctx_base_lo sts_rd_ctx_base_lo; + reg_sts_rd_ctx_base_hi sts_rd_ctx_base_hi; + reg_sts_rd_ctx_id sts_rd_ctx_id; + reg_sts_rd_hb_axi_addr_lo sts_rd_hb_axi_addr_lo; + reg_sts_rd_hb_axi_addr_hi sts_rd_hb_axi_addr_hi; + reg_sts_rd_lb_axi_addr sts_rd_lb_axi_addr; + reg_sts_wr_ctx_sel sts_wr_ctx_sel; + reg_sts_wr_ctx_size sts_wr_ctx_size; + reg_sts_wr_ctx_base_lo sts_wr_ctx_base_lo; + reg_sts_wr_ctx_base_hi sts_wr_ctx_base_hi; + reg_sts_wr_ctx_id sts_wr_ctx_id; + reg_sts_wr_hb_axi_addr_lo sts_wr_hb_axi_addr_lo; + reg_sts_wr_hb_axi_addr_hi sts_wr_hb_axi_addr_hi; + reg_sts_wr_lb_axi_addr sts_wr_lb_axi_addr; + uint32_t _pad1088[176]; + reg_pwrlp_cfg pwrlp_cfg; + reg_pwrlp_sts pwrlp_sts; + uint32_t _pad1800[2]; + reg_dbg_desc_cnt dbg_desc_cnt; + reg_dbg_sts dbg_sts; + reg_dbg_buf_sts dbg_buf_sts; + uint32_t _pad1820[1]; + reg_dbg_rd_desc_id dbg_rd_desc_id; + reg_dbg_wr_desc_id dbg_wr_desc_id; + reg_apb_dma_lbw_base apb_dma_lbw_base; + reg_apb_mstr_if_lbw_base apb_mstr_if_lbw_base; + reg_e2e_cred_async_cfg e2e_cred_async_cfg; + uint32_t _pad1844[51]; + block_axuser ctx_axuser; + uint32_t _pad2128[4]; + block_dma_core_ctx ctx; + uint32_t _pad2288[324]; + block_qman_cgm kdma_cgm; + uint32_t _pad3596[4]; + reg_dbg_apb_enabler dbg_apb_enabler; + reg_l2h_cmpr_lo l2h_cmpr_lo; + reg_l2h_cmpr_hi l2h_cmpr_hi; + reg_l2h_mask_lo l2h_mask_lo; + reg_l2h_mask_hi l2h_mask_hi; + reg_idle_ind_mask idle_ind_mask; + reg_apb_enabler apb_enabler; + uint32_t _pad3640[18]; + block_special_regs special; +} block_dma_core; +#endif + +const offsetVal block_dma_core_defaults[] = +{ + // offset // value + { 0x104 , 0x3fff , 1 }, // wr_hbw_max_awid + { 0x110 , 0x80040003 , 1 }, // wr_hbw_rate_lim_cfg + { 0x144 , 0x7f , 1 }, // wr_lbw_max_awid + { 0x180 , 0x14 , 1 }, // wr_comp_max_outstand + { 0x41c , 0x40000000 , 1 }, // sts_rd_lb_axi_addr + { 0x434 , 0x40000000 , 1 }, // sts_wr_hb_axi_addr_lo + { 0x438 , 0x40000000 , 1 }, // sts_wr_hb_axi_addr_hi + { 0x43c , 0x40000000 , 1 }, // sts_wr_lb_axi_addr + { 0x714 , 0x178 , 1 }, // dbg_sts + { 0x728 , 0xb000 , 1 }, // apb_dma_lbw_base + { 0x72c , 0xc000 , 1 }, // apb_mstr_if_lbw_base + { 0x804 , 0x11 , 1 }, // hb_mmu_bp + { 0x808 , 0x11 , 1 }, // hb_strong_order + { 0x820 , 0x11 , 1 }, // hb_emem_cpage + { 0x830 , 0xffffffff , 1 }, // hb_wr_ovrd_lo + { 0x834 , 0x3ff , 1 }, // hb_wr_ovrd_hi + { 0x838 , 0xffffffff , 1 }, // hb_rd_ovrd_lo + { 0x83c , 0x3ff , 1 }, // hb_rd_ovrd_hi + { 0x84c , 0xffffffff , 1 }, // lb_ovrd + { 0x860 , 0x40004 , 1 }, // rate_lim_tkn + { 0xe00 , 0x100080 , 1 }, // cfg + { 0xe04 , 0xf00 , 1 }, // sts + { 0xe08 , 0x10 , 1 }, // cfg1 + { 0xe20 , 0xfc000000 , 1 }, // l2h_cmpr_lo + { 0xe24 , 0x1000007f , 1 }, // l2h_cmpr_hi + { 0xe28 , 0xfc000000 , 1 }, // l2h_mask_lo + { 0xe2c , 0xffffffff , 1 }, // l2h_mask_hi + { 0xe30 , 0x3000000 , 1 }, // idle_ind_mask + { 0xe80 , 0xffffffff , 32 }, // glbl_priv + { 0xf24 , 0xffff , 1 }, // mem_ecc_err_addr + { 0xf44 , 0xffffffff , 1 }, // glbl_err_addr + { 0xf80 , 0xffffffff , 32 }, // glbl_sec +}; + +#ifdef __cplusplus +} /* gaudi2 namespace */ +#endif + +#pragma pack(pop) +#endif /* ASIC_REG_STRUCTS_DMA_CORE_H_ */ diff --git a/external_includes/gaudi2/asic_reg_structs/gaudi2_types.h b/external_includes/gaudi2/asic_reg_structs/gaudi2_types.h new file mode 100644 index 0000000..2eafb48 --- /dev/null +++ b/external_includes/gaudi2/asic_reg_structs/gaudi2_types.h @@ -0,0 +1,23 @@ +/*********************************** +** This is an auto-generated file ** +** DO NOT EDIT BELOW ** +************************************/ + +#ifndef ASIC_REG_STRUCTS_GAUDI2_TYPES_H_ +#define ASIC_REG_STRUCTS_GAUDI2_TYPES_H_ + +#include + +#pragma pack(push, 1) +namespace gaudi2 +{ +typedef struct offsetVal +{ + uint32_t offset; + uint32_t val; + int copies; +}offsetVal; + +} //namespace gaudi2 +#pragma pack(pop) +#endif /* ASIC_REG_STRUCTS_GAUDI2_TYPES_H_ */ diff --git a/external_includes/gaudi2/asic_reg_structs/ic_lbw_dbg_cnt_regs.h b/external_includes/gaudi2/asic_reg_structs/ic_lbw_dbg_cnt_regs.h new file mode 100644 index 0000000..05ea386 --- /dev/null +++ b/external_includes/gaudi2/asic_reg_structs/ic_lbw_dbg_cnt_regs.h @@ -0,0 +1,402 @@ +/*********************************** +** This is an auto-generated file ** +** DO NOT EDIT BELOW ** +************************************/ + +#ifndef ASIC_REG_STRUCTS_IC_LBW_DBG_CNT_H_ +#define ASIC_REG_STRUCTS_IC_LBW_DBG_CNT_H_ + +#include +#include "gaudi2_types.h" + +#pragma pack(push, 1) + +#ifdef __cplusplus +namespace gaudi2 { +namespace ic_lbw_dbg_cnt { +#else +# ifndef static_assert +# if defined( __STDC__ ) && defined( __STDC_VERSION__ ) && __STDC_VERSION__ >= 201112L +# define static_assert(...) _Static_assert(__VA_ARGS__) +# else +# define static_assert(...) +# endif +# endif +#endif + +/* + BP_AW_CNT + b'WR req address phase (AW) backpressure counter' +*/ +typedef struct reg_bp_aw_cnt { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_bp_aw_cnt; +static_assert((sizeof(struct reg_bp_aw_cnt) == 4), "reg_bp_aw_cnt size is not 32-bit"); +/* + BP_W_CNT + b'WR req data phase (W) backpressure counter' +*/ +typedef struct reg_bp_w_cnt { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_bp_w_cnt; +static_assert((sizeof(struct reg_bp_w_cnt) == 4), "reg_bp_w_cnt size is not 32-bit"); +/* + BP_AR_CNT + b'RD req address phase (AR) backpressure counter' +*/ +typedef struct reg_bp_ar_cnt { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_bp_ar_cnt; +static_assert((sizeof(struct reg_bp_ar_cnt) == 4), "reg_bp_ar_cnt size is not 32-bit"); +/* + BP_B_CNT + b'WR rsp (B) backpressure counter' +*/ +typedef struct reg_bp_b_cnt { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_bp_b_cnt; +static_assert((sizeof(struct reg_bp_b_cnt) == 4), "reg_bp_b_cnt size is not 32-bit"); +/* + BP_R_CNT + b'RD rsp (B) backpressure counter' +*/ +typedef struct reg_bp_r_cnt { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_bp_r_cnt; +static_assert((sizeof(struct reg_bp_r_cnt) == 4), "reg_bp_r_cnt size is not 32-bit"); +/* + TRAN_AW_CNT + b'Count outgoing AXI write transactions' +*/ +typedef struct reg_tran_aw_cnt { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_tran_aw_cnt; +static_assert((sizeof(struct reg_tran_aw_cnt) == 4), "reg_tran_aw_cnt size is not 32-bit"); +/* + TRAN_W_CNT + b'Count outgoing AXI write transactions (only LAST)' +*/ +typedef struct reg_tran_w_cnt { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_tran_w_cnt; +static_assert((sizeof(struct reg_tran_w_cnt) == 4), "reg_tran_w_cnt size is not 32-bit"); +/* + TRAN_AR_CNT + b'Count outgoing AXI read transactions' +*/ +typedef struct reg_tran_ar_cnt { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_tran_ar_cnt; +static_assert((sizeof(struct reg_tran_ar_cnt) == 4), "reg_tran_ar_cnt size is not 32-bit"); +/* + TRAN_B_CNT + b'Count incoming AXI write completions' +*/ +typedef struct reg_tran_b_cnt { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_tran_b_cnt; +static_assert((sizeof(struct reg_tran_b_cnt) == 4), "reg_tran_b_cnt size is not 32-bit"); +/* + TRAN_R_CNT + b'Count incoming AXI read completions' +*/ +typedef struct reg_tran_r_cnt { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_tran_r_cnt; +static_assert((sizeof(struct reg_tran_r_cnt) == 4), "reg_tran_r_cnt size is not 32-bit"); +/* + OTF_WR_TOTAL_CNT + b'Outstanding write request counter' +*/ +typedef struct reg_otf_wr_total_cnt { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_otf_wr_total_cnt; +static_assert((sizeof(struct reg_otf_wr_total_cnt) == 4), "reg_otf_wr_total_cnt size is not 32-bit"); +/* + OTF_RD_TOTAL_CNT + b'Outstanding read request counter' +*/ +typedef struct reg_otf_rd_total_cnt { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_otf_rd_total_cnt; +static_assert((sizeof(struct reg_otf_rd_total_cnt) == 4), "reg_otf_rd_total_cnt size is not 32-bit"); +/* + OTF_OVER_TH_WR_TOTAL_REQ_CNT + b'Count WR req when OTF is higher than threshold' +*/ +typedef struct reg_otf_over_th_wr_total_req_cnt { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_otf_over_th_wr_total_req_cnt; +static_assert((sizeof(struct reg_otf_over_th_wr_total_req_cnt) == 4), "reg_otf_over_th_wr_total_req_cnt size is not 32-bit"); +/* + OTF_OVER_TH_RD_TOTAL_REQ_CNT + b'Count RD req when OTF is higher than threshold' +*/ +typedef struct reg_otf_over_th_rd_total_req_cnt { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_otf_over_th_rd_total_req_cnt; +static_assert((sizeof(struct reg_otf_over_th_rd_total_req_cnt) == 4), "reg_otf_over_th_rd_total_req_cnt size is not 32-bit"); +/* + OTF_OVER_TH_WR_TOTAL_CYC_CNT + b'Count cycles when OTF is higher than threshold' +*/ +typedef struct reg_otf_over_th_wr_total_cyc_cnt { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_otf_over_th_wr_total_cyc_cnt; +static_assert((sizeof(struct reg_otf_over_th_wr_total_cyc_cnt) == 4), "reg_otf_over_th_wr_total_cyc_cnt size is not 32-bit"); +/* + OTF_OVER_TH_RD_TOTAL_CYC_CNT + b'Count cycles when OTF is higher than threshold' +*/ +typedef struct reg_otf_over_th_rd_total_cyc_cnt { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_otf_over_th_rd_total_cyc_cnt; +static_assert((sizeof(struct reg_otf_over_th_rd_total_cyc_cnt) == 4), "reg_otf_over_th_rd_total_cyc_cnt size is not 32-bit"); +/* + OTF_OVER_TH_WR_TOTAL_REQ_TH + b'Threshold for outstanding requests counter' +*/ +typedef struct reg_otf_over_th_wr_total_req_th { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_otf_over_th_wr_total_req_th; +static_assert((sizeof(struct reg_otf_over_th_wr_total_req_th) == 4), "reg_otf_over_th_wr_total_req_th size is not 32-bit"); +/* + OTF_OVER_TH_RD_TOTAL_REQ_TH + b'Threshold for outstanding requests counter' +*/ +typedef struct reg_otf_over_th_rd_total_req_th { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_otf_over_th_rd_total_req_th; +static_assert((sizeof(struct reg_otf_over_th_rd_total_req_th) == 4), "reg_otf_over_th_rd_total_req_th size is not 32-bit"); +/* + OTF_OVER_TH_WR_TOTAL_CYC_TH + b'Threshold for outstanding cycles counter' +*/ +typedef struct reg_otf_over_th_wr_total_cyc_th { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_otf_over_th_wr_total_cyc_th; +static_assert((sizeof(struct reg_otf_over_th_wr_total_cyc_th) == 4), "reg_otf_over_th_wr_total_cyc_th size is not 32-bit"); +/* + OTF_OVER_TH_RD_TOTAL_CYC_TH + b'Threshold for outstanding cycles counter' +*/ +typedef struct reg_otf_over_th_rd_total_cyc_th { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_otf_over_th_rd_total_cyc_th; +static_assert((sizeof(struct reg_otf_over_th_rd_total_cyc_th) == 4), "reg_otf_over_th_rd_total_cyc_th size is not 32-bit"); +/* + OTF_CNT_DEST_SEL + b'Select which destination to present on OTF counter' +*/ +typedef struct reg_otf_cnt_dest_sel { + union { + struct { + uint32_t val : 3, + _reserved3 : 29; + }; + uint32_t _raw; + }; +} reg_otf_cnt_dest_sel; +static_assert((sizeof(struct reg_otf_cnt_dest_sel) == 4), "reg_otf_cnt_dest_sel size is not 32-bit"); +/* + DBG_EN + b'Enable debug counters' +*/ +typedef struct reg_dbg_en { + union { + struct { + uint32_t val : 1, + _reserved1 : 31; + }; + uint32_t _raw; + }; +} reg_dbg_en; +static_assert((sizeof(struct reg_dbg_en) == 4), "reg_dbg_en size is not 32-bit"); + +#ifdef __cplusplus +} /* ic_lbw_dbg_cnt namespace */ +#endif + +/* + IC_LBW_DBG_CNT block +*/ + +#ifdef __cplusplus + +struct block_ic_lbw_dbg_cnt { + struct ic_lbw_dbg_cnt::reg_bp_aw_cnt bp_aw_cnt; + struct ic_lbw_dbg_cnt::reg_bp_w_cnt bp_w_cnt; + struct ic_lbw_dbg_cnt::reg_bp_ar_cnt bp_ar_cnt; + struct ic_lbw_dbg_cnt::reg_bp_b_cnt bp_b_cnt; + struct ic_lbw_dbg_cnt::reg_bp_r_cnt bp_r_cnt; + struct ic_lbw_dbg_cnt::reg_tran_aw_cnt tran_aw_cnt; + struct ic_lbw_dbg_cnt::reg_tran_w_cnt tran_w_cnt; + struct ic_lbw_dbg_cnt::reg_tran_ar_cnt tran_ar_cnt; + struct ic_lbw_dbg_cnt::reg_tran_b_cnt tran_b_cnt; + struct ic_lbw_dbg_cnt::reg_tran_r_cnt tran_r_cnt; + struct ic_lbw_dbg_cnt::reg_otf_wr_total_cnt otf_wr_total_cnt; + struct ic_lbw_dbg_cnt::reg_otf_rd_total_cnt otf_rd_total_cnt; + struct ic_lbw_dbg_cnt::reg_otf_over_th_wr_total_req_cnt otf_over_th_wr_total_req_cnt; + struct ic_lbw_dbg_cnt::reg_otf_over_th_rd_total_req_cnt otf_over_th_rd_total_req_cnt; + struct ic_lbw_dbg_cnt::reg_otf_over_th_wr_total_cyc_cnt otf_over_th_wr_total_cyc_cnt; + struct ic_lbw_dbg_cnt::reg_otf_over_th_rd_total_cyc_cnt otf_over_th_rd_total_cyc_cnt; + struct ic_lbw_dbg_cnt::reg_otf_over_th_wr_total_req_th otf_over_th_wr_total_req_th; + struct ic_lbw_dbg_cnt::reg_otf_over_th_rd_total_req_th otf_over_th_rd_total_req_th; + struct ic_lbw_dbg_cnt::reg_otf_over_th_wr_total_cyc_th otf_over_th_wr_total_cyc_th; + struct ic_lbw_dbg_cnt::reg_otf_over_th_rd_total_cyc_th otf_over_th_rd_total_cyc_th; + struct ic_lbw_dbg_cnt::reg_otf_cnt_dest_sel otf_cnt_dest_sel; + struct ic_lbw_dbg_cnt::reg_dbg_en dbg_en; +}; +#else + +typedef struct block_ic_lbw_dbg_cnt { + reg_bp_aw_cnt bp_aw_cnt; + reg_bp_w_cnt bp_w_cnt; + reg_bp_ar_cnt bp_ar_cnt; + reg_bp_b_cnt bp_b_cnt; + reg_bp_r_cnt bp_r_cnt; + reg_tran_aw_cnt tran_aw_cnt; + reg_tran_w_cnt tran_w_cnt; + reg_tran_ar_cnt tran_ar_cnt; + reg_tran_b_cnt tran_b_cnt; + reg_tran_r_cnt tran_r_cnt; + reg_otf_wr_total_cnt otf_wr_total_cnt; + reg_otf_rd_total_cnt otf_rd_total_cnt; + reg_otf_over_th_wr_total_req_cnt otf_over_th_wr_total_req_cnt; + reg_otf_over_th_rd_total_req_cnt otf_over_th_rd_total_req_cnt; + reg_otf_over_th_wr_total_cyc_cnt otf_over_th_wr_total_cyc_cnt; + reg_otf_over_th_rd_total_cyc_cnt otf_over_th_rd_total_cyc_cnt; + reg_otf_over_th_wr_total_req_th otf_over_th_wr_total_req_th; + reg_otf_over_th_rd_total_req_th otf_over_th_rd_total_req_th; + reg_otf_over_th_wr_total_cyc_th otf_over_th_wr_total_cyc_th; + reg_otf_over_th_rd_total_cyc_th otf_over_th_rd_total_cyc_th; + reg_otf_cnt_dest_sel otf_cnt_dest_sel; + reg_dbg_en dbg_en; +} block_ic_lbw_dbg_cnt; +#endif + +const offsetVal block_ic_lbw_dbg_cnt_defaults[] = +{ + // offset // value + { 0x40 , 0x100 , 1 }, // otf_over_th_wr_total_req_th + { 0x44 , 0x100 , 1 }, // otf_over_th_rd_total_req_th + { 0x48 , 0x100 , 1 }, // otf_over_th_wr_total_cyc_th + { 0x4c , 0x100 , 1 }, // otf_over_th_rd_total_cyc_th +}; + +#ifdef __cplusplus +} /* gaudi2 namespace */ +#endif + +#pragma pack(pop) +#endif /* ASIC_REG_STRUCTS_IC_LBW_DBG_CNT_H_ */ diff --git a/external_includes/gaudi2/asic_reg_structs/qman_cgm_regs.h b/external_includes/gaudi2/asic_reg_structs/qman_cgm_regs.h new file mode 100644 index 0000000..a12d290 --- /dev/null +++ b/external_includes/gaudi2/asic_reg_structs/qman_cgm_regs.h @@ -0,0 +1,119 @@ +/*********************************** +** This is an auto-generated file ** +** DO NOT EDIT BELOW ** +************************************/ + +#ifndef ASIC_REG_STRUCTS_QMAN_CGM_H_ +#define ASIC_REG_STRUCTS_QMAN_CGM_H_ + +#include +#include "gaudi2_types.h" + +#pragma pack(push, 1) + +#ifdef __cplusplus +namespace gaudi2 { +namespace qman_cgm { +#else +# ifndef static_assert +# if defined( __STDC__ ) && defined( __STDC_VERSION__ ) && __STDC_VERSION__ >= 201112L +# define static_assert(...) _Static_assert(__VA_ARGS__) +# else +# define static_assert(...) +# endif +# endif +#endif + +/* + CFG + b'Clock gate Manager config' +*/ +typedef struct reg_cfg { + union { + struct { + uint32_t idle_th : 12, + _reserved16 : 4, + g2f_th : 8, + cp_idle_mask : 5, + hbw_wr_idle_mask : 1, + _reserved31 : 1, + en : 1; + }; + uint32_t _raw; + }; +} reg_cfg; +static_assert((sizeof(struct reg_cfg) == 4), "reg_cfg size is not 32-bit"); +/* + STS + b'Clock Manager Status' +*/ +typedef struct reg_sts { + union { + struct { + uint32_t st : 2, + _reserved4 : 2, + cg : 1, + _reserved8 : 3, + agent_idle : 1, + axi_idle : 1, + cp_idle : 1, + axi_wr_idle : 1, + _reserved12 : 20; + }; + uint32_t _raw; + }; +} reg_sts; +static_assert((sizeof(struct reg_sts) == 4), "reg_sts size is not 32-bit"); +/* + CFG1 + b'CGM config reg 1 HBW mask Thresh' +*/ +typedef struct reg_cfg1 { + union { + struct { + uint32_t mask_th : 8, + _reserved8 : 24; + }; + uint32_t _raw; + }; +} reg_cfg1; +static_assert((sizeof(struct reg_cfg1) == 4), "reg_cfg1 size is not 32-bit"); + +#ifdef __cplusplus +} /* qman_cgm namespace */ +#endif + +/* + QMAN_CGM block +*/ + +#ifdef __cplusplus + +struct block_qman_cgm { + struct qman_cgm::reg_cfg cfg; + struct qman_cgm::reg_sts sts; + struct qman_cgm::reg_cfg1 cfg1; +}; +#else + +typedef struct block_qman_cgm { + reg_cfg cfg; + reg_sts sts; + reg_cfg1 cfg1; +} block_qman_cgm; +#endif + +const offsetVal block_qman_cgm_defaults[] = +{ + // offset // value + { 0x0 , 0x100080 , 1 }, // cfg + { 0x4 , 0xf00 , 1 }, // sts + { 0x8 , 0x10 , 1 }, // cfg1 +}; + +#ifdef __cplusplus +} /* gaudi2 namespace */ +#endif + +#pragma pack(pop) +#endif /* ASIC_REG_STRUCTS_QMAN_CGM_H_ */ diff --git a/external_includes/gaudi2/asic_reg_structs/qman_regs.h b/external_includes/gaudi2/asic_reg_structs/qman_regs.h new file mode 100644 index 0000000..860f043 --- /dev/null +++ b/external_includes/gaudi2/asic_reg_structs/qman_regs.h @@ -0,0 +1,3387 @@ +/*********************************** +** This is an auto-generated file ** +** DO NOT EDIT BELOW ** +************************************/ + +#ifndef ASIC_REG_STRUCTS_QMAN_H_ +#define ASIC_REG_STRUCTS_QMAN_H_ + +#include +#include "gaudi2_types.h" +#include "axuser_regs.h" +#include "ic_lbw_dbg_cnt_regs.h" +#include "qman_cgm_regs.h" +#include "qman_wr64_base_addr_regs.h" +#include "special_regs_regs.h" + +#pragma pack(push, 1) + +#ifdef __cplusplus +namespace gaudi2 { +namespace qman { +#else +# ifndef static_assert +# if defined( __STDC__ ) && defined( __STDC_VERSION__ ) && __STDC_VERSION__ >= 201112L +# define static_assert(...) _Static_assert(__VA_ARGS__) +# else +# define static_assert(...) +# endif +# endif +#endif + +/* + GLBL_CFG0 + b'Configuration: Enable PQ/CQF/ARC-CQF/CP' +*/ +typedef struct reg_glbl_cfg0 { + union { + struct { + uint32_t pqf_en : 4, + cqf_en : 5, + cp_en : 5, + arc_cqf_en : 1, + _reserved15 : 17; + }; + uint32_t _raw; + }; +} reg_glbl_cfg0; +static_assert((sizeof(struct reg_glbl_cfg0) == 4), "reg_glbl_cfg0 size is not 32-bit"); +/* + GLBL_CFG1 + b'Configuration: Stop/Flush PQ/CQF/CP' +*/ +typedef struct reg_glbl_cfg1 { + union { + struct { + uint32_t pqf_stop : 4, + cqf_stop : 5, + cp_stop : 5, + _reserved16 : 2, + pqf_flush : 4, + cqf_flush : 5, + cp_flush : 5, + _reserved30 : 2; + }; + uint32_t _raw; + }; +} reg_glbl_cfg1; +static_assert((sizeof(struct reg_glbl_cfg1) == 4), "reg_glbl_cfg1 size is not 32-bit"); +/* + GLBL_CFG2 + b'Configuration: HBW/LBW override (AxUSER + AxPROT)' +*/ +typedef struct reg_glbl_cfg2 { + union { + struct { + uint32_t arc_cqf_stop : 1, + arc_cqf_flush : 1, + _reserved4 : 2, + arc_hbw_awuser_ovrd : 1, + arc_hbw_aruser_ovrd : 1, + arc_lbw_awuser_ovrd : 1, + arc_lbw_aruser_ovrd : 1, + arc_hbw_awprot_ovrd : 1, + arc_hbw_arprot_ovrd : 1, + arc_lbw_awprot_ovrd : 1, + arc_lbw_arprot_ovrd : 1, + arc_hbw_awcache_ovrd : 1, + arc_hbw_arcache_ovrd : 1, + arc_lbw_awcache_ovrd : 1, + arc_lbw_arcache_ovrd : 1, + arc_lbw_buser_ovrd : 1, + _reserved17 : 15; + }; + uint32_t _raw; + }; +} reg_glbl_cfg2; +static_assert((sizeof(struct reg_glbl_cfg2) == 4), "reg_glbl_cfg2 size is not 32-bit"); +/* + GLBL_ERR_CFG + b'Err configuration: Stop on Error & Message enable' +*/ +typedef struct reg_glbl_err_cfg { + union { + struct { + uint32_t pqf_err_msg_en : 4, + cqf_err_msg_en : 5, + cp_err_msg_en : 5, + _reserved16 : 2, + pqf_stop_on_err : 4, + cqf_stop_on_err : 5, + cp_stop_on_err : 5, + _reserved31 : 1, + arb_stop_on_err : 1; + }; + uint32_t _raw; + }; +} reg_glbl_err_cfg; +static_assert((sizeof(struct reg_glbl_err_cfg) == 4), "reg_glbl_err_cfg size is not 32-bit"); +/* + GLBL_ERR_CFG1 + b'Err configuration: Stop on Error & Message enable' +*/ +typedef struct reg_glbl_err_cfg1 { + union { + struct { + uint32_t cqf_err_msg_en : 1, + cqf_stop_on_err : 1, + arc_stop_on_err : 1, + _reserved3 : 29; + }; + uint32_t _raw; + }; +} reg_glbl_err_cfg1; +static_assert((sizeof(struct reg_glbl_err_cfg1) == 4), "reg_glbl_err_cfg1 size is not 32-bit"); +/* + GLBL_ERR_ARC_HALT_EN + b'Err configuration: Halt ARC upon error' +*/ +typedef struct reg_glbl_err_arc_halt_en { + union { + struct { + uint32_t err_ind : 24, + _reserved24 : 8; + }; + uint32_t _raw; + }; +} reg_glbl_err_arc_halt_en; +static_assert((sizeof(struct reg_glbl_err_arc_halt_en) == 4), "reg_glbl_err_arc_halt_en size is not 32-bit"); +/* + GLBL_AXCACHE + b'Configuration: HBW & LBW ARCACHE/AWCACHE' +*/ +typedef struct reg_glbl_axcache { + union { + struct { + uint32_t hbw_ar : 4, + _reserved16 : 12, + hbw_aw : 4, + lbw_aw : 4, + lbw_ar : 4, + _reserved28 : 4; + }; + uint32_t _raw; + }; +} reg_glbl_axcache; +static_assert((sizeof(struct reg_glbl_axcache) == 4), "reg_glbl_axcache size is not 32-bit"); +/* + GLBL_STS0 + b'Status: Idle & Stop' +*/ +typedef struct reg_glbl_sts0 { + union { + struct { + uint32_t pqf_idle : 4, + cqf_idle : 5, + cp_idle : 5, + _reserved16 : 2, + pqf_is_stop : 4, + cqf_is_stop : 5, + cp_is_stop : 5, + _reserved31 : 1, + arb_is_stop : 1; + }; + uint32_t _raw; + }; +} reg_glbl_sts0; +static_assert((sizeof(struct reg_glbl_sts0) == 4), "reg_glbl_sts0 size is not 32-bit"); +/* + GLBL_STS1 + b'Status: Idle & Stop (ARC-CQF)' +*/ +typedef struct reg_glbl_sts1 { + union { + struct { + uint32_t arc_cqf_idle : 1, + arc_cqf_is_stop : 1, + _reserved2 : 30; + }; + uint32_t _raw; + }; +} reg_glbl_sts1; +static_assert((sizeof(struct reg_glbl_sts1) == 4), "reg_glbl_sts1 size is not 32-bit"); +/* + GLBL_ERR_STS + b'Error: Error cause' +*/ +typedef struct reg_glbl_err_sts { + union { + struct { + uint32_t pqf_rd_err : 1, + cqf_rd_err : 1, + cp_rd_err : 1, + cp_undef_cmd_err : 1, + cp_stop_op : 1, + cp_msg_wr_err : 1, + cp_wreg_err : 1, + _reserved8 : 1, + cp_fence0_ovf_err : 1, + cp_fence1_ovf_err : 1, + cp_fence2_ovf_err : 1, + cp_fence3_ovf_err : 1, + cp_fence0_udf_err : 1, + cp_fence1_udf_err : 1, + cp_fence2_udf_err : 1, + cp_fence3_udf_err : 1, + cpdma_up_ovf_err : 1, + pqc_l2h_err : 1, + rsvd_18_24 : 7, + _reserved25 : 7; + }; + uint32_t _raw; + }; +} reg_glbl_err_sts; +static_assert((sizeof(struct reg_glbl_err_sts) == 4), "reg_glbl_err_sts size is not 32-bit"); +/* + GLBL_ERR_STS_4 + b'Error: Error cause (continue ..)' +*/ +typedef struct reg_glbl_err_sts_4 { + union { + struct { + uint32_t rsvd0 : 1, + cqf_rd_err : 1, + cp_rd_err : 1, + cp_undef_cmd_err : 1, + cp_stop_op : 1, + cp_msg_wr_err : 1, + cp_wreg_err : 1, + _reserved8 : 1, + cp_fence0_ovf_err : 1, + cp_fence1_ovf_err : 1, + cp_fence2_ovf_err : 1, + cp_fence3_ovf_err : 1, + cp_fence0_udf_err : 1, + cp_fence1_udf_err : 1, + cp_fence2_udf_err : 1, + cp_fence3_udf_err : 1, + cpdma_up_ovf_err : 1, + rsvd17 : 1, + cq_wr_ififo_ci_err : 1, + cq_wr_ctl_ci_err : 1, + arc_cqf_rd_err : 1, + arc_cq_wr_ififo_ci_err : 1, + arc_cq_wr_ctl_ci_err : 1, + arc_axi_err : 1, + cp_switch_wdt_err : 1, + _reserved25 : 7; + }; + uint32_t _raw; + }; +} reg_glbl_err_sts_4; +static_assert((sizeof(struct reg_glbl_err_sts_4) == 4), "reg_glbl_err_sts_4 size is not 32-bit"); +/* + GLBL_ERR_MSG_EN + b'Error-Msg: MSG EN per indication' +*/ +typedef struct reg_glbl_err_msg_en { + union { + struct { + uint32_t pqf_rd_err : 1, + cqf_rd_err : 1, + cp_rd_err : 1, + cp_undef_cmd_err : 1, + cp_stop_op : 1, + cp_msg_wr_err : 1, + cp_wreg_err : 1, + _reserved8 : 1, + cp_fence0_ovf_err : 1, + cp_fence1_ovf_err : 1, + cp_fence2_ovf_err : 1, + cp_fence3_ovf_err : 1, + cp_fence0_udf_err : 1, + cp_fence1_udf_err : 1, + cp_fence2_udf_err : 1, + cp_fence3_udf_err : 1, + cpdma_up_ovf_err : 1, + pqc_l2h_err : 1, + rsvd_18_24 : 7, + _reserved25 : 7; + }; + uint32_t _raw; + }; +} reg_glbl_err_msg_en; +static_assert((sizeof(struct reg_glbl_err_msg_en) == 4), "reg_glbl_err_msg_en size is not 32-bit"); +/* + GLBL_ERR_MSG_EN_4 + b'Error-Msg: MSG EN per indication' +*/ +typedef struct reg_glbl_err_msg_en_4 { + union { + struct { + uint32_t rsvd0 : 1, + cqf_rd_err : 1, + cp_rd_err : 1, + cp_undef_cmd_err : 1, + cp_stop_op : 1, + cp_msg_wr_err : 1, + cp_wreg_err : 1, + _reserved8 : 1, + cp_fence0_ovf_err : 1, + cp_fence1_ovf_err : 1, + cp_fence2_ovf_err : 1, + cp_fence3_ovf_err : 1, + cp_fence0_udf_err : 1, + cp_fence1_udf_err : 1, + cp_fence2_udf_err : 1, + cp_fence3_udf_err : 1, + cpdma_up_ovf_err : 1, + rsvd17 : 1, + cq_wr_ififo_ci_err : 1, + cq_wr_ctl_ci_err : 1, + arc_cqf_rd_err : 1, + arc_cq_wr_ififo_ci_err : 1, + arc_cq_wr_ctl_ci_err : 1, + arc_axi_err : 1, + cp_switch_wdt_err : 1, + _reserved25 : 7; + }; + uint32_t _raw; + }; +} reg_glbl_err_msg_en_4; +static_assert((sizeof(struct reg_glbl_err_msg_en_4) == 4), "reg_glbl_err_msg_en_4 size is not 32-bit"); +/* + GLBL_PROT + b'Protection bit (1-Secured/0-User)' +*/ +typedef struct reg_glbl_prot { + union { + struct { + uint32_t pqf : 4, + cqf : 5, + cp : 5, + err : 1, + arb : 1, + pqc : 1, + cq_ififo_msg : 1, + arc_cq_ififo_msg : 1, + cq_ctl_msg : 1, + arc_cq_ctl_msg : 1, + cp_wr_arc : 1, + arc_cqf : 1, + arc_core : 1, + _reserved24 : 8; + }; + uint32_t _raw; + }; +} reg_glbl_prot; +static_assert((sizeof(struct reg_glbl_prot) == 4), "reg_glbl_prot size is not 32-bit"); +/* + PQ_BASE_LO + b'PQ: Base-Address (bytes 3-0)' +*/ +typedef struct reg_pq_base_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_pq_base_lo; +static_assert((sizeof(struct reg_pq_base_lo) == 4), "reg_pq_base_lo size is not 32-bit"); +/* + PQ_BASE_HI + b'PQ: Base address (bytes 7-4)' +*/ +typedef struct reg_pq_base_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_pq_base_hi; +static_assert((sizeof(struct reg_pq_base_hi) == 4), "reg_pq_base_hi size is not 32-bit"); +/* + PQ_SIZE + b'PQ: Size (LOG2) [EG:8 is 256)' +*/ +typedef struct reg_pq_size { + union { + struct { + uint32_t val : 5, + _reserved5 : 27; + }; + uint32_t _raw; + }; +} reg_pq_size; +static_assert((sizeof(struct reg_pq_size) == 4), "reg_pq_size size is not 32-bit"); +/* + PQ_PI + b'PQ: WR pointer. SW managed. raps at 2xPOW2(size)' +*/ +typedef struct reg_pq_pi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_pq_pi; +static_assert((sizeof(struct reg_pq_pi) == 4), "reg_pq_pi size is not 32-bit"); +/* + PQ_CI + b'PQ: RD pointer. HW managed. wraps at 2xPOW2(size)' +*/ +typedef struct reg_pq_ci { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_pq_ci; +static_assert((sizeof(struct reg_pq_ci) == 4), "reg_pq_ci size is not 32-bit"); +/* + PQ_CFG0 + b'PQ: Stall PQ buffer' +*/ +typedef struct reg_pq_cfg0 { + union { + struct { + uint32_t force_stall : 1, + _reserved1 : 31; + }; + uint32_t _raw; + }; +} reg_pq_cfg0; +static_assert((sizeof(struct reg_pq_cfg0) == 4), "reg_pq_cfg0 size is not 32-bit"); +/* + PQ_CFG1 + b'PQ: Buffer limit & Inflight limit' +*/ +typedef struct reg_pq_cfg1 { + union { + struct { + uint32_t credit_lim : 8, + _reserved16 : 8, + max_inflight : 8, + _reserved24 : 8; + }; + uint32_t _raw; + }; +} reg_pq_cfg1; +static_assert((sizeof(struct reg_pq_cfg1) == 4), "reg_pq_cfg1 size is not 32-bit"); +/* + PQ_STS0 + b'PQ-STS: Credit/Free/Inflight counters' +*/ +typedef struct reg_pq_sts0 { + union { + struct { + uint32_t credit_cnt : 8, + free_cnt : 8, + inflight_cnt : 8, + _reserved24 : 8; + }; + uint32_t _raw; + }; +} reg_pq_sts0; +static_assert((sizeof(struct reg_pq_sts0) == 4), "reg_pq_sts0 size is not 32-bit"); +/* + PQ_STS1 + b'PQ-STS: Bus-empty/Busy' +*/ +typedef struct reg_pq_sts1 { + union { + struct { + uint32_t buf_empty : 1, + busy : 1, + _reserved2 : 30; + }; + uint32_t _raw; + }; +} reg_pq_sts1; +static_assert((sizeof(struct reg_pq_sts1) == 4), "reg_pq_sts1 size is not 32-bit"); +/* + CQ_CFG0 + b'CQF-CFG: B2B Enable / MSG-Enable' +*/ +typedef struct reg_cq_cfg0 { + union { + struct { + uint32_t if_b2b_en : 1, + if_msg_en : 1, + ctl_msg_en : 1, + _reserved3 : 29; + }; + uint32_t _raw; + }; +} reg_cq_cfg0; +static_assert((sizeof(struct reg_cq_cfg0) == 4), "reg_cq_cfg0 size is not 32-bit"); +/* + CQ_STS0 + b'CQ-STS: Credit/Free/Inflight counters' +*/ +typedef struct reg_cq_sts0 { + union { + struct { + uint32_t credit_cnt : 8, + free_cnt : 8, + inflight_cnt : 8, + _reserved24 : 8; + }; + uint32_t _raw; + }; +} reg_cq_sts0; +static_assert((sizeof(struct reg_cq_sts0) == 4), "reg_cq_sts0 size is not 32-bit"); +/* + CQ_CFG1 + b'CQ-CFG: Buffer and Inflight limit' +*/ +typedef struct reg_cq_cfg1 { + union { + struct { + uint32_t credit_lim : 8, + _reserved16 : 8, + max_inflight : 8, + _reserved24 : 8; + }; + uint32_t _raw; + }; +} reg_cq_cfg1; +static_assert((sizeof(struct reg_cq_cfg1) == 4), "reg_cq_cfg1 size is not 32-bit"); +/* + CQ_STS1 + b'CQ-STS: Bus-empty/Busy' +*/ +typedef struct reg_cq_sts1 { + union { + struct { + uint32_t buf_empty : 1, + busy : 1, + _reserved2 : 30; + }; + uint32_t _raw; + }; +} reg_cq_sts1; +static_assert((sizeof(struct reg_cq_sts1) == 4), "reg_cq_sts1 size is not 32-bit"); +/* + CQ_PTR_LO_0 + b'CQF0(Upper): Pointer (LSB)' +*/ +typedef struct reg_cq_ptr_lo_0 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_ptr_lo_0; +static_assert((sizeof(struct reg_cq_ptr_lo_0) == 4), "reg_cq_ptr_lo_0 size is not 32-bit"); +/* + CQ_PTR_HI_0 + b'CQF0(Upper): Pointer (MSB)' +*/ +typedef struct reg_cq_ptr_hi_0 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_ptr_hi_0; +static_assert((sizeof(struct reg_cq_ptr_hi_0) == 4), "reg_cq_ptr_hi_0 size is not 32-bit"); +/* + CQ_TSIZE_0 + b'CQF0(Upper): Size in bytes' +*/ +typedef struct reg_cq_tsize_0 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_tsize_0; +static_assert((sizeof(struct reg_cq_tsize_0) == 4), "reg_cq_tsize_0 size is not 32-bit"); +/* + CQ_CTL_0 + b'CQF0(Upper): Control (WR initiate CQ read)' +*/ +typedef struct reg_cq_ctl_0 { + union { + struct { + uint32_t _reserved28 : 28, +up : 4; + }; + uint32_t _raw; + }; +} reg_cq_ctl_0; +static_assert((sizeof(struct reg_cq_ctl_0) == 4), "reg_cq_ctl_0 size is not 32-bit"); +/* + CQ_PTR_LO_1 + b'CQF1(Upper): Pointer (LSB)' +*/ +typedef struct reg_cq_ptr_lo_1 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_ptr_lo_1; +static_assert((sizeof(struct reg_cq_ptr_lo_1) == 4), "reg_cq_ptr_lo_1 size is not 32-bit"); +/* + CQ_PTR_HI_1 + b'CQF1(Upper): Pointer (MSB)' +*/ +typedef struct reg_cq_ptr_hi_1 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_ptr_hi_1; +static_assert((sizeof(struct reg_cq_ptr_hi_1) == 4), "reg_cq_ptr_hi_1 size is not 32-bit"); +/* + CQ_TSIZE_1 + b'CQF1(Upper): Size in bytes' +*/ +typedef struct reg_cq_tsize_1 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_tsize_1; +static_assert((sizeof(struct reg_cq_tsize_1) == 4), "reg_cq_tsize_1 size is not 32-bit"); +/* + CQ_CTL_1 + b'CQF1(Upper): Control (WR initiate CQ read)' +*/ +typedef struct reg_cq_ctl_1 { + union { + struct { + uint32_t _reserved28 : 28, +up : 4; + }; + uint32_t _raw; + }; +} reg_cq_ctl_1; +static_assert((sizeof(struct reg_cq_ctl_1) == 4), "reg_cq_ctl_1 size is not 32-bit"); +/* + CQ_PTR_LO_2 + b'CQF2(Upper): Pointer (LSB)' +*/ +typedef struct reg_cq_ptr_lo_2 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_ptr_lo_2; +static_assert((sizeof(struct reg_cq_ptr_lo_2) == 4), "reg_cq_ptr_lo_2 size is not 32-bit"); +/* + CQ_PTR_HI_2 + b'CQF2(Upper): Pointer (MSB)' +*/ +typedef struct reg_cq_ptr_hi_2 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_ptr_hi_2; +static_assert((sizeof(struct reg_cq_ptr_hi_2) == 4), "reg_cq_ptr_hi_2 size is not 32-bit"); +/* + CQ_TSIZE_2 + b'CQF2(Upper): Size in bytes' +*/ +typedef struct reg_cq_tsize_2 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_tsize_2; +static_assert((sizeof(struct reg_cq_tsize_2) == 4), "reg_cq_tsize_2 size is not 32-bit"); +/* + CQ_CTL_2 + b'CQF2(Upper): Control (WR initiate CQ read)' +*/ +typedef struct reg_cq_ctl_2 { + union { + struct { + uint32_t _reserved28 : 28, +up : 4; + }; + uint32_t _raw; + }; +} reg_cq_ctl_2; +static_assert((sizeof(struct reg_cq_ctl_2) == 4), "reg_cq_ctl_2 size is not 32-bit"); +/* + CQ_PTR_LO_3 + b'CQF3(Upper): Pointer (LSB)' +*/ +typedef struct reg_cq_ptr_lo_3 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_ptr_lo_3; +static_assert((sizeof(struct reg_cq_ptr_lo_3) == 4), "reg_cq_ptr_lo_3 size is not 32-bit"); +/* + CQ_PTR_HI_3 + b'CQF3(Upper): Pointer (MSB)' +*/ +typedef struct reg_cq_ptr_hi_3 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_ptr_hi_3; +static_assert((sizeof(struct reg_cq_ptr_hi_3) == 4), "reg_cq_ptr_hi_3 size is not 32-bit"); +/* + CQ_TSIZE_3 + b'CQF3(Upper): Size in bytes' +*/ +typedef struct reg_cq_tsize_3 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_tsize_3; +static_assert((sizeof(struct reg_cq_tsize_3) == 4), "reg_cq_tsize_3 size is not 32-bit"); +/* + CQ_CTL_3 + b'CQF4(Lower): Control (WR initiate CQ read)' +*/ +typedef struct reg_cq_ctl_3 { + union { + struct { + uint32_t _reserved28 : 28, +up : 4; + }; + uint32_t _raw; + }; +} reg_cq_ctl_3; +static_assert((sizeof(struct reg_cq_ctl_3) == 4), "reg_cq_ctl_3 size is not 32-bit"); +/* + CQ_PTR_LO_4 + b'CQF4(Lower: Pointer (LSB)' +*/ +typedef struct reg_cq_ptr_lo_4 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_ptr_lo_4; +static_assert((sizeof(struct reg_cq_ptr_lo_4) == 4), "reg_cq_ptr_lo_4 size is not 32-bit"); +/* + CQ_PTR_HI_4 + b'CQF4(Lower): Pointer (MSB)' +*/ +typedef struct reg_cq_ptr_hi_4 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_ptr_hi_4; +static_assert((sizeof(struct reg_cq_ptr_hi_4) == 4), "reg_cq_ptr_hi_4 size is not 32-bit"); +/* + CQ_TSIZE_4 + b'CQF4(Lower): Size in bytes' +*/ +typedef struct reg_cq_tsize_4 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_tsize_4; +static_assert((sizeof(struct reg_cq_tsize_4) == 4), "reg_cq_tsize_4 size is not 32-bit"); +/* + CQ_CTL_4 + b'CQF4(Lower): Control (WR initiate CQ read)' +*/ +typedef struct reg_cq_ctl_4 { + union { + struct { + uint32_t _reserved28 : 28, +up : 4; + }; + uint32_t _raw; + }; +} reg_cq_ctl_4; +static_assert((sizeof(struct reg_cq_ctl_4) == 4), "reg_cq_ctl_4 size is not 32-bit"); +/* + CQ_TSIZE_STS + b'CQ-STS: Current transfer size in bytes' +*/ +typedef struct reg_cq_tsize_sts { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_tsize_sts; +static_assert((sizeof(struct reg_cq_tsize_sts) == 4), "reg_cq_tsize_sts size is not 32-bit"); +/* + CQ_PTR_LO_STS + b'CQ-STS: Current Transfer base address byte 3-0' +*/ +typedef struct reg_cq_ptr_lo_sts { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_ptr_lo_sts; +static_assert((sizeof(struct reg_cq_ptr_lo_sts) == 4), "reg_cq_ptr_lo_sts size is not 32-bit"); +/* + CQ_PTR_HI_STS + b'CQ-STS: Current transfer base address byte 7-4' +*/ +typedef struct reg_cq_ptr_hi_sts { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_ptr_hi_sts; +static_assert((sizeof(struct reg_cq_ptr_hi_sts) == 4), "reg_cq_ptr_hi_sts size is not 32-bit"); +/* + CQ_IFIFO_STS + b'CQ-STATUS: Input FIFO (Occupancy/Ready-Busy)' +*/ +typedef struct reg_cq_ififo_sts { + union { + struct { + uint32_t cnt : 3, + _reserved4 : 1, + rdy : 1, + _reserved8 : 3, + ctl_stall : 1, + _reserved9 : 23; + }; + uint32_t _raw; + }; +} reg_cq_ififo_sts; +static_assert((sizeof(struct reg_cq_ififo_sts) == 4), "reg_cq_ififo_sts size is not 32-bit"); +/* + CP_MSG_BASE0_ADDR_LO + b'CP: MESSAGE_BASE_ADDR_0 (LSB)' +*/ +typedef struct reg_cp_msg_base0_addr_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cp_msg_base0_addr_lo; +static_assert((sizeof(struct reg_cp_msg_base0_addr_lo) == 4), "reg_cp_msg_base0_addr_lo size is not 32-bit"); +/* + CP_MSG_BASE0_ADDR_HI + b'CP: MESSAGE_BASE_ADDR_0 (MSB)' +*/ +typedef struct reg_cp_msg_base0_addr_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cp_msg_base0_addr_hi; +static_assert((sizeof(struct reg_cp_msg_base0_addr_hi) == 4), "reg_cp_msg_base0_addr_hi size is not 32-bit"); +/* + CP_MSG_BASE1_ADDR_LO + b'CP: MESSAGE_BASE_ADDR_1 (LSB)' +*/ +typedef struct reg_cp_msg_base1_addr_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cp_msg_base1_addr_lo; +static_assert((sizeof(struct reg_cp_msg_base1_addr_lo) == 4), "reg_cp_msg_base1_addr_lo size is not 32-bit"); +/* + CP_MSG_BASE1_ADDR_HI + b'CP: MESSAGE_BASE_ADDR_1 (MSB)' +*/ +typedef struct reg_cp_msg_base1_addr_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cp_msg_base1_addr_hi; +static_assert((sizeof(struct reg_cp_msg_base1_addr_hi) == 4), "reg_cp_msg_base1_addr_hi size is not 32-bit"); +/* + CP_MSG_BASE2_ADDR_LO + b'CP: MESSAGE_BASE_ADDR_2 (LSB)' +*/ +typedef struct reg_cp_msg_base2_addr_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cp_msg_base2_addr_lo; +static_assert((sizeof(struct reg_cp_msg_base2_addr_lo) == 4), "reg_cp_msg_base2_addr_lo size is not 32-bit"); +/* + CP_MSG_BASE2_ADDR_HI + b'CP: MESSAGE_BASE_ADDR_2 (MSB)' +*/ +typedef struct reg_cp_msg_base2_addr_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cp_msg_base2_addr_hi; +static_assert((sizeof(struct reg_cp_msg_base2_addr_hi) == 4), "reg_cp_msg_base2_addr_hi size is not 32-bit"); +/* + CP_MSG_BASE3_ADDR_LO + b'CP: MESSAGE_BASE_ADDR_3 (LSB)' +*/ +typedef struct reg_cp_msg_base3_addr_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cp_msg_base3_addr_lo; +static_assert((sizeof(struct reg_cp_msg_base3_addr_lo) == 4), "reg_cp_msg_base3_addr_lo size is not 32-bit"); +/* + CP_MSG_BASE3_ADDR_HI + b'CP: MESSAGE_BASE_ADDR_3 (MSB)' +*/ +typedef struct reg_cp_msg_base3_addr_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cp_msg_base3_addr_hi; +static_assert((sizeof(struct reg_cp_msg_base3_addr_hi) == 4), "reg_cp_msg_base3_addr_hi size is not 32-bit"); +/* + CP_FENCE0_RDATA + b'CP-FENCE-0: Increment value for fence 0' +*/ +typedef struct reg_cp_fence0_rdata { + union { + struct { + uint32_t inc_val : 4, + _reserved4 : 28; + }; + uint32_t _raw; + }; +} reg_cp_fence0_rdata; +static_assert((sizeof(struct reg_cp_fence0_rdata) == 4), "reg_cp_fence0_rdata size is not 32-bit"); +/* + CP_FENCE1_RDATA + b'CP-FENCE-1: Increment value for fence 1' +*/ +typedef struct reg_cp_fence1_rdata { + union { + struct { + uint32_t inc_val : 4, + _reserved4 : 28; + }; + uint32_t _raw; + }; +} reg_cp_fence1_rdata; +static_assert((sizeof(struct reg_cp_fence1_rdata) == 4), "reg_cp_fence1_rdata size is not 32-bit"); +/* + CP_FENCE2_RDATA + b'CP-FENCE-2:Increment value for fence 2' +*/ +typedef struct reg_cp_fence2_rdata { + union { + struct { + uint32_t inc_val : 4, + _reserved4 : 28; + }; + uint32_t _raw; + }; +} reg_cp_fence2_rdata; +static_assert((sizeof(struct reg_cp_fence2_rdata) == 4), "reg_cp_fence2_rdata size is not 32-bit"); +/* + CP_FENCE3_RDATA + b'CP-FENCE-3:Increment value for fence 3' +*/ +typedef struct reg_cp_fence3_rdata { + union { + struct { + uint32_t inc_val : 4, + _reserved4 : 28; + }; + uint32_t _raw; + }; +} reg_cp_fence3_rdata; +static_assert((sizeof(struct reg_cp_fence3_rdata) == 4), "reg_cp_fence3_rdata size is not 32-bit"); +/* + CP_FENCE0_CNT + b'CP-FENCE-0: Fence 0 (Value)' +*/ +typedef struct reg_cp_fence0_cnt { + union { + struct { + uint32_t val : 14, + _reserved14 : 18; + }; + uint32_t _raw; + }; +} reg_cp_fence0_cnt; +static_assert((sizeof(struct reg_cp_fence0_cnt) == 4), "reg_cp_fence0_cnt size is not 32-bit"); +/* + CP_FENCE1_CNT + b'CP-FENCE-1: Fence 1 (Value)' +*/ +typedef struct reg_cp_fence1_cnt { + union { + struct { + uint32_t val : 14, + _reserved14 : 18; + }; + uint32_t _raw; + }; +} reg_cp_fence1_cnt; +static_assert((sizeof(struct reg_cp_fence1_cnt) == 4), "reg_cp_fence1_cnt size is not 32-bit"); +/* + CP_FENCE2_CNT + b'CP-FENCE-2: Fence 2 (Value)' +*/ +typedef struct reg_cp_fence2_cnt { + union { + struct { + uint32_t val : 14, + _reserved14 : 18; + }; + uint32_t _raw; + }; +} reg_cp_fence2_cnt; +static_assert((sizeof(struct reg_cp_fence2_cnt) == 4), "reg_cp_fence2_cnt size is not 32-bit"); +/* + CP_FENCE3_CNT + b'CP-FENCE-3: Fence 3 (Value)' +*/ +typedef struct reg_cp_fence3_cnt { + union { + struct { + uint32_t val : 14, + _reserved14 : 18; + }; + uint32_t _raw; + }; +} reg_cp_fence3_cnt; +static_assert((sizeof(struct reg_cp_fence3_cnt) == 4), "reg_cp_fence3_cnt size is not 32-bit"); +/* + CP_BARRIER_CFG + b'CP: Guard band (Allow engine to de-assert idle)' +*/ +typedef struct reg_cp_barrier_cfg { + union { + struct { + uint32_t ebguard : 12, + _reserved16 : 4, + rbguard : 4, + _reserved20 : 12; + }; + uint32_t _raw; + }; +} reg_cp_barrier_cfg; +static_assert((sizeof(struct reg_cp_barrier_cfg) == 4), "reg_cp_barrier_cfg size is not 32-bit"); +/* + CP_LDMA_SRC_BASE_LO_OFFSET + b'CP:LDMA: SRC_BASE_LO OFFSET (relative to DMA QMAN)' +*/ +typedef struct reg_cp_ldma_src_base_lo_offset { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_cp_ldma_src_base_lo_offset; +static_assert((sizeof(struct reg_cp_ldma_src_base_lo_offset) == 4), "reg_cp_ldma_src_base_lo_offset size is not 32-bit"); +/* + CP_LDMA_DST_BASE_LO_OFFSET + b'CP:LDMA: DST_BASE_LO OFFSET (relative to DMA QMAN)' +*/ +typedef struct reg_cp_ldma_dst_base_lo_offset { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_cp_ldma_dst_base_lo_offset; +static_assert((sizeof(struct reg_cp_ldma_dst_base_lo_offset) == 4), "reg_cp_ldma_dst_base_lo_offset size is not 32-bit"); +/* + CP_LDMA_TSIZE_OFFSET + b'CP:LDMA. DST_TSIZE_0 OFFSET (relative to DMA QMAN)' +*/ +typedef struct reg_cp_ldma_tsize_offset { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_cp_ldma_tsize_offset; +static_assert((sizeof(struct reg_cp_ldma_tsize_offset) == 4), "reg_cp_ldma_tsize_offset size is not 32-bit"); +/* + CP_CQ_PTR_LO_OFFSET_0 + b'CP: CPDMA CQ_PTR_LO_0 OFFSET(relative to QMAN)' +*/ +typedef struct reg_cp_cq_ptr_lo_offset_0 { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_cp_cq_ptr_lo_offset_0; +static_assert((sizeof(struct reg_cp_cq_ptr_lo_offset_0) == 4), "reg_cp_cq_ptr_lo_offset_0 size is not 32-bit"); +/* + CP_CQ_PTR_LO_OFFSET_1 + b'CP: CPDMA CQ_PTR_LO_1 OFFSET(relative to QMAN)' +*/ +typedef struct reg_cp_cq_ptr_lo_offset_1 { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_cp_cq_ptr_lo_offset_1; +static_assert((sizeof(struct reg_cp_cq_ptr_lo_offset_1) == 4), "reg_cp_cq_ptr_lo_offset_1 size is not 32-bit"); +/* + CP_CQ_PTR_LO_OFFSET_2 + b'CP: CPDMA CQ_PTR_LO_2 OFFSET(relative to QMAN)' +*/ +typedef struct reg_cp_cq_ptr_lo_offset_2 { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_cp_cq_ptr_lo_offset_2; +static_assert((sizeof(struct reg_cp_cq_ptr_lo_offset_2) == 4), "reg_cp_cq_ptr_lo_offset_2 size is not 32-bit"); +/* + CP_CQ_PTR_LO_OFFSET_3 + b'CP: CPDMA CQ_PTR_LO_3 OFFSET(relative to QMAN)' +*/ +typedef struct reg_cp_cq_ptr_lo_offset_3 { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_cp_cq_ptr_lo_offset_3; +static_assert((sizeof(struct reg_cp_cq_ptr_lo_offset_3) == 4), "reg_cp_cq_ptr_lo_offset_3 size is not 32-bit"); +/* + CP_CQ_PTR_LO_OFFSET_4 + b'CP: CPDMA CQ_PTR_LO_4 OFFSET (relative to QMAN)' +*/ +typedef struct reg_cp_cq_ptr_lo_offset_4 { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_cp_cq_ptr_lo_offset_4; +static_assert((sizeof(struct reg_cp_cq_ptr_lo_offset_4) == 4), "reg_cp_cq_ptr_lo_offset_4 size is not 32-bit"); +/* + CP_STS + b'CP-STS: CP Status (Switch/Fence-ID/In-flights..)' +*/ +typedef struct reg_cp_sts { + union { + struct { + uint32_t msg_inflight_cnt : 8, + erdy : 1, + switch_en : 1, + mrdy : 1, + sw_stop : 1, + fence_id : 2, + fence_in_progress : 1, + _reserved16 : 1, + fence_target : 14, + cur_cq : 1, + _reserved31 : 1; + }; + uint32_t _raw; + }; +} reg_cp_sts; +static_assert((sizeof(struct reg_cp_sts) == 4), "reg_cp_sts size is not 32-bit"); +/* + CP_CURRENT_INST_LO + b'CP: Current CP instruction (Byte 3-0)' +*/ +typedef struct reg_cp_current_inst_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cp_current_inst_lo; +static_assert((sizeof(struct reg_cp_current_inst_lo) == 4), "reg_cp_current_inst_lo size is not 32-bit"); +/* + CP_CURRENT_INST_HI + b'CP: Current CP instruction (Byte 7-4)' +*/ +typedef struct reg_cp_current_inst_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cp_current_inst_hi; +static_assert((sizeof(struct reg_cp_current_inst_hi) == 4), "reg_cp_current_inst_hi size is not 32-bit"); +/* + CP_PRED + b'CP: Predicates (Can also be updated by LOAD_N_EXE)' +*/ +typedef struct reg_cp_pred { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cp_pred; +static_assert((sizeof(struct reg_cp_pred) == 4), "reg_cp_pred size is not 32-bit"); +/* + CP_PRED_UPEN + b'CP:Bit per predicate to allow update by LOAD_N_EXE' +*/ +typedef struct reg_cp_pred_upen { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cp_pred_upen; +static_assert((sizeof(struct reg_cp_pred_upen) == 4), "reg_cp_pred_upen size is not 32-bit"); +/* + CP_DBG_0 + b'CP: CP state (Debug)' +*/ +typedef struct reg_cp_dbg_0 { + union { + struct { + uint32_t cs : 5, + eb_cnt_not_zero : 1, + bulk_cnt_not_zero : 1, + mreb_stall : 1, + stall : 1, + _reserved9 : 23; + }; + uint32_t _raw; + }; +} reg_cp_dbg_0; +static_assert((sizeof(struct reg_cp_dbg_0) == 4), "reg_cp_dbg_0 size is not 32-bit"); +/* + CP_CPDMA_UP_CRED + b'CP-DMA: Status ,threshold, inflight CPDMA count' +*/ +typedef struct reg_cp_cpdma_up_cred { + union { + struct { + uint32_t th : 2, + _reserved8 : 6, + val : 2, + _reserved10 : 22; + }; + uint32_t _raw; + }; +} reg_cp_cpdma_up_cred; +static_assert((sizeof(struct reg_cp_cpdma_up_cred) == 4), "reg_cp_cpdma_up_cred size is not 32-bit"); +/* + CP_IN_DATA_LO + b'CP: Head of CQ2CP DATA Q (instructions Q) Byte 3-0' +*/ +typedef struct reg_cp_in_data_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cp_in_data_lo; +static_assert((sizeof(struct reg_cp_in_data_lo) == 4), "reg_cp_in_data_lo size is not 32-bit"); +/* + CP_IN_DATA_HI + b'CP: Head of CQ2CP DATA Q (instructions Q) Byte 7-4' +*/ +typedef struct reg_cp_in_data_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cp_in_data_hi; +static_assert((sizeof(struct reg_cp_in_data_hi) == 4), "reg_cp_in_data_hi size is not 32-bit"); +/* + PQC_HBW_BASE_LO + b'PQ-CQ: Completion Q base address bytes 3 to 0' +*/ +typedef struct reg_pqc_hbw_base_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_pqc_hbw_base_lo; +static_assert((sizeof(struct reg_pqc_hbw_base_lo) == 4), "reg_pqc_hbw_base_lo size is not 32-bit"); +/* + PQC_HBW_BASE_HI + b'PQ-CQ: Completion Q base address bytes 7 to 4' +*/ +typedef struct reg_pqc_hbw_base_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_pqc_hbw_base_hi; +static_assert((sizeof(struct reg_pqc_hbw_base_hi) == 4), "reg_pqc_hbw_base_hi size is not 32-bit"); +/* + PQC_SIZE + b'PQ-CQ: CQ size (Log2) per PQ.4B granularity' +*/ +typedef struct reg_pqc_size { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_pqc_size; +static_assert((sizeof(struct reg_pqc_size) == 4), "reg_pqc_size size is not 32-bit"); +/* + PQC_PI + b'PQ-CQ: Val of HW MNG PQC PI. Host WR allowed' +*/ +typedef struct reg_pqc_pi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_pqc_pi; +static_assert((sizeof(struct reg_pqc_pi) == 4), "reg_pqc_pi size is not 32-bit"); +/* + PQC_LBW_WDATA + b'PQ-CQ: LBW completion data' +*/ +typedef struct reg_pqc_lbw_wdata { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_pqc_lbw_wdata; +static_assert((sizeof(struct reg_pqc_lbw_wdata) == 4), "reg_pqc_lbw_wdata size is not 32-bit"); +/* + PQC_LBW_BASE_LO + b'PQ-CQ: Completion address (LSB) .PQE offset added' +*/ +typedef struct reg_pqc_lbw_base_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_pqc_lbw_base_lo; +static_assert((sizeof(struct reg_pqc_lbw_base_lo) == 4), "reg_pqc_lbw_base_lo size is not 32-bit"); +/* + PQC_LBW_BASE_HI + b'PQ-CQ: Completion address (MSB) .PQE offset added' +*/ +typedef struct reg_pqc_lbw_base_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_pqc_lbw_base_hi; +static_assert((sizeof(struct reg_pqc_lbw_base_hi) == 4), "reg_pqc_lbw_base_hi size is not 32-bit"); +/* + PQC_CFG + b'PQ-CQ: Completion flow enable and mode' +*/ +typedef struct reg_pqc_cfg { + union { + struct { + uint32_t en : 1, + _reserved4 : 3, + direct : 1, + _reserved5 : 27; + }; + uint32_t _raw; + }; +} reg_pqc_cfg; +static_assert((sizeof(struct reg_pqc_cfg) == 4), "reg_pqc_cfg size is not 32-bit"); +/* + PQC_SECURE_PUSH_IND + b'PQ-CQ: For completion indirect mode upper CPs push' +*/ +typedef struct reg_pqc_secure_push_ind { + union { + struct { + uint32_t cp_num : 2, + _reserved2 : 30; + }; + uint32_t _raw; + }; +} reg_pqc_secure_push_ind; +static_assert((sizeof(struct reg_pqc_secure_push_ind) == 4), "reg_pqc_secure_push_ind size is not 32-bit"); +/* + ARB_MASK + b'ARB: QMAN BASE_ADDR for CSMR access' +*/ +typedef struct reg_arb_mask { + union { + struct { + uint32_t val : 4, + _reserved4 : 28; + }; + uint32_t _raw; + }; +} reg_arb_mask; +static_assert((sizeof(struct reg_arb_mask) == 4), "reg_arb_mask size is not 32-bit"); +/* + ARB_CFG_0 + b'ARB-CFG: Enable /Type (WRR/Priority) / Is-Master' +*/ +typedef struct reg_arb_cfg_0 { + union { + struct { + uint32_t prio_type : 1, + _reserved4 : 3, + is_master : 1, + _reserved8 : 3, + en : 1, + mst_msg_nostall : 1, + _reserved10 : 22; + }; + uint32_t _raw; + }; +} reg_arb_cfg_0; +static_assert((sizeof(struct reg_arb_cfg_0) == 4), "reg_arb_cfg_0 size is not 32-bit"); +/* + ARB_CHOICE_Q_PUSH + b'ARB:SLV: Push choice Q from master' +*/ +typedef struct reg_arb_choice_q_push { + union { + struct { + uint32_t val : 2, + _reserved2 : 30; + }; + uint32_t _raw; + }; +} reg_arb_choice_q_push; +static_assert((sizeof(struct reg_arb_choice_q_push) == 4), "reg_arb_choice_q_push size is not 32-bit"); +/* + ARB_WRR_WEIGHT + b'ARB: WRR Weight' +*/ +typedef struct reg_arb_wrr_weight { + union { + struct { + uint32_t val : 8, + _reserved8 : 24; + }; + uint32_t _raw; + }; +} reg_arb_wrr_weight; +static_assert((sizeof(struct reg_arb_wrr_weight) == 4), "reg_arb_wrr_weight size is not 32-bit"); +/* + ARB_CFG_1 + b'ARB-CFG: Reset choice-Q' +*/ +typedef struct reg_arb_cfg_1 { + union { + struct { + uint32_t clr : 1, + _reserved1 : 31; + }; + uint32_t _raw; + }; +} reg_arb_cfg_1; +static_assert((sizeof(struct reg_arb_cfg_1) == 4), "reg_arb_cfg_1 size is not 32-bit"); +/* + ARB_MST_AVAIL_CRED + b'ARB-MST: Limit queue credits (Master side)' +*/ +typedef struct reg_arb_mst_avail_cred { + union { + struct { + uint32_t val : 7, + _reserved7 : 25; + }; + uint32_t _raw; + }; +} reg_arb_mst_avail_cred; +static_assert((sizeof(struct reg_arb_mst_avail_cred) == 4), "reg_arb_mst_avail_cred size is not 32-bit"); +/* + ARB_MST_CRED_INC + b'ARB-MST: Credits increment (Slave->Master)' +*/ +typedef struct reg_arb_mst_cred_inc { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_arb_mst_cred_inc; +static_assert((sizeof(struct reg_arb_mst_cred_inc) == 4), "reg_arb_mst_cred_inc size is not 32-bit"); +/* + ARB_MST_CHOICE_PUSH_OFST + b'ARB-MST: Choice Queue PUSH offsets' +*/ +typedef struct reg_arb_mst_choice_push_ofst { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_arb_mst_choice_push_ofst; +static_assert((sizeof(struct reg_arb_mst_choice_push_ofst) == 4), "reg_arb_mst_choice_push_ofst size is not 32-bit"); +/* + ARB_SLV_MASTER_INC_CRED_OFST + b'ARB-SLV: Addr of slave choice-queue push' +*/ +typedef struct reg_arb_slv_master_inc_cred_ofst { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_arb_slv_master_inc_cred_ofst; +static_assert((sizeof(struct reg_arb_slv_master_inc_cred_ofst) == 4), "reg_arb_slv_master_inc_cred_ofst size is not 32-bit"); +/* + ARB_MST_SLAVE_EN + b'ARB-SLV: Enable notify on CP priority grant (31:0' +*/ +typedef struct reg_arb_mst_slave_en { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_arb_mst_slave_en; +static_assert((sizeof(struct reg_arb_mst_slave_en) == 4), "reg_arb_mst_slave_en size is not 32-bit"); +/* + ARB_MST_SLAVE_EN_1 + b'ARB-SLV: Enable notify on CP priority grant (63:32' +*/ +typedef struct reg_arb_mst_slave_en_1 { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_arb_mst_slave_en_1; +static_assert((sizeof(struct reg_arb_mst_slave_en_1) == 4), "reg_arb_mst_slave_en_1 size is not 32-bit"); +/* + ARB_SLV_CHOICE_WDT + b'ARB-SLV:Watch Dog For ChoiceQ not popped but ready' +*/ +typedef struct reg_arb_slv_choice_wdt { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_arb_slv_choice_wdt; +static_assert((sizeof(struct reg_arb_slv_choice_wdt) == 4), "reg_arb_slv_choice_wdt size is not 32-bit"); +/* + ARB_SLV_ID + b'ARB-SLV: QMAN Slave ID (For credit management)' +*/ +typedef struct reg_arb_slv_id { + union { + struct { + uint32_t val : 7, + _reserved7 : 25; + }; + uint32_t _raw; + }; +} reg_arb_slv_id; +static_assert((sizeof(struct reg_arb_slv_id) == 4), "reg_arb_slv_id size is not 32-bit"); +/* + ARB_MST_QUIET_PER + b'ARB-SLV: Quiet period before new grant' +*/ +typedef struct reg_arb_mst_quiet_per { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_arb_mst_quiet_per; +static_assert((sizeof(struct reg_arb_mst_quiet_per) == 4), "reg_arb_mst_quiet_per size is not 32-bit"); +/* + ARB_MSG_MAX_INFLIGHT + b'ARB-CFG: Limit maximum in-flights' +*/ +typedef struct reg_arb_msg_max_inflight { + union { + struct { + uint32_t val : 6, + _reserved6 : 26; + }; + uint32_t _raw; + }; +} reg_arb_msg_max_inflight; +static_assert((sizeof(struct reg_arb_msg_max_inflight) == 4), "reg_arb_msg_max_inflight size is not 32-bit"); +/* + ARB_BASE_LO + b'ARB-CFG: Base address for arb LBW access (LSB)' +*/ +typedef struct reg_arb_base_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_arb_base_lo; +static_assert((sizeof(struct reg_arb_base_lo) == 4), "reg_arb_base_lo size is not 32-bit"); +/* + ARB_BASE_HI + b'ARB-CFG: Base address for arb LBW access(MSB)' +*/ +typedef struct reg_arb_base_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_arb_base_hi; +static_assert((sizeof(struct reg_arb_base_hi) == 4), "reg_arb_base_hi size is not 32-bit"); +/* + ARB_STATE_STS + b'ARB-STS: Current granted CP' +*/ +typedef struct reg_arb_state_sts { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_arb_state_sts; +static_assert((sizeof(struct reg_arb_state_sts) == 4), "reg_arb_state_sts size is not 32-bit"); +/* + ARB_CHOICE_FULLNESS_STS + b'ARB-STS: Choice-Q full level' +*/ +typedef struct reg_arb_choice_fullness_sts { + union { + struct { + uint32_t val : 7, + _reserved7 : 25; + }; + uint32_t _raw; + }; +} reg_arb_choice_fullness_sts; +static_assert((sizeof(struct reg_arb_choice_fullness_sts) == 4), "reg_arb_choice_fullness_sts size is not 32-bit"); +/* + ARB_MSG_STS + b'ARB-STS: Choice-Q full / No-Inflights' +*/ +typedef struct reg_arb_msg_sts { + union { + struct { + uint32_t full : 1, + no_inflight : 1, + _reserved2 : 30; + }; + uint32_t _raw; + }; +} reg_arb_msg_sts; +static_assert((sizeof(struct reg_arb_msg_sts) == 4), "reg_arb_msg_sts size is not 32-bit"); +/* + ARB_SLV_CHOICE_Q_HEAD + b'ARB-STS: Head of choice Q next CP to be granted' +*/ +typedef struct reg_arb_slv_choice_q_head { + union { + struct { + uint32_t val : 2, + _reserved2 : 30; + }; + uint32_t _raw; + }; +} reg_arb_slv_choice_q_head; +static_assert((sizeof(struct reg_arb_slv_choice_q_head) == 4), "reg_arb_slv_choice_q_head size is not 32-bit"); +/* + ARB_ERR_CAUSE + b'ARB-ERR: Arbiter error cause (OVF/WD/LBW-ERR)' +*/ +typedef struct reg_arb_err_cause { + union { + struct { + uint32_t choice_ovf : 1, + choice_wdt : 1, + axi_lbw_err : 1, + _reserved3 : 29; + }; + uint32_t _raw; + }; +} reg_arb_err_cause; +static_assert((sizeof(struct reg_arb_err_cause) == 4), "reg_arb_err_cause size is not 32-bit"); +/* + ARB_ERR_MSG_EN + b'ARB-ERR: Message enable (Bit for each error)' +*/ +typedef struct reg_arb_err_msg_en { + union { + struct { + uint32_t choice_ovf : 1, + choice_wdt : 1, + axi_lbw_err : 1, + _reserved3 : 29; + }; + uint32_t _raw; + }; +} reg_arb_err_msg_en; +static_assert((sizeof(struct reg_arb_err_msg_en) == 4), "reg_arb_err_msg_en size is not 32-bit"); +/* + ARB_ERR_STS_DRP + b'ARB-ERR: CP number that got error' +*/ +typedef struct reg_arb_err_sts_drp { + union { + struct { + uint32_t val : 2, + _reserved2 : 30; + }; + uint32_t _raw; + }; +} reg_arb_err_sts_drp; +static_assert((sizeof(struct reg_arb_err_sts_drp) == 4), "reg_arb_err_sts_drp size is not 32-bit"); +/* + ARB_MST_CRED_STS + b'ARB-MST: Credits per slave [31:0]' +*/ +typedef struct reg_arb_mst_cred_sts { + union { + struct { + uint32_t val : 7, + _reserved24 : 17, + idx : 5, + _reserved29 : 3; + }; + uint32_t _raw; + }; +} reg_arb_mst_cred_sts; +static_assert((sizeof(struct reg_arb_mst_cred_sts) == 4), "reg_arb_mst_cred_sts size is not 32-bit"); +/* + ARB_MST_CRED_STS_1 + b'ARB-MST: Credits per slave [63:32]' +*/ +typedef struct reg_arb_mst_cred_sts_1 { + union { + struct { + uint32_t val : 7, + _reserved24 : 17, + idx : 5, + _reserved29 : 3; + }; + uint32_t _raw; + }; +} reg_arb_mst_cred_sts_1; +static_assert((sizeof(struct reg_arb_mst_cred_sts_1) == 4), "reg_arb_mst_cred_sts_1 size is not 32-bit"); +/* + CSMR_STRICT_PRIO_CFG + b'ARB: Arbitration type (RR-0/Strict-1) ,Each CMD/8B' +*/ +typedef struct reg_csmr_strict_prio_cfg { + union { + struct { + uint32_t arb_type : 1, + _reserved4 : 3, + per_entry : 1, + _reserved5 : 27; + }; + uint32_t _raw; + }; +} reg_csmr_strict_prio_cfg; +static_assert((sizeof(struct reg_csmr_strict_prio_cfg) == 4), "reg_csmr_strict_prio_cfg size is not 32-bit"); +/* + ARC_CQ_CFG0 + b'ARCCQF-CFG: B2B Enable / MSG-Enable' +*/ +typedef struct reg_arc_cq_cfg0 { + union { + struct { + uint32_t if_b2b_en : 1, + if_msg_en : 1, + ctl_msg_en : 1, + _reserved3 : 29; + }; + uint32_t _raw; + }; +} reg_arc_cq_cfg0; +static_assert((sizeof(struct reg_arc_cq_cfg0) == 4), "reg_arc_cq_cfg0 size is not 32-bit"); +/* + ARC_CQ_CFG1 + b'ARCCQF-CFG: Buffer & Inflight limit' +*/ +typedef struct reg_arc_cq_cfg1 { + union { + struct { + uint32_t credit_lim : 8, + _reserved16 : 8, + max_inflight : 8, + _reserved24 : 8; + }; + uint32_t _raw; + }; +} reg_arc_cq_cfg1; +static_assert((sizeof(struct reg_arc_cq_cfg1) == 4), "reg_arc_cq_cfg1 size is not 32-bit"); +/* + ARC_CQ_PTR_LO + b'ARCCQF(Upper): Pointer (LSB)' +*/ +typedef struct reg_arc_cq_ptr_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_arc_cq_ptr_lo; +static_assert((sizeof(struct reg_arc_cq_ptr_lo) == 4), "reg_arc_cq_ptr_lo size is not 32-bit"); +/* + ARC_CQ_PTR_HI + b'ARCCQF(Upper): Pointer (MSB)' +*/ +typedef struct reg_arc_cq_ptr_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_arc_cq_ptr_hi; +static_assert((sizeof(struct reg_arc_cq_ptr_hi) == 4), "reg_arc_cq_ptr_hi size is not 32-bit"); +/* + ARC_CQ_TSIZE + b'ARC-CQF(Lower): Size in bytes' +*/ +typedef struct reg_arc_cq_tsize { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_arc_cq_tsize; +static_assert((sizeof(struct reg_arc_cq_tsize) == 4), "reg_arc_cq_tsize size is not 32-bit"); +/* + ARC_CQ_CTL + b'ARC-CQF(Lower): Control (WR initiate CQ read)' +*/ +typedef struct reg_arc_cq_ctl { + union { + struct { + uint32_t _reserved28 : 28, +up : 4; + }; + uint32_t _raw; + }; +} reg_arc_cq_ctl; +static_assert((sizeof(struct reg_arc_cq_ctl) == 4), "reg_arc_cq_ctl size is not 32-bit"); +/* + ARC_CQ_IFIFO_STS + b'ARC-CQ-STS: Input FIFO (Occupancy/Ready-Busy)' +*/ +typedef struct reg_arc_cq_ififo_sts { + union { + struct { + uint32_t cnt : 3, + _reserved4 : 1, + rdy : 1, + _reserved8 : 3, + ctl_stall : 1, + _reserved9 : 23; + }; + uint32_t _raw; + }; +} reg_arc_cq_ififo_sts; +static_assert((sizeof(struct reg_arc_cq_ififo_sts) == 4), "reg_arc_cq_ififo_sts size is not 32-bit"); +/* + ARC_CQ_STS0 + b'ARC-CQ-STS: Credit/Free/Inflight co' +*/ +typedef struct reg_arc_cq_sts0 { + union { + struct { + uint32_t credit_cnt : 8, + free_cnt : 8, + inflight_cnt : 8, + _reserved24 : 8; + }; + uint32_t _raw; + }; +} reg_arc_cq_sts0; +static_assert((sizeof(struct reg_arc_cq_sts0) == 4), "reg_arc_cq_sts0 size is not 32-bit"); +/* + ARC_CQ_STS1 + b'ARC-CQ-STS: Bus-empty/Busy' +*/ +typedef struct reg_arc_cq_sts1 { + union { + struct { + uint32_t buf_empty : 1, + busy : 1, + _reserved2 : 30; + }; + uint32_t _raw; + }; +} reg_arc_cq_sts1; +static_assert((sizeof(struct reg_arc_cq_sts1) == 4), "reg_arc_cq_sts1 size is not 32-bit"); +/* + ARC_CQ_TSIZE_STS + b'ARC-CQ-STS: Current transfer size in bytes' +*/ +typedef struct reg_arc_cq_tsize_sts { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_arc_cq_tsize_sts; +static_assert((sizeof(struct reg_arc_cq_tsize_sts) == 4), "reg_arc_cq_tsize_sts size is not 32-bit"); +/* + ARC_CQ_PTR_LO_STS + b'ARC-CQ-STS: Current Transfer base address byte 3-0' +*/ +typedef struct reg_arc_cq_ptr_lo_sts { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_arc_cq_ptr_lo_sts; +static_assert((sizeof(struct reg_arc_cq_ptr_lo_sts) == 4), "reg_arc_cq_ptr_lo_sts size is not 32-bit"); +/* + ARC_CQ_PTR_HI_STS + b'ARC-CQ-STS: Current Transfer base address byte 4-7' +*/ +typedef struct reg_arc_cq_ptr_hi_sts { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_arc_cq_ptr_hi_sts; +static_assert((sizeof(struct reg_arc_cq_ptr_hi_sts) == 4), "reg_arc_cq_ptr_hi_sts size is not 32-bit"); +/* + CP_WR_ARC_ADDR_HI + b'CP: WR_ARC_ADDRESS (MSB)' +*/ +typedef struct reg_cp_wr_arc_addr_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cp_wr_arc_addr_hi; +static_assert((sizeof(struct reg_cp_wr_arc_addr_hi) == 4), "reg_cp_wr_arc_addr_hi size is not 32-bit"); +/* + CP_WR_ARC_ADDR_LO + b'CP: WR_ARC_ADDRESS (LSB)' +*/ +typedef struct reg_cp_wr_arc_addr_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cp_wr_arc_addr_lo; +static_assert((sizeof(struct reg_cp_wr_arc_addr_lo) == 4), "reg_cp_wr_arc_addr_lo size is not 32-bit"); +/* + ARC_CQ_IFIFO_MSG_BASE_HI + b'ARC-CQ: ARC-CQ-IFIFO Shadow CI ADDR (Byte 7-4)' +*/ +typedef struct reg_arc_cq_ififo_msg_base_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_arc_cq_ififo_msg_base_hi; +static_assert((sizeof(struct reg_arc_cq_ififo_msg_base_hi) == 4), "reg_arc_cq_ififo_msg_base_hi size is not 32-bit"); +/* + ARC_CQ_IFIFO_MSG_BASE_LO + b'ARC-CQ: ARC-CQ-IFIFO Shadow CI ADDR (Byte 3-0)' +*/ +typedef struct reg_arc_cq_ififo_msg_base_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_arc_cq_ififo_msg_base_lo; +static_assert((sizeof(struct reg_arc_cq_ififo_msg_base_lo) == 4), "reg_arc_cq_ififo_msg_base_lo size is not 32-bit"); +/* + ARC_CQ_CTL_MSG_BASE_HI + b'ARC-CQ: CTL shadow CI address Byte 7-4' +*/ +typedef struct reg_arc_cq_ctl_msg_base_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_arc_cq_ctl_msg_base_hi; +static_assert((sizeof(struct reg_arc_cq_ctl_msg_base_hi) == 4), "reg_arc_cq_ctl_msg_base_hi size is not 32-bit"); +/* + ARC_CQ_CTL_MSG_BASE_LO + b'ARC CQ CTL shadow CI address Byte 3-0' +*/ +typedef struct reg_arc_cq_ctl_msg_base_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_arc_cq_ctl_msg_base_lo; +static_assert((sizeof(struct reg_arc_cq_ctl_msg_base_lo) == 4), "reg_arc_cq_ctl_msg_base_lo size is not 32-bit"); +/* + CQ_IFIFO_MSG_BASE_HI + b'CQ: CQ-IFIFO Shadow CI ADDR (Byte 7-4)' +*/ +typedef struct reg_cq_ififo_msg_base_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_ififo_msg_base_hi; +static_assert((sizeof(struct reg_cq_ififo_msg_base_hi) == 4), "reg_cq_ififo_msg_base_hi size is not 32-bit"); +/* + CQ_IFIFO_MSG_BASE_LO + b'CQ: CQ-IFIFO Shadow CI ADDR (Byte 3-0)' +*/ +typedef struct reg_cq_ififo_msg_base_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_ififo_msg_base_lo; +static_assert((sizeof(struct reg_cq_ififo_msg_base_lo) == 4), "reg_cq_ififo_msg_base_lo size is not 32-bit"); +/* + CQ_CTL_MSG_BASE_HI + b'CQ CTL shadow CI address Byte 7-4.' +*/ +typedef struct reg_cq_ctl_msg_base_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_ctl_msg_base_hi; +static_assert((sizeof(struct reg_cq_ctl_msg_base_hi) == 4), "reg_cq_ctl_msg_base_hi size is not 32-bit"); +/* + CQ_CTL_MSG_BASE_LO + b'CQ CTL shadow CI address Byte 3-0' +*/ +typedef struct reg_cq_ctl_msg_base_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_ctl_msg_base_lo; +static_assert((sizeof(struct reg_cq_ctl_msg_base_lo) == 4), "reg_cq_ctl_msg_base_lo size is not 32-bit"); +/* + ADDR_OVRD + b'QMAN-OVRIDE:ADDR[31:16] X-Y based / CFG-REG-OVRIDE' +*/ +typedef struct reg_addr_ovrd { + union { + struct { + uint32_t idx : 8, + _reserved8 : 24; + }; + uint32_t _raw; + }; +} reg_addr_ovrd; +static_assert((sizeof(struct reg_addr_ovrd) == 4), "reg_addr_ovrd size is not 32-bit"); +/* + CQ_IFIFO_CI + b'CQ: IFIFO CI per CQ [5xCopies] (Shadow)' +*/ +typedef struct reg_cq_ififo_ci { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_ififo_ci; +static_assert((sizeof(struct reg_cq_ififo_ci) == 4), "reg_cq_ififo_ci size is not 32-bit"); +/* + ARC_CQ_IFIFO_CI + b'ARC-CQ: IFIFO CI per ARC-CQ [5xCopies] (Shadow)' +*/ +typedef struct reg_arc_cq_ififo_ci { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_arc_cq_ififo_ci; +static_assert((sizeof(struct reg_arc_cq_ififo_ci) == 4), "reg_arc_cq_ififo_ci size is not 32-bit"); +/* + CQ_CTL_CI + b'CQ: CQ CTL CI per CQ [5xcopies] (Shadow)' +*/ +typedef struct reg_cq_ctl_ci { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_ctl_ci; +static_assert((sizeof(struct reg_cq_ctl_ci) == 4), "reg_cq_ctl_ci size is not 32-bit"); +/* + ARC_CQ_CTL_CI + b'ARC-CQ: ARC-CQ CTL CI per CQ [5xcopies] (Shadow)' +*/ +typedef struct reg_arc_cq_ctl_ci { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_arc_cq_ctl_ci; +static_assert((sizeof(struct reg_arc_cq_ctl_ci) == 4), "reg_arc_cq_ctl_ci size is not 32-bit"); +/* + CP_CFG + b'CP-SWITCH: Configuration (Enable Switch & its WD)' +*/ +typedef struct reg_cp_cfg { + union { + struct { + uint32_t switch_en : 1, + switch_wd_en : 1, + _reserved2 : 30; + }; + uint32_t _raw; + }; +} reg_cp_cfg; +static_assert((sizeof(struct reg_cp_cfg) == 4), "reg_cp_cfg size is not 32-bit"); +/* + CP_EXT_SWITCH + b'CP-SWITCH-WD: Over-write switch (CQ/ARCCQ) state' +*/ +typedef struct reg_cp_ext_switch { + union { + struct { + uint32_t val : 1, + _reserved1 : 31; + }; + uint32_t _raw; + }; +} reg_cp_ext_switch; +static_assert((sizeof(struct reg_cp_ext_switch) == 4), "reg_cp_ext_switch size is not 32-bit"); +/* + CP_SWITCH_WD_SET + b'CP-SWITCH-WD: Set switch WD counter value' +*/ +typedef struct reg_cp_switch_wd_set { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cp_switch_wd_set; +static_assert((sizeof(struct reg_cp_switch_wd_set) == 4), "reg_cp_switch_wd_set size is not 32-bit"); +/* + CP_SWITCH_WD + b'CP-SWITCH-WD: Set switch WD target value' +*/ +typedef struct reg_cp_switch_wd { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cp_switch_wd; +static_assert((sizeof(struct reg_cp_switch_wd) == 4), "reg_cp_switch_wd size is not 32-bit"); +/* + ARC_LB_ADDR_BASE_LO + b'QMAN-ADDR: QMAN-LBW base address (LSB)' +*/ +typedef struct reg_arc_lb_addr_base_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_arc_lb_addr_base_lo; +static_assert((sizeof(struct reg_arc_lb_addr_base_lo) == 4), "reg_arc_lb_addr_base_lo size is not 32-bit"); +/* + ARC_LB_ADDR_BASE_HI + b'QMAN-ADDR: QMAN-LBW base address (MSB)' +*/ +typedef struct reg_arc_lb_addr_base_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_arc_lb_addr_base_hi; +static_assert((sizeof(struct reg_arc_lb_addr_base_hi) == 4), "reg_arc_lb_addr_base_hi size is not 32-bit"); +/* + ENGINE_BASE_ADDR_HI + b'QMAN-ADDR: QMAN-ENGINE BASE_ADDR (MSB)' +*/ +typedef struct reg_engine_base_addr_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_engine_base_addr_hi; +static_assert((sizeof(struct reg_engine_base_addr_hi) == 4), "reg_engine_base_addr_hi size is not 32-bit"); +/* + ENGINE_BASE_ADDR_LO + b'QMAN-ADDR: QMAN-ENGINE BASE_ADDR (MSB)' +*/ +typedef struct reg_engine_base_addr_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_engine_base_addr_lo; +static_assert((sizeof(struct reg_engine_base_addr_lo) == 4), "reg_engine_base_addr_lo size is not 32-bit"); +/* + ENGINE_ADDR_RANGE_SIZE + b'QMAN-ADDR: QMAN-ENGINE Address size' +*/ +typedef struct reg_engine_addr_range_size { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_engine_addr_range_size; +static_assert((sizeof(struct reg_engine_addr_range_size) == 4), "reg_engine_addr_range_size size is not 32-bit"); +/* + QM_ARC_AUX_BASE_ADDR_HI + b'QMAN-ADDR: QMAN-ARC-AUX BASE_ADDR (MSB)' +*/ +typedef struct reg_qm_arc_aux_base_addr_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_qm_arc_aux_base_addr_hi; +static_assert((sizeof(struct reg_qm_arc_aux_base_addr_hi) == 4), "reg_qm_arc_aux_base_addr_hi size is not 32-bit"); +/* + QM_ARC_AUX_BASE_ADDR_LO + b'QMAN-ADDR: QMAN-ARC-AUX BASE_ADDR (LSB)' +*/ +typedef struct reg_qm_arc_aux_base_addr_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_qm_arc_aux_base_addr_lo; +static_assert((sizeof(struct reg_qm_arc_aux_base_addr_lo) == 4), "reg_qm_arc_aux_base_addr_lo size is not 32-bit"); +/* + QM_BASE_ADDR_HI + b'QMAN-ADDR: QMAN-CFG BASE_ADDR (MSB)' +*/ +typedef struct reg_qm_base_addr_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_qm_base_addr_hi; +static_assert((sizeof(struct reg_qm_base_addr_hi) == 4), "reg_qm_base_addr_hi size is not 32-bit"); +/* + QM_BASE_ADDR_LO + b'QMAN-ADDR: QMAN-CFG BASE_ADDR (LSB)' +*/ +typedef struct reg_qm_base_addr_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_qm_base_addr_lo; +static_assert((sizeof(struct reg_qm_base_addr_lo) == 4), "reg_qm_base_addr_lo size is not 32-bit"); +/* + ARC_PQC_SECURE_PUSH_IND + b'PQ-CQ:ARC/UCP indication to pass completion to LCQ' +*/ +typedef struct reg_arc_pqc_secure_push_ind { + union { + struct { + uint32_t cp_num : 2, + _reserved2 : 30; + }; + uint32_t _raw; + }; +} reg_arc_pqc_secure_push_ind; +static_assert((sizeof(struct reg_arc_pqc_secure_push_ind) == 4), "reg_arc_pqc_secure_push_ind size is not 32-bit"); +/* + PQC_STS_0 + b'PQ-CQ: Completion Q status' +*/ +typedef struct reg_pqc_sts_0 { + union { + struct { + uint32_t comp_data : 16, + comp_ofst : 16; + }; + uint32_t _raw; + }; +} reg_pqc_sts_0; +static_assert((sizeof(struct reg_pqc_sts_0) == 4), "reg_pqc_sts_0 size is not 32-bit"); +/* + PQC_STS_1 + b'PQ-CQ: Completion Q status (cont..)' +*/ +typedef struct reg_pqc_sts_1 { + union { + struct { + uint32_t comp_fifo_cntr : 4, + comp_fifo_empty : 1, + comp_fifo_full : 1, + _reserved6 : 26; + }; + uint32_t _raw; + }; +} reg_pqc_sts_1; +static_assert((sizeof(struct reg_pqc_sts_1) == 4), "reg_pqc_sts_1 size is not 32-bit"); +/* + SEI_STATUS + b'EXCEPTIONS: SEI cause (System Error Interrupts)' +*/ +typedef struct reg_sei_status { + union { + struct { + uint32_t qm_int : 1, + arc_int : 1, + _reserved2 : 30; + }; + uint32_t _raw; + }; +} reg_sei_status; +static_assert((sizeof(struct reg_sei_status) == 4), "reg_sei_status size is not 32-bit"); +/* + SEI_MASK + b'EXCEPTIONS: SEI mask (System Error Interrupts)' +*/ +typedef struct reg_sei_mask { + union { + struct { + uint32_t qm_int : 1, + arc_int : 1, + _reserved2 : 30; + }; + uint32_t _raw; + }; +} reg_sei_mask; +static_assert((sizeof(struct reg_sei_mask) == 4), "reg_sei_mask size is not 32-bit"); +/* + GLBL_ERR_ADDR_LO + b'GLOBAL-ERR: Global Error ADDRESS LSB (0..3)' +*/ +typedef struct reg_glbl_err_addr_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_glbl_err_addr_lo; +static_assert((sizeof(struct reg_glbl_err_addr_lo) == 4), "reg_glbl_err_addr_lo size is not 32-bit"); +/* + GLBL_ERR_ADDR_HI + b'GLOBAL-ERR: Global Error ADDRESS MSB (4..7)' +*/ +typedef struct reg_glbl_err_addr_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_glbl_err_addr_hi; +static_assert((sizeof(struct reg_glbl_err_addr_hi) == 4), "reg_glbl_err_addr_hi size is not 32-bit"); +/* + GLBL_ERR_WDATA + b'GLOBAL-ERR: Global Error DATA to send (LBW)' +*/ +typedef struct reg_glbl_err_wdata { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_glbl_err_wdata; +static_assert((sizeof(struct reg_glbl_err_wdata) == 4), "reg_glbl_err_wdata size is not 32-bit"); +/* + L2H_MASK_LO + b'L2H:Addr mask (LSB) to select HBW over LBW' +*/ +typedef struct reg_l2h_mask_lo { + union { + struct { + uint32_t _reserved20 : 20, +val : 12; + }; + uint32_t _raw; + }; +} reg_l2h_mask_lo; +static_assert((sizeof(struct reg_l2h_mask_lo) == 4), "reg_l2h_mask_lo size is not 32-bit"); +/* + L2H_MASK_HI + b'L2H:Addr mask (MSB) to select HBW over LBW' +*/ +typedef struct reg_l2h_mask_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_l2h_mask_hi; +static_assert((sizeof(struct reg_l2h_mask_hi) == 4), "reg_l2h_mask_hi size is not 32-bit"); +/* + L2H_CMPR_LO + b'L2H:Addr compare (LSB) to select HBW over LBW' +*/ +typedef struct reg_l2h_cmpr_lo { + union { + struct { + uint32_t _reserved20 : 20, +val : 12; + }; + uint32_t _raw; + }; +} reg_l2h_cmpr_lo; +static_assert((sizeof(struct reg_l2h_cmpr_lo) == 4), "reg_l2h_cmpr_lo size is not 32-bit"); +/* + L2H_CMPR_HI + b'L2H:Addr compare (MSB) to select HBW over LBW' +*/ +typedef struct reg_l2h_cmpr_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_l2h_cmpr_hi; +static_assert((sizeof(struct reg_l2h_cmpr_hi) == 4), "reg_l2h_cmpr_hi size is not 32-bit"); +/* + LOCAL_RANGE_BASE + b'LCL:QMAN location relative to 64KB 0xA000 Int. use' +*/ +typedef struct reg_local_range_base { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_local_range_base; +static_assert((sizeof(struct reg_local_range_base) == 4), "reg_local_range_base size is not 32-bit"); +/* + LOCAL_RANGE_SIZE + b'LCL: Size of QMAN ADDR space 0x1000 (Int. use)' +*/ +typedef struct reg_local_range_size { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_local_range_size; +static_assert((sizeof(struct reg_local_range_size) == 4), "reg_local_range_size size is not 32-bit"); +/* + HBW_RD_RATE_LIM_CFG_1 + b'RATE-LIMIT: QMAN rate limiter CFG0 (HBW port)' +*/ +typedef struct reg_hbw_rd_rate_lim_cfg_1 { + union { + struct { + uint32_t tout : 8, + _reserved31 : 23, + en : 1; + }; + uint32_t _raw; + }; +} reg_hbw_rd_rate_lim_cfg_1; +static_assert((sizeof(struct reg_hbw_rd_rate_lim_cfg_1) == 4), "reg_hbw_rd_rate_lim_cfg_1 size is not 32-bit"); +/* + LBW_WR_RATE_LIM_CFG_0 + b'RATE-LIMIT: QMAN rate limiter CFG0 (LBW port)' +*/ +typedef struct reg_lbw_wr_rate_lim_cfg_0 { + union { + struct { + uint32_t rst_token : 8, + _reserved16 : 8, + sat : 8, + _reserved24 : 8; + }; + uint32_t _raw; + }; +} reg_lbw_wr_rate_lim_cfg_0; +static_assert((sizeof(struct reg_lbw_wr_rate_lim_cfg_0) == 4), "reg_lbw_wr_rate_lim_cfg_0 size is not 32-bit"); +/* + LBW_WR_RATE_LIM_CFG_1 + b'RATE-LIMIT: QMAN rate limiter CFG1 (LBW port)' +*/ +typedef struct reg_lbw_wr_rate_lim_cfg_1 { + union { + struct { + uint32_t tout : 8, + _reserved31 : 23, + en : 1; + }; + uint32_t _raw; + }; +} reg_lbw_wr_rate_lim_cfg_1; +static_assert((sizeof(struct reg_lbw_wr_rate_lim_cfg_1) == 4), "reg_lbw_wr_rate_lim_cfg_1 size is not 32-bit"); +/* + HBW_RD_RATE_LIM_CFG_0 + b'RATE-LIMIT: QMAN rate limiter CFG1 (HBW port)' +*/ +typedef struct reg_hbw_rd_rate_lim_cfg_0 { + union { + struct { + uint32_t rst_token : 8, + _reserved16 : 8, + sat : 8, + _reserved24 : 8; + }; + uint32_t _raw; + }; +} reg_hbw_rd_rate_lim_cfg_0; +static_assert((sizeof(struct reg_hbw_rd_rate_lim_cfg_0) == 4), "reg_hbw_rd_rate_lim_cfg_0 size is not 32-bit"); +/* + IND_GW_APB_CFG + b'QMAN-MEM-IND-ACC: Set ADDR for QMAN memory access' +*/ +typedef struct reg_ind_gw_apb_cfg { + union { + struct { + uint32_t addr : 31, + cmd : 1; + }; + uint32_t _raw; + }; +} reg_ind_gw_apb_cfg; +static_assert((sizeof(struct reg_ind_gw_apb_cfg) == 4), "reg_ind_gw_apb_cfg size is not 32-bit"); +/* + IND_GW_APB_WDATA + b'QMAN-MEM-IND-ACC: Data to write' +*/ +typedef struct reg_ind_gw_apb_wdata { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_ind_gw_apb_wdata; +static_assert((sizeof(struct reg_ind_gw_apb_wdata) == 4), "reg_ind_gw_apb_wdata size is not 32-bit"); +/* + IND_GW_APB_RDATA + b'QMAN-MEM-IND-ACC: Data readf' +*/ +typedef struct reg_ind_gw_apb_rdata { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_ind_gw_apb_rdata; +static_assert((sizeof(struct reg_ind_gw_apb_rdata) == 4), "reg_ind_gw_apb_rdata size is not 32-bit"); +/* + IND_GW_APB_STATUS + b'QMAN-MEM-IND-ACC: Status & Ready' +*/ +typedef struct reg_ind_gw_apb_status { + union { + struct { + uint32_t rdy : 1, + err : 1, + _reserved2 : 30; + }; + uint32_t _raw; + }; +} reg_ind_gw_apb_status; +static_assert((sizeof(struct reg_ind_gw_apb_status) == 4), "reg_ind_gw_apb_status size is not 32-bit"); +/* + PERF_CNT_FREE_LO + b'PERF-CNT: Free-Run counter (LSB)' +*/ +typedef struct reg_perf_cnt_free_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_perf_cnt_free_lo; +static_assert((sizeof(struct reg_perf_cnt_free_lo) == 4), "reg_perf_cnt_free_lo size is not 32-bit"); +/* + PERF_CNT_FREE_HI + b'PERF-CNT: Free-Run counter (MSB)' +*/ +typedef struct reg_perf_cnt_free_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_perf_cnt_free_hi; +static_assert((sizeof(struct reg_perf_cnt_free_hi) == 4), "reg_perf_cnt_free_hi size is not 32-bit"); +/* + PERF_CNT_IDLE_LO + b'PERF-CNT: Idle cycles counter for monitoring (LSB)' +*/ +typedef struct reg_perf_cnt_idle_lo { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_perf_cnt_idle_lo; +static_assert((sizeof(struct reg_perf_cnt_idle_lo) == 4), "reg_perf_cnt_idle_lo size is not 32-bit"); +/* + PERF_CNT_IDLE_HI + b'PERF-CNT: Idle cycles counter for monitoring (MSB)' +*/ +typedef struct reg_perf_cnt_idle_hi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_perf_cnt_idle_hi; +static_assert((sizeof(struct reg_perf_cnt_idle_hi) == 4), "reg_perf_cnt_idle_hi size is not 32-bit"); +/* + PERF_CNT_CFG + b'PERF-CNT: Enable / Set IDLE mask' +*/ +typedef struct reg_perf_cnt_cfg { + union { + struct { + uint32_t pq_mask : 4, + _reserved8 : 4, + cq_mask : 5, + _reserved16 : 3, + cp_mask : 5, + _reserved24 : 3, + agent_mask : 1, + _reserved30 : 5, + en_free : 1, + en_idle : 1; + }; + uint32_t _raw; + }; +} reg_perf_cnt_cfg; +static_assert((sizeof(struct reg_perf_cnt_cfg) == 4), "reg_perf_cnt_cfg size is not 32-bit"); + +#ifdef __cplusplus +} /* qman namespace */ +#endif + +/* + QMAN block +*/ + +#ifdef __cplusplus + +struct block_qman { + struct qman::reg_glbl_cfg0 glbl_cfg0; + struct qman::reg_glbl_cfg1 glbl_cfg1; + struct qman::reg_glbl_cfg2 glbl_cfg2; + struct qman::reg_glbl_err_cfg glbl_err_cfg; + struct qman::reg_glbl_err_cfg1 glbl_err_cfg1; + struct qman::reg_glbl_err_arc_halt_en glbl_err_arc_halt_en; + struct qman::reg_glbl_axcache glbl_axcache; + struct qman::reg_glbl_sts0 glbl_sts0; + struct qman::reg_glbl_sts1 glbl_sts1; + struct qman::reg_glbl_err_sts glbl_err_sts[4]; + struct qman::reg_glbl_err_sts_4 glbl_err_sts_4; + struct qman::reg_glbl_err_msg_en glbl_err_msg_en[4]; + struct qman::reg_glbl_err_msg_en_4 glbl_err_msg_en_4; + struct qman::reg_glbl_prot glbl_prot; + struct qman::reg_pq_base_lo pq_base_lo[4]; + struct qman::reg_pq_base_hi pq_base_hi[4]; + struct qman::reg_pq_size pq_size[4]; + struct qman::reg_pq_pi pq_pi[4]; + struct qman::reg_pq_ci pq_ci[4]; + struct qman::reg_pq_cfg0 pq_cfg0[4]; + struct qman::reg_pq_cfg1 pq_cfg1[4]; + struct qman::reg_pq_sts0 pq_sts0[4]; + struct qman::reg_pq_sts1 pq_sts1[4]; + struct qman::reg_cq_cfg0 cq_cfg0[5]; + struct qman::reg_cq_sts0 cq_sts0[5]; + struct qman::reg_cq_cfg1 cq_cfg1[5]; + struct qman::reg_cq_sts1 cq_sts1[5]; + uint32_t _pad304[8]; + struct qman::reg_cq_ptr_lo_0 cq_ptr_lo_0; + struct qman::reg_cq_ptr_hi_0 cq_ptr_hi_0; + struct qman::reg_cq_tsize_0 cq_tsize_0; + struct qman::reg_cq_ctl_0 cq_ctl_0; + struct qman::reg_cq_ptr_lo_1 cq_ptr_lo_1; + struct qman::reg_cq_ptr_hi_1 cq_ptr_hi_1; + struct qman::reg_cq_tsize_1 cq_tsize_1; + struct qman::reg_cq_ctl_1 cq_ctl_1; + struct qman::reg_cq_ptr_lo_2 cq_ptr_lo_2; + struct qman::reg_cq_ptr_hi_2 cq_ptr_hi_2; + struct qman::reg_cq_tsize_2 cq_tsize_2; + struct qman::reg_cq_ctl_2 cq_ctl_2; + struct qman::reg_cq_ptr_lo_3 cq_ptr_lo_3; + struct qman::reg_cq_ptr_hi_3 cq_ptr_hi_3; + struct qman::reg_cq_tsize_3 cq_tsize_3; + struct qman::reg_cq_ctl_3 cq_ctl_3; + struct qman::reg_cq_ptr_lo_4 cq_ptr_lo_4; + struct qman::reg_cq_ptr_hi_4 cq_ptr_hi_4; + struct qman::reg_cq_tsize_4 cq_tsize_4; + struct qman::reg_cq_ctl_4 cq_ctl_4; + struct qman::reg_cq_tsize_sts cq_tsize_sts[5]; + struct qman::reg_cq_ptr_lo_sts cq_ptr_lo_sts[5]; + struct qman::reg_cq_ptr_hi_sts cq_ptr_hi_sts[5]; + struct qman::reg_cq_ififo_sts cq_ififo_sts[5]; + struct qman::reg_cp_msg_base0_addr_lo cp_msg_base0_addr_lo[5]; + struct qman::reg_cp_msg_base0_addr_hi cp_msg_base0_addr_hi[5]; + struct qman::reg_cp_msg_base1_addr_lo cp_msg_base1_addr_lo[5]; + struct qman::reg_cp_msg_base1_addr_hi cp_msg_base1_addr_hi[5]; + struct qman::reg_cp_msg_base2_addr_lo cp_msg_base2_addr_lo[5]; + struct qman::reg_cp_msg_base2_addr_hi cp_msg_base2_addr_hi[5]; + struct qman::reg_cp_msg_base3_addr_lo cp_msg_base3_addr_lo[5]; + struct qman::reg_cp_msg_base3_addr_hi cp_msg_base3_addr_hi[5]; + struct qman::reg_cp_fence0_rdata cp_fence0_rdata[5]; + struct qman::reg_cp_fence1_rdata cp_fence1_rdata[5]; + struct qman::reg_cp_fence2_rdata cp_fence2_rdata[5]; + struct qman::reg_cp_fence3_rdata cp_fence3_rdata[5]; + struct qman::reg_cp_fence0_cnt cp_fence0_cnt[5]; + struct qman::reg_cp_fence1_cnt cp_fence1_cnt[5]; + struct qman::reg_cp_fence2_cnt cp_fence2_cnt[5]; + struct qman::reg_cp_fence3_cnt cp_fence3_cnt[5]; + struct qman::reg_cp_barrier_cfg cp_barrier_cfg; + struct qman::reg_cp_ldma_src_base_lo_offset cp_ldma_src_base_lo_offset; + struct qman::reg_cp_ldma_dst_base_lo_offset cp_ldma_dst_base_lo_offset; + struct qman::reg_cp_ldma_tsize_offset cp_ldma_tsize_offset; + struct qman::reg_cp_cq_ptr_lo_offset_0 cp_cq_ptr_lo_offset_0; + struct qman::reg_cp_cq_ptr_lo_offset_1 cp_cq_ptr_lo_offset_1; + struct qman::reg_cp_cq_ptr_lo_offset_2 cp_cq_ptr_lo_offset_2; + struct qman::reg_cp_cq_ptr_lo_offset_3 cp_cq_ptr_lo_offset_3; + struct qman::reg_cp_cq_ptr_lo_offset_4 cp_cq_ptr_lo_offset_4; + uint32_t _pad852[5]; + struct qman::reg_cp_sts cp_sts[5]; + struct qman::reg_cp_current_inst_lo cp_current_inst_lo[5]; + struct qman::reg_cp_current_inst_hi cp_current_inst_hi[5]; + struct qman::reg_cp_pred cp_pred[5]; + struct qman::reg_cp_pred_upen cp_pred_upen[5]; + struct qman::reg_cp_dbg_0 cp_dbg_0[5]; + struct qman::reg_cp_cpdma_up_cred cp_cpdma_up_cred[5]; + struct qman::reg_cp_in_data_lo cp_in_data_lo[5]; + struct qman::reg_cp_in_data_hi cp_in_data_hi[5]; + struct qman::reg_pqc_hbw_base_lo pqc_hbw_base_lo[4]; + struct qman::reg_pqc_hbw_base_hi pqc_hbw_base_hi[4]; + struct qman::reg_pqc_size pqc_size[4]; + struct qman::reg_pqc_pi pqc_pi[4]; + struct qman::reg_pqc_lbw_wdata pqc_lbw_wdata[4]; + struct qman::reg_pqc_lbw_base_lo pqc_lbw_base_lo[4]; + struct qman::reg_pqc_lbw_base_hi pqc_lbw_base_hi[4]; + struct qman::reg_pqc_cfg pqc_cfg; + struct qman::reg_pqc_secure_push_ind pqc_secure_push_ind; + uint32_t _pad1172[3]; + struct qman::reg_arb_mask arb_mask; + struct qman::reg_arb_cfg_0 arb_cfg_0; + struct qman::reg_arb_choice_q_push arb_choice_q_push; + struct qman::reg_arb_wrr_weight arb_wrr_weight[4]; + struct qman::reg_arb_cfg_1 arb_cfg_1; + struct qman::reg_arb_mst_avail_cred arb_mst_avail_cred[64]; + uint32_t _pad1472[8]; + struct qman::reg_arb_mst_cred_inc arb_mst_cred_inc; + struct qman::reg_arb_mst_choice_push_ofst arb_mst_choice_push_ofst[64]; + uint32_t _pad1764[8]; + struct qman::reg_arb_slv_master_inc_cred_ofst arb_slv_master_inc_cred_ofst; + struct qman::reg_arb_mst_slave_en arb_mst_slave_en; + struct qman::reg_arb_mst_slave_en_1 arb_mst_slave_en_1; + struct qman::reg_arb_slv_choice_wdt arb_slv_choice_wdt; + struct qman::reg_arb_slv_id arb_slv_id; + struct qman::reg_arb_mst_quiet_per arb_mst_quiet_per; + uint32_t _pad1820[10]; + struct qman::reg_arb_msg_max_inflight arb_msg_max_inflight; + uint32_t _pad1864[3]; + struct qman::reg_arb_base_lo arb_base_lo; + struct qman::reg_arb_base_hi arb_base_hi; + uint32_t _pad1884[9]; + struct qman::reg_arb_state_sts arb_state_sts; + struct qman::reg_arb_choice_fullness_sts arb_choice_fullness_sts; + struct qman::reg_arb_msg_sts arb_msg_sts; + struct qman::reg_arb_slv_choice_q_head arb_slv_choice_q_head; + uint32_t _pad1936[3]; + struct qman::reg_arb_err_cause arb_err_cause; + struct qman::reg_arb_err_msg_en arb_err_msg_en; + uint32_t _pad1956[1]; + struct qman::reg_arb_err_sts_drp arb_err_sts_drp; + uint32_t _pad1964[1]; + struct qman::reg_arb_mst_cred_sts arb_mst_cred_sts; + struct qman::reg_arb_mst_cred_sts_1 arb_mst_cred_sts_1; + uint32_t _pad1976[17]; + struct qman::reg_csmr_strict_prio_cfg csmr_strict_prio_cfg; + struct qman::reg_arc_cq_cfg0 arc_cq_cfg0; + struct qman::reg_arc_cq_cfg1 arc_cq_cfg1; + struct qman::reg_arc_cq_ptr_lo arc_cq_ptr_lo; + struct qman::reg_arc_cq_ptr_hi arc_cq_ptr_hi; + struct qman::reg_arc_cq_tsize arc_cq_tsize; + struct qman::reg_arc_cq_ctl arc_cq_ctl; + uint32_t _pad2072[1]; + struct qman::reg_arc_cq_ififo_sts arc_cq_ififo_sts; + struct qman::reg_arc_cq_sts0 arc_cq_sts0; + struct qman::reg_arc_cq_sts1 arc_cq_sts1; + struct qman::reg_arc_cq_tsize_sts arc_cq_tsize_sts; + struct qman::reg_arc_cq_ptr_lo_sts arc_cq_ptr_lo_sts; + struct qman::reg_arc_cq_ptr_hi_sts arc_cq_ptr_hi_sts; + struct qman::reg_cp_wr_arc_addr_hi cp_wr_arc_addr_hi; + struct qman::reg_cp_wr_arc_addr_lo cp_wr_arc_addr_lo; + struct qman::reg_arc_cq_ififo_msg_base_hi arc_cq_ififo_msg_base_hi; + struct qman::reg_arc_cq_ififo_msg_base_lo arc_cq_ififo_msg_base_lo; + struct qman::reg_arc_cq_ctl_msg_base_hi arc_cq_ctl_msg_base_hi; + struct qman::reg_arc_cq_ctl_msg_base_lo arc_cq_ctl_msg_base_lo; + struct qman::reg_cq_ififo_msg_base_hi cq_ififo_msg_base_hi; + struct qman::reg_cq_ififo_msg_base_lo cq_ififo_msg_base_lo; + struct qman::reg_cq_ctl_msg_base_hi cq_ctl_msg_base_hi; + struct qman::reg_cq_ctl_msg_base_lo cq_ctl_msg_base_lo; + struct qman::reg_addr_ovrd addr_ovrd; + struct qman::reg_cq_ififo_ci cq_ififo_ci[5]; + struct qman::reg_arc_cq_ififo_ci arc_cq_ififo_ci; + struct qman::reg_cq_ctl_ci cq_ctl_ci[5]; + struct qman::reg_arc_cq_ctl_ci arc_cq_ctl_ci; + struct qman::reg_cp_cfg cp_cfg; + struct qman::reg_cp_ext_switch cp_ext_switch; + struct qman::reg_cp_switch_wd_set cp_switch_wd_set; + struct qman::reg_cp_switch_wd cp_switch_wd; + uint32_t _pad2208[1]; + struct qman::reg_arc_lb_addr_base_lo arc_lb_addr_base_lo; + struct qman::reg_arc_lb_addr_base_hi arc_lb_addr_base_hi; + struct qman::reg_engine_base_addr_hi engine_base_addr_hi; + struct qman::reg_engine_base_addr_lo engine_base_addr_lo; + struct qman::reg_engine_addr_range_size engine_addr_range_size; + struct qman::reg_qm_arc_aux_base_addr_hi qm_arc_aux_base_addr_hi; + struct qman::reg_qm_arc_aux_base_addr_lo qm_arc_aux_base_addr_lo; + struct qman::reg_qm_base_addr_hi qm_base_addr_hi; + struct qman::reg_qm_base_addr_lo qm_base_addr_lo; + struct qman::reg_arc_pqc_secure_push_ind arc_pqc_secure_push_ind; + uint32_t _pad2252[1]; + struct qman::reg_pqc_sts_0 pqc_sts_0[4]; + struct qman::reg_pqc_sts_1 pqc_sts_1[4]; + struct qman::reg_sei_status sei_status; + struct qman::reg_sei_mask sei_mask; + uint32_t _pad2296[2]; + struct block_qman_wr64_base_addr qman_wr64_base_addr0; + struct block_qman_wr64_base_addr qman_wr64_base_addr1; + struct block_qman_wr64_base_addr qman_wr64_base_addr2; + struct block_qman_wr64_base_addr qman_wr64_base_addr3; + struct block_qman_wr64_base_addr qman_wr64_base_addr4; + struct block_qman_wr64_base_addr qman_wr64_base_addr5; + struct block_qman_wr64_base_addr qman_wr64_base_addr6; + struct block_qman_wr64_base_addr qman_wr64_base_addr7; + struct block_qman_wr64_base_addr qman_wr64_base_addr8; + struct block_qman_wr64_base_addr qman_wr64_base_addr9; + struct block_qman_wr64_base_addr qman_wr64_base_addr10; + struct block_qman_wr64_base_addr qman_wr64_base_addr11; + struct block_qman_wr64_base_addr qman_wr64_base_addr12; + struct block_qman_wr64_base_addr qman_wr64_base_addr13; + struct block_qman_wr64_base_addr qman_wr64_base_addr14; + struct block_qman_wr64_base_addr qman_wr64_base_addr15; + uint32_t _pad2432[96]; + struct block_axuser axuser_secured; + uint32_t _pad2896[12]; + struct block_axuser axuser_nonsecured; + uint32_t _pad3024[12]; + struct block_ic_lbw_dbg_cnt dbg_hbw; + uint32_t _pad3160[10]; + struct block_ic_lbw_dbg_cnt dbg_lbw; + uint32_t _pad3288[10]; + struct qman::reg_glbl_err_addr_lo glbl_err_addr_lo; + struct qman::reg_glbl_err_addr_hi glbl_err_addr_hi; + struct qman::reg_glbl_err_wdata glbl_err_wdata; + uint32_t _pad3340[2]; + struct qman::reg_l2h_mask_lo l2h_mask_lo; + struct qman::reg_l2h_mask_hi l2h_mask_hi; + struct qman::reg_l2h_cmpr_lo l2h_cmpr_lo; + struct qman::reg_l2h_cmpr_hi l2h_cmpr_hi; + struct qman::reg_local_range_base local_range_base; + struct qman::reg_local_range_size local_range_size; + uint32_t _pad3372[1]; + struct qman::reg_hbw_rd_rate_lim_cfg_1 hbw_rd_rate_lim_cfg_1; + struct qman::reg_lbw_wr_rate_lim_cfg_0 lbw_wr_rate_lim_cfg_0; + struct qman::reg_lbw_wr_rate_lim_cfg_1 lbw_wr_rate_lim_cfg_1; + struct qman::reg_hbw_rd_rate_lim_cfg_0 hbw_rd_rate_lim_cfg_0; + struct qman::reg_ind_gw_apb_cfg ind_gw_apb_cfg; + struct qman::reg_ind_gw_apb_wdata ind_gw_apb_wdata; + struct qman::reg_ind_gw_apb_rdata ind_gw_apb_rdata; + struct qman::reg_ind_gw_apb_status ind_gw_apb_status; + uint32_t _pad3408[4]; + struct qman::reg_perf_cnt_free_lo perf_cnt_free_lo; + struct qman::reg_perf_cnt_free_hi perf_cnt_free_hi; + struct qman::reg_perf_cnt_idle_lo perf_cnt_idle_lo; + struct qman::reg_perf_cnt_idle_hi perf_cnt_idle_hi; + struct qman::reg_perf_cnt_cfg perf_cnt_cfg; + uint32_t _pad3444[3]; + struct block_qman_cgm cgm; + uint32_t _pad3468[61]; + struct block_special_regs special; +}; +#else + +typedef struct block_qman { + reg_glbl_cfg0 glbl_cfg0; + reg_glbl_cfg1 glbl_cfg1; + reg_glbl_cfg2 glbl_cfg2; + reg_glbl_err_cfg glbl_err_cfg; + reg_glbl_err_cfg1 glbl_err_cfg1; + reg_glbl_err_arc_halt_en glbl_err_arc_halt_en; + reg_glbl_axcache glbl_axcache; + reg_glbl_sts0 glbl_sts0; + reg_glbl_sts1 glbl_sts1; + reg_glbl_err_sts glbl_err_sts[4]; + reg_glbl_err_sts_4 glbl_err_sts_4; + reg_glbl_err_msg_en glbl_err_msg_en[4]; + reg_glbl_err_msg_en_4 glbl_err_msg_en_4; + reg_glbl_prot glbl_prot; + reg_pq_base_lo pq_base_lo[4]; + reg_pq_base_hi pq_base_hi[4]; + reg_pq_size pq_size[4]; + reg_pq_pi pq_pi[4]; + reg_pq_ci pq_ci[4]; + reg_pq_cfg0 pq_cfg0[4]; + reg_pq_cfg1 pq_cfg1[4]; + reg_pq_sts0 pq_sts0[4]; + reg_pq_sts1 pq_sts1[4]; + reg_cq_cfg0 cq_cfg0[5]; + reg_cq_sts0 cq_sts0[5]; + reg_cq_cfg1 cq_cfg1[5]; + reg_cq_sts1 cq_sts1[5]; + uint32_t _pad304[8]; + reg_cq_ptr_lo_0 cq_ptr_lo_0; + reg_cq_ptr_hi_0 cq_ptr_hi_0; + reg_cq_tsize_0 cq_tsize_0; + reg_cq_ctl_0 cq_ctl_0; + reg_cq_ptr_lo_1 cq_ptr_lo_1; + reg_cq_ptr_hi_1 cq_ptr_hi_1; + reg_cq_tsize_1 cq_tsize_1; + reg_cq_ctl_1 cq_ctl_1; + reg_cq_ptr_lo_2 cq_ptr_lo_2; + reg_cq_ptr_hi_2 cq_ptr_hi_2; + reg_cq_tsize_2 cq_tsize_2; + reg_cq_ctl_2 cq_ctl_2; + reg_cq_ptr_lo_3 cq_ptr_lo_3; + reg_cq_ptr_hi_3 cq_ptr_hi_3; + reg_cq_tsize_3 cq_tsize_3; + reg_cq_ctl_3 cq_ctl_3; + reg_cq_ptr_lo_4 cq_ptr_lo_4; + reg_cq_ptr_hi_4 cq_ptr_hi_4; + reg_cq_tsize_4 cq_tsize_4; + reg_cq_ctl_4 cq_ctl_4; + reg_cq_tsize_sts cq_tsize_sts[5]; + reg_cq_ptr_lo_sts cq_ptr_lo_sts[5]; + reg_cq_ptr_hi_sts cq_ptr_hi_sts[5]; + reg_cq_ififo_sts cq_ififo_sts[5]; + reg_cp_msg_base0_addr_lo cp_msg_base0_addr_lo[5]; + reg_cp_msg_base0_addr_hi cp_msg_base0_addr_hi[5]; + reg_cp_msg_base1_addr_lo cp_msg_base1_addr_lo[5]; + reg_cp_msg_base1_addr_hi cp_msg_base1_addr_hi[5]; + reg_cp_msg_base2_addr_lo cp_msg_base2_addr_lo[5]; + reg_cp_msg_base2_addr_hi cp_msg_base2_addr_hi[5]; + reg_cp_msg_base3_addr_lo cp_msg_base3_addr_lo[5]; + reg_cp_msg_base3_addr_hi cp_msg_base3_addr_hi[5]; + reg_cp_fence0_rdata cp_fence0_rdata[5]; + reg_cp_fence1_rdata cp_fence1_rdata[5]; + reg_cp_fence2_rdata cp_fence2_rdata[5]; + reg_cp_fence3_rdata cp_fence3_rdata[5]; + reg_cp_fence0_cnt cp_fence0_cnt[5]; + reg_cp_fence1_cnt cp_fence1_cnt[5]; + reg_cp_fence2_cnt cp_fence2_cnt[5]; + reg_cp_fence3_cnt cp_fence3_cnt[5]; + reg_cp_barrier_cfg cp_barrier_cfg; + reg_cp_ldma_src_base_lo_offset cp_ldma_src_base_lo_offset; + reg_cp_ldma_dst_base_lo_offset cp_ldma_dst_base_lo_offset; + reg_cp_ldma_tsize_offset cp_ldma_tsize_offset; + reg_cp_cq_ptr_lo_offset_0 cp_cq_ptr_lo_offset_0; + reg_cp_cq_ptr_lo_offset_1 cp_cq_ptr_lo_offset_1; + reg_cp_cq_ptr_lo_offset_2 cp_cq_ptr_lo_offset_2; + reg_cp_cq_ptr_lo_offset_3 cp_cq_ptr_lo_offset_3; + reg_cp_cq_ptr_lo_offset_4 cp_cq_ptr_lo_offset_4; + uint32_t _pad852[5]; + reg_cp_sts cp_sts[5]; + reg_cp_current_inst_lo cp_current_inst_lo[5]; + reg_cp_current_inst_hi cp_current_inst_hi[5]; + reg_cp_pred cp_pred[5]; + reg_cp_pred_upen cp_pred_upen[5]; + reg_cp_dbg_0 cp_dbg_0[5]; + reg_cp_cpdma_up_cred cp_cpdma_up_cred[5]; + reg_cp_in_data_lo cp_in_data_lo[5]; + reg_cp_in_data_hi cp_in_data_hi[5]; + reg_pqc_hbw_base_lo pqc_hbw_base_lo[4]; + reg_pqc_hbw_base_hi pqc_hbw_base_hi[4]; + reg_pqc_size pqc_size[4]; + reg_pqc_pi pqc_pi[4]; + reg_pqc_lbw_wdata pqc_lbw_wdata[4]; + reg_pqc_lbw_base_lo pqc_lbw_base_lo[4]; + reg_pqc_lbw_base_hi pqc_lbw_base_hi[4]; + reg_pqc_cfg pqc_cfg; + reg_pqc_secure_push_ind pqc_secure_push_ind; + uint32_t _pad1172[3]; + reg_arb_mask arb_mask; + reg_arb_cfg_0 arb_cfg_0; + reg_arb_choice_q_push arb_choice_q_push; + reg_arb_wrr_weight arb_wrr_weight[4]; + reg_arb_cfg_1 arb_cfg_1; + reg_arb_mst_avail_cred arb_mst_avail_cred[64]; + uint32_t _pad1472[8]; + reg_arb_mst_cred_inc arb_mst_cred_inc; + reg_arb_mst_choice_push_ofst arb_mst_choice_push_ofst[64]; + uint32_t _pad1764[8]; + reg_arb_slv_master_inc_cred_ofst arb_slv_master_inc_cred_ofst; + reg_arb_mst_slave_en arb_mst_slave_en; + reg_arb_mst_slave_en_1 arb_mst_slave_en_1; + reg_arb_slv_choice_wdt arb_slv_choice_wdt; + reg_arb_slv_id arb_slv_id; + reg_arb_mst_quiet_per arb_mst_quiet_per; + uint32_t _pad1820[10]; + reg_arb_msg_max_inflight arb_msg_max_inflight; + uint32_t _pad1864[3]; + reg_arb_base_lo arb_base_lo; + reg_arb_base_hi arb_base_hi; + uint32_t _pad1884[9]; + reg_arb_state_sts arb_state_sts; + reg_arb_choice_fullness_sts arb_choice_fullness_sts; + reg_arb_msg_sts arb_msg_sts; + reg_arb_slv_choice_q_head arb_slv_choice_q_head; + uint32_t _pad1936[3]; + reg_arb_err_cause arb_err_cause; + reg_arb_err_msg_en arb_err_msg_en; + uint32_t _pad1956[1]; + reg_arb_err_sts_drp arb_err_sts_drp; + uint32_t _pad1964[1]; + reg_arb_mst_cred_sts arb_mst_cred_sts; + reg_arb_mst_cred_sts_1 arb_mst_cred_sts_1; + uint32_t _pad1976[17]; + reg_csmr_strict_prio_cfg csmr_strict_prio_cfg; + reg_arc_cq_cfg0 arc_cq_cfg0; + reg_arc_cq_cfg1 arc_cq_cfg1; + reg_arc_cq_ptr_lo arc_cq_ptr_lo; + reg_arc_cq_ptr_hi arc_cq_ptr_hi; + reg_arc_cq_tsize arc_cq_tsize; + reg_arc_cq_ctl arc_cq_ctl; + uint32_t _pad2072[1]; + reg_arc_cq_ififo_sts arc_cq_ififo_sts; + reg_arc_cq_sts0 arc_cq_sts0; + reg_arc_cq_sts1 arc_cq_sts1; + reg_arc_cq_tsize_sts arc_cq_tsize_sts; + reg_arc_cq_ptr_lo_sts arc_cq_ptr_lo_sts; + reg_arc_cq_ptr_hi_sts arc_cq_ptr_hi_sts; + reg_cp_wr_arc_addr_hi cp_wr_arc_addr_hi; + reg_cp_wr_arc_addr_lo cp_wr_arc_addr_lo; + reg_arc_cq_ififo_msg_base_hi arc_cq_ififo_msg_base_hi; + reg_arc_cq_ififo_msg_base_lo arc_cq_ififo_msg_base_lo; + reg_arc_cq_ctl_msg_base_hi arc_cq_ctl_msg_base_hi; + reg_arc_cq_ctl_msg_base_lo arc_cq_ctl_msg_base_lo; + reg_cq_ififo_msg_base_hi cq_ififo_msg_base_hi; + reg_cq_ififo_msg_base_lo cq_ififo_msg_base_lo; + reg_cq_ctl_msg_base_hi cq_ctl_msg_base_hi; + reg_cq_ctl_msg_base_lo cq_ctl_msg_base_lo; + reg_addr_ovrd addr_ovrd; + reg_cq_ififo_ci cq_ififo_ci[5]; + reg_arc_cq_ififo_ci arc_cq_ififo_ci; + reg_cq_ctl_ci cq_ctl_ci[5]; + reg_arc_cq_ctl_ci arc_cq_ctl_ci; + reg_cp_cfg cp_cfg; + reg_cp_ext_switch cp_ext_switch; + reg_cp_switch_wd_set cp_switch_wd_set; + reg_cp_switch_wd cp_switch_wd; + uint32_t _pad2208[1]; + reg_arc_lb_addr_base_lo arc_lb_addr_base_lo; + reg_arc_lb_addr_base_hi arc_lb_addr_base_hi; + reg_engine_base_addr_hi engine_base_addr_hi; + reg_engine_base_addr_lo engine_base_addr_lo; + reg_engine_addr_range_size engine_addr_range_size; + reg_qm_arc_aux_base_addr_hi qm_arc_aux_base_addr_hi; + reg_qm_arc_aux_base_addr_lo qm_arc_aux_base_addr_lo; + reg_qm_base_addr_hi qm_base_addr_hi; + reg_qm_base_addr_lo qm_base_addr_lo; + reg_arc_pqc_secure_push_ind arc_pqc_secure_push_ind; + uint32_t _pad2252[1]; + reg_pqc_sts_0 pqc_sts_0[4]; + reg_pqc_sts_1 pqc_sts_1[4]; + reg_sei_status sei_status; + reg_sei_mask sei_mask; + uint32_t _pad2296[2]; + block_qman_wr64_base_addr qman_wr64_base_addr0; + block_qman_wr64_base_addr qman_wr64_base_addr1; + block_qman_wr64_base_addr qman_wr64_base_addr2; + block_qman_wr64_base_addr qman_wr64_base_addr3; + block_qman_wr64_base_addr qman_wr64_base_addr4; + block_qman_wr64_base_addr qman_wr64_base_addr5; + block_qman_wr64_base_addr qman_wr64_base_addr6; + block_qman_wr64_base_addr qman_wr64_base_addr7; + block_qman_wr64_base_addr qman_wr64_base_addr8; + block_qman_wr64_base_addr qman_wr64_base_addr9; + block_qman_wr64_base_addr qman_wr64_base_addr10; + block_qman_wr64_base_addr qman_wr64_base_addr11; + block_qman_wr64_base_addr qman_wr64_base_addr12; + block_qman_wr64_base_addr qman_wr64_base_addr13; + block_qman_wr64_base_addr qman_wr64_base_addr14; + block_qman_wr64_base_addr qman_wr64_base_addr15; + uint32_t _pad2432[96]; + block_axuser axuser_secured; + uint32_t _pad2896[12]; + block_axuser axuser_nonsecured; + uint32_t _pad3024[12]; + block_ic_lbw_dbg_cnt dbg_hbw; + uint32_t _pad3160[10]; + block_ic_lbw_dbg_cnt dbg_lbw; + uint32_t _pad3288[10]; + reg_glbl_err_addr_lo glbl_err_addr_lo; + reg_glbl_err_addr_hi glbl_err_addr_hi; + reg_glbl_err_wdata glbl_err_wdata; + uint32_t _pad3340[2]; + reg_l2h_mask_lo l2h_mask_lo; + reg_l2h_mask_hi l2h_mask_hi; + reg_l2h_cmpr_lo l2h_cmpr_lo; + reg_l2h_cmpr_hi l2h_cmpr_hi; + reg_local_range_base local_range_base; + reg_local_range_size local_range_size; + uint32_t _pad3372[1]; + reg_hbw_rd_rate_lim_cfg_1 hbw_rd_rate_lim_cfg_1; + reg_lbw_wr_rate_lim_cfg_0 lbw_wr_rate_lim_cfg_0; + reg_lbw_wr_rate_lim_cfg_1 lbw_wr_rate_lim_cfg_1; + reg_hbw_rd_rate_lim_cfg_0 hbw_rd_rate_lim_cfg_0; + reg_ind_gw_apb_cfg ind_gw_apb_cfg; + reg_ind_gw_apb_wdata ind_gw_apb_wdata; + reg_ind_gw_apb_rdata ind_gw_apb_rdata; + reg_ind_gw_apb_status ind_gw_apb_status; + uint32_t _pad3408[4]; + reg_perf_cnt_free_lo perf_cnt_free_lo; + reg_perf_cnt_free_hi perf_cnt_free_hi; + reg_perf_cnt_idle_lo perf_cnt_idle_lo; + reg_perf_cnt_idle_hi perf_cnt_idle_hi; + reg_perf_cnt_cfg perf_cnt_cfg; + uint32_t _pad3444[3]; + block_qman_cgm cgm; + uint32_t _pad3468[61]; + block_special_regs special; +} block_qman; +#endif + +const offsetVal block_qman_defaults[] = +{ + // offset // value + { 0x1c , 0x3fff , 1 }, // glbl_sts0 + { 0x20 , 0x1 , 1 }, // glbl_sts1 + { 0x38 , 0x3ff7f , 4 }, // glbl_err_msg_en + { 0x48 , 0x1fdff7e , 1 }, // glbl_err_msg_en_4 + { 0x4c , 0x10000 , 1 }, // glbl_prot + { 0xb0 , 0x10001 , 4 }, // pq_cfg1 + { 0xd0 , 0x1 , 4 }, // pq_sts1 + { 0x108 , 0x140014 , 5 }, // cq_cfg1 + { 0x11c , 0x1 , 5 }, // cq_sts1 + { 0x1dc , 0x10 , 5 }, // cq_ififo_sts + { 0x330 , 0x28 , 1 }, // cp_barrier_cfg + { 0x334 , 0xb8d8 , 1 }, // cp_ldma_src_base_lo_offset + { 0x338 , 0xb8e0 , 1 }, // cp_ldma_dst_base_lo_offset + { 0x33c , 0xb8e8 , 1 }, // cp_ldma_tsize_offset + { 0x340 , 0xa150 , 1 }, // cp_cq_ptr_lo_offset_0 + { 0x344 , 0xa160 , 1 }, // cp_cq_ptr_lo_offset_1 + { 0x348 , 0xa170 , 1 }, // cp_cq_ptr_lo_offset_2 + { 0x34c , 0xa180 , 1 }, // cp_cq_ptr_lo_offset_3 + { 0x350 , 0xa190 , 1 }, // cp_cq_ptr_lo_offset_4 + { 0x3a4 , 0x1 , 5 }, // cp_pred + { 0x3b8 , 0xfffffffe , 5 }, // cp_pred_upen + { 0x3cc , 0x20 , 5 }, // cp_dbg_0 + { 0x3e0 , 0x1 , 5 }, // cp_cpdma_up_cred + { 0x47c , 0x1000007f , 4 }, // pqc_lbw_base_hi + { 0x4c0 , 0x40 , 64 }, // arb_mst_avail_cred + { 0x710 , 0x4000 , 1 }, // arb_slv_choice_wdt + { 0x718 , 0x10 , 1 }, // arb_mst_quiet_per + { 0x744 , 0x20 , 1 }, // arb_msg_max_inflight + { 0x780 , 0xffffffff , 1 }, // arb_state_sts + { 0x788 , 0x2 , 1 }, // arb_msg_sts + { 0x7b0 , 0x40 , 1 }, // arb_mst_cred_sts + { 0x7b4 , 0x40 , 1 }, // arb_mst_cred_sts_1 + { 0x804 , 0x140014 , 1 }, // arc_cq_cfg1 + { 0x81c , 0x10 , 1 }, // arc_cq_ififo_sts + { 0x824 , 0x1 , 1 }, // arc_cq_sts1 + { 0x834 , 0x1000007f , 1 }, // cp_wr_arc_addr_hi + { 0x838 , 0xfca08580 , 1 }, // cp_wr_arc_addr_lo + { 0x83c , 0x1000007f , 1 }, // arc_cq_ififo_msg_base_hi + { 0x840 , 0xfca08654 , 1 }, // arc_cq_ififo_msg_base_lo + { 0x844 , 0x1000007f , 1 }, // arc_cq_ctl_msg_base_hi + { 0x848 , 0xfca0865c , 1 }, // arc_cq_ctl_msg_base_lo + { 0x84c , 0x1000007f , 1 }, // cq_ififo_msg_base_hi + { 0x850 , 0xfca08650 , 1 }, // cq_ififo_msg_base_lo + { 0x854 , 0x1000007f , 1 }, // cq_ctl_msg_base_hi + { 0x858 , 0xfca08658 , 1 }, // cq_ctl_msg_base_lo + { 0x89c , 0x4000 , 1 }, // cp_switch_wd + { 0x8a4 , 0xf8000000 , 1 }, // arc_lb_addr_base_lo + { 0x8a8 , 0x1000007f , 1 }, // arc_lb_addr_base_hi + { 0x8ac , 0x1000007f , 1 }, // engine_base_addr_hi + { 0x8b0 , 0xfca00000 , 1 }, // engine_base_addr_lo + { 0x8b4 , 0x40000 , 1 }, // engine_addr_range_size + { 0x8b8 , 0x1000007f , 1 }, // qm_arc_aux_base_addr_hi + { 0x8bc , 0xfca08000 , 1 }, // qm_arc_aux_base_addr_lo + { 0x8c0 , 0x1000007f , 1 }, // qm_base_addr_hi + { 0x8c4 , 0xfca0a000 , 1 }, // qm_base_addr_lo + { 0x8e0 , 0x10 , 4 }, // pqc_sts_1 + { 0xb04 , 0x11 , 1 }, // hb_mmu_bp + { 0xb08 , 0x11 , 1 }, // hb_strong_order + { 0xb20 , 0x11 , 1 }, // hb_emem_cpage + { 0xb30 , 0xffffffff , 1 }, // hb_wr_ovrd_lo + { 0xb34 , 0x3ff , 1 }, // hb_wr_ovrd_hi + { 0xb38 , 0xffffffff , 1 }, // hb_rd_ovrd_lo + { 0xb3c , 0x3ff , 1 }, // hb_rd_ovrd_hi + { 0xb4c , 0xffffffff , 1 }, // lb_ovrd + { 0xb84 , 0x11 , 1 }, // hb_mmu_bp + { 0xb88 , 0x11 , 1 }, // hb_strong_order + { 0xba0 , 0x11 , 1 }, // hb_emem_cpage + { 0xbb0 , 0xffffffff , 1 }, // hb_wr_ovrd_lo + { 0xbb4 , 0x3ff , 1 }, // hb_wr_ovrd_hi + { 0xbb8 , 0xffffffff , 1 }, // hb_rd_ovrd_lo + { 0xbbc , 0x3ff , 1 }, // hb_rd_ovrd_hi + { 0xbcc , 0xffffffff , 1 }, // lb_ovrd + { 0xc40 , 0x100 , 1 }, // otf_over_th_wr_total_req_th + { 0xc44 , 0x100 , 1 }, // otf_over_th_rd_total_req_th + { 0xc48 , 0x100 , 1 }, // otf_over_th_wr_total_cyc_th + { 0xc4c , 0x100 , 1 }, // otf_over_th_rd_total_cyc_th + { 0xcc0 , 0x100 , 1 }, // otf_over_th_wr_total_req_th + { 0xcc4 , 0x100 , 1 }, // otf_over_th_rd_total_req_th + { 0xcc8 , 0x100 , 1 }, // otf_over_th_wr_total_cyc_th + { 0xccc , 0x100 , 1 }, // otf_over_th_rd_total_cyc_th + { 0xd14 , 0xf8000000 , 1 }, // l2h_mask_lo + { 0xd18 , 0xffffffff , 1 }, // l2h_mask_hi + { 0xd1c , 0xf8000000 , 1 }, // l2h_cmpr_lo + { 0xd20 , 0x1000007f , 1 }, // l2h_cmpr_hi + { 0xd24 , 0xa000 , 1 }, // local_range_base + { 0xd28 , 0x1000 , 1 }, // local_range_size + { 0xd70 , 0x1f1f0f , 1 }, // perf_cnt_cfg + { 0xd80 , 0x100080 , 1 }, // cfg + { 0xd84 , 0xf00 , 1 }, // sts + { 0xd88 , 0x10 , 1 }, // cfg1 + { 0xe80 , 0xffffffff , 32 }, // glbl_priv + { 0xf24 , 0xffff , 1 }, // mem_ecc_err_addr + { 0xf44 , 0xffffffff , 1 }, // glbl_err_addr + { 0xf80 , 0xffffffff , 32 }, // glbl_sec +}; + +#ifdef __cplusplus +} /* gaudi2 namespace */ +#endif + +#pragma pack(pop) +#endif /* ASIC_REG_STRUCTS_QMAN_H_ */ diff --git a/external_includes/gaudi2/asic_reg_structs/qman_wr64_base_addr_regs.h b/external_includes/gaudi2/asic_reg_structs/qman_wr64_base_addr_regs.h new file mode 100644 index 0000000..f2a8c7e --- /dev/null +++ b/external_includes/gaudi2/asic_reg_structs/qman_wr64_base_addr_regs.h @@ -0,0 +1,82 @@ +/*********************************** +** This is an auto-generated file ** +** DO NOT EDIT BELOW ** +************************************/ + +#ifndef ASIC_REG_STRUCTS_QMAN_WR64_BASE_ADDR_H_ +#define ASIC_REG_STRUCTS_QMAN_WR64_BASE_ADDR_H_ + +#include +#include "gaudi2_types.h" + +#pragma pack(push, 1) + +#ifdef __cplusplus +namespace gaudi2 { +namespace qman_wr64_base_addr { +#else +# ifndef static_assert +# if defined( __STDC__ ) && defined( __STDC_VERSION__ ) && __STDC_VERSION__ >= 201112L +# define static_assert(...) _Static_assert(__VA_ARGS__) +# else +# define static_assert(...) +# endif +# endif +#endif + +/* + LSB + b'qman wrreg64 base address [31:0]' +*/ +typedef struct reg_lsb { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_lsb; +static_assert((sizeof(struct reg_lsb) == 4), "reg_lsb size is not 32-bit"); +/* + MSB + b'qman wrreg64 base address [63:32]' +*/ +typedef struct reg_msb { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_msb; +static_assert((sizeof(struct reg_msb) == 4), "reg_msb size is not 32-bit"); + +#ifdef __cplusplus +} /* qman_wr64_base_addr namespace */ +#endif + +/* + QMAN_WR64_BASE_ADDR block +*/ + +#ifdef __cplusplus + +struct block_qman_wr64_base_addr { + struct qman_wr64_base_addr::reg_lsb lsb; + struct qman_wr64_base_addr::reg_msb msb; +}; +#else + +typedef struct block_qman_wr64_base_addr { + reg_lsb lsb; + reg_msb msb; +} block_qman_wr64_base_addr; +#endif + + +#ifdef __cplusplus +} /* gaudi2 namespace */ +#endif + +#pragma pack(pop) +#endif /* ASIC_REG_STRUCTS_QMAN_WR64_BASE_ADDR_H_ */ diff --git a/external_includes/gaudi2/asic_reg_structs/sob_glbl_regs.h b/external_includes/gaudi2/asic_reg_structs/sob_glbl_regs.h new file mode 100644 index 0000000..acd21ee --- /dev/null +++ b/external_includes/gaudi2/asic_reg_structs/sob_glbl_regs.h @@ -0,0 +1,449 @@ +/*********************************** +** This is an auto-generated file ** +** DO NOT EDIT BELOW ** +************************************/ + +#ifndef ASIC_REG_STRUCTS_SOB_GLBL_H_ +#define ASIC_REG_STRUCTS_SOB_GLBL_H_ + +#include +#include "gaudi2_types.h" +#include "special_regs_regs.h" + +#pragma pack(push, 1) + +#ifdef __cplusplus +namespace gaudi2 { +namespace sob_glbl { +#else +# ifndef static_assert +# if defined( __STDC__ ) && defined( __STDC_VERSION__ ) && __STDC_VERSION__ >= 201112L +# define static_assert(...) _Static_assert(__VA_ARGS__) +# else +# define static_assert(...) +# endif +# endif +#endif + +/* + SM_SEI_MASK + b'SM System Error Indication Mask' +*/ +typedef struct reg_sm_sei_mask { + union { + struct { + uint32_t so_overflow : 1, + mst_unalign4b : 1, + mst_rsp_err : 1, + _reserved3 : 29; + }; + uint32_t _raw; + }; +} reg_sm_sei_mask; +static_assert((sizeof(struct reg_sm_sei_mask) == 4), "reg_sm_sei_mask size is not 32-bit"); +/* + SM_SEI_CAUSE + b'SM System Error Indication Cause' +*/ +typedef struct reg_sm_sei_cause { + union { + struct { + uint32_t cause : 3, + _reserved4 : 1, + log : 16, + _reserved20 : 12; + }; + uint32_t _raw; + }; +} reg_sm_sei_cause; +static_assert((sizeof(struct reg_sm_sei_cause) == 4), "reg_sm_sei_cause size is not 32-bit"); +/* + L2H_CPMR_L + b'Base address for LBW access (LSB) [units 1MB]' +*/ +typedef struct reg_l2h_cpmr_l { + union { + struct { + uint32_t val : 12, + _reserved12 : 20; + }; + uint32_t _raw; + }; +} reg_l2h_cpmr_l; +static_assert((sizeof(struct reg_l2h_cpmr_l) == 4), "reg_l2h_cpmr_l size is not 32-bit"); +/* + L2H_CPMR_H + b'Base address for LBW access (MSB) [units 1MB]' +*/ +typedef struct reg_l2h_cpmr_h { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_l2h_cpmr_h; +static_assert((sizeof(struct reg_l2h_cpmr_h) == 4), "reg_l2h_cpmr_h size is not 32-bit"); +/* + L2H_MASK_L + b'Address Mask (LSB) for LBW access units 1MB' +*/ +typedef struct reg_l2h_mask_l { + union { + struct { + uint32_t val : 12, + _reserved12 : 20; + }; + uint32_t _raw; + }; +} reg_l2h_mask_l; +static_assert((sizeof(struct reg_l2h_mask_l) == 4), "reg_l2h_mask_l size is not 32-bit"); +/* + L2H_MASK_H + b'Address Mask (MSB ) for LBW access units 1MB' +*/ +typedef struct reg_l2h_mask_h { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_l2h_mask_h; +static_assert((sizeof(struct reg_l2h_mask_h) == 4), "reg_l2h_mask_h size is not 32-bit"); +/* + ASID_SEC + b'ASID (Secure Access)' +*/ +typedef struct reg_asid_sec { + union { + struct { + uint32_t asid : 16, + bp_mmu : 1, + _reserved17 : 15; + }; + uint32_t _raw; + }; +} reg_asid_sec; +static_assert((sizeof(struct reg_asid_sec) == 4), "reg_asid_sec size is not 32-bit"); +/* + ASID_PRIV_ONLY + b'ASID (Privileged Access)' +*/ +typedef struct reg_asid_priv_only { + union { + struct { + uint32_t asid : 16, + bp_mmu : 1, + _reserved17 : 15; + }; + uint32_t _raw; + }; +} reg_asid_priv_only; +static_assert((sizeof(struct reg_asid_priv_only) == 4), "reg_asid_priv_only size is not 32-bit"); +/* + LBW_DELAY + b'LBW Delay' +*/ +typedef struct reg_lbw_delay { + union { + struct { + uint32_t val : 16, + en : 1, + _reserved17 : 15; + }; + uint32_t _raw; + }; +} reg_lbw_delay; +static_assert((sizeof(struct reg_lbw_delay) == 4), "reg_lbw_delay size is not 32-bit"); +/* + PI_SIZE + b'PI increment size (Default is 4)' +*/ +typedef struct reg_pi_size { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_pi_size; +static_assert((sizeof(struct reg_pi_size) == 4), "reg_pi_size size is not 32-bit"); +/* + SOB_ONLY + b'Disable SM HBW access' +*/ +typedef struct reg_sob_only { + union { + struct { + uint32_t en : 1, + _reserved1 : 31; + }; + uint32_t _raw; + }; +} reg_sob_only; +static_assert((sizeof(struct reg_sob_only) == 4), "reg_sob_only size is not 32-bit"); +/* + CQ_INTR + b'CQ Interrupt (Mask & Queue ID)' +*/ +typedef struct reg_cq_intr { + union { + struct { + uint32_t cq_sec_intr : 1, + _reserved8 : 7, + cq_sec_intr_mask : 1, + _reserved16 : 7, + cq_intr_queue_index : 6, + _reserved22 : 10; + }; + uint32_t _raw; + }; +} reg_cq_intr; +static_assert((sizeof(struct reg_cq_intr) == 4), "reg_cq_intr size is not 32-bit"); +/* + ASID_NONE_SEC_PRIV + b'ASID (User)' +*/ +typedef struct reg_asid_none_sec_priv { + union { + struct { + uint32_t asid : 16, + bp_mmu : 1, + _reserved17 : 15; + }; + uint32_t _raw; + }; +} reg_asid_none_sec_priv; +static_assert((sizeof(struct reg_asid_none_sec_priv) == 4), "reg_asid_none_sec_priv size is not 32-bit"); +/* + PI_INC_MODE_SIZE + b'PI INC mode size' +*/ +typedef struct reg_pi_inc_mode_size { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_pi_inc_mode_size; +static_assert((sizeof(struct reg_pi_inc_mode_size) == 4), "reg_pi_inc_mode_size size is not 32-bit"); +/* + CQ_BASE_ADDR_L + b'CQ Base address LSB (Statically set before MON-ARM' +*/ +typedef struct reg_cq_base_addr_l { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_base_addr_l; +static_assert((sizeof(struct reg_cq_base_addr_l) == 4), "reg_cq_base_addr_l size is not 32-bit"); +/* + CQ_BASE_ADDR_H + b'CQ Base address MSB (Statically set before MON-AR' +*/ +typedef struct reg_cq_base_addr_h { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_base_addr_h; +static_assert((sizeof(struct reg_cq_base_addr_h) == 4), "reg_cq_base_addr_h size is not 32-bit"); +/* + CQ_SIZE_LOG2 + b'CQ Size , Always power of 2 , (Statically set befo' +*/ +typedef struct reg_cq_size_log2 { + union { + struct { + uint32_t val : 8, + _reserved8 : 24; + }; + uint32_t _raw; + }; +} reg_cq_size_log2; +static_assert((sizeof(struct reg_cq_size_log2) == 4), "reg_cq_size_log2 size is not 32-bit"); +/* + CQ_PI + b'CQ producer index , incremented by the HW every ti' +*/ +typedef struct reg_cq_pi { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_cq_pi; +static_assert((sizeof(struct reg_cq_pi) == 4), "reg_cq_pi size is not 32-bit"); +/* + CQ_SEC + b'CQ Security' +*/ +typedef struct reg_cq_sec { + union { + struct { + uint32_t sec : 1, + _reserved4 : 3, + priv : 1, + _reserved5 : 27; + }; + uint32_t _raw; + }; +} reg_cq_sec; +static_assert((sizeof(struct reg_cq_sec) == 4), "reg_cq_sec size is not 32-bit"); +/* + LBW_ADDR_L + b'LBW_ADDRESS (LSB) ,Send LBW once CQ was written' +*/ +typedef struct reg_lbw_addr_l { + union { + struct { + uint32_t addrl : 32; + }; + uint32_t _raw; + }; +} reg_lbw_addr_l; +static_assert((sizeof(struct reg_lbw_addr_l) == 4), "reg_lbw_addr_l size is not 32-bit"); +/* + LBW_ADDR_H + b'LBW_ADDRESS (MSB) ,Send LBW once CQ was written' +*/ +typedef struct reg_lbw_addr_h { + union { + struct { + uint32_t addrh : 32; + }; + uint32_t _raw; + }; +} reg_lbw_addr_h; +static_assert((sizeof(struct reg_lbw_addr_h) == 4), "reg_lbw_addr_h size is not 32-bit"); +/* + LBW_DATA + b'LBW payload data to send once CQ was written (HBW)' +*/ +typedef struct reg_lbw_data { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_lbw_data; +static_assert((sizeof(struct reg_lbw_data) == 4), "reg_lbw_data size is not 32-bit"); +/* + CQ_INC_MODE + b'Support 32-Bit & 64-Bit incremental modes' +*/ +typedef struct reg_cq_inc_mode { + union { + struct { + uint32_t mode : 1, + _reserved1 : 31; + }; + uint32_t _raw; + }; +} reg_cq_inc_mode; +static_assert((sizeof(struct reg_cq_inc_mode) == 4), "reg_cq_inc_mode size is not 32-bit"); + +#ifdef __cplusplus +} /* sob_glbl namespace */ +#endif + +/* + SOB_GLBL block +*/ + +#ifdef __cplusplus + +struct block_sob_glbl { + struct sob_glbl::reg_sm_sei_mask sm_sei_mask; + struct sob_glbl::reg_sm_sei_cause sm_sei_cause; + struct sob_glbl::reg_l2h_cpmr_l l2h_cpmr_l; + struct sob_glbl::reg_l2h_cpmr_h l2h_cpmr_h; + uint32_t _pad16[4]; + struct sob_glbl::reg_l2h_mask_l l2h_mask_l; + struct sob_glbl::reg_l2h_mask_h l2h_mask_h; + uint32_t _pad40[2]; + struct sob_glbl::reg_asid_sec asid_sec; + struct sob_glbl::reg_asid_priv_only asid_priv_only; + struct sob_glbl::reg_lbw_delay lbw_delay; + struct sob_glbl::reg_pi_size pi_size; + struct sob_glbl::reg_sob_only sob_only; + struct sob_glbl::reg_cq_intr cq_intr; + struct sob_glbl::reg_asid_none_sec_priv asid_none_sec_priv; + struct sob_glbl::reg_pi_inc_mode_size pi_inc_mode_size; + struct sob_glbl::reg_cq_base_addr_l cq_base_addr_l[64]; + struct sob_glbl::reg_cq_base_addr_h cq_base_addr_h[64]; + struct sob_glbl::reg_cq_size_log2 cq_size_log2[64]; + struct sob_glbl::reg_cq_pi cq_pi[64]; + struct sob_glbl::reg_cq_sec cq_sec[64]; + struct sob_glbl::reg_lbw_addr_l lbw_addr_l[64]; + struct sob_glbl::reg_lbw_addr_h lbw_addr_h[64]; + struct sob_glbl::reg_lbw_data lbw_data[64]; + struct sob_glbl::reg_cq_inc_mode cq_inc_mode[64]; + uint32_t _pad2384[332]; + struct block_special_regs special; +}; +#else + +typedef struct block_sob_glbl { + reg_sm_sei_mask sm_sei_mask; + reg_sm_sei_cause sm_sei_cause; + reg_l2h_cpmr_l l2h_cpmr_l; + reg_l2h_cpmr_h l2h_cpmr_h; + uint32_t _pad16[4]; + reg_l2h_mask_l l2h_mask_l; + reg_l2h_mask_h l2h_mask_h; + uint32_t _pad40[2]; + reg_asid_sec asid_sec; + reg_asid_priv_only asid_priv_only; + reg_lbw_delay lbw_delay; + reg_pi_size pi_size; + reg_sob_only sob_only; + reg_cq_intr cq_intr; + reg_asid_none_sec_priv asid_none_sec_priv; + reg_pi_inc_mode_size pi_inc_mode_size; + reg_cq_base_addr_l cq_base_addr_l[64]; + reg_cq_base_addr_h cq_base_addr_h[64]; + reg_cq_size_log2 cq_size_log2[64]; + reg_cq_pi cq_pi[64]; + reg_cq_sec cq_sec[64]; + reg_lbw_addr_l lbw_addr_l[64]; + reg_lbw_addr_h lbw_addr_h[64]; + reg_lbw_data lbw_data[64]; + reg_cq_inc_mode cq_inc_mode[64]; + uint32_t _pad2384[332]; + block_special_regs special; +} block_sob_glbl; +#endif + +const offsetVal block_sob_glbl_defaults[] = +{ + // offset // value + { 0x8 , 0xf80 , 1 }, // l2h_cpmr_l + { 0xc , 0x1000007f , 1 }, // l2h_cpmr_h + { 0x20 , 0xf80 , 1 }, // l2h_mask_l + { 0x24 , 0xffffffff , 1 }, // l2h_mask_h + { 0x38 , 0xff , 1 }, // lbw_delay + { 0x3c , 0x4 , 1 }, // pi_size + { 0x4c , 0x8 , 1 }, // pi_inc_mode_size + { 0x250 , 0x8 , 64 }, // cq_size_log2 + { 0xe80 , 0xffffffff , 32 }, // glbl_priv + { 0xf24 , 0xffff , 1 }, // mem_ecc_err_addr + { 0xf44 , 0xffffffff , 1 }, // glbl_err_addr + { 0xf80 , 0xffffffff , 32 }, // glbl_sec +}; + +#ifdef __cplusplus +} /* gaudi2 namespace */ +#endif + +#pragma pack(pop) +#endif /* ASIC_REG_STRUCTS_SOB_GLBL_H_ */ diff --git a/external_includes/gaudi2/asic_reg_structs/sob_objs_regs.h b/external_includes/gaudi2/asic_reg_structs/sob_objs_regs.h new file mode 100644 index 0000000..e7da0f3 --- /dev/null +++ b/external_includes/gaudi2/asic_reg_structs/sob_objs_regs.h @@ -0,0 +1,217 @@ +/*********************************** +** This is an auto-generated file ** +** DO NOT EDIT BELOW ** +************************************/ + +#ifndef ASIC_REG_STRUCTS_SOB_OBJS_H_ +#define ASIC_REG_STRUCTS_SOB_OBJS_H_ + +#include +#include "gaudi2_types.h" + +#pragma pack(push, 1) + +#ifdef __cplusplus +namespace gaudi2 { +namespace sob_objs { +#else +# ifndef static_assert +# if defined( __STDC__ ) && defined( __STDC_VERSION__ ) && __STDC_VERSION__ >= 201112L +# define static_assert(...) _Static_assert(__VA_ARGS__) +# else +# define static_assert(...) +# endif +# endif +#endif + +/* + SOB_OBJ + b'Sync object counters' +*/ +typedef struct reg_sob_obj { + union { + struct { + uint32_t val : 15, + _reserved24 : 9, + long_sob : 1, + _reserved30 : 5, + trace_evict : 1, + inc : 1; + }; + uint32_t _raw; + }; +} reg_sob_obj; +static_assert((sizeof(struct reg_sob_obj) == 4), "reg_sob_obj size is not 32-bit"); +/* + MON_PAY_ADDRL + b'Monitor Address (LSB)' +*/ +typedef struct reg_mon_pay_addrl { + union { + struct { + uint32_t addrl : 32; + }; + uint32_t _raw; + }; +} reg_mon_pay_addrl; +static_assert((sizeof(struct reg_mon_pay_addrl) == 4), "reg_mon_pay_addrl size is not 32-bit"); +/* + MON_PAY_ADDRH + b'Monitor Address (MSB)' +*/ +typedef struct reg_mon_pay_addrh { + union { + struct { + uint32_t addrh : 32; + }; + uint32_t _raw; + }; +} reg_mon_pay_addrh; +static_assert((sizeof(struct reg_mon_pay_addrh) == 4), "reg_mon_pay_addrh size is not 32-bit"); +/* + MON_PAY_DATA + b'Monitor Data (Payload)' +*/ +typedef struct reg_mon_pay_data { + union { + struct { + uint32_t data : 32; + }; + uint32_t _raw; + }; +} reg_mon_pay_data; +static_assert((sizeof(struct reg_mon_pay_data) == 4), "reg_mon_pay_data size is not 32-bit"); +/* + MON_ARM + b'Monitor ARM configuration' +*/ +typedef struct reg_mon_arm { + union { + struct { + uint32_t sid : 8, + mask : 8, + sop : 1, + sod : 15; + }; + uint32_t _raw; + }; +} reg_mon_arm; +static_assert((sizeof(struct reg_mon_arm) == 4), "reg_mon_arm size is not 32-bit"); +/* + MON_CONFIG + b'Monitor ARM configuration (Additional..)' +*/ +typedef struct reg_mon_config { + union { + struct { + uint32_t long_sob : 1, + _reserved4 : 3, + cq_en : 1, + wr_num : 2, + _reserved8 : 1, + lbw_en : 1, + _reserved16 : 7, + msb_sid : 4, + _reserved31 : 11, + long_high_group : 1; + }; + uint32_t _raw; + }; +} reg_mon_config; +static_assert((sizeof(struct reg_mon_config) == 4), "reg_mon_config size is not 32-bit"); +/* + MON_STATUS + b'Monitor status' +*/ +typedef struct reg_mon_status { + union { + struct { + uint32_t valid : 1, + pending : 8, + prot : 1, + priv : 1, + _reserved11 : 21; + }; + uint32_t _raw; + }; +} reg_mon_status; +static_assert((sizeof(struct reg_mon_status) == 4), "reg_mon_status size is not 32-bit"); +/* + SM_SEC + b'SM security setting (Secured)' +*/ +typedef struct reg_sm_sec { + union { + struct { + uint32_t sec_vec : 32; + }; + uint32_t _raw; + }; +} reg_sm_sec; +static_assert((sizeof(struct reg_sm_sec) == 4), "reg_sm_sec size is not 32-bit"); +/* + SM_PRIV + b'SM security setting (Privileged)' +*/ +typedef struct reg_sm_priv { + union { + struct { + uint32_t priv : 32; + }; + uint32_t _raw; + }; +} reg_sm_priv; +static_assert((sizeof(struct reg_sm_priv) == 4), "reg_sm_priv size is not 32-bit"); + +#ifdef __cplusplus +} /* sob_objs namespace */ +#endif + +/* + SOB_OBJS block +*/ + +#ifdef __cplusplus + +struct block_sob_objs { + struct sob_objs::reg_sob_obj sob_obj[8192]; + struct sob_objs::reg_mon_pay_addrl mon_pay_addrl[2048]; + struct sob_objs::reg_mon_pay_addrh mon_pay_addrh[2048]; + struct sob_objs::reg_mon_pay_data mon_pay_data[2048]; + struct sob_objs::reg_mon_arm mon_arm[2048]; + struct sob_objs::reg_mon_config mon_config[2048]; + struct sob_objs::reg_mon_status mon_status[2048]; + struct sob_objs::reg_sm_sec sm_sec[640]; + uint32_t _pad84480[384]; + struct sob_objs::reg_sm_priv sm_priv[640]; +}; +#else + +typedef struct block_sob_objs { + reg_sob_obj sob_obj[8192]; + reg_mon_pay_addrl mon_pay_addrl[2048]; + reg_mon_pay_addrh mon_pay_addrh[2048]; + reg_mon_pay_data mon_pay_data[2048]; + reg_mon_arm mon_arm[2048]; + reg_mon_config mon_config[2048]; + reg_mon_status mon_status[2048]; + reg_sm_sec sm_sec[640]; + uint32_t _pad84480[384]; + reg_sm_priv sm_priv[640]; +} block_sob_objs; +#endif + +const offsetVal block_sob_objs_defaults[] = +{ + // offset // value + { 0x12000, 0x200 , 2048 }, // mon_status + { 0x14000, 0xffffffff , 640 }, // sm_sec + { 0x15000, 0xffffffff , 640 }, // sm_priv +}; + +#ifdef __cplusplus +} /* gaudi2 namespace */ +#endif + +#pragma pack(pop) +#endif /* ASIC_REG_STRUCTS_SOB_OBJS_H_ */ diff --git a/external_includes/gaudi2/asic_reg_structs/special_regs_regs.h b/external_includes/gaudi2/asic_reg_structs/special_regs_regs.h new file mode 100644 index 0000000..e7462e8 --- /dev/null +++ b/external_includes/gaudi2/asic_reg_structs/special_regs_regs.h @@ -0,0 +1,344 @@ +/*********************************** +** This is an auto-generated file ** +** DO NOT EDIT BELOW ** +************************************/ + +#ifndef ASIC_REG_STRUCTS_SPECIAL_REGS_H_ +#define ASIC_REG_STRUCTS_SPECIAL_REGS_H_ + +#include +#include "gaudi2_types.h" + +#pragma pack(push, 1) + +#ifdef __cplusplus +namespace gaudi2 { +namespace special_regs { +#else +# ifndef static_assert +# if defined( __STDC__ ) && defined( __STDC_VERSION__ ) && __STDC_VERSION__ >= 201112L +# define static_assert(...) _Static_assert(__VA_ARGS__) +# else +# define static_assert(...) +# endif +# endif +#endif + +/* + GLBL_PRIV + b'Privilege configuration' +*/ +typedef struct reg_glbl_priv { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_glbl_priv; +static_assert((sizeof(struct reg_glbl_priv) == 4), "reg_glbl_priv size is not 32-bit"); +/* + MEM_GW_DATA + b'Memory gateway read/write data' +*/ +typedef struct reg_mem_gw_data { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_mem_gw_data; +static_assert((sizeof(struct reg_mem_gw_data) == 4), "reg_mem_gw_data size is not 32-bit"); +/* + MEM_GW_REQ + b'Memory gateway configuration and address' +*/ +typedef struct reg_mem_gw_req { + union { + struct { + uint32_t addr : 22, + mid : 8, + wnr : 1, + vld : 1; + }; + uint32_t _raw; + }; +} reg_mem_gw_req; +static_assert((sizeof(struct reg_mem_gw_req) == 4), "reg_mem_gw_req size is not 32-bit"); +/* + MEM_NUMOF + b'Number of memories of the block' +*/ +typedef struct reg_mem_numof { + union { + struct { + uint32_t val : 8, + _reserved8 : 24; + }; + uint32_t _raw; + }; +} reg_mem_numof; +static_assert((sizeof(struct reg_mem_numof) == 4), "reg_mem_numof size is not 32-bit"); +/* + MEM_ECC_SEL + b'Select memory to access regarding init or ecc' +*/ +typedef struct reg_mem_ecc_sel { + union { + struct { + uint32_t val : 8, + _reserved8 : 24; + }; + uint32_t _raw; + }; +} reg_mem_ecc_sel; +static_assert((sizeof(struct reg_mem_ecc_sel) == 4), "reg_mem_ecc_sel size is not 32-bit"); +/* + MEM_ECC_CTL + b'Memory control ECC_INJ ECC_CLR' +*/ +typedef struct reg_mem_ecc_ctl { + union { + struct { + uint32_t serr_inj : 1, + derr_inj : 1, + serr_clr : 1, + derr_clr : 1, + _reserved4 : 28; + }; + uint32_t _raw; + }; +} reg_mem_ecc_ctl; +static_assert((sizeof(struct reg_mem_ecc_ctl) == 4), "reg_mem_ecc_ctl size is not 32-bit"); +/* + MEM_ECC_ERR_MASK + b'SERR DERR mask per memory' +*/ +typedef struct reg_mem_ecc_err_mask { + union { + struct { + uint32_t serr : 1, + derr : 1, + _reserved2 : 30; + }; + uint32_t _raw; + }; +} reg_mem_ecc_err_mask; +static_assert((sizeof(struct reg_mem_ecc_err_mask) == 4), "reg_mem_ecc_err_mask size is not 32-bit"); +/* + MEM_ECC_GLBL_ERR_MASK + b'Global SERR and DERR mask' +*/ +typedef struct reg_mem_ecc_glbl_err_mask { + union { + struct { + uint32_t serr : 1, + derr : 1, + _reserved2 : 30; + }; + uint32_t _raw; + }; +} reg_mem_ecc_glbl_err_mask; +static_assert((sizeof(struct reg_mem_ecc_glbl_err_mask) == 4), "reg_mem_ecc_glbl_err_mask size is not 32-bit"); +/* + MEM_ECC_ERR_STS + b'Captured syndrom on ECC error selected by MEM_SEL' +*/ +typedef struct reg_mem_ecc_err_sts { + union { + struct { + uint32_t synd : 16, + serr : 1, + derr : 1, + _reserved18 : 14; + }; + uint32_t _raw; + }; +} reg_mem_ecc_err_sts; +static_assert((sizeof(struct reg_mem_ecc_err_sts) == 4), "reg_mem_ecc_err_sts size is not 32-bit"); +/* + MEM_ECC_ERR_ADDR + b'Captured address on ECC error selected by MEM_SEL' +*/ +typedef struct reg_mem_ecc_err_addr { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_mem_ecc_err_addr; +static_assert((sizeof(struct reg_mem_ecc_err_addr) == 4), "reg_mem_ecc_err_addr size is not 32-bit"); +/* + MEM_RM + b'Control memory read margin' +*/ +typedef struct reg_mem_rm { + union { + struct { + uint32_t val : 30, + _reserved30 : 2; + }; + uint32_t _raw; + }; +} reg_mem_rm; +static_assert((sizeof(struct reg_mem_rm) == 4), "reg_mem_rm size is not 32-bit"); +/* + GLBL_ERR_MASK + b'Mask APB from returning bus error' +*/ +typedef struct reg_glbl_err_mask { + union { + struct { + uint32_t apb_priv_rd : 1, + apb_sec_rd : 1, + apb_unmapped_rd : 1, + apb_priv_wr : 1, + apb_sec_wr : 1, + apb_unmapped_wr : 1, + _reserved16 : 10, + ext_sec_wr : 1, + ext_unmapped_wr : 1, + _reserved18 : 14; + }; + uint32_t _raw; + }; +} reg_glbl_err_mask; +static_assert((sizeof(struct reg_glbl_err_mask) == 4), "reg_glbl_err_mask size is not 32-bit"); +/* + GLBL_ERR_ADDR + b'Captured address on security or unmapped violation' +*/ +typedef struct reg_glbl_err_addr { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_glbl_err_addr; +static_assert((sizeof(struct reg_glbl_err_addr) == 4), "reg_glbl_err_addr size is not 32-bit"); +/* + GLBL_ERR_CAUSE + b'Error cause register' +*/ +typedef struct reg_glbl_err_cause { + union { + struct { + uint32_t apb_priv_rd : 1, + apb_sec_rd : 1, + apb_unmapped_rd : 1, + apb_priv_wr : 1, + apb_sec_wr : 1, + apb_unmapped_wr : 1, + _reserved16 : 10, + ext_sec_wr : 1, + ext_unmapped_wr : 1, + _reserved18 : 14; + }; + uint32_t _raw; + }; +} reg_glbl_err_cause; +static_assert((sizeof(struct reg_glbl_err_cause) == 4), "reg_glbl_err_cause size is not 32-bit"); +/* + GLBL_SPARE + b'Spare registers' +*/ +typedef struct reg_glbl_spare { + union { + struct { + uint32_t r : 32; + }; + uint32_t _raw; + }; +} reg_glbl_spare; +static_assert((sizeof(struct reg_glbl_spare) == 4), "reg_glbl_spare size is not 32-bit"); +/* + GLBL_SEC + b'Security configuration' +*/ +typedef struct reg_glbl_sec { + union { + struct { + uint32_t val : 32; + }; + uint32_t _raw; + }; +} reg_glbl_sec; +static_assert((sizeof(struct reg_glbl_sec) == 4), "reg_glbl_sec size is not 32-bit"); + +#ifdef __cplusplus +} /* special_regs namespace */ +#endif + +/* + SPECIAL_REGS block +*/ + +#ifdef __cplusplus + +struct block_special_regs { + struct special_regs::reg_glbl_priv glbl_priv[32]; + struct special_regs::reg_mem_gw_data mem_gw_data; + struct special_regs::reg_mem_gw_req mem_gw_req; + uint32_t _pad136[1]; + struct special_regs::reg_mem_numof mem_numof; + struct special_regs::reg_mem_ecc_sel mem_ecc_sel; + struct special_regs::reg_mem_ecc_ctl mem_ecc_ctl; + struct special_regs::reg_mem_ecc_err_mask mem_ecc_err_mask; + struct special_regs::reg_mem_ecc_glbl_err_mask mem_ecc_glbl_err_mask; + struct special_regs::reg_mem_ecc_err_sts mem_ecc_err_sts; + struct special_regs::reg_mem_ecc_err_addr mem_ecc_err_addr; + struct special_regs::reg_mem_rm mem_rm; + uint32_t _pad172[5]; + struct special_regs::reg_glbl_err_mask glbl_err_mask; + struct special_regs::reg_glbl_err_addr glbl_err_addr; + struct special_regs::reg_glbl_err_cause glbl_err_cause; + uint32_t _pad204[5]; + struct special_regs::reg_glbl_spare glbl_spare[4]; + uint32_t _pad240[4]; + struct special_regs::reg_glbl_sec glbl_sec[32]; +}; +#else + +typedef struct block_special_regs { + reg_glbl_priv glbl_priv[32]; + reg_mem_gw_data mem_gw_data; + reg_mem_gw_req mem_gw_req; + uint32_t _pad136[1]; + reg_mem_numof mem_numof; + reg_mem_ecc_sel mem_ecc_sel; + reg_mem_ecc_ctl mem_ecc_ctl; + reg_mem_ecc_err_mask mem_ecc_err_mask; + reg_mem_ecc_glbl_err_mask mem_ecc_glbl_err_mask; + reg_mem_ecc_err_sts mem_ecc_err_sts; + reg_mem_ecc_err_addr mem_ecc_err_addr; + reg_mem_rm mem_rm; + uint32_t _pad172[5]; + reg_glbl_err_mask glbl_err_mask; + reg_glbl_err_addr glbl_err_addr; + reg_glbl_err_cause glbl_err_cause; + uint32_t _pad204[5]; + reg_glbl_spare glbl_spare[4]; + uint32_t _pad240[4]; + reg_glbl_sec glbl_sec[32]; +} block_special_regs; +#endif + +const offsetVal block_special_regs_defaults[] = +{ + // offset // value + { 0x0 , 0xffffffff , 32 }, // glbl_priv + { 0xa4 , 0xffff , 1 }, // mem_ecc_err_addr + { 0xc4 , 0xffffffff , 1 }, // glbl_err_addr + { 0x100 , 0xffffffff , 32 }, // glbl_sec +}; + +#ifdef __cplusplus +} /* gaudi2 namespace */ +#endif + +#pragma pack(pop) +#endif /* ASIC_REG_STRUCTS_SPECIAL_REGS_H_ */ diff --git a/external_includes/gaudi2/asic_reg_structs/sync_object_regs.h b/external_includes/gaudi2/asic_reg_structs/sync_object_regs.h new file mode 100644 index 0000000..b6298ee --- /dev/null +++ b/external_includes/gaudi2/asic_reg_structs/sync_object_regs.h @@ -0,0 +1,84 @@ +/*********************************** +** This is an auto-generated file ** +** DO NOT EDIT BELOW ** +************************************/ + +#ifndef ASIC_REG_STRUCTS_SYNC_OBJECT_H_ +#define ASIC_REG_STRUCTS_SYNC_OBJECT_H_ + +#include +#include "gaudi2_types.h" + +#pragma pack(push, 1) + +#ifdef __cplusplus +namespace gaudi2 { +namespace sync_object { +#else +# ifndef static_assert +# if defined( __STDC__ ) && defined( __STDC_VERSION__ ) && __STDC_VERSION__ >= 201112L +# define static_assert(...) _Static_assert(__VA_ARGS__) +# else +# define static_assert(...) +# endif +# endif +#endif + +/* + MESSAGE + b'Sync Object message configurations' +*/ +typedef struct reg_message { + union { + struct { + uint32_t so_write_value : 16, + rsv : 13, + so_operation : 3; + }; + uint32_t _raw; + }; +} reg_message; +static_assert((sizeof(struct reg_message) == 4), "reg_message size is not 32-bit"); +/* + ADDR + b'Sync Object address configuration' +*/ +typedef struct reg_addr { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_addr; +static_assert((sizeof(struct reg_addr) == 4), "reg_addr size is not 32-bit"); + +#ifdef __cplusplus +} /* sync_object namespace */ +#endif + +/* + SYNC_OBJECT block +*/ + +#ifdef __cplusplus + +struct block_sync_object { + struct sync_object::reg_message message; + struct sync_object::reg_addr addr; +}; +#else + +typedef struct block_sync_object { + reg_message message; + reg_addr addr; +} block_sync_object; +#endif + + +#ifdef __cplusplus +} /* gaudi2 namespace */ +#endif + +#pragma pack(pop) +#endif /* ASIC_REG_STRUCTS_SYNC_OBJECT_H_ */ diff --git a/external_includes/gaudi2/asic_reg_structs/tpc_non_tensor_descriptor_regs.h b/external_includes/gaudi2/asic_reg_structs/tpc_non_tensor_descriptor_regs.h new file mode 100644 index 0000000..f3b4659 --- /dev/null +++ b/external_includes/gaudi2/asic_reg_structs/tpc_non_tensor_descriptor_regs.h @@ -0,0 +1,414 @@ +/*********************************** +** This is an auto-generated file ** +** DO NOT EDIT BELOW ** +************************************/ + +#ifndef ASIC_REG_STRUCTS_TPC_NON_TENSOR_DESCRIPTOR_H_ +#define ASIC_REG_STRUCTS_TPC_NON_TENSOR_DESCRIPTOR_H_ + +#include +#include "gaudi2_types.h" + +#pragma pack(push, 1) + +#ifdef __cplusplus +namespace gaudi2 { +namespace tpc_non_tensor_descriptor { +#else +# ifndef static_assert +# if defined( __STDC__ ) && defined( __STDC_VERSION__ ) && __STDC_VERSION__ >= 201112L +# define static_assert(...) _Static_assert(__VA_ARGS__) +# else +# define static_assert(...) +# endif +# endif +#endif + +/* + KERNEL_BASE_ADDRESS_LOW + b'lower 32 bits of the kernel base address' +*/ +typedef struct reg_kernel_base_address_low { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_kernel_base_address_low; +static_assert((sizeof(struct reg_kernel_base_address_low) == 4), "reg_kernel_base_address_low size is not 32-bit"); +/* + KERNEL_BASE_ADDRESS_HIGH + b'higher 32 bits of the kernel base address' +*/ +typedef struct reg_kernel_base_address_high { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_kernel_base_address_high; +static_assert((sizeof(struct reg_kernel_base_address_high) == 4), "reg_kernel_base_address_high size is not 32-bit"); +/* + TID_BASE_DIM_0 + b'init value for IRF0[0]' +*/ +typedef struct reg_tid_base_dim_0 { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_tid_base_dim_0; +static_assert((sizeof(struct reg_tid_base_dim_0) == 4), "reg_tid_base_dim_0 size is not 32-bit"); +/* + TID_SIZE_DIM_0 + b'init value for IRF1[0]' +*/ +typedef struct reg_tid_size_dim_0 { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_tid_size_dim_0; +static_assert((sizeof(struct reg_tid_size_dim_0) == 4), "reg_tid_size_dim_0 size is not 32-bit"); +/* + TID_BASE_DIM_1 + b'init value for IRF0[1]' +*/ +typedef struct reg_tid_base_dim_1 { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_tid_base_dim_1; +static_assert((sizeof(struct reg_tid_base_dim_1) == 4), "reg_tid_base_dim_1 size is not 32-bit"); +/* + TID_SIZE_DIM_1 + b'init value for IRF1[1]' +*/ +typedef struct reg_tid_size_dim_1 { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_tid_size_dim_1; +static_assert((sizeof(struct reg_tid_size_dim_1) == 4), "reg_tid_size_dim_1 size is not 32-bit"); +/* + TID_BASE_DIM_2 + b'init value for IRF0[2]' +*/ +typedef struct reg_tid_base_dim_2 { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_tid_base_dim_2; +static_assert((sizeof(struct reg_tid_base_dim_2) == 4), "reg_tid_base_dim_2 size is not 32-bit"); +/* + TID_SIZE_DIM_2 + b'init value for IRF1[2]' +*/ +typedef struct reg_tid_size_dim_2 { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_tid_size_dim_2; +static_assert((sizeof(struct reg_tid_size_dim_2) == 4), "reg_tid_size_dim_2 size is not 32-bit"); +/* + TID_BASE_DIM_3 + b'init value for IRF0[3]' +*/ +typedef struct reg_tid_base_dim_3 { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_tid_base_dim_3; +static_assert((sizeof(struct reg_tid_base_dim_3) == 4), "reg_tid_base_dim_3 size is not 32-bit"); +/* + TID_SIZE_DIM_3 + b'init value for IRF1[3]' +*/ +typedef struct reg_tid_size_dim_3 { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_tid_size_dim_3; +static_assert((sizeof(struct reg_tid_size_dim_3) == 4), "reg_tid_size_dim_3 size is not 32-bit"); +/* + TID_BASE_DIM_4 + b'init value for IRF0[4]' +*/ +typedef struct reg_tid_base_dim_4 { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_tid_base_dim_4; +static_assert((sizeof(struct reg_tid_base_dim_4) == 4), "reg_tid_base_dim_4 size is not 32-bit"); +/* + TID_SIZE_DIM_4 + b'init value for IRF1[4]' +*/ +typedef struct reg_tid_size_dim_4 { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_tid_size_dim_4; +static_assert((sizeof(struct reg_tid_size_dim_4) == 4), "reg_tid_size_dim_4 size is not 32-bit"); +/* + KERNEL_CONFIG + b'a few cfg (small VLM, num valid SRFs,IRF44,...)' +*/ +typedef struct reg_kernel_config { + union { + struct { + uint32_t small_vlm : 1, + aso_evict_l0 : 1, + num_valid_srfs : 6, + rd_rate_limit_rst_token : 8, + wr_rate_limit_rst_token : 8, + irf_32bit_compatibility : 1, + _reserved25 : 7; + }; + uint32_t _raw; + }; +} reg_kernel_config; +static_assert((sizeof(struct reg_kernel_config) == 4), "reg_kernel_config size is not 32-bit"); +/* + KERNEL_ID + b'used by profiler' +*/ +typedef struct reg_kernel_id { + union { + struct { + uint32_t v : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_kernel_id; +static_assert((sizeof(struct reg_kernel_id) == 4), "reg_kernel_id size is not 32-bit"); +/* + POWER_LOOP + b'en/dis messages to ARC at start/end descriptor' +*/ +typedef struct reg_power_loop { + union { + struct { + uint32_t start_en : 1, + end_en : 1, + _reserved4 : 2, + payload : 8, + _reserved12 : 20; + }; + uint32_t _raw; + }; +} reg_power_loop; +static_assert((sizeof(struct reg_power_loop) == 4), "reg_power_loop size is not 32-bit"); +/* + SRF + b'the 32 register which should be preloaded into SRF' +*/ +typedef struct reg_srf { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_srf; +static_assert((sizeof(struct reg_srf) == 4), "reg_srf size is not 32-bit"); +/* + KERNEL_ID_INC + b'by how much to increment kernel_id (auto_inc)' +*/ +typedef struct reg_kernel_id_inc { + union { + struct { + uint32_t v : 8, + _reserved8 : 24; + }; + uint32_t _raw; + }; +} reg_kernel_id_inc; +static_assert((sizeof(struct reg_kernel_id_inc) == 4), "reg_kernel_id_inc size is not 32-bit"); +/* + TID_BASE_SIZE_HIGH_DIM_0 + b'12 upper bits init value for IRF0[0]/IRF1[0]' +*/ +typedef struct reg_tid_base_size_high_dim_0 { + union { + struct { + uint32_t base_high : 12, + _reserved16 : 4, + size_high : 12, + _reserved28 : 4; + }; + uint32_t _raw; + }; +} reg_tid_base_size_high_dim_0; +static_assert((sizeof(struct reg_tid_base_size_high_dim_0) == 4), "reg_tid_base_size_high_dim_0 size is not 32-bit"); +/* + TID_BASE_SIZE_HIGH_DIM_1 + b'12 upper bits init value for IRF0[1]/IRF1[1]' +*/ +typedef struct reg_tid_base_size_high_dim_1 { + union { + struct { + uint32_t base_high : 12, + _reserved16 : 4, + size_high : 12, + _reserved28 : 4; + }; + uint32_t _raw; + }; +} reg_tid_base_size_high_dim_1; +static_assert((sizeof(struct reg_tid_base_size_high_dim_1) == 4), "reg_tid_base_size_high_dim_1 size is not 32-bit"); +/* + TID_BASE_SIZE_HIGH_DIM_2 + b'12 upper bits init value for IRF0[2]/IRF1[2]' +*/ +typedef struct reg_tid_base_size_high_dim_2 { + union { + struct { + uint32_t base_high : 12, + _reserved16 : 4, + size_high : 12, + _reserved28 : 4; + }; + uint32_t _raw; + }; +} reg_tid_base_size_high_dim_2; +static_assert((sizeof(struct reg_tid_base_size_high_dim_2) == 4), "reg_tid_base_size_high_dim_2 size is not 32-bit"); +/* + TID_BASE_SIZE_HIGH_DIM_3 + b'12 upper bits init value for IRF0[3]/IRF1[3]' +*/ +typedef struct reg_tid_base_size_high_dim_3 { + union { + struct { + uint32_t base_high : 12, + _reserved16 : 4, + size_high : 12, + _reserved28 : 4; + }; + uint32_t _raw; + }; +} reg_tid_base_size_high_dim_3; +static_assert((sizeof(struct reg_tid_base_size_high_dim_3) == 4), "reg_tid_base_size_high_dim_3 size is not 32-bit"); +/* + TID_BASE_SIZE_HIGH_DIM_4 + b'12 upper bits init value for IRF0[4]/IRF1[4]' +*/ +typedef struct reg_tid_base_size_high_dim_4 { + union { + struct { + uint32_t base_high : 12, + _reserved16 : 4, + size_high : 12, + _reserved28 : 4; + }; + uint32_t _raw; + }; +} reg_tid_base_size_high_dim_4; +static_assert((sizeof(struct reg_tid_base_size_high_dim_4) == 4), "reg_tid_base_size_high_dim_4 size is not 32-bit"); + +#ifdef __cplusplus +} /* tpc_non_tensor_descriptor namespace */ +#endif + +/* + TPC_NON_TENSOR_DESCRIPTOR block +*/ + +#ifdef __cplusplus + +struct block_tpc_non_tensor_descriptor { + struct tpc_non_tensor_descriptor::reg_kernel_base_address_low kernel_base_address_low; + struct tpc_non_tensor_descriptor::reg_kernel_base_address_high kernel_base_address_high; + struct tpc_non_tensor_descriptor::reg_tid_base_dim_0 tid_base_dim_0; + struct tpc_non_tensor_descriptor::reg_tid_size_dim_0 tid_size_dim_0; + struct tpc_non_tensor_descriptor::reg_tid_base_dim_1 tid_base_dim_1; + struct tpc_non_tensor_descriptor::reg_tid_size_dim_1 tid_size_dim_1; + struct tpc_non_tensor_descriptor::reg_tid_base_dim_2 tid_base_dim_2; + struct tpc_non_tensor_descriptor::reg_tid_size_dim_2 tid_size_dim_2; + struct tpc_non_tensor_descriptor::reg_tid_base_dim_3 tid_base_dim_3; + struct tpc_non_tensor_descriptor::reg_tid_size_dim_3 tid_size_dim_3; + struct tpc_non_tensor_descriptor::reg_tid_base_dim_4 tid_base_dim_4; + struct tpc_non_tensor_descriptor::reg_tid_size_dim_4 tid_size_dim_4; + struct tpc_non_tensor_descriptor::reg_kernel_config kernel_config; + struct tpc_non_tensor_descriptor::reg_kernel_id kernel_id; + struct tpc_non_tensor_descriptor::reg_power_loop power_loop; + struct tpc_non_tensor_descriptor::reg_srf srf[32]; + struct tpc_non_tensor_descriptor::reg_kernel_id_inc kernel_id_inc; + struct tpc_non_tensor_descriptor::reg_tid_base_size_high_dim_0 tid_base_size_high_dim_0; + struct tpc_non_tensor_descriptor::reg_tid_base_size_high_dim_1 tid_base_size_high_dim_1; + struct tpc_non_tensor_descriptor::reg_tid_base_size_high_dim_2 tid_base_size_high_dim_2; + struct tpc_non_tensor_descriptor::reg_tid_base_size_high_dim_3 tid_base_size_high_dim_3; + struct tpc_non_tensor_descriptor::reg_tid_base_size_high_dim_4 tid_base_size_high_dim_4; +}; +#else + +typedef struct block_tpc_non_tensor_descriptor { + reg_kernel_base_address_low kernel_base_address_low; + reg_kernel_base_address_high kernel_base_address_high; + reg_tid_base_dim_0 tid_base_dim_0; + reg_tid_size_dim_0 tid_size_dim_0; + reg_tid_base_dim_1 tid_base_dim_1; + reg_tid_size_dim_1 tid_size_dim_1; + reg_tid_base_dim_2 tid_base_dim_2; + reg_tid_size_dim_2 tid_size_dim_2; + reg_tid_base_dim_3 tid_base_dim_3; + reg_tid_size_dim_3 tid_size_dim_3; + reg_tid_base_dim_4 tid_base_dim_4; + reg_tid_size_dim_4 tid_size_dim_4; + reg_kernel_config kernel_config; + reg_kernel_id kernel_id; + reg_power_loop power_loop; + reg_srf srf[32]; + reg_kernel_id_inc kernel_id_inc; + reg_tid_base_size_high_dim_0 tid_base_size_high_dim_0; + reg_tid_base_size_high_dim_1 tid_base_size_high_dim_1; + reg_tid_base_size_high_dim_2 tid_base_size_high_dim_2; + reg_tid_base_size_high_dim_3 tid_base_size_high_dim_3; + reg_tid_base_size_high_dim_4 tid_base_size_high_dim_4; +} block_tpc_non_tensor_descriptor; +#endif + +const offsetVal block_tpc_non_tensor_descriptor_defaults[] = +{ + // offset // value + { 0x30 , 0x1040482 , 1 }, // kernel_config +}; + +#ifdef __cplusplus +} /* gaudi2 namespace */ +#endif + +#pragma pack(pop) +#endif /* ASIC_REG_STRUCTS_TPC_NON_TENSOR_DESCRIPTOR_H_ */ diff --git a/external_includes/gaudi2/asic_reg_structs/tpc_regs.h b/external_includes/gaudi2/asic_reg_structs/tpc_regs.h new file mode 100644 index 0000000..c770618 --- /dev/null +++ b/external_includes/gaudi2/asic_reg_structs/tpc_regs.h @@ -0,0 +1,1524 @@ +/*********************************** +** This is an auto-generated file ** +** DO NOT EDIT BELOW ** +************************************/ + +#ifndef ASIC_REG_STRUCTS_TPC_H_ +#define ASIC_REG_STRUCTS_TPC_H_ + +#include +#include "gaudi2_types.h" +#include "axuser_regs.h" +#include "special_regs_regs.h" +#include "sync_object_regs.h" +#include "tpc_non_tensor_descriptor_regs.h" +#include "tpc_tensor_regs.h" + +#pragma pack(push, 1) + +#ifdef __cplusplus +namespace gaudi2 { +namespace tpc { +#else +# ifndef static_assert +# if defined( __STDC__ ) && defined( __STDC_VERSION__ ) && __STDC_VERSION__ >= 201112L +# define static_assert(...) _Static_assert(__VA_ARGS__) +# else +# define static_assert(...) +# endif +# endif +#endif + +/* + TPC_COUNT + b"number of TPC's" +*/ +typedef struct reg_tpc_count { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_tpc_count; +static_assert((sizeof(struct reg_tpc_count) == 4), "reg_tpc_count size is not 32-bit"); +/* + TPC_ID + b'TPC unique ID' +*/ +typedef struct reg_tpc_id { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_tpc_id; +static_assert((sizeof(struct reg_tpc_id) == 4), "reg_tpc_id size is not 32-bit"); +/* + STALL_ON_ERR + b'stall TPC when interrupt occurs' +*/ +typedef struct reg_stall_on_err { + union { + struct { + uint32_t v : 1, + _reserved1 : 31; + }; + uint32_t _raw; + }; +} reg_stall_on_err; +static_assert((sizeof(struct reg_stall_on_err) == 4), "reg_stall_on_err size is not 32-bit"); +/* + CLK_EN + b'chicken bits: disable waking up HBW upon LBW/DBG' +*/ +typedef struct reg_clk_en { + union { + struct { + uint32_t lbw_cfg_dis : 1, + _reserved4 : 3, + dbg_cfg_dis : 1, + _reserved5 : 27; + }; + uint32_t _raw; + }; +} reg_clk_en; +static_assert((sizeof(struct reg_clk_en) == 4), "reg_clk_en size is not 32-bit"); +/* + IQ_RL_EN + b'Tpc IQ rate limiter enable' +*/ +typedef struct reg_iq_rl_en { + union { + struct { + uint32_t v : 1, + _reserved1 : 31; + }; + uint32_t _raw; + }; +} reg_iq_rl_en; +static_assert((sizeof(struct reg_iq_rl_en) == 4), "reg_iq_rl_en size is not 32-bit"); +/* + IQ_RL_SAT + b'Tpc IQ rate limiter saturation value' +*/ +typedef struct reg_iq_rl_sat { + union { + struct { + uint32_t v : 8, + _reserved8 : 24; + }; + uint32_t _raw; + }; +} reg_iq_rl_sat; +static_assert((sizeof(struct reg_iq_rl_sat) == 4), "reg_iq_rl_sat size is not 32-bit"); +/* + IQ_RL_RST_TOKEN + b'Tpc IQ rate limiter reset token' +*/ +typedef struct reg_iq_rl_rst_token { + union { + struct { + uint32_t v : 8, + _reserved8 : 24; + }; + uint32_t _raw; + }; +} reg_iq_rl_rst_token; +static_assert((sizeof(struct reg_iq_rl_rst_token) == 4), "reg_iq_rl_rst_token size is not 32-bit"); +/* + IQ_RL_TIMEOUT + b'Tpc IQ rate limiter timeout' +*/ +typedef struct reg_iq_rl_timeout { + union { + struct { + uint32_t v : 8, + _reserved8 : 24; + }; + uint32_t _raw; + }; +} reg_iq_rl_timeout; +static_assert((sizeof(struct reg_iq_rl_timeout) == 4), "reg_iq_rl_timeout size is not 32-bit"); +/* + TSB_CFG_MTRR_2 + b'TSB MTRR cfg2' +*/ +typedef struct reg_tsb_cfg_mtrr_2 { + union { + struct { + uint32_t phy_base_add_lo : 24, + _reserved24 : 8; + }; + uint32_t _raw; + }; +} reg_tsb_cfg_mtrr_2; +static_assert((sizeof(struct reg_tsb_cfg_mtrr_2) == 4), "reg_tsb_cfg_mtrr_2 size is not 32-bit"); +/* + IQ_LBW_CLK_EN + b'use lbw_clk bypass for iq' +*/ +typedef struct reg_iq_lbw_clk_en { + union { + struct { + uint32_t v : 1, + _reserved1 : 31; + }; + uint32_t _raw; + }; +} reg_iq_lbw_clk_en; +static_assert((sizeof(struct reg_iq_lbw_clk_en) == 4), "reg_iq_lbw_clk_en size is not 32-bit"); +/* + TPC_LOCK_VALUE + b'TPC lock value' +*/ +typedef struct reg_tpc_lock_value { + union { + struct { + uint32_t value : 32; + }; + uint32_t _raw; + }; +} reg_tpc_lock_value; +static_assert((sizeof(struct reg_tpc_lock_value) == 4), "reg_tpc_lock_value size is not 32-bit"); +/* + TPC_LOCK + b'TPC lock' +*/ +typedef struct reg_tpc_lock { + union { + struct { + uint32_t lock : 1, + _reserved1 : 31; + }; + uint32_t _raw; + }; +} reg_tpc_lock; +static_assert((sizeof(struct reg_tpc_lock) == 4), "reg_tpc_lock size is not 32-bit"); +/* + CGU_SB + b'CGU SB Configuration Disable' +*/ +typedef struct reg_cgu_sb { + union { + struct { + uint32_t tsb_disable : 1, + _reserved1 : 31; + }; + uint32_t _raw; + }; +} reg_cgu_sb; +static_assert((sizeof(struct reg_cgu_sb) == 4), "reg_cgu_sb size is not 32-bit"); +/* + CGU_CNT + b'CGU CNT Configuration Disable' +*/ +typedef struct reg_cgu_cnt { + union { + struct { + uint32_t dcache_disable : 1, + wq_disable : 1, + spu_agu_addsub_0_disable : 1, + spu_agu_addsub_1_disable : 1, + spu_agu_addsub_2_disable : 1, + spu_agu_addsub_3_disable : 1, + spu_agu_addsub_4_disable : 1, + spu_agu_cmp_0_disable : 1, + spu_agu_cmp_1_disable : 1, + spu_agu_cmp_2_disable : 1, + spu_agu_cmp_3_disable : 1, + spu_agu_cmp_4_disable : 1, + msac_disable : 1, + conv_disable : 1, + nearbyint_disable : 1, + cmp_disable : 1, + fp_mac_disable : 1, + sops_src_a_d2_disable : 1, + sops_src_b_d2_disable : 1, + sops_src_e_d2_disable : 1, + sops_fma_src_c_e1_disable : 1, + ld_sops_src_a_d2_disable : 1, + st_sops_src_a_d2_disable : 1, + fp_addsub_disable : 1, + _reserved24 : 8; + }; + uint32_t _raw; + }; +} reg_cgu_cnt; +static_assert((sizeof(struct reg_cgu_cnt) == 4), "reg_cgu_cnt size is not 32-bit"); +/* + CGU_CPE + b'CGU CPE Configuration Disable' +*/ +typedef struct reg_cgu_cpe { + union { + struct { + uint32_t nearbyint_disable : 1, + sops_src_a_disable : 1, + sops_src_b_disable : 1, + sops_src_e_disable : 1, + sops_src_d_disable : 1, + sops_src_c_disable : 1, + ld_sops_src_a_disable : 1, + msac_disable : 1, + addsub_disable : 1, + shift_disable : 1, + gle_disable : 1, + cmp_disable : 1, + conv_disable : 1, + sb_disable : 1, + tbuf_disable : 1, + st_g_disable : 1, + fp_mac_0_disable : 1, + fp_mac_1_disable : 1, + fp_addsub_disable : 1, + st_sops_src_c_disable : 1, + _reserved20 : 12; + }; + uint32_t _raw; + }; +} reg_cgu_cpe; +static_assert((sizeof(struct reg_cgu_cpe) == 4), "reg_cgu_cpe size is not 32-bit"); +/* + FP16_FTZ_IN + b'Flush FP16 denormals to 0 at FMA input\xc3\xa2\xc2\x80\xc2\x8b' +*/ +typedef struct reg_fp16_ftz_in { + union { + struct { + uint32_t mode : 1, + _reserved1 : 31; + }; + uint32_t _raw; + }; +} reg_fp16_ftz_in; +static_assert((sizeof(struct reg_fp16_ftz_in) == 4), "reg_fp16_ftz_in size is not 32-bit"); +/* + DCACHE_CFG + b'Dcache Config' +*/ +typedef struct reg_dcache_cfg { + union { + struct { + uint32_t g_pref_dis : 1, + g_pref_vld_clr : 1, + halt_flush : 1, + dealign_dis : 1, + _reserved4 : 28; + }; + uint32_t _raw; + }; +} reg_dcache_cfg; +static_assert((sizeof(struct reg_dcache_cfg) == 4), "reg_dcache_cfg size is not 32-bit"); +/* + E2E_CRDT_TOP + b'e2e crdt top force en and force val' +*/ +typedef struct reg_e2e_crdt_top { + union { + struct { + uint32_t force_en : 1, + _reserved4 : 3, + y_x_force : 9, + _reserved13 : 19; + }; + uint32_t _raw; + }; +} reg_e2e_crdt_top; +static_assert((sizeof(struct reg_e2e_crdt_top) == 4), "reg_e2e_crdt_top size is not 32-bit"); +/* + TPC_DCACHE_L0CD + b'L0 DCACHE Cache Disable' +*/ +typedef struct reg_tpc_dcache_l0cd { + union { + struct { + uint32_t val : 1, + _reserved1 : 31; + }; + uint32_t _raw; + }; +} reg_tpc_dcache_l0cd; +static_assert((sizeof(struct reg_tpc_dcache_l0cd) == 4), "reg_tpc_dcache_l0cd size is not 32-bit"); +/* + TPC_SB_L0CD + b'L0 SB Cache Disable' +*/ +typedef struct reg_tpc_sb_l0cd { + union { + struct { + uint32_t val : 1, + _reserved1 : 31; + }; + uint32_t _raw; + }; +} reg_tpc_sb_l0cd; +static_assert((sizeof(struct reg_tpc_sb_l0cd) == 4), "reg_tpc_sb_l0cd size is not 32-bit"); +/* + CONV_ROUND_CSR + b'Converter Round CSR' +*/ +typedef struct reg_conv_round_csr { + union { + struct { + uint32_t mode : 3, + _reserved3 : 29; + }; + uint32_t _raw; + }; +} reg_conv_round_csr; +static_assert((sizeof(struct reg_conv_round_csr) == 4), "reg_conv_round_csr size is not 32-bit"); +/* + TSB_OCCUPANCY + b'current number of CLs in SB' +*/ +typedef struct reg_tsb_occupancy { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_tsb_occupancy; +static_assert((sizeof(struct reg_tsb_occupancy) == 4), "reg_tsb_occupancy size is not 32-bit"); +/* + ARB_QNT_HBW_WEIGHT + b'QNT hbw arbitration weight' +*/ +typedef struct reg_arb_qnt_hbw_weight { + union { + struct { + uint32_t ar : 12, + aw : 8, + _reserved20 : 12; + }; + uint32_t _raw; + }; +} reg_arb_qnt_hbw_weight; +static_assert((sizeof(struct reg_arb_qnt_hbw_weight) == 4), "reg_arb_qnt_hbw_weight size is not 32-bit"); +/* + ARB_QNT_LBW_WEIGHT + b'QNT lbw arbitration weight' +*/ +typedef struct reg_arb_qnt_lbw_weight { + union { + struct { + uint32_t aw : 8, + ar : 8, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_arb_qnt_lbw_weight; +static_assert((sizeof(struct reg_arb_qnt_lbw_weight) == 4), "reg_arb_qnt_lbw_weight size is not 32-bit"); +/* + ARB_CNT_HBW_WEIGHT + b'CNT hbw arbitration weight' +*/ +typedef struct reg_arb_cnt_hbw_weight { + union { + struct { + uint32_t ar : 12, + aw : 12, + _reserved24 : 8; + }; + uint32_t _raw; + }; +} reg_arb_cnt_hbw_weight; +static_assert((sizeof(struct reg_arb_cnt_hbw_weight) == 4), "reg_arb_cnt_hbw_weight size is not 32-bit"); +/* + ARB_CNT_LBW_WEIGHT + b'CNT lbw arbitration weight' +*/ +typedef struct reg_arb_cnt_lbw_weight { + union { + struct { + uint32_t ar : 8, + aw : 12, + _reserved20 : 12; + }; + uint32_t _raw; + }; +} reg_arb_cnt_lbw_weight; +static_assert((sizeof(struct reg_arb_cnt_lbw_weight) == 4), "reg_arb_cnt_lbw_weight size is not 32-bit"); +/* + LUT_FUNC32_BASE2_ADDR_LO + b'LOOKUP TABLE 32 lines Base2 Address 32 LSB' +*/ +typedef struct reg_lut_func32_base2_addr_lo { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_lut_func32_base2_addr_lo; +static_assert((sizeof(struct reg_lut_func32_base2_addr_lo) == 4), "reg_lut_func32_base2_addr_lo size is not 32-bit"); +/* + LUT_FUNC32_BASE2_ADDR_HI + b'LOOKUP TABLE 32 lines Base2 Address 32 MSB' +*/ +typedef struct reg_lut_func32_base2_addr_hi { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_lut_func32_base2_addr_hi; +static_assert((sizeof(struct reg_lut_func32_base2_addr_hi) == 4), "reg_lut_func32_base2_addr_hi size is not 32-bit"); +/* + LUT_FUNC64_BASE2_ADDR_LO + b'LOOKUP TABLE 64 lines Base2 Address 32 LSB' +*/ +typedef struct reg_lut_func64_base2_addr_lo { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_lut_func64_base2_addr_lo; +static_assert((sizeof(struct reg_lut_func64_base2_addr_lo) == 4), "reg_lut_func64_base2_addr_lo size is not 32-bit"); +/* + LUT_FUNC64_BASE2_ADDR_HI + b'LOOKUP TABLE 64 lines Base2 Address 32 MSB' +*/ +typedef struct reg_lut_func64_base2_addr_hi { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_lut_func64_base2_addr_hi; +static_assert((sizeof(struct reg_lut_func64_base2_addr_hi) == 4), "reg_lut_func64_base2_addr_hi size is not 32-bit"); +/* + LUT_FUNC128_BASE2_ADDR_LO + b'LOOKUP TABLE 128 lines Base2 Address 32 LSB' +*/ +typedef struct reg_lut_func128_base2_addr_lo { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_lut_func128_base2_addr_lo; +static_assert((sizeof(struct reg_lut_func128_base2_addr_lo) == 4), "reg_lut_func128_base2_addr_lo size is not 32-bit"); +/* + LUT_FUNC128_BASE2_ADDR_HI + b'LOOKUP TABLE 128 lines Base2 Address 32 MSB' +*/ +typedef struct reg_lut_func128_base2_addr_hi { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_lut_func128_base2_addr_hi; +static_assert((sizeof(struct reg_lut_func128_base2_addr_hi) == 4), "reg_lut_func128_base2_addr_hi size is not 32-bit"); +/* + LUT_FUNC256_BASE2_ADDR_LO + b'LOOKUP TABLE 256 lines Base2 Address 32 LSB' +*/ +typedef struct reg_lut_func256_base2_addr_lo { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_lut_func256_base2_addr_lo; +static_assert((sizeof(struct reg_lut_func256_base2_addr_lo) == 4), "reg_lut_func256_base2_addr_lo size is not 32-bit"); +/* + LUT_FUNC256_BASE2_ADDR_HI + b'LOOKUP TABLE 256 lines Base2 Address 32 MSB' +*/ +typedef struct reg_lut_func256_base2_addr_hi { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_lut_func256_base2_addr_hi; +static_assert((sizeof(struct reg_lut_func256_base2_addr_hi) == 4), "reg_lut_func256_base2_addr_hi size is not 32-bit"); +/* + SPE_LFSR_POLYNOM + b'LFSR polynom' +*/ +typedef struct reg_spe_lfsr_polynom { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_spe_lfsr_polynom; +static_assert((sizeof(struct reg_spe_lfsr_polynom) == 4), "reg_spe_lfsr_polynom size is not 32-bit"); +/* + TSB_CFG_MTRR_GLBL + b'TSB MTRR Global cfg' +*/ +typedef struct reg_tsb_cfg_mtrr_glbl { + union { + struct { + uint32_t en : 1, + _reserved4 : 3, + default_memory_type : 1, + _reserved5 : 27; + }; + uint32_t _raw; + }; +} reg_tsb_cfg_mtrr_glbl; +static_assert((sizeof(struct reg_tsb_cfg_mtrr_glbl) == 4), "reg_tsb_cfg_mtrr_glbl size is not 32-bit"); +/* + TSB_CFG_MTRR + b'TSB MTRR cfg' +*/ +typedef struct reg_tsb_cfg_mtrr { + union { + struct { + uint32_t valid : 1, + _reserved4 : 3, + memory_type : 1, + _reserved8 : 3, + phy_base_add : 16, + _reserved24 : 8; + }; + uint32_t _raw; + }; +} reg_tsb_cfg_mtrr; +static_assert((sizeof(struct reg_tsb_cfg_mtrr) == 4), "reg_tsb_cfg_mtrr size is not 32-bit"); +/* + TSB_CFG_MTRR_MASK_LO + b'TSB MTRR mask cfg lo' +*/ +typedef struct reg_tsb_cfg_mtrr_mask_lo { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_tsb_cfg_mtrr_mask_lo; +static_assert((sizeof(struct reg_tsb_cfg_mtrr_mask_lo) == 4), "reg_tsb_cfg_mtrr_mask_lo size is not 32-bit"); +/* + TSB_CFG_MTRR_MASK_HI + b'TSB MTRR mask cfg hi' +*/ +typedef struct reg_tsb_cfg_mtrr_mask_hi { + union { + struct { + uint32_t v : 8, + _reserved8 : 24; + }; + uint32_t _raw; + }; +} reg_tsb_cfg_mtrr_mask_hi; +static_assert((sizeof(struct reg_tsb_cfg_mtrr_mask_hi) == 4), "reg_tsb_cfg_mtrr_mask_hi size is not 32-bit"); +/* + FP8_143_BIAS + b'FP8 143 Bias value' +*/ +typedef struct reg_fp8_143_bias { + union { + struct { + uint32_t bias_143 : 4, + _reserved4 : 28; + }; + uint32_t _raw; + }; +} reg_fp8_143_bias; +static_assert((sizeof(struct reg_fp8_143_bias) == 4), "reg_fp8_143_bias size is not 32-bit"); +/* + ROUND_CSR + b'round mode for FMA operations' +*/ +typedef struct reg_round_csr { + union { + struct { + uint32_t mode : 3, + _reserved3 : 29; + }; + uint32_t _raw; + }; +} reg_round_csr; +static_assert((sizeof(struct reg_round_csr) == 4), "reg_round_csr size is not 32-bit"); +/* + HB_PROT + b'AXI HBW AxPROT bits' +*/ +typedef struct reg_hb_prot { + union { + struct { + uint32_t awprot : 3, + arprot : 3, + _reserved6 : 26; + }; + uint32_t _raw; + }; +} reg_hb_prot; +static_assert((sizeof(struct reg_hb_prot) == 4), "reg_hb_prot size is not 32-bit"); +/* + LB_PROT + b'AXI LBW AxPROT bits' +*/ +typedef struct reg_lb_prot { + union { + struct { + uint32_t awprot : 3, + arprot : 3, + _reserved6 : 26; + }; + uint32_t _raw; + }; +} reg_lb_prot; +static_assert((sizeof(struct reg_lb_prot) == 4), "reg_lb_prot size is not 32-bit"); +/* + SEMAPHORE + b'atomic semaphore (used for spu/vpu sync)' +*/ +typedef struct reg_semaphore { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_semaphore; +static_assert((sizeof(struct reg_semaphore) == 4), "reg_semaphore size is not 32-bit"); +/* + VFLAGS + b'Vector Flags' +*/ +typedef struct reg_vflags { + union { + struct { + uint32_t v : 7, + _reserved7 : 25; + }; + uint32_t _raw; + }; +} reg_vflags; +static_assert((sizeof(struct reg_vflags) == 4), "reg_vflags size is not 32-bit"); +/* + SFLAGS + b'Scalar Flags' +*/ +typedef struct reg_sflags { + union { + struct { + uint32_t v : 7, + _reserved7 : 25; + }; + uint32_t _raw; + }; +} reg_sflags; +static_assert((sizeof(struct reg_sflags) == 4), "reg_sflags size is not 32-bit"); +/* + LFSR_POLYNOM + b'VPU LFSR polynom' +*/ +typedef struct reg_lfsr_polynom { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_lfsr_polynom; +static_assert((sizeof(struct reg_lfsr_polynom) == 4), "reg_lfsr_polynom size is not 32-bit"); +/* + STATUS + b'Used to qeury the status of the TPC' +*/ +typedef struct reg_status { + union { + struct { + uint32_t _reserved1 : 1, +scalar_pipe_empty : 1, + vector_pipe_empty : 1, + iq_empty : 1, + _reserved5 : 1, + sb_empty : 1, + qm_idle : 1, + qm_rdy : 1, + _reserved8 : 24; + }; + uint32_t _raw; + }; +} reg_status; +static_assert((sizeof(struct reg_status) == 4), "reg_status size is not 32-bit"); +/* + CFG_BASE_ADDRESS_HIGH + b'higher 32 bits of the CFG base address' +*/ +typedef struct reg_cfg_base_address_high { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_cfg_base_address_high; +static_assert((sizeof(struct reg_cfg_base_address_high) == 4), "reg_cfg_base_address_high size is not 32-bit"); +/* + CFG_SUBTRACT_VALUE + b'MMIO address offset for outbound LBW' +*/ +typedef struct reg_cfg_subtract_value { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_cfg_subtract_value; +static_assert((sizeof(struct reg_cfg_subtract_value) == 4), "reg_cfg_subtract_value size is not 32-bit"); +/* + SM_BASE_ADDRESS_HIGH + b'32 MSBs of SM Base address' +*/ +typedef struct reg_sm_base_address_high { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_sm_base_address_high; +static_assert((sizeof(struct reg_sm_base_address_high) == 4), "reg_sm_base_address_high size is not 32-bit"); +/* + TPC_CMD + b'enable sequencer operations before next descriptor' +*/ +typedef struct reg_tpc_cmd { + union { + struct { + uint32_t icache_invalidate : 1, + dcache_invalidate : 1, + lcache_invalidate : 1, + tcache_invalidate : 1, + icache_prefetch_64kb : 1, + icache_prefetch_32kb : 1, + qman_stop : 1, + _reserved7 : 25; + }; + uint32_t _raw; + }; +} reg_tpc_cmd; +static_assert((sizeof(struct reg_tpc_cmd) == 4), "reg_tpc_cmd size is not 32-bit"); +/* + TPC_EXECUTE + b'push descriptor to TPC' +*/ +typedef struct reg_tpc_execute { + union { + struct { + uint32_t v : 1, + _reserved1 : 31; + }; + uint32_t _raw; + }; +} reg_tpc_execute; +static_assert((sizeof(struct reg_tpc_execute) == 4), "reg_tpc_execute size is not 32-bit"); +/* + TPC_STALL + b'stalls TPC core' +*/ +typedef struct reg_tpc_stall { + union { + struct { + uint32_t v : 1, + _reserved1 : 31; + }; + uint32_t _raw; + }; +} reg_tpc_stall; +static_assert((sizeof(struct reg_tpc_stall) == 4), "reg_tpc_stall size is not 32-bit"); +/* + ICACHE_BASE_ADDERESS_LOW + b'32 LSBs of the base address to prefetch in a 64KB' +*/ +typedef struct reg_icache_base_adderess_low { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_icache_base_adderess_low; +static_assert((sizeof(struct reg_icache_base_adderess_low) == 4), "reg_icache_base_adderess_low size is not 32-bit"); +/* + ICACHE_BASE_ADDERESS_HIGH + b'32 MSBs of the base address to prefetch in a 64KB' +*/ +typedef struct reg_icache_base_adderess_high { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_icache_base_adderess_high; +static_assert((sizeof(struct reg_icache_base_adderess_high) == 4), "reg_icache_base_adderess_high size is not 32-bit"); +/* + RD_RATE_LIMIT + b'AXI Read Port RATE LIMIT Static Config' +*/ +typedef struct reg_rd_rate_limit { + union { + struct { + uint32_t enable : 1, + saturation : 8, + timeout : 8, + _reserved17 : 15; + }; + uint32_t _raw; + }; +} reg_rd_rate_limit; +static_assert((sizeof(struct reg_rd_rate_limit) == 4), "reg_rd_rate_limit size is not 32-bit"); +/* + WR_RATE_LIMIT + b'AXI Write Port RATE LIMIT Static Config' +*/ +typedef struct reg_wr_rate_limit { + union { + struct { + uint32_t enable : 1, + saturation : 8, + timeout : 8, + _reserved17 : 15; + }; + uint32_t _raw; + }; +} reg_wr_rate_limit; +static_assert((sizeof(struct reg_wr_rate_limit) == 4), "reg_wr_rate_limit size is not 32-bit"); +/* + MSS_CONFIG + b'configurations related to caches' +*/ +typedef struct reg_mss_config { + union { + struct { + uint32_t awcache : 4, + arcache : 4, + icache_fetch_line_num : 2, + exposed_pipe_dis : 1, + dcache_prefetch_dis : 1, + _reserved12 : 20; + }; + uint32_t _raw; + }; +} reg_mss_config; +static_assert((sizeof(struct reg_mss_config) == 4), "reg_mss_config size is not 32-bit"); +/* + TPC_INTR_CAUSE + b'TPC interrupts cause' +*/ +typedef struct reg_tpc_intr_cause { + union { + struct { + uint32_t cause : 32; + }; + uint32_t _raw; + }; +} reg_tpc_intr_cause; +static_assert((sizeof(struct reg_tpc_intr_cause) == 4), "reg_tpc_intr_cause size is not 32-bit"); +/* + TPC_INTR_MASK + b'Set 1 to mask the corresponding interrupt' +*/ +typedef struct reg_tpc_intr_mask { + union { + struct { + uint32_t mask : 32; + }; + uint32_t _raw; + }; +} reg_tpc_intr_mask; +static_assert((sizeof(struct reg_tpc_intr_mask) == 4), "reg_tpc_intr_mask size is not 32-bit"); +/* + WQ_CREDITS + b'WQ_CREDITS' +*/ +typedef struct reg_wq_credits { + union { + struct { + uint32_t st_g : 4, + kernel_fifo : 3, + _reserved7 : 25; + }; + uint32_t _raw; + }; +} reg_wq_credits; +static_assert((sizeof(struct reg_wq_credits) == 4), "reg_wq_credits size is not 32-bit"); +/* + OPCODE_EXEC + b'Opcodes Executed for Counters' +*/ +typedef struct reg_opcode_exec { + union { + struct { + uint32_t spu_op : 7, + spu_en : 1, + vpu_op : 7, + vpu_en : 1, + ld_op : 7, + ld_en : 1, + st_op : 7, + st_en : 1; + }; + uint32_t _raw; + }; +} reg_opcode_exec; +static_assert((sizeof(struct reg_opcode_exec) == 4), "reg_opcode_exec size is not 32-bit"); +/* + LUT_FUNC32_BASE_ADDR_LO + b'LOOKUP TABLE 32 lines Base Address 32 LSB' +*/ +typedef struct reg_lut_func32_base_addr_lo { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_lut_func32_base_addr_lo; +static_assert((sizeof(struct reg_lut_func32_base_addr_lo) == 4), "reg_lut_func32_base_addr_lo size is not 32-bit"); +/* + LUT_FUNC32_BASE_ADDR_HI + b'LOOKUP TABLE 32 lines Base Address 32 MSB' +*/ +typedef struct reg_lut_func32_base_addr_hi { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_lut_func32_base_addr_hi; +static_assert((sizeof(struct reg_lut_func32_base_addr_hi) == 4), "reg_lut_func32_base_addr_hi size is not 32-bit"); +/* + LUT_FUNC64_BASE_ADDR_LO + b'LOOKUP TABLE 64 lines Base Address 32 LSB' +*/ +typedef struct reg_lut_func64_base_addr_lo { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_lut_func64_base_addr_lo; +static_assert((sizeof(struct reg_lut_func64_base_addr_lo) == 4), "reg_lut_func64_base_addr_lo size is not 32-bit"); +/* + LUT_FUNC64_BASE_ADDR_HI + b'LOOKUP TABLE 64 lines Base Address 32 MSB' +*/ +typedef struct reg_lut_func64_base_addr_hi { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_lut_func64_base_addr_hi; +static_assert((sizeof(struct reg_lut_func64_base_addr_hi) == 4), "reg_lut_func64_base_addr_hi size is not 32-bit"); +/* + LUT_FUNC128_BASE_ADDR_LO + b'LOOKUP TABLE 128 lines Base Address 32 LSB' +*/ +typedef struct reg_lut_func128_base_addr_lo { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_lut_func128_base_addr_lo; +static_assert((sizeof(struct reg_lut_func128_base_addr_lo) == 4), "reg_lut_func128_base_addr_lo size is not 32-bit"); +/* + LUT_FUNC128_BASE_ADDR_HI + b'LOOKUP TABLE 128 lines Base Address 32 MSB' +*/ +typedef struct reg_lut_func128_base_addr_hi { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_lut_func128_base_addr_hi; +static_assert((sizeof(struct reg_lut_func128_base_addr_hi) == 4), "reg_lut_func128_base_addr_hi size is not 32-bit"); +/* + LUT_FUNC256_BASE_ADDR_LO + b'LOOKUP TABLE 256 lines Base Address 32 LSB' +*/ +typedef struct reg_lut_func256_base_addr_lo { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_lut_func256_base_addr_lo; +static_assert((sizeof(struct reg_lut_func256_base_addr_lo) == 4), "reg_lut_func256_base_addr_lo size is not 32-bit"); +/* + LUT_FUNC256_BASE_ADDR_HI + b'LOOKUP TABLE 256 lines Base Address 32 MSB' +*/ +typedef struct reg_lut_func256_base_addr_hi { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_lut_func256_base_addr_hi; +static_assert((sizeof(struct reg_lut_func256_base_addr_hi) == 4), "reg_lut_func256_base_addr_hi size is not 32-bit"); +/* + TSB_CFG_MAX_SIZE + b'TSB Configuration' +*/ +typedef struct reg_tsb_cfg_max_size { + union { + struct { + uint32_t data : 16, + md : 16; + }; + uint32_t _raw; + }; +} reg_tsb_cfg_max_size; +static_assert((sizeof(struct reg_tsb_cfg_max_size) == 4), "reg_tsb_cfg_max_size size is not 32-bit"); +/* + TSB_CFG + b'more TSB configuration' +*/ +typedef struct reg_tsb_cfg { + union { + struct { + uint32_t cache_disable : 1, + max_os : 16, + enable_cgate : 1, + _reserved18 : 14; + }; + uint32_t _raw; + }; +} reg_tsb_cfg; +static_assert((sizeof(struct reg_tsb_cfg) == 4), "reg_tsb_cfg size is not 32-bit"); +/* + TSB_INFLIGHT_CNTR + b'number of inflight req. of SB' +*/ +typedef struct reg_tsb_inflight_cntr { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_tsb_inflight_cntr; +static_assert((sizeof(struct reg_tsb_inflight_cntr) == 4), "reg_tsb_inflight_cntr size is not 32-bit"); +/* + WQ_INFLIGHT_CNTR + b'number of inflight req. of WQ' +*/ +typedef struct reg_wq_inflight_cntr { + union { + struct { + uint32_t hbw : 16, + lbw : 9, + _reserved25 : 7; + }; + uint32_t _raw; + }; +} reg_wq_inflight_cntr; +static_assert((sizeof(struct reg_wq_inflight_cntr) == 4), "reg_wq_inflight_cntr size is not 32-bit"); +/* + WQ_LBW_TOTAL_CNTR + b'writing reset counter' +*/ +typedef struct reg_wq_lbw_total_cntr { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_wq_lbw_total_cntr; +static_assert((sizeof(struct reg_wq_lbw_total_cntr) == 4), "reg_wq_lbw_total_cntr size is not 32-bit"); +/* + WQ_HBW_TOTAL_CNTR + b'writing reset counter' +*/ +typedef struct reg_wq_hbw_total_cntr { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_wq_hbw_total_cntr; +static_assert((sizeof(struct reg_wq_hbw_total_cntr) == 4), "reg_wq_hbw_total_cntr size is not 32-bit"); +/* + IRQ_OCCOUPY_CNTR + b'number of instructions in IQ' +*/ +typedef struct reg_irq_occoupy_cntr { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_irq_occoupy_cntr; +static_assert((sizeof(struct reg_irq_occoupy_cntr) == 4), "reg_irq_occoupy_cntr size is not 32-bit"); + +#ifdef __cplusplus +} /* tpc namespace */ +#endif + +/* + TPC block +*/ + +#ifdef __cplusplus + +struct block_tpc { + struct block_tpc_tensor kernel_tensor_0; + struct block_tpc_tensor kernel_tensor_1; + struct block_tpc_tensor kernel_tensor_2; + struct block_tpc_tensor kernel_tensor_3; + struct block_tpc_tensor kernel_tensor_4; + struct block_tpc_tensor kernel_tensor_5; + struct block_tpc_tensor kernel_tensor_6; + struct block_tpc_tensor kernel_tensor_7; + struct block_tpc_tensor kernel_tensor_8; + struct block_tpc_tensor kernel_tensor_9; + struct block_tpc_tensor kernel_tensor_10; + struct block_tpc_tensor kernel_tensor_11; + struct block_tpc_tensor kernel_tensor_12; + struct block_tpc_tensor kernel_tensor_13; + struct block_tpc_tensor kernel_tensor_14; + struct block_tpc_tensor kernel_tensor_15; + struct block_sync_object kernel_sync_object; + struct block_tpc_non_tensor_descriptor kernel; + struct block_tpc_tensor qm_tensor_0; + struct block_tpc_tensor qm_tensor_1; + struct block_tpc_tensor qm_tensor_2; + struct block_tpc_tensor qm_tensor_3; + struct block_tpc_tensor qm_tensor_4; + struct block_tpc_tensor qm_tensor_5; + struct block_tpc_tensor qm_tensor_6; + struct block_tpc_tensor qm_tensor_7; + struct block_tpc_tensor qm_tensor_8; + struct block_tpc_tensor qm_tensor_9; + struct block_tpc_tensor qm_tensor_10; + struct block_tpc_tensor qm_tensor_11; + struct block_tpc_tensor qm_tensor_12; + struct block_tpc_tensor qm_tensor_13; + struct block_tpc_tensor qm_tensor_14; + struct block_tpc_tensor qm_tensor_15; + struct block_sync_object qm_sync_object; + struct block_tpc_non_tensor_descriptor qm; + uint32_t _pad3000[24]; + struct tpc::reg_tpc_count tpc_count; + struct tpc::reg_tpc_id tpc_id; + struct tpc::reg_stall_on_err stall_on_err; + struct tpc::reg_clk_en clk_en; + struct tpc::reg_iq_rl_en iq_rl_en; + struct tpc::reg_iq_rl_sat iq_rl_sat; + struct tpc::reg_iq_rl_rst_token iq_rl_rst_token; + struct tpc::reg_iq_rl_timeout iq_rl_timeout; + struct tpc::reg_tsb_cfg_mtrr_2 tsb_cfg_mtrr_2[4]; + struct tpc::reg_iq_lbw_clk_en iq_lbw_clk_en; + struct tpc::reg_tpc_lock_value tpc_lock_value[4]; + struct tpc::reg_tpc_lock tpc_lock[4]; + struct tpc::reg_cgu_sb cgu_sb; + struct tpc::reg_cgu_cnt cgu_cnt; + struct tpc::reg_cgu_cpe cgu_cpe[8]; + struct tpc::reg_fp16_ftz_in fp16_ftz_in; + struct tpc::reg_dcache_cfg dcache_cfg; + struct tpc::reg_e2e_crdt_top e2e_crdt_top; + struct tpc::reg_tpc_dcache_l0cd tpc_dcache_l0cd; + struct tpc::reg_tpc_sb_l0cd tpc_sb_l0cd; + struct tpc::reg_conv_round_csr conv_round_csr; + struct tpc::reg_tsb_occupancy tsb_occupancy; + struct tpc::reg_arb_qnt_hbw_weight arb_qnt_hbw_weight; + struct tpc::reg_arb_qnt_lbw_weight arb_qnt_lbw_weight; + struct tpc::reg_arb_cnt_hbw_weight arb_cnt_hbw_weight; + struct tpc::reg_arb_cnt_lbw_weight arb_cnt_lbw_weight; + struct tpc::reg_lut_func32_base2_addr_lo lut_func32_base2_addr_lo; + struct tpc::reg_lut_func32_base2_addr_hi lut_func32_base2_addr_hi; + struct tpc::reg_lut_func64_base2_addr_lo lut_func64_base2_addr_lo; + struct tpc::reg_lut_func64_base2_addr_hi lut_func64_base2_addr_hi; + struct tpc::reg_lut_func128_base2_addr_lo lut_func128_base2_addr_lo; + struct tpc::reg_lut_func128_base2_addr_hi lut_func128_base2_addr_hi; + struct tpc::reg_lut_func256_base2_addr_lo lut_func256_base2_addr_lo; + struct tpc::reg_lut_func256_base2_addr_hi lut_func256_base2_addr_hi; + struct tpc::reg_spe_lfsr_polynom spe_lfsr_polynom; + struct tpc::reg_tsb_cfg_mtrr_glbl tsb_cfg_mtrr_glbl; + struct tpc::reg_tsb_cfg_mtrr tsb_cfg_mtrr[4]; + struct tpc::reg_tsb_cfg_mtrr_mask_lo tsb_cfg_mtrr_mask_lo[4]; + struct tpc::reg_tsb_cfg_mtrr_mask_hi tsb_cfg_mtrr_mask_hi[4]; + uint32_t _pad3352[19]; + struct tpc::reg_fp8_143_bias fp8_143_bias; + struct tpc::reg_round_csr round_csr; + struct tpc::reg_hb_prot hb_prot; + struct tpc::reg_lb_prot lb_prot; + struct tpc::reg_semaphore semaphore; + struct tpc::reg_vflags vflags; + struct tpc::reg_sflags sflags; + struct tpc::reg_lfsr_polynom lfsr_polynom; + struct tpc::reg_status status; + struct tpc::reg_cfg_base_address_high cfg_base_address_high; + struct tpc::reg_cfg_subtract_value cfg_subtract_value; + struct tpc::reg_sm_base_address_high sm_base_address_high; + struct tpc::reg_tpc_cmd tpc_cmd; + struct tpc::reg_tpc_execute tpc_execute; + struct tpc::reg_tpc_stall tpc_stall; + struct tpc::reg_icache_base_adderess_low icache_base_adderess_low; + struct tpc::reg_icache_base_adderess_high icache_base_adderess_high; + struct tpc::reg_rd_rate_limit rd_rate_limit; + struct tpc::reg_wr_rate_limit wr_rate_limit; + struct tpc::reg_mss_config mss_config; + struct tpc::reg_tpc_intr_cause tpc_intr_cause; + struct tpc::reg_tpc_intr_mask tpc_intr_mask; + struct tpc::reg_wq_credits wq_credits; + struct tpc::reg_opcode_exec opcode_exec; + struct tpc::reg_lut_func32_base_addr_lo lut_func32_base_addr_lo; + struct tpc::reg_lut_func32_base_addr_hi lut_func32_base_addr_hi; + struct tpc::reg_lut_func64_base_addr_lo lut_func64_base_addr_lo; + struct tpc::reg_lut_func64_base_addr_hi lut_func64_base_addr_hi; + struct tpc::reg_lut_func128_base_addr_lo lut_func128_base_addr_lo; + struct tpc::reg_lut_func128_base_addr_hi lut_func128_base_addr_hi; + struct tpc::reg_lut_func256_base_addr_lo lut_func256_base_addr_lo; + struct tpc::reg_lut_func256_base_addr_hi lut_func256_base_addr_hi; + struct tpc::reg_tsb_cfg_max_size tsb_cfg_max_size; + struct tpc::reg_tsb_cfg tsb_cfg; + struct tpc::reg_tsb_inflight_cntr tsb_inflight_cntr; + struct tpc::reg_wq_inflight_cntr wq_inflight_cntr; + struct tpc::reg_wq_lbw_total_cntr wq_lbw_total_cntr; + struct tpc::reg_wq_hbw_total_cntr wq_hbw_total_cntr; + struct tpc::reg_irq_occoupy_cntr irq_occoupy_cntr; + struct block_axuser axuser; + uint32_t _pad3664[12]; + struct block_special_regs special; +}; +#else + +typedef struct block_tpc { + block_tpc_tensor kernel_tensor_0; + block_tpc_tensor kernel_tensor_1; + block_tpc_tensor kernel_tensor_2; + block_tpc_tensor kernel_tensor_3; + block_tpc_tensor kernel_tensor_4; + block_tpc_tensor kernel_tensor_5; + block_tpc_tensor kernel_tensor_6; + block_tpc_tensor kernel_tensor_7; + block_tpc_tensor kernel_tensor_8; + block_tpc_tensor kernel_tensor_9; + block_tpc_tensor kernel_tensor_10; + block_tpc_tensor kernel_tensor_11; + block_tpc_tensor kernel_tensor_12; + block_tpc_tensor kernel_tensor_13; + block_tpc_tensor kernel_tensor_14; + block_tpc_tensor kernel_tensor_15; + block_sync_object kernel_sync_object; + block_tpc_non_tensor_descriptor kernel; + block_tpc_tensor qm_tensor_0; + block_tpc_tensor qm_tensor_1; + block_tpc_tensor qm_tensor_2; + block_tpc_tensor qm_tensor_3; + block_tpc_tensor qm_tensor_4; + block_tpc_tensor qm_tensor_5; + block_tpc_tensor qm_tensor_6; + block_tpc_tensor qm_tensor_7; + block_tpc_tensor qm_tensor_8; + block_tpc_tensor qm_tensor_9; + block_tpc_tensor qm_tensor_10; + block_tpc_tensor qm_tensor_11; + block_tpc_tensor qm_tensor_12; + block_tpc_tensor qm_tensor_13; + block_tpc_tensor qm_tensor_14; + block_tpc_tensor qm_tensor_15; + block_sync_object qm_sync_object; + block_tpc_non_tensor_descriptor qm; + uint32_t _pad3000[24]; + reg_tpc_count tpc_count; + reg_tpc_id tpc_id; + reg_stall_on_err stall_on_err; + reg_clk_en clk_en; + reg_iq_rl_en iq_rl_en; + reg_iq_rl_sat iq_rl_sat; + reg_iq_rl_rst_token iq_rl_rst_token; + reg_iq_rl_timeout iq_rl_timeout; + reg_tsb_cfg_mtrr_2 tsb_cfg_mtrr_2[4]; + reg_iq_lbw_clk_en iq_lbw_clk_en; + reg_tpc_lock_value tpc_lock_value[4]; + reg_tpc_lock tpc_lock[4]; + reg_cgu_sb cgu_sb; + reg_cgu_cnt cgu_cnt; + reg_cgu_cpe cgu_cpe[8]; + reg_fp16_ftz_in fp16_ftz_in; + reg_dcache_cfg dcache_cfg; + reg_e2e_crdt_top e2e_crdt_top; + reg_tpc_dcache_l0cd tpc_dcache_l0cd; + reg_tpc_sb_l0cd tpc_sb_l0cd; + reg_conv_round_csr conv_round_csr; + reg_tsb_occupancy tsb_occupancy; + reg_arb_qnt_hbw_weight arb_qnt_hbw_weight; + reg_arb_qnt_lbw_weight arb_qnt_lbw_weight; + reg_arb_cnt_hbw_weight arb_cnt_hbw_weight; + reg_arb_cnt_lbw_weight arb_cnt_lbw_weight; + reg_lut_func32_base2_addr_lo lut_func32_base2_addr_lo; + reg_lut_func32_base2_addr_hi lut_func32_base2_addr_hi; + reg_lut_func64_base2_addr_lo lut_func64_base2_addr_lo; + reg_lut_func64_base2_addr_hi lut_func64_base2_addr_hi; + reg_lut_func128_base2_addr_lo lut_func128_base2_addr_lo; + reg_lut_func128_base2_addr_hi lut_func128_base2_addr_hi; + reg_lut_func256_base2_addr_lo lut_func256_base2_addr_lo; + reg_lut_func256_base2_addr_hi lut_func256_base2_addr_hi; + reg_spe_lfsr_polynom spe_lfsr_polynom; + reg_tsb_cfg_mtrr_glbl tsb_cfg_mtrr_glbl; + reg_tsb_cfg_mtrr tsb_cfg_mtrr[4]; + reg_tsb_cfg_mtrr_mask_lo tsb_cfg_mtrr_mask_lo[4]; + reg_tsb_cfg_mtrr_mask_hi tsb_cfg_mtrr_mask_hi[4]; + uint32_t _pad3352[19]; + reg_fp8_143_bias fp8_143_bias; + reg_round_csr round_csr; + reg_hb_prot hb_prot; + reg_lb_prot lb_prot; + reg_semaphore semaphore; + reg_vflags vflags; + reg_sflags sflags; + reg_lfsr_polynom lfsr_polynom; + reg_status status; + reg_cfg_base_address_high cfg_base_address_high; + reg_cfg_subtract_value cfg_subtract_value; + reg_sm_base_address_high sm_base_address_high; + reg_tpc_cmd tpc_cmd; + reg_tpc_execute tpc_execute; + reg_tpc_stall tpc_stall; + reg_icache_base_adderess_low icache_base_adderess_low; + reg_icache_base_adderess_high icache_base_adderess_high; + reg_rd_rate_limit rd_rate_limit; + reg_wr_rate_limit wr_rate_limit; + reg_mss_config mss_config; + reg_tpc_intr_cause tpc_intr_cause; + reg_tpc_intr_mask tpc_intr_mask; + reg_wq_credits wq_credits; + reg_opcode_exec opcode_exec; + reg_lut_func32_base_addr_lo lut_func32_base_addr_lo; + reg_lut_func32_base_addr_hi lut_func32_base_addr_hi; + reg_lut_func64_base_addr_lo lut_func64_base_addr_lo; + reg_lut_func64_base_addr_hi lut_func64_base_addr_hi; + reg_lut_func128_base_addr_lo lut_func128_base_addr_lo; + reg_lut_func128_base_addr_hi lut_func128_base_addr_hi; + reg_lut_func256_base_addr_lo lut_func256_base_addr_lo; + reg_lut_func256_base_addr_hi lut_func256_base_addr_hi; + reg_tsb_cfg_max_size tsb_cfg_max_size; + reg_tsb_cfg tsb_cfg; + reg_tsb_inflight_cntr tsb_inflight_cntr; + reg_wq_inflight_cntr wq_inflight_cntr; + reg_wq_lbw_total_cntr wq_lbw_total_cntr; + reg_wq_hbw_total_cntr wq_hbw_total_cntr; + reg_irq_occoupy_cntr irq_occoupy_cntr; + block_axuser axuser; + uint32_t _pad3664[12]; + block_special_regs special; +} block_tpc; +#endif + +const offsetVal block_tpc_defaults[] = +{ + // offset // value + { 0xc , 0x50000 , 1 }, // tensor_config + { 0x5c , 0x50000 , 1 }, // tensor_config + { 0xac , 0x50000 , 1 }, // tensor_config + { 0xfc , 0x50000 , 1 }, // tensor_config + { 0x14c , 0x50000 , 1 }, // tensor_config + { 0x19c , 0x50000 , 1 }, // tensor_config + { 0x1ec , 0x50000 , 1 }, // tensor_config + { 0x23c , 0x50000 , 1 }, // tensor_config + { 0x28c , 0x50000 , 1 }, // tensor_config + { 0x2dc , 0x50000 , 1 }, // tensor_config + { 0x32c , 0x50000 , 1 }, // tensor_config + { 0x37c , 0x50000 , 1 }, // tensor_config + { 0x3cc , 0x50000 , 1 }, // tensor_config + { 0x41c , 0x50000 , 1 }, // tensor_config + { 0x46c , 0x50000 , 1 }, // tensor_config + { 0x4bc , 0x50000 , 1 }, // tensor_config + { 0x538 , 0x1040482 , 1 }, // kernel_config + { 0x5e8 , 0x50000 , 1 }, // tensor_config + { 0x638 , 0x50000 , 1 }, // tensor_config + { 0x688 , 0x50000 , 1 }, // tensor_config + { 0x6d8 , 0x50000 , 1 }, // tensor_config + { 0x728 , 0x50000 , 1 }, // tensor_config + { 0x778 , 0x50000 , 1 }, // tensor_config + { 0x7c8 , 0x50000 , 1 }, // tensor_config + { 0x818 , 0x50000 , 1 }, // tensor_config + { 0x868 , 0x50000 , 1 }, // tensor_config + { 0x8b8 , 0x50000 , 1 }, // tensor_config + { 0x908 , 0x50000 , 1 }, // tensor_config + { 0x958 , 0x50000 , 1 }, // tensor_config + { 0x9a8 , 0x50000 , 1 }, // tensor_config + { 0x9f8 , 0x50000 , 1 }, // tensor_config + { 0xa48 , 0x50000 , 1 }, // tensor_config + { 0xa98 , 0x50000 , 1 }, // tensor_config + { 0xb14 , 0x1040482 , 1 }, // kernel_config + { 0xc18 , 0x18 , 1 }, // tpc_count + { 0xc2c , 0x4 , 1 }, // iq_rl_sat + { 0xc30 , 0x8 , 1 }, // iq_rl_rst_token + { 0xc34 , 0xf , 1 }, // iq_rl_timeout + { 0xc6c , 0x1 , 1 }, // cgu_sb + { 0xc70 , 0xffffff , 1 }, // cgu_cnt + { 0xc74 , 0xfffff , 8 }, // cgu_cpe + { 0xc98 , 0x4 , 1 }, // dcache_cfg + { 0xcb0 , 0x1414f , 1 }, // arb_qnt_hbw_weight + { 0xcb4 , 0xff14 , 1 }, // arb_qnt_lbw_weight + { 0xcb8 , 0x14f14f , 1 }, // arb_cnt_hbw_weight + { 0xcbc , 0x14f14 , 1 }, // arb_cnt_lbw_weight + { 0xcc0 , 0x17000 , 1 }, // lut_func32_base2_addr_lo + { 0xcc8 , 0x13800 , 1 }, // lut_func64_base2_addr_lo + { 0xcd0 , 0xd000 , 1 }, // lut_func128_base2_addr_lo + { 0xce0 , 0x800002cc , 1 }, // spe_lfsr_polynom + { 0xd64 , 0x7 , 1 }, // fp8_143_bias + { 0xd6c , 0x12 , 1 }, // hb_prot + { 0xd70 , 0x12 , 1 }, // lb_prot + { 0xd80 , 0x800002cc , 1 }, // lfsr_polynom + { 0xd84 , 0xee , 1 }, // status + { 0xd88 , 0x7f , 1 }, // cfg_base_address_high + { 0xda8 , 0xe0b , 1 }, // rd_rate_limit + { 0xdac , 0xe0b , 1 }, // wr_rate_limit + { 0xdbc , 0x4a , 1 }, // wq_credits + { 0xdc0 , 0xffffffff , 1 }, // opcode_exec + { 0xdc4 , 0x17000 , 1 }, // lut_func32_base_addr_lo + { 0xdcc , 0x13800 , 1 }, // lut_func64_base_addr_lo + { 0xdd4 , 0xd000 , 1 }, // lut_func128_base_addr_lo + { 0xde8 , 0x20000 , 1 }, // tsb_cfg + { 0xe04 , 0x11 , 1 }, // hb_mmu_bp + { 0xe08 , 0x11 , 1 }, // hb_strong_order + { 0xe20 , 0x11 , 1 }, // hb_emem_cpage + { 0xe30 , 0xffffffff , 1 }, // hb_wr_ovrd_lo + { 0xe34 , 0x3ff , 1 }, // hb_wr_ovrd_hi + { 0xe38 , 0xffffffff , 1 }, // hb_rd_ovrd_lo + { 0xe3c , 0x3ff , 1 }, // hb_rd_ovrd_hi + { 0xe4c , 0xffffffff , 1 }, // lb_ovrd + { 0xe80 , 0xffffffff , 32 }, // glbl_priv + { 0xf24 , 0xffff , 1 }, // mem_ecc_err_addr + { 0xf44 , 0xffffffff , 1 }, // glbl_err_addr + { 0xf80 , 0xffffffff , 32 }, // glbl_sec +}; + +#ifdef __cplusplus +} /* gaudi2 namespace */ +#endif + +#pragma pack(pop) +#endif /* ASIC_REG_STRUCTS_TPC_H_ */ diff --git a/external_includes/gaudi2/asic_reg_structs/tpc_tensor_regs.h b/external_includes/gaudi2/asic_reg_structs/tpc_tensor_regs.h new file mode 100644 index 0000000..548f736 --- /dev/null +++ b/external_includes/gaudi2/asic_reg_structs/tpc_tensor_regs.h @@ -0,0 +1,385 @@ +/*********************************** +** This is an auto-generated file ** +** DO NOT EDIT BELOW ** +************************************/ + +#ifndef ASIC_REG_STRUCTS_TPC_TENSOR_H_ +#define ASIC_REG_STRUCTS_TPC_TENSOR_H_ + +#include +#include "gaudi2_types.h" + +#pragma pack(push, 1) + +#ifdef __cplusplus +namespace gaudi2 { +namespace tpc_tensor { +#else +# ifndef static_assert +# if defined( __STDC__ ) && defined( __STDC_VERSION__ ) && __STDC_VERSION__ >= 201112L +# define static_assert(...) _Static_assert(__VA_ARGS__) +# else +# define static_assert(...) +# endif +# endif +#endif + +/* + BASE_ADDR_LOW + b'bits 31 to 0 of the base address' +*/ +typedef struct reg_base_addr_low { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_base_addr_low; +static_assert((sizeof(struct reg_base_addr_low) == 4), "reg_base_addr_low size is not 32-bit"); +/* + BASE_ADDR_HIGH + b'bits 63 to 32 of the base address' +*/ +typedef struct reg_base_addr_high { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_base_addr_high; +static_assert((sizeof(struct reg_base_addr_high) == 4), "reg_base_addr_high size is not 32-bit"); +/* + PADDING_VALUE + b'padding value when tensor access is out of bound' +*/ +typedef struct reg_padding_value { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_padding_value; +static_assert((sizeof(struct reg_padding_value) == 4), "reg_padding_value size is not 32-bit"); +/* + TENSOR_CONFIG + b'general tensor configuration' +*/ +typedef struct reg_tensor_config { + union { + struct { + uint32_t data_type : 4, + _reserved8 : 4, + valid_dim_mask : 5, + last_dim64 : 1, + _reserved16 : 2, + last_dim : 3, + rmw_set : 1, + _reserved21 : 1, + rmw_op : 3, + dup_oob : 1, + l0cd : 1, + t_pref_dis : 1, + _reserved27 : 5; + }; + uint32_t _raw; + }; +} reg_tensor_config; +static_assert((sizeof(struct reg_tensor_config) == 4), "reg_tensor_config size is not 32-bit"); +/* + DIM_0_SIZE + b'number of elements in dimension 0' +*/ +typedef struct reg_dim_0_size { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_dim_0_size; +static_assert((sizeof(struct reg_dim_0_size) == 4), "reg_dim_0_size size is not 32-bit"); +/* + DIM_0_STRIDE + b'dimension 0 stride' +*/ +typedef struct reg_dim_0_stride { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_dim_0_stride; +static_assert((sizeof(struct reg_dim_0_stride) == 4), "reg_dim_0_stride size is not 32-bit"); +/* + DIM_1_SIZE + b'number of elements in dimension 1' +*/ +typedef struct reg_dim_1_size { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_dim_1_size; +static_assert((sizeof(struct reg_dim_1_size) == 4), "reg_dim_1_size size is not 32-bit"); +/* + DIM_1_STRIDE + b'dimension 1 stride' +*/ +typedef struct reg_dim_1_stride { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_dim_1_stride; +static_assert((sizeof(struct reg_dim_1_stride) == 4), "reg_dim_1_stride size is not 32-bit"); +/* + DIM_2_SIZE + b'number of elements in dimension 2' +*/ +typedef struct reg_dim_2_size { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_dim_2_size; +static_assert((sizeof(struct reg_dim_2_size) == 4), "reg_dim_2_size size is not 32-bit"); +/* + DIM_2_STRIDE + b'dimension 2 stride' +*/ +typedef struct reg_dim_2_stride { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_dim_2_stride; +static_assert((sizeof(struct reg_dim_2_stride) == 4), "reg_dim_2_stride size is not 32-bit"); +/* + DIM_3_SIZE + b'number of elements in dimension 3' +*/ +typedef struct reg_dim_3_size { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_dim_3_size; +static_assert((sizeof(struct reg_dim_3_size) == 4), "reg_dim_3_size size is not 32-bit"); +/* + DIM_3_STRIDE + b'dimension 3 stride' +*/ +typedef struct reg_dim_3_stride { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_dim_3_stride; +static_assert((sizeof(struct reg_dim_3_stride) == 4), "reg_dim_3_stride size is not 32-bit"); +/* + DIM_4_SIZE + b'number of elements in dimension4' +*/ +typedef struct reg_dim_4_size { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_dim_4_size; +static_assert((sizeof(struct reg_dim_4_size) == 4), "reg_dim_4_size size is not 32-bit"); +/* + DIM_4_STRIDE + b'dimension 4 stride' +*/ +typedef struct reg_dim_4_stride { + union { + struct { + uint32_t v : 32; + }; + uint32_t _raw; + }; +} reg_dim_4_stride; +static_assert((sizeof(struct reg_dim_4_stride) == 4), "reg_dim_4_stride size is not 32-bit"); +/* + PREF_STRIDE + b'Prefetcher strides' +*/ +typedef struct reg_pref_stride { + union { + struct { + uint32_t val : 16, + _reserved16 : 16; + }; + uint32_t _raw; + }; +} reg_pref_stride; +static_assert((sizeof(struct reg_pref_stride) == 4), "reg_pref_stride size is not 32-bit"); +/* + DIM_0_SIZE_STRIDE_HIGH + b'Size and Stride high part dim 0' +*/ +typedef struct reg_dim_0_size_stride_high { + union { + struct { + uint32_t stride_high : 12, + _reserved16 : 4, + size_high : 12, + _reserved28 : 4; + }; + uint32_t _raw; + }; +} reg_dim_0_size_stride_high; +static_assert((sizeof(struct reg_dim_0_size_stride_high) == 4), "reg_dim_0_size_stride_high size is not 32-bit"); +/* + DIM_1_SIZE_STRIDE_HIGH + b'Size and Stride high part dim 1' +*/ +typedef struct reg_dim_1_size_stride_high { + union { + struct { + uint32_t stride_high : 12, + _reserved16 : 4, + size_high : 12, + _reserved28 : 4; + }; + uint32_t _raw; + }; +} reg_dim_1_size_stride_high; +static_assert((sizeof(struct reg_dim_1_size_stride_high) == 4), "reg_dim_1_size_stride_high size is not 32-bit"); +/* + DIM_2_SIZE_STRIDE_HIGH + b'Size and Stride high part dim 2' +*/ +typedef struct reg_dim_2_size_stride_high { + union { + struct { + uint32_t stride_high : 12, + _reserved16 : 4, + size_high : 12, + _reserved28 : 4; + }; + uint32_t _raw; + }; +} reg_dim_2_size_stride_high; +static_assert((sizeof(struct reg_dim_2_size_stride_high) == 4), "reg_dim_2_size_stride_high size is not 32-bit"); +/* + DIM_3_SIZE_STRIDE_HIGH + b'Size and Stride high part dim 3' +*/ +typedef struct reg_dim_3_size_stride_high { + union { + struct { + uint32_t stride_high : 12, + _reserved16 : 4, + size_high : 12, + _reserved28 : 4; + }; + uint32_t _raw; + }; +} reg_dim_3_size_stride_high; +static_assert((sizeof(struct reg_dim_3_size_stride_high) == 4), "reg_dim_3_size_stride_high size is not 32-bit"); +/* + DIM_4_SIZE_STRIDE_HIGH + b'Size and Stride high part dim 4' +*/ +typedef struct reg_dim_4_size_stride_high { + union { + struct { + uint32_t stride_high : 12, + _reserved16 : 4, + size_high : 12, + _reserved28 : 4; + }; + uint32_t _raw; + }; +} reg_dim_4_size_stride_high; +static_assert((sizeof(struct reg_dim_4_size_stride_high) == 4), "reg_dim_4_size_stride_high size is not 32-bit"); + +#ifdef __cplusplus +} /* tpc_tensor namespace */ +#endif + +/* + TPC_TENSOR block +*/ + +#ifdef __cplusplus + +struct block_tpc_tensor { + struct tpc_tensor::reg_base_addr_low base_addr_low; + struct tpc_tensor::reg_base_addr_high base_addr_high; + struct tpc_tensor::reg_padding_value padding_value; + struct tpc_tensor::reg_tensor_config tensor_config; + struct tpc_tensor::reg_dim_0_size dim_0_size; + struct tpc_tensor::reg_dim_0_stride dim_0_stride; + struct tpc_tensor::reg_dim_1_size dim_1_size; + struct tpc_tensor::reg_dim_1_stride dim_1_stride; + struct tpc_tensor::reg_dim_2_size dim_2_size; + struct tpc_tensor::reg_dim_2_stride dim_2_stride; + struct tpc_tensor::reg_dim_3_size dim_3_size; + struct tpc_tensor::reg_dim_3_stride dim_3_stride; + struct tpc_tensor::reg_dim_4_size dim_4_size; + struct tpc_tensor::reg_dim_4_stride dim_4_stride; + struct tpc_tensor::reg_pref_stride pref_stride; + struct tpc_tensor::reg_dim_0_size_stride_high dim_0_size_stride_high; + struct tpc_tensor::reg_dim_1_size_stride_high dim_1_size_stride_high; + struct tpc_tensor::reg_dim_2_size_stride_high dim_2_size_stride_high; + struct tpc_tensor::reg_dim_3_size_stride_high dim_3_size_stride_high; + struct tpc_tensor::reg_dim_4_size_stride_high dim_4_size_stride_high; +}; +#else + +typedef struct block_tpc_tensor { + reg_base_addr_low base_addr_low; + reg_base_addr_high base_addr_high; + reg_padding_value padding_value; + reg_tensor_config tensor_config; + reg_dim_0_size dim_0_size; + reg_dim_0_stride dim_0_stride; + reg_dim_1_size dim_1_size; + reg_dim_1_stride dim_1_stride; + reg_dim_2_size dim_2_size; + reg_dim_2_stride dim_2_stride; + reg_dim_3_size dim_3_size; + reg_dim_3_stride dim_3_stride; + reg_dim_4_size dim_4_size; + reg_dim_4_stride dim_4_stride; + reg_pref_stride pref_stride; + reg_dim_0_size_stride_high dim_0_size_stride_high; + reg_dim_1_size_stride_high dim_1_size_stride_high; + reg_dim_2_size_stride_high dim_2_size_stride_high; + reg_dim_3_size_stride_high dim_3_size_stride_high; + reg_dim_4_size_stride_high dim_4_size_stride_high; +} block_tpc_tensor; +#endif + +const offsetVal block_tpc_tensor_defaults[] = +{ + // offset // value + { 0xc , 0x50000 , 1 }, // tensor_config +}; + +#ifdef __cplusplus +} /* gaudi2 namespace */ +#endif + +#pragma pack(pop) +#endif /* ASIC_REG_STRUCTS_TPC_TENSOR_H_ */ diff --git a/external_includes/gaudi2/gaudi2_packets.h b/external_includes/gaudi2/gaudi2_packets.h new file mode 100644 index 0000000..2e15b13 --- /dev/null +++ b/external_includes/gaudi2/gaudi2_packets.h @@ -0,0 +1,427 @@ +/* SPDX-License-Identifier: MIT + * + * Copyright 2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#ifndef GAUDI2_PACKETS_H +#define GAUDI2_PACKETS_H + +#include + +#define PACKET_HEADER_PACKET_ID_SHIFT 56 +#define PACKET_HEADER_PACKET_ID_MASK 0x1F00000000000000ull +namespace gaudi2 +{ +enum packet_id { + PACKET_WREG_32 = 0x1, + PACKET_WREG_BULK = 0x2, + PACKET_MSG_LONG = 0x3, + PACKET_MSG_SHORT = 0x4, + PACKET_CP_DMA = 0x5, + PACKET_REPEAT = 0x6, + PACKET_MSG_PROT = 0x7, + PACKET_FENCE = 0x8, + PACKET_LIN_DMA = 0x9, + PACKET_NOP = 0xA, + PACKET_STOP = 0xB, + PACKET_ARB_POINT = 0xC, + PACKET_WAIT = 0xD, + PACKET_CB_LIST = 0xE, + PACKET_LOAD_AND_EXE = 0xF, + PACKET_WRITE_ARC_STREAM = 0x10, + PACKET_WREG_64_SHORT = 0x12, + PACKET_WREG_64_LONG = 0x13, + MAX_PACKET_ID = (PACKET_HEADER_PACKET_ID_MASK >> + PACKET_HEADER_PACKET_ID_SHIFT) + 1 +}; + +struct packet_nop { + __u32 reserved; + union { + struct { + __u32 :24; + __u32 opcode :5; + __u32 eng_barrier :1; + __u32 swtc :1; + __u32 msg_barrier :1; + }; + __u32 ctl; + }; +}; + +struct packet_stop { + __u32 reserved; + union { + struct { + __u32 :24; + __u32 opcode :5; + __u32 eng_barrier :1; + __u32 swtc :1; + __u32 msg_barrier :1; + }; + __u32 ctl; + }; +}; + +struct packet_wreg32 { + union { + struct { + __u32 reg_id :2; + __u32 :30; + }; + __u32 value; + }; + union { + struct { + __u32 pred :5; + __u32 reg :1; + __u32 :2; + __u32 reg_offset :16; + __u32 opcode :5; + __u32 eng_barrier :1; + __u32 swtc :1; + __u32 msg_barrier :1; + }; + __u32 ctl; + }; +}; + +struct packet_wreg_bulk { + __u32 size64 :16; + __u32 :16; + union { + struct { + __u32 pred :5; + __u32 :3; + __u32 reg_offset :16; + __u32 opcode :5; + __u32 eng_barrier :1; + __u32 swtc :1; + __u32 msg_barrier :1; + }; + __u32 ctl; + }; + __u64 values[0]; /* data starts here */ +}; + +struct packet_msg_long { + __u32 value; + union { + struct { + __u32 pred :5; + __u32 :11; + __u32 weakly_ordered :1; + __u32 no_snoop :1; + __u32 :2; + __u32 op :2; /* 0: write . 1: write timestamp. */ + __u32 :2; + __u32 opcode :5; + __u32 eng_barrier :1; + __u32 swtc :1; + __u32 msg_barrier :1; + }; + __u32 ctl; + }; + __u64 addr; +}; + +struct packet_msg_short { + union { + struct { + __u32 sync_group_id :8; + __u32 mask :8; + __u32 mode :1; + __u32 sync_value :15; + } mon_arm_register; + struct { + __u32 long_sob :1; + __u32:3; + __u32 cq_en :1; + __u32 wr_num :2; + __u32:1; + __u32 lbw_en :1; + __u32:7; + __u32 msb_sid :4; + __u32:11; + __u32 long_high_group :1; + } mon_config_register; + struct { + __u32 sync_value :15; + __u32:9; + __u32 long_mode :1; + __u32:5; + __u32 te :1; + __u32 mode :1; + } so_upd; + __u32 value; + }; + union { + struct { + __u32 msg_addr_offset :16; + __u32 weakly_ordered :1; + __u32 no_snoop :1; + __u32 dw :1; + __u32 :1; + __u32 op :2; + __u32 base :2; + __u32 opcode :5; + __u32 eng_barrier :1; + __u32 swtc :1; + __u32 msg_barrier :1; + }; + __u32 ctl; + }; +}; + +struct packet_msg_prot { + __u32 value; + union { + struct { + __u32 pred :5; + __u32 :11; + __u32 weakly_ordered :1; + __u32 no_snoop :1; + __u32 :2; + __u32 op :2; /* 0: write . 1: write timestamp. */ + __u32 :2; + __u32 opcode :5; + __u32 eng_barrier :1; + __u32 swtc :1; + __u32 msg_barrier :1; + }; + __u32 ctl; + }; + __u64 addr; +}; + +struct packet_fence { + union { + struct { + __u32 dec_val :4; + __u32 :12; + __u32 target_val :8; + __u32 :6; + __u32 id :2; + }; + __u32 cfg; + }; + union { + struct { + __u32 pred :5; + __u32 :19; + __u32 opcode :5; + __u32 eng_barrier :1; + __u32 swtc :1; + __u32 msg_barrier :1; + }; + __u32 ctl; + }; +}; + +struct packet_lin_dma { + __u32 tsize; + union { + struct { + __u32 wrcomp :1; + __u32 endian :2; + __u32 :1; + __u32 memset :1; + __u32 :1; + __u32 bf16 :1; + __u32 fp16 :1; + __u32 context_id_inc :1; + __u32 add_offset_0 :1; + __u32 :14; + __u32 opcode :5; + __u32 eng_barrier :1; + __u32 swtc :1; + __u32 msg_barrier :1; + }; + __u32 ctl; + }; + __u64 src_addr; + __u64 dst_addr; +}; + +struct packet_arb_point { + union { + struct { + __u32 priority :24; + __u32:7; + __u32 rls :1; + }; + __u32 cfg; + }; + union { + struct { + __u32 pred :5; + __u32 :19; + __u32 opcode :5; + __u32 eng_barrier :1; + __u32 :1; + __u32 msg_barrier :1; + }; + __u32 ctl; + }; +}; + +struct packet_repeat { + __u32 sore :1; + __u32 outer :1; + __u32 :14; + __u32 jmp_ptr :16; + union { + struct { + __u32 pred :5; + __u32 :19; + __u32 opcode :5; + __u32 eng_barrier :1; + __u32 :1; + __u32 msg_barrier :1; + }; + __u32 ctl; + }; +}; + +struct packet_wait { + __u32 num_cycles_to_wait :24; + __u32 inc_val :4; + __u32 id :2; + __u32 :2; + union { + struct { + __u32 :24; + __u32 opcode :5; + __u32 eng_barrier :1; + __u32 :1; + __u32 msg_barrier :1; + }; + __u32 ctl; + }; +}; + +struct packet_cb_list { + __u32 reserved; + union { + struct { + __u32 pred :5; + __u32 size_desc :1; + __u32 :18; + __u32 opcode :5; + __u32 eng_barrier :1; + __u32 :1; + __u32 msg_barrier :1; + }; + __u32 ctl; + }; + __u64 index_addr; + __u64 table_addr; +}; + +struct packet_load_and_exe { + union { + struct { + __u32 dst :1; + __u32 pmap :1; + __u32 :6; + __u32 load :1; + __u32 exe :1; + __u32 etype :1; + __u32 :21; + }; + __u32 cfg; + }; + union { + struct { + __u32 pred :5; + __u32 :19; + __u32 opcode :5; + __u32 eng_barrier :1; + __u32 swtc :1; + __u32 msg_barrier :1; + }; + __u32 ctl; + }; + __u64 src_addr; +}; + +struct packet_cp_dma { + __u32 tsize; + union { + struct { + __u32 pred :5; + __u32 upper_cp :1; + __u32 :18; + __u32 opcode :5; + __u32 eng_barrier :1; + __u32 :1; + __u32 msg_barrier :1; + }; + __u32 ctl; + }; + __u64 src_addr; +}; + +struct packet_write_arc_stream { + __u32 size64 :16; + __u32 :16; + union { + struct { + __u32 :24; + __u32 opcode :5; + __u32 eng_barrier :1; + __u32 swtc :1; + __u32 msg_barrier :1; + }; + __u32 ctl; + }; + __u64 values[0]; /* data starts here */ +}; + +struct packet_wreg64_short { + union { + struct { + __u32 reg_id :2; + __u32 :30; + }; + __u32 offset; + }; + union { + struct { + __u32 pred :5; + __u32 base :4; + __u32 reg :1; + __u32 dreg_offset :14; + __u32 opcode :5; + __u32 eng_barrier :1; + __u32 swtc :1; + __u32 msg_barrier :1; + }; + __u32 ctl; + }; +}; + +struct packet_wreg64_long { + __u32 dw_enable :2; + __u32 :30; + union { + struct { + __u32 pred :5; + __u32 base :4; + __u32 rel :1; + __u32 dreg_offset :14; + __u32 opcode :5; + __u32 eng_barrier :1; + __u32 swtc :1; + __u32 msg_barrier :1; + }; + __u32 ctl; + }; + __u64 offset; +}; + +} //namespace gaudi2 + +#endif /* GAUDI2_PACKETS_ */ diff --git a/external_includes/gaudi2/gaudi2_tpc_descriptor.h b/external_includes/gaudi2/gaudi2_tpc_descriptor.h new file mode 100644 index 0000000..3b089f4 --- /dev/null +++ b/external_includes/gaudi2/gaudi2_tpc_descriptor.h @@ -0,0 +1,23 @@ +#ifndef _GAUDI2_TPC_DESC_H_ +#define _GAUDI2_TPC_DESC_H_ + +#include + +#include "asic_reg/gaudi2_blocks.h" +#include "asic_reg_structs/tpc_regs.h" + +#pragma pack(push, 4) +namespace gaudi2 +{ +struct Gaudi2TpcDesc +{ + static const int c_max_tensor_dims = 5; + static const int c_max_tensors_nr = 16; + + gaudi2::block_tpc_tensor m_tensors[c_max_tensors_nr]; + gaudi2::block_sync_object m_so; + gaudi2::block_tpc_non_tensor_descriptor m_desc; +}; +} // namespace gaudi2 +#pragma pack(pop) +#endif // _GAUDI2_TPC_DESC_H_ diff --git a/external_includes/gc_interface.h b/external_includes/gc_interface.h index eab4b98..248d8be 100644 --- a/external_includes/gc_interface.h +++ b/external_includes/gc_interface.h @@ -40,6 +40,7 @@ typedef enum _DeviceId_t { DEVICE_ID_GOYA = 0 , DEVICE_ID_GAUDI = 1 , + DEVICE_ID_GAUDI2 = 3 , // MUST BE LAST DEVICE_ID_MAX = 5 } DeviceId_t; @@ -196,7 +197,9 @@ typedef enum _TensorDataType_t DATA_U4 = 10, DATA_F8_152 = 11, DATA_F8_143 = 12, - NUM_DATATYPES = 13 + DATA_I64 = 13, + DATA_U64 = 14, + NUM_DATATYPES = 15 } TensorDataType_t; typedef enum _KernelType_t diff --git a/external_includes/synapse_common_types.h b/external_includes/synapse_common_types.h index f12c324..bd0f2a9 100644 --- a/external_includes/synapse_common_types.h +++ b/external_includes/synapse_common_types.h @@ -105,6 +105,7 @@ typedef enum synMemFlags typedef enum synDeviceType { synDeviceGaudi, + synDeviceGaudi2, synDeviceTypeInvalid, synDeviceTypeSize } synDeviceType; diff --git a/synapse_backend/infra/heap_allocator.cpp b/synapse_backend/infra/heap_allocator.cpp index 8a9189e..8ef9fc4 100644 --- a/synapse_backend/infra/heap_allocator.cpp +++ b/synapse_backend/infra/heap_allocator.cpp @@ -14,11 +14,14 @@ HeapAllocator::HeapAllocator(const std::string &name) : MemoryAllocatorBase(name { } -void HeapAllocator::Init(uint64_t memorySize, uint64_t base) +void HeapAllocator::Init(DriverDevice* device, bool mmuEnabled, uint64_t memorySize, uint64_t base) { std::lock_guard l(m_mutex); - MemoryAllocatorBase::Init(memorySize, base); - + MemoryAllocatorBase::Init(device, mmuEnabled, memorySize, base); + if (m_mmuEnabled) + { + m_device->dramMemoryAllocAndMap(); + } Range allRanges; allRanges.size = m_memorySize; allRanges.base = m_base; @@ -33,6 +36,10 @@ void HeapAllocator::Deinit() m_occupiedRanges.clear(); m_memorySize = 0; m_base = 0; + if (m_mmuEnabled) + { + m_device->dramMemoryFree(); + } } uint64_t HeapAllocator::Allocate(uint64_t size, uint64_t alignment, uint64_t offset) diff --git a/synapse_backend/infra/heap_allocator.h b/synapse_backend/infra/heap_allocator.h index 02f9b87..66c29b4 100644 --- a/synapse_backend/infra/heap_allocator.h +++ b/synapse_backend/infra/heap_allocator.h @@ -23,7 +23,7 @@ class HeapAllocator : public MemoryAllocatorBase HeapAllocator(const std::string& name); virtual ~HeapAllocator() {} - virtual void Init(uint64_t memorySize, uint64_t base = 0) override; + virtual void Init(DriverDevice* device, bool mmuEnabled, uint64_t memorySize, uint64_t base = 0) override; void Deinit(); virtual uint64_t Allocate(uint64_t size, uint64_t alignment, uint64_t offset = 0) override; virtual void Free(uint64_t ptr) override; diff --git a/synapse_backend/infra/memory_allocator.cpp b/synapse_backend/infra/memory_allocator.cpp index 81892a1..1bae092 100644 --- a/synapse_backend/infra/memory_allocator.cpp +++ b/synapse_backend/infra/memory_allocator.cpp @@ -14,8 +14,10 @@ MemoryAllocatorBase::MemoryAllocatorBase(const std::string& name) { } -void MemoryAllocatorBase::Init(uint64_t memorySize, uint64_t base) +void MemoryAllocatorBase::Init(DriverDevice* device, bool mmuEnabled, uint64_t memorySize, uint64_t base) { m_memorySize = memorySize; m_base = base; + m_device = device; + m_mmuEnabled = mmuEnabled; } diff --git a/synapse_backend/infra/memory_allocator.h b/synapse_backend/infra/memory_allocator.h index 5617c5c..0d399c8 100644 --- a/synapse_backend/infra/memory_allocator.h +++ b/synapse_backend/infra/memory_allocator.h @@ -8,6 +8,7 @@ #ifndef _MEMORY_ALLOCATOR_H_ #define _MEMORY_ALLOCATOR_H_ +#include "driver_device.h" #include #include @@ -16,7 +17,7 @@ class SynMemoryAllocator public: SynMemoryAllocator() {} virtual ~SynMemoryAllocator() {} - virtual void Init(uint64_t memorySize, uint64_t base = 0) = 0; + virtual void Init(DriverDevice* device, bool mmuEnabled, uint64_t memorySize, uint64_t base = 0) = 0; virtual uint64_t Allocate(uint64_t size, uint64_t alignment, uint64_t offset = 0) = 0; virtual void Free(uint64_t ptr) = 0; virtual uint64_t GetMemorySize() const = 0; @@ -30,7 +31,7 @@ class MemoryAllocatorBase : public SynMemoryAllocator public: MemoryAllocatorBase(const std::string& name); virtual ~MemoryAllocatorBase() {} - virtual void Init(uint64_t memorySize, uint64_t base = 0) override; + virtual void Init(DriverDevice* device, bool mmuEnabled, uint64_t memorySize, uint64_t base = 0) override; virtual uint64_t Allocate(uint64_t size, uint64_t alignment, uint64_t offset = 0) = 0; virtual void Free(uint64_t ptr) override = 0; @@ -40,7 +41,8 @@ class MemoryAllocatorBase : public SynMemoryAllocator protected: uint64_t m_base; uint64_t m_memorySize; - + DriverDevice* m_device = nullptr; + bool m_mmuEnabled = false; const std::string m_name; }; diff --git a/synapse_backend/low_level_driver/device.h b/synapse_backend/low_level_driver/device.h index 5d3074c..0b22478 100644 --- a/synapse_backend/low_level_driver/device.h +++ b/synapse_backend/low_level_driver/device.h @@ -30,7 +30,7 @@ class Device typedef uint64_t Handle; - virtual bool OpenDevice(const char *pciId) = 0; + virtual bool OpenDevice(const char *pciId, const hlthunk_device_name deviceName) = 0; virtual void CloseDevice() = 0; virtual bool SubmitWklds( const std::list &setup, diff --git a/synapse_backend/low_level_driver/driver_device.cpp b/synapse_backend/low_level_driver/driver_device.cpp index b082328..206ffc5 100644 --- a/synapse_backend/low_level_driver/driver_device.cpp +++ b/synapse_backend/low_level_driver/driver_device.cpp @@ -34,17 +34,17 @@ DriverDevice::~DriverDevice() assert(m_fd == -1); } -bool DriverDevice::OpenDevice(const char* pciId) +bool DriverDevice::OpenDevice(const char* pciId, const hlthunk_device_name deviceName) { for (unsigned tries = 0; tries < c_open_device_max_tries_num; tries++) { if (!strcmp(pciId, "")) { - m_fd = hlthunk_open(HLTHUNK_DEVICE_GAUDI, NULL); + m_fd = hlthunk_open(deviceName, NULL); } else { - m_fd = hlthunk_open(HLTHUNK_DEVICE_GAUDI, pciId); + m_fd = hlthunk_open(deviceName, pciId); } if ((m_fd == -1) && ((errno == EBUSY) || (errno == EAGAIN))) @@ -59,7 +59,7 @@ bool DriverDevice::OpenDevice(const char* pciId) if (m_fd < 0) { - assert(0 && "Check Driver availability. If using -pci, check pci address provided."); + assert(0 && "Check Driver availability."); return false; } else @@ -87,12 +87,11 @@ bool DriverDevice::SubmitWklds(const std::list& setup, } assert(!wklds.empty() || !setup.empty()); - hl_cs_chunk setupChunks[GAUDI_ENGINE_ID_SIZE]; - hl_cs_chunk exeChunks[GAUDI_ENGINE_ID_SIZE]; - memset(&exeChunks, 0, sizeof(exeChunks)); - memset(&setupChunks, 0, sizeof(setupChunks)); - assert(setup.size() <= (sizeof(setupChunks) / sizeof(setupChunks[0]))); - assert(wklds.size() <= (sizeof(exeChunks) / sizeof(exeChunks[0]))); + std::vector setupChunks(GetHal()->GetQidSize(), hl_cs_chunk{}); + std::vector exeChunks(GetHal()->GetQidSize(), hl_cs_chunk{}); + + assert(setup.size() <= setupChunks.size()); + assert(wklds.size() <= exeChunks.size()); unsigned idx = 0; for (auto& su : setup) @@ -118,8 +117,8 @@ bool DriverDevice::SubmitWklds(const std::list& setup, hlthunk_cs_out argsOut; memset(&argsIn, 0, sizeof(hlthunk_cs_in)); memset(&argsOut, 0, sizeof(hlthunk_cs_out)); - argsIn.chunks_restore = setupChunks; - argsIn.chunks_execute = exeChunks; + argsIn.chunks_restore = setupChunks.data(); + argsIn.chunks_execute = exeChunks.data(); argsIn.num_chunks_restore = setup.size(); argsIn.num_chunks_execute = wklds.size(); argsIn.flags = forceSetup ? HL_CS_FLAGS_FORCE_RESTORE : 0; @@ -169,36 +168,51 @@ bool DriverDevice::GetCB(unsigned size, Handle& handle, void*& hostAddr, unsigne static const unsigned int c_page_size = getpagesize(); assert(size); unsigned requestedSize = std::max(size, c_page_size); - + uint64_t hostVA = 0; int ret; - - ret = hlthunk_request_command_buffer(m_fd, requestedSize, &handle); - - if (ret != 0) + bool isUserCb; + if (IsMmuEnabled()) { - assert(0); - return false; - } + hostAddr = (void*)(new uint8_t[requestedSize]); - if (m_cbHandles.find(handle) != m_cbHandles.end()) - { - assert(0); - return false; + ret = MapHostMemory((uint64_t)hostAddr, requestedSize, hostVA); + assert(hostVA); + handle = hostVA; + isUserCb = true; + flags = HL_CS_CHUNK_FLAGS_USER_ALLOC_CB; // CB is allocated by the user } - flags = 0; // CB is not allocated by the user - // mapping handle to host address - hostAddr = mmap(0, size, PROT_READ | PROT_WRITE, MAP_SHARED, m_fd, (off_t)handle); - - if (!hostAddr) + else { - assert(0); - return false; - } + ret = hlthunk_request_command_buffer(m_fd, requestedSize, &handle); + if (ret != 0) + { + assert(0); + return false; + } + + if (m_cbHandles.find(handle) != m_cbHandles.end()) + { + assert(0); + return false; + } + flags = 0; // CB is not allocated by the user + // mapping handle to host address + hostAddr = mmap(0, size, PROT_READ | PROT_WRITE, MAP_SHARED, m_fd, (off_t)handle); + + if (!hostAddr) + { + assert(0); + return false; + } + isUserCb = false; + } VirtMem vm = {0}; + vm.addrVirt = hostVA; vm.addr = hostAddr; vm.size = size; vm.cbSize = requestedSize; + vm.isUserCb = isUserCb; m_cbHandles[handle] = vm; @@ -222,34 +236,34 @@ bool DriverDevice::ReleaseCB(Handle handle) VirtMem vm = m_cbHandles[handle]; int ret; - hlthunk_device_name deviceName = GetDeviceName(); - if ((deviceName == HLTHUNK_DEVICE_GOYA) || (deviceName == HLTHUNK_DEVICE_GAUDI) || - (!IsMmuEnabled())) + if (vm.isUserCb) { - ret = munmap(vm.addr, vm.size); - if (ret != 0) + ret = UnmapMemory(vm.addrVirt); + delete[](uint8_t*) vm.addr; + if (!ret) { assert(0); return false; } - - ret = hlthunk_destroy_command_buffer(m_fd, (__u64)handle); } else { - hlthunk_memory_unmap(m_fd, handle); - free(m_cbHandles[handle].addr); - ret = 0; + ret = munmap(vm.addr, vm.cbSize); + if (ret != 0) + { + assert(0); + return false; + } + ret = hlthunk_destroy_command_buffer(m_fd, (__u64)handle); + if (ret != 0) + { + assert(0); + return false; + } } m_cbHandles.erase(handle); - if (ret != 0) - { - assert(0); - return false; - } - return true; } @@ -292,6 +306,38 @@ bool DriverDevice::UnmapMemory(uint64_t addr) return true; } +uint64_t DriverDevice::dramMemoryAllocAndMap() +{ + uint64_t size = c_dram_phys_size; + + m_dramHandle = hlthunk_device_memory_alloc(m_fd, size, 0, false, false); // contiguous = 0 + m_dramVirtAddr = 0; + assert(m_dramHandle); + m_dramVirtAddr = hlthunk_device_memory_map(m_fd, m_dramHandle, 0); + if (!m_dramVirtAddr) + { + dramMemoryFree(); + assert(0); + return 0; + } + + return m_dramVirtAddr; +} + +bool DriverDevice::dramMemoryFree() +{ + if (m_dramHandle) { + int ret = hlthunk_device_memory_free(m_fd, m_dramHandle); + if (ret) { + return false; + } else { + } + m_dramHandle = 0; + } + + return true; +} + bool DriverDevice::GetHwIpInfo(hlthunk_hw_ip_info& hwInfo) { if (m_fd == -1) @@ -309,7 +355,7 @@ bool DriverDevice::GetHwIpInfo(hlthunk_hw_ip_info& hwInfo) assert(0); return false; } - + c_dram_phys_size = hwInfo.dram_size; return true; } @@ -350,7 +396,7 @@ bool DriverDevice::IsDramEnabled() bool DriverDevice::IsMmuEnabled() { - return true; + return GetHal()->isMmuEnabled(); } bool DriverDevice::CopyHostDevice(bool toDevice, uint64_t hostPtr, uint64_t devicePtr, uint32_t size) @@ -378,9 +424,9 @@ bool DriverDevice::CopyHostDevice(bool toDevice, uint64_t hostPtr, uint64_t devi std::list execute; workload.size = cmdSize; - workload.flags = 0; + workload.flags = flags; workload.buffer = handle; - workload.qid = toDevice ? GAUDI_QUEUE_ID_DMA_0_0 : GAUDI_QUEUE_ID_DMA_1_0; + workload.qid = toDevice ? GetHal()->GetDMAInQid() : GetHal()->GetDMAOutQid(); execute.push_back(workload); diff --git a/synapse_backend/low_level_driver/driver_device.h b/synapse_backend/low_level_driver/driver_device.h index 37d4b0b..fe74760 100644 --- a/synapse_backend/low_level_driver/driver_device.h +++ b/synapse_backend/low_level_driver/driver_device.h @@ -16,7 +16,7 @@ class DriverDevice : public Device DriverDevice(HWAbstractionLayer* pHal); virtual ~DriverDevice(); - bool OpenDevice(const char* pciId); + bool OpenDevice(const char* pciId, const hlthunk_device_name deviceName); void CloseDevice(); bool SubmitWklds(const std::list& setup, const std::list& wklds, bool forceSetup, Handle& handle); @@ -25,7 +25,8 @@ class DriverDevice : public Device bool ReleaseCB(Handle handle); bool MapHostMemory(Handle hostAddr, unsigned size, uint64_t& virtualAddr, uint64_t hintAddr = 0); bool UnmapMemory(uint64_t addr); - + uint64_t dramMemoryAllocAndMap(); + bool dramMemoryFree(); virtual bool CopyHostDevice(bool toDevice, uint64_t hostPtr, uint64_t devicePtr, uint32_t size); bool GetHwIpInfo(hlthunk_hw_ip_info& hwInfo); @@ -38,13 +39,18 @@ class DriverDevice : public Device private: struct VirtMem { + uint64_t addrVirt; void* addr; unsigned size; unsigned cbSize; + bool isUserCb; }; std::map m_cbHandles; int m_fd; + uint64_t m_dramVirtAddr; + uint64_t m_dramHandle; + uint64_t c_dram_phys_size = 0; DriverDevice(const DriverDevice& other) = delete; DriverDevice& operator=(const DriverDevice& other) = delete; diff --git a/synapse_backend/low_level_driver/gaudi_device.cpp b/synapse_backend/low_level_driver/gaudi/gaudi_device.cpp similarity index 88% rename from synapse_backend/low_level_driver/gaudi_device.cpp rename to synapse_backend/low_level_driver/gaudi/gaudi_device.cpp index 4b754bc..7abb519 100644 --- a/synapse_backend/low_level_driver/gaudi_device.cpp +++ b/synapse_backend/low_level_driver/gaudi/gaudi_device.cpp @@ -8,17 +8,21 @@ #include #include +#include "TensorDescriptor.h" #include "gaudi_device.h" #include "SpecialFuncCoefficients.h" -#include "SpecialFuncCoefficients_defGen2.h" -#include "asic_reg_structs/sync_mngr_regs.h" -#include "asic_reg_structs/qman_regs.h" -#include "asic_reg_structs/dma_core_regs.h" -#include "asic_reg_structs/tpc_regs.h" +#include "gaudi/SpecialFuncCoefficients_defGen2.h" +#include "gaudi/asic_reg_structs/sync_mngr_regs.h" +#include "gaudi/asic_reg_structs/qman_regs.h" +#include "gaudi/asic_reg_structs/dma_core_regs.h" +#include "gaudi/asic_reg_structs/tpc_regs.h" #include "gaudi_packet_gen.h" -#include "asic_reg/gaudi_blocks.h" -#include "gaudi_tpc_descriptor.h" +#include "gaudi/asic_reg/gaudi_blocks.h" +#include "gaudi/gaudi_tpc_descriptor.h" +#include "synapse_common_types.h" +namespace gaudi +{ const unsigned GaudiDevice::c_tpcNr = 8; const unsigned GaudiDevice::c_syncObjNr = 2048; const unsigned GaudiDevice::c_monitorObjNr = 512; @@ -31,7 +35,7 @@ constexpr uint64_t GaudiDevice::GetSyncObjectAddress(int synObjIndex) return c_syncObjectsBaseAddr + (c_syncObjectSizeInBytes * synObjIndex); } -unsigned GaudiDevice::GetTensorSizeFromDesc(TensorDescriptorGaudi& desc) const +unsigned GaudiDevice::GetTensorSizeFromDesc(TensorDescriptor& desc) const { unsigned size = 1; unsigned dims = tpc_gaudi::get_TensorDescriptorLastDim(desc.configuration) + 1; @@ -47,7 +51,7 @@ unsigned GaudiDevice::GetTensorSizeFromDesc(TensorDescriptorGaudi& desc) const return size; } -unsigned GaudiDevice::GetTensorSizeFromDesc(TensorDescriptorGaudi& desc0, TensorDescriptorGaudi& desc1) const +unsigned GaudiDevice::GetTensorSizeFromDesc(TensorDescriptor& desc0, TensorDescriptor& desc1) const { unsigned size = 1; unsigned dims0 = tpc_gaudi::get_TensorDescriptorLastDim(desc0.configuration) + 1; @@ -89,7 +93,7 @@ void GaudiDevice::CopySpecialFuncTab( std::vector>& specialFunctionCoefficients) const { specialFunctionCoefficients.resize(SPECIAL_FUNC_NUM_OF_DIFFERENT_INTERVALS); - tpc_gaudi::buildSpecialFunctionCoefficients(specialFunctionCoefficients); + ::tpc_gaudi::buildSpecialFunctionCoefficients(specialFunctionCoefficients); } int GaudiDevice::GetDmaUpSyncObjectIndex() const @@ -511,7 +515,7 @@ unsigned GaudiDevice::GetTpcCfgVarOffset(std::string varName) const return offset; } -unsigned GaudiDevice::GetMonArmRawVal(unsigned mask, unsigned sid, unsigned sod, unsigned sop) const +unsigned GaudiDevice::GetMonArmRawVal(uint8_t mask, uint8_t sid, unsigned sod, unsigned sop) const { sob_objs::reg_mon_arm monArm; memset(&monArm, 0, sizeof(sob_objs::reg_mon_arm)); @@ -523,52 +527,52 @@ unsigned GaudiDevice::GetMonArmRawVal(unsigned mask, unsigned sid, unsigned sod, return monArm._raw; } -std::shared_ptr GaudiDevice::GenCpDma(uint64_t src, uint32_t size) const +std::shared_ptr<::CPCommand::CpDma> GaudiDevice::GenCpDma(uint64_t src, uint32_t size) const { - std::shared_ptr pCommand; + std::shared_ptr<::CPCommand::CpDma> pCommand; pCommand = std::make_shared(src, size); return pCommand; } -std::shared_ptr GaudiDevice::GenFence(unsigned id, uint8_t targetVal, +std::shared_ptr<::CPCommand::Fence> GaudiDevice::GenFence(unsigned id, uint8_t targetVal, unsigned decVal) const { - std::shared_ptr pCommand; + std::shared_ptr<::CPCommand::Fence> pCommand; pCommand = std::make_shared(id, targetVal, decVal); return pCommand; } -std::shared_ptr GaudiDevice::GenLinDma(uint64_t dst, uint64_t src, +std::shared_ptr<::CPCommand::LinDma> GaudiDevice::GenLinDma(uint64_t dst, uint64_t src, uint32_t tsize, unsigned dmaDir, uint16_t ctxId, bool wrComp) const { // dmaDir not required for Gaudi, only for Goya - std::shared_ptr pCommand; + std::shared_ptr<::CPCommand::LinDma> pCommand; pCommand = std::make_shared(dst, src, tsize, 0, wrComp); pCommand->m_ctxId = ctxId; return pCommand; } -std::shared_ptr GaudiDevice::GenMsgLong(uint64_t addr, uint32_t value, bool mb, +std::shared_ptr<::CPCommand::MsgLong> GaudiDevice::GenMsgLong(uint64_t addr, uint32_t value, bool mb, bool rb, bool eb) const { - std::shared_ptr pCommand; + std::shared_ptr<::CPCommand::MsgLong> pCommand; pCommand = std::make_shared(addr, value, mb, rb, eb); return pCommand; } -std::shared_ptr GaudiDevice::GenWReg32(uint16_t offset, uint32_t value, bool mb, +std::shared_ptr<::CPCommand::WReg32> GaudiDevice::GenWReg32(uint16_t offset, uint32_t value, bool mb, bool rb, bool eb) const { - std::shared_ptr pCommand; + std::shared_ptr<::CPCommand::WReg32> pCommand; pCommand = std::make_shared(offset, value, mb, rb, eb); return pCommand; } -std::shared_ptr GaudiDevice::GenWRegBulk(uint16_t offset, uint32_t* values, +std::shared_ptr<::CPCommand::WRegBulk> GaudiDevice::GenWRegBulk(uint16_t offset, uint32_t* values, unsigned numValues) const { - std::shared_ptr pCommand; + std::shared_ptr<::CPCommand::WRegBulk> pCommand; pCommand = std::make_shared(offset, values, numValues); return pCommand; } @@ -601,18 +605,17 @@ void GaudiDevice::WriteKernelAddr(HWAbstractionLayer::TpcDescHandle tpcDesc, } void GaudiDevice::WriteTensorDesc(HWAbstractionLayer::TpcDescHandle tpcDesc, - TensorDescriptorGaudi& tensorDesc, unsigned tensorId) const + TensorDescriptor& tensorDesc, unsigned tensorId) const { memcpy(&(((GaudiTpcDesc*)(tpcDesc))->m_tensors[tensorId]), &tensorDesc, - sizeof(TensorDescriptorGaudi)); + sizeof(TensorDescriptor)); } void GaudiDevice::WriteTpcJobDesc(HWAbstractionLayer::TpcDescHandle tpcDesc, - const IndexSpace& partition, uint32_t contextId, uint32_t soAddr, - uint32_t soMsg, uint32_t soIdx, bool updatePrintfAddr, + const IndexSpace& partition, uint32_t soAddr, + uint32_t soMsg, bool updatePrintfAddr, int printfTensorIdx) const { - // soIdx not used in Gaudi, only in Goya // load IRF0/1 ((GaudiTpcDesc*)(tpcDesc))->m_desc.tid_size_dim_0.v = partition.size[0]; ((GaudiTpcDesc*)(tpcDesc))->m_desc.tid_size_dim_1.v = partition.size[1]; @@ -626,10 +629,32 @@ void GaudiDevice::WriteTpcJobDesc(HWAbstractionLayer::TpcDescHandle tpcDesc, ((GaudiTpcDesc*)(tpcDesc))->m_desc.tid_base_dim_3.v = partition.offset[3]; ((GaudiTpcDesc*)(tpcDesc))->m_desc.tid_base_dim_4.v = partition.offset[4]; - // generates a unique context ID for each TPC for trace use. - ((GaudiTpcDesc*)(tpcDesc))->m_desc.kernel_id.v = contextId; - ((GaudiTpcDesc*)(tpcDesc))->m_so.addr.v = soAddr; ((GaudiTpcDesc*)(tpcDesc))->m_so.message._raw = soMsg; } + +uint32_t GaudiDevice::GenTpcCmd() const +{ + gaudi::tpc::reg_tpc_cmd command; + memset(&command, 0, sizeof(command)); + command.icache_invalidate = 1; + command.dcache_invalidate = 1; + command.lcache_invalidate = 1; + command.tcache_invalidate = 1; + command.icache_prefetch_64kb = 0; + return command._raw; +} + +uint32_t GaudiDevice::GetTpcTensorConfig() const +{ + struct gaudi::tpc_tensor::reg_tensor_config config; + config._raw = 0; + config.last_dim = 3; + config.valid_dim_mask = 0xF; + config.data_type = TensorDataType::TensorDT_FP32; + return config._raw; + +} + +} // namespace gaudi diff --git a/synapse_backend/low_level_driver/gaudi_device.h b/synapse_backend/low_level_driver/gaudi/gaudi_device.h similarity index 81% rename from synapse_backend/low_level_driver/gaudi_device.h rename to synapse_backend/low_level_driver/gaudi/gaudi_device.h index e99f915..25ec904 100644 --- a/synapse_backend/low_level_driver/gaudi_device.h +++ b/synapse_backend/low_level_driver/gaudi/gaudi_device.h @@ -8,15 +8,18 @@ #pragma once #include "hw_abstraction_layer.h" - +#include "synapse_common_types.h" +namespace gaudi +{ class GaudiDevice : public HWAbstractionLayer { public: GaudiDevice() {} virtual ~GaudiDevice() {} - virtual unsigned GetTensorSizeFromDesc(TensorDescriptorGaudi& desc) const override; - virtual unsigned GetTensorSizeFromDesc(TensorDescriptorGaudi& desc0, TensorDescriptorGaudi& desc1) const override; + virtual synDeviceType getDeviceType() const override {return synDeviceGaudi;} + virtual unsigned GetTensorSizeFromDesc(TensorDescriptor& desc) const override; + virtual unsigned GetTensorSizeFromDesc(TensorDescriptor& desc0, TensorDescriptor& desc1) const override; virtual unsigned GetSpecialFuncTabNr() const override; virtual void GetSpecialFuncTabSizes(uint32_t* sizes, unsigned sizesLen) const override; @@ -42,7 +45,7 @@ class GaudiDevice : public HWAbstractionLayer virtual uint64_t GetSyncMngrVarAddr(std::string varName, unsigned idx) const override; virtual unsigned GetDmaDownVarOffset(std::string varName) const override; virtual unsigned GetTpcCfgVarOffset(std::string varName) const override; - virtual unsigned GetMonArmRawVal(unsigned mask, unsigned sid, unsigned sod, unsigned sop) const override; + virtual unsigned GetMonArmRawVal(uint8_t mask, uint8_t sid, unsigned sod, unsigned sop) const override; virtual void GetTpcTabOffset(int TabIdx, uint32_t* baseAddrLow, uint32_t* baseAddrHigh) const override; virtual std::shared_ptr GenWReg32(uint16_t offset, uint32_t value, bool mb = false, bool rb = false, bool eb = false) const override; @@ -56,8 +59,13 @@ class GaudiDevice : public HWAbstractionLayer virtual void WriteSrf(TpcDescHandle tpcDesc, const uint32_t* params, unsigned paramsNr) const override; virtual void WriteKernelCfg(TpcDescHandle tpcDesc, uint32_t smallVlm) const override; virtual void WriteKernelAddr(TpcDescHandle tpcDesc, uint64_t kernelAddr) const override; - virtual void WriteTensorDesc(TpcDescHandle tpcDesc, TensorDescriptorGaudi& tensorDesc, unsigned tensorId) const override; - virtual void WriteTpcJobDesc(TpcDescHandle tpcDesc, const IndexSpace& partition, uint32_t contextId, uint32_t soAddr, uint32_t soMsg, uint32_t soIdx, bool updatePrintfAddr, int printfTensorIdx) const override; + virtual void WriteTensorDesc(TpcDescHandle tpcDesc, TensorDescriptor& tensorDesc, unsigned tensorId) const override; + virtual void WriteTpcJobDesc(TpcDescHandle tpcDesc, const IndexSpace& partition, uint32_t soAddr, uint32_t soMsg, bool updatePrintfAddr, int printfTensorIdx) const override; + virtual uint32_t GenTpcCmd() const override; + virtual uint32_t GetTpcTensorConfig() const override; + + virtual bool isMmuEnabled() const override {return false;} + virtual bool shouldConfigureMonCfg() const override {return false;} private: GaudiDevice(const GaudiDevice& other) = delete; @@ -74,3 +82,5 @@ class GaudiDevice : public HWAbstractionLayer static const uint64_t c_syncObjectsBaseAddr; static constexpr uint64_t GetSyncObjectAddress(int synObjIndex); }; + +} // namespace gaudi diff --git a/synapse_backend/low_level_driver/gaudi_packet_gen.cpp b/synapse_backend/low_level_driver/gaudi/gaudi_packet_gen.cpp similarity index 87% rename from synapse_backend/low_level_driver/gaudi_packet_gen.cpp rename to synapse_backend/low_level_driver/gaudi/gaudi_packet_gen.cpp index 4ab6613..99074c2 100644 --- a/synapse_backend/low_level_driver/gaudi_packet_gen.cpp +++ b/synapse_backend/low_level_driver/gaudi/gaudi_packet_gen.cpp @@ -6,8 +6,9 @@ */ #include "gaudi_packet_gen.h" -#include "gaudi_packets.h" - +#include "gaudi/gaudi_packets.h" +namespace gaudi +{ unsigned CPCommand::NopGen2::GetSize() const { return sizeof(packet_nop); } unsigned CPCommand::StopGen2::GetSize() const { return sizeof(packet_stop); } unsigned CPCommand::WReg32Gen2::GetSize() const { return sizeof(packet_wreg32); } @@ -26,20 +27,20 @@ unsigned CPCommand::LoadAndExecGen2::GetSize() const { return sizeof(packet_load unsigned CPCommand::CpDmaGen2::GetSize() const { return sizeof(packet_cp_dma); } unsigned CPCommand::ArbPointGen2::GetSize() const { return sizeof(packet_arb_point); } -CPCommand::Command* CPCommand::NopGen2::Clone() const { return new NopGen2(*this); } -CPCommand::Command* CPCommand::StopGen2::Clone() const { return new StopGen2(*this); } -CPCommand::Command* CPCommand::WReg32Gen2::Clone() const { return new WReg32Gen2(*this); } -CPCommand::Command* CPCommand::WRegBulkGen2::Clone() const { return new WRegBulkGen2(*this); } -CPCommand::Command* CPCommand::MsgLongGen2::Clone() const { return new MsgLongGen2(*this); } -CPCommand::Command* CPCommand::MsgShortGen2::Clone() const { return new MsgShortGen2(*this); } -CPCommand::Command* CPCommand::MsgProtGen2::Clone() const { return new MsgProtGen2(*this); } -CPCommand::Command* CPCommand::FenceGen2::Clone() const { return new FenceGen2(*this); } -CPCommand::Command* CPCommand::LinDmaGen2::Clone() const { return new LinDmaGen2(*this); } -CPCommand::Command* CPCommand::RepeatGen2::Clone() const { return new RepeatGen2(*this); } -CPCommand::Command* CPCommand::WaitGen2::Clone() const { return new WaitGen2(*this); } -CPCommand::Command* CPCommand::LoadAndExecGen2::Clone() const { return new LoadAndExecGen2(*this); } -CPCommand::Command* CPCommand::CpDmaGen2::Clone() const { return new CpDmaGen2(*this); } -CPCommand::Command* CPCommand::ArbPointGen2::Clone() const { return new ArbPointGen2(*this); } +::CPCommand::Command* CPCommand::NopGen2::Clone() const { return new NopGen2(*this); } +::CPCommand::Command* CPCommand::StopGen2::Clone() const { return new StopGen2(*this); } +::CPCommand::Command* CPCommand::WReg32Gen2::Clone() const { return new WReg32Gen2(*this); } +::CPCommand::Command* CPCommand::WRegBulkGen2::Clone() const { return new WRegBulkGen2(*this); } +::CPCommand::Command* CPCommand::MsgLongGen2::Clone() const { return new MsgLongGen2(*this); } +::CPCommand::Command* CPCommand::MsgShortGen2::Clone() const { return new MsgShortGen2(*this); } +::CPCommand::Command* CPCommand::MsgProtGen2::Clone() const { return new MsgProtGen2(*this); } +::CPCommand::Command* CPCommand::FenceGen2::Clone() const { return new FenceGen2(*this); } +::CPCommand::Command* CPCommand::LinDmaGen2::Clone() const { return new LinDmaGen2(*this); } +::CPCommand::Command* CPCommand::RepeatGen2::Clone() const { return new RepeatGen2(*this); } +::CPCommand::Command* CPCommand::WaitGen2::Clone() const { return new WaitGen2(*this); } +::CPCommand::Command* CPCommand::LoadAndExecGen2::Clone() const { return new LoadAndExecGen2(*this); } +::CPCommand::Command* CPCommand::CpDmaGen2::Clone() const { return new CpDmaGen2(*this); } +::CPCommand::Command* CPCommand::ArbPointGen2::Clone() const { return new ArbPointGen2(*this); } void CPCommand::NopGen2::Serialize(void** buff) const { @@ -237,3 +238,5 @@ void CPCommand::ArbPointGen2::Serialize(void** buff) const ((packet_arb_point*)(*buff))->pred = m_pred; (*(uint8_t**)buff) += GetSize(); } + +} // namespace gaudi \ No newline at end of file diff --git a/synapse_backend/low_level_driver/gaudi/gaudi_packet_gen.h b/synapse_backend/low_level_driver/gaudi/gaudi_packet_gen.h new file mode 100644 index 0000000..33fb5b4 --- /dev/null +++ b/synapse_backend/low_level_driver/gaudi/gaudi_packet_gen.h @@ -0,0 +1,223 @@ +/* SPDX-License-Identifier: MIT + * + * Copyright 2016-2021 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#pragma once + +#include "program.h" +namespace gaudi +{ +namespace CPCommand +{ + class NopGen2 : public ::CPCommand::Nop + { + public: + NopGen2(bool mb = true, bool rb = true, bool eb = true) : Nop(mb, eb), m_rb(rb) {}; + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_rb = true; + + }; + + class StopGen2 : public ::CPCommand::Stop + { + public: + StopGen2() : Stop() {}; + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_rb = true; + }; + + class WReg32Gen2 : public ::CPCommand::WReg32 + { + public: + WReg32Gen2(uint16_t offset, uint32_t value, bool mb = true, bool rb = true, bool eb = true) : + WReg32(offset, value, mb, eb), m_rb(rb) {}; + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_rb = true; + }; + + class WRegBulkGen2 : public ::CPCommand::WRegBulk + { + public: + WRegBulkGen2() : WRegBulk() {}; + + WRegBulkGen2(uint16_t offset, uint64_t* values, unsigned numValues) : + WRegBulk(offset, values, numValues) {} + + // wregbulk writes in 64-bit words , need to divide num of iteartion by 2. + WRegBulkGen2(uint16_t offset, uint32_t* values, unsigned numValues) : + WRegBulk(offset, (uint64_t*)values, numValues/2) {} + + + WRegBulkGen2(uint16_t offset, std::list::const_iterator &begin, std::list::const_iterator &end) : + WRegBulk(offset, begin, end) {} + + WRegBulkGen2(uint16_t offset, std::list &list) : + WRegBulk(offset, list) {} + + WRegBulkGen2(uint16_t offset, std::list &list) : + WRegBulk(offset, list) {} + + WRegBulkGen2(const WRegBulkGen2 &other) : + WRegBulk(other), m_rb(other.m_rb) {} + + virtual ~WRegBulkGen2() {} + + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_rb = true; + }; + + class MsgLongGen2 : public ::CPCommand::MsgLong + { + public: + MsgLongGen2(uint64_t addr, uint32_t value, bool mb = true, bool rb = true, bool eb = true) : + MsgLong(addr, value, mb, eb), m_rb(rb) {} + + MsgLongGen2() : MsgLong() {} + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_rb = true; + }; + + class MsgShortGen2 : public ::CPCommand::MsgShort + { + public: + MsgShortGen2(unsigned base, uint16_t offset, uint32_t value) : + MsgShort(base, offset, value) {} + + MsgShortGen2() : MsgShort() {} + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_rb = true; + }; + + class MsgProtGen2 : public ::CPCommand::MsgProt + { + public: + MsgProtGen2(uint64_t addr, uint32_t value, bool mb = true, bool rb = true, bool eb = true) : + MsgProt(addr, value, mb, eb), m_rb(rb) {} + + MsgProtGen2() : MsgProt() {} + + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_rb = true; + }; + + class FenceGen2 : public ::CPCommand::Fence + { + public: + FenceGen2(unsigned id, uint8_t targetVal, unsigned decVal, bool mb = true, bool rb = true, bool eb = true) + : Fence(id, targetVal, decVal, mb, eb), m_rb(rb) {} + + FenceGen2() : Fence() {} + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_rb = true; + }; + + class LinDmaGen2 : public ::CPCommand::LinDma + { + public: + LinDmaGen2(uint64_t dst, uint64_t src, uint32_t tsize, unsigned dmaDir, bool wrComp = 0) : + LinDma(dst, src, tsize, dmaDir, wrComp) {} + + LinDmaGen2(const LinDmaGen2& other) : LinDma(other), m_rb(other.m_rb) {} + + LinDmaGen2() : LinDma() {}; + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_rb = true; + }; + + class RepeatGen2 : public ::CPCommand::Repeat + { + public: + RepeatGen2(uint16_t jumpPtr = 0) : Repeat(jumpPtr) {} + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_rb = true; + }; + + class WaitGen2 : public ::CPCommand::Wait + { + public: + WaitGen2(uint32_t cycles, unsigned incVal, unsigned id) : + Wait(cycles, incVal, id) {} + + WaitGen2() : Wait() {}; + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_rb = true; + }; + + class LoadAndExecGen2 : public ::CPCommand::LoadAndExec + { + public: + LoadAndExecGen2() : + LoadAndExec() {} + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_rb = true; + }; + + class CpDmaGen2 : public ::CPCommand::CpDma + { + public: + CpDmaGen2(uint64_t src, uint32_t size) : + CpDma(src, size) {} + + CpDmaGen2() : CpDma() {} + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_rb = true; + }; + + class ArbPointGen2 : public ::CPCommand::ArbPoint + { + public: + ArbPointGen2(uint8_t prio) : + ArbPoint(prio) {} + + ArbPointGen2() : ArbPoint() {} + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_rb = true; + }; +}; + +} // namespace gaudi \ No newline at end of file diff --git a/synapse_backend/low_level_driver/gaudi2/gaudi2_device.cpp b/synapse_backend/low_level_driver/gaudi2/gaudi2_device.cpp new file mode 100644 index 0000000..505a7c4 --- /dev/null +++ b/synapse_backend/low_level_driver/gaudi2/gaudi2_device.cpp @@ -0,0 +1,802 @@ +/* SPDX-License-Identifier: MIT + * + * Copyright 2016-2021 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#include +#include + +#include "TensorDescriptor.h" +#include "gaudi2/asic_reg_structs/sob_objs_regs.h" +#include "gaudi2_device.h" +#include "SpecialFuncCoefficients.h" +#include "gaudi2/SpecialFuncCoefficients_defGen6.h" +#include "gaudi2/asic_reg_structs/qman_regs.h" +#include "gaudi2/asic_reg_structs/dma_core_regs.h" +#include "gaudi2/asic_reg_structs/tpc_regs.h" +#include "gaudi2_packet_gen.h" +#include "gaudi2/asic_reg/gaudi2_blocks.h" +#include "gaudi2/gaudi2_tpc_descriptor.h" + +namespace gaudi2 +{ + +const unsigned Gaudi2Device::c_tpcNr = 24; +const unsigned Gaudi2Device::c_syncObjNr = 8192; +const unsigned Gaudi2Device::c_monitorObjNr = 2048; +const unsigned Gaudi2Device::c_syncObjectGroupSize = 8; +const uint64_t Gaudi2Device::c_syncManagerBase = mmDCORE0_SYNC_MNGR_GLBL_BASE; +const uint64_t Gaudi2Device::c_syncObjectsBaseAddr = mmDCORE0_SYNC_MNGR_OBJS_BASE; +const unsigned Gaudi2Device::c_dmaCoreBlockOffset = mmPDMA0_CORE_BASE - mmPDMA0_QM_ARC_DCCM_BASE; +const unsigned Gaudi2Device::c_tpcCfgBlockOffset = mmDCORE0_TPC0_CFG_BASE - mmDCORE0_TPC0_QM_DCCM_BASE; +inline static uint64_t div_round_up(uint64_t a, uint64_t b) +{ + return (a + b - 1) / b; +} +inline static uint64_t round_to_multiple(uint64_t a, uint64_t mul) +{ + return mul * div_round_up(a, mul); +} + +constexpr uint64_t Gaudi2Device::GetSyncObjectAddress(int synObjIndex) +{ + return c_syncObjectsBaseAddr + (c_syncObjectSizeInBytes * synObjIndex); +} + +unsigned Gaudi2Device::GetTensorSizeFromDesc(TensorDescriptor& desc) const +{ + unsigned size = 1; + unsigned dims = tpc_gaudi2::get_TensorDescriptorLastDim(desc.configuration) + 1; + for (unsigned i = 0; i < dims; i++) + { + size *= desc.dimDescriptors[i].size; + } + // multiply by element size to get result in bytes + unsigned descElement = tpc_gaudi2::get_TensorDescriptorElementSizeType(desc.configuration); + unsigned elementSize = + tpc_gaudi2::get_ElementSizeInBytesFromDataType((TensorDataType)descElement); + size *= elementSize; + return size; +} + +unsigned Gaudi2Device::GetTensorSizeFromDesc(TensorDescriptor& desc0, TensorDescriptor& desc1) const +{ + unsigned size = 1; + unsigned dims0 = tpc_gaudi2::get_TensorDescriptorLastDim(desc0.configuration) + 1; + unsigned dims1 = tpc_gaudi2::get_TensorDescriptorLastDim(desc1.configuration) + 1; + for (unsigned i = 0; i < dims0; i++) + { + size *= desc0.dimDescriptors[i].size; + } + + for (unsigned i = 0; i < dims1; i++) + { + size *= desc1.dimDescriptors[i].size; + } + + // multiply by element size to get result in bytes + unsigned descElement = tpc_gaudi2::get_TensorDescriptorElementSizeType(desc0.configuration); + unsigned elementSize = + tpc_gaudi2::get_ElementSizeInBytesFromDataType((TensorDataType)descElement); + size *= elementSize; + + return size; +} + +unsigned Gaudi2Device::GetSpecialFuncTabNr() const +{ + return SPECIAL_FUNC_NUM_OF_DIFFERENT_INTERVALS; +} + +void Gaudi2Device::GetSpecialFuncTabSizes(uint32_t* sizes, unsigned sizesLen) const +{ + assert(sizesLen >= 4); + sizes[0] = SPECIAL_FUNC256_SIZE_BYTES; + sizes[1] = SPECIAL_FUNC128_SIZE_BYTES; + sizes[2] = SPECIAL_FUNC64_SIZE_BYTES; + sizes[3] = SPECIAL_FUNC32_SIZE_BYTES; +} + +void Gaudi2Device::CopySpecialFuncTab( + std::vector>& specialFunctionCoefficients) const +{ + specialFunctionCoefficients.resize(SPECIAL_FUNC_NUM_OF_DIFFERENT_INTERVALS); + tpc_gaudi2::buildSpecialFunctionCoefficients(specialFunctionCoefficients); +} + +int Gaudi2Device::getAlignedFirstAvailableSOB() const +{ + return round_to_multiple(m_firstAvailSyncObj, c_syncObjectGroupSize); +} + +int Gaudi2Device::GetDmaUpSyncObjectIndex() const +{ + auto sobObjIdx = getAlignedFirstAvailableSOB() + c_syncObjectGroupSize; + return sobObjIdx; +} + +uint64_t Gaudi2Device::GetDmaUpSyncObjectAddr() const +{ + return GetSyncObjectAddress(GetDmaUpSyncObjectIndex()); +} + +int Gaudi2Device::GetDmaDownSyncObjectIndex() const +{ + auto sobIdx = getAlignedFirstAvailableSOB(); + return sobIdx; +} + +uint64_t Gaudi2Device::GetDmaDownSyncObjectAddr() const +{ + return GetSyncObjectAddress(GetDmaDownSyncObjectIndex()); +} + +uint64_t Gaudi2Device::GetSyncManagerBaseAddr() const { return c_syncManagerBase; } + +int Gaudi2Device::GetMonitorObjectBaseIndex() const { return m_firstAvailMonitor; } + +unsigned Gaudi2Device::GetTPCNr() const { return c_tpcNr; } + +unsigned Gaudi2Device::GetTPCQueueId(unsigned tpcId) const +{ + unsigned queueId = GAUDI2_QUEUE_ID_DCORE0_TPC_0_0; + switch (tpcId) + { + case 0: + queueId = GAUDI2_QUEUE_ID_DCORE0_TPC_0_0; + break; + case 1: + queueId = GAUDI2_QUEUE_ID_DCORE0_TPC_1_0; + break; + case 2: + queueId = GAUDI2_QUEUE_ID_DCORE0_TPC_2_0; + break; + case 3: + queueId = GAUDI2_QUEUE_ID_DCORE0_TPC_3_0; + break; + case 4: + queueId = GAUDI2_QUEUE_ID_DCORE0_TPC_4_0; + break; + case 5: + queueId = GAUDI2_QUEUE_ID_DCORE0_TPC_5_0; + break; + case 6: + queueId = GAUDI2_QUEUE_ID_DCORE1_TPC_0_0; + break; + case 7: + queueId = GAUDI2_QUEUE_ID_DCORE1_TPC_1_0; + break; + case 8: + queueId = GAUDI2_QUEUE_ID_DCORE1_TPC_2_0; + break; + case 9: + queueId = GAUDI2_QUEUE_ID_DCORE1_TPC_3_0; + break; + case 10: + queueId = GAUDI2_QUEUE_ID_DCORE1_TPC_4_0; + break; + case 11: + queueId = GAUDI2_QUEUE_ID_DCORE1_TPC_5_0; + break; + case 12: + queueId = GAUDI2_QUEUE_ID_DCORE2_TPC_0_0; + break; + case 13: + queueId = GAUDI2_QUEUE_ID_DCORE2_TPC_1_0; + break; + case 14: + queueId = GAUDI2_QUEUE_ID_DCORE2_TPC_2_0; + break; + case 15: + queueId = GAUDI2_QUEUE_ID_DCORE2_TPC_3_0; + break; + case 16: + queueId = GAUDI2_QUEUE_ID_DCORE2_TPC_4_0; + break; + case 17: + queueId = GAUDI2_QUEUE_ID_DCORE2_TPC_5_0; + break; + case 18: + queueId = GAUDI2_QUEUE_ID_DCORE3_TPC_0_0; + break; + case 19: + queueId = GAUDI2_QUEUE_ID_DCORE3_TPC_1_0; + break; + case 20: + queueId = GAUDI2_QUEUE_ID_DCORE3_TPC_2_0; + break; + case 21: + queueId = GAUDI2_QUEUE_ID_DCORE3_TPC_3_0; + break; + case 22: + queueId = GAUDI2_QUEUE_ID_DCORE3_TPC_4_0; + break; + case 23: + queueId = GAUDI2_QUEUE_ID_DCORE3_TPC_5_0; + break; + default: + assert(0); + } + return queueId; +} + +unsigned Gaudi2Device::GetSyncObjectGroupSize() const { return c_syncObjectGroupSize; } + +void Gaudi2Device::Qid2Qman(unsigned qid, uint64_t& base, unsigned& pqIdx) const +{ + switch (qid) { + case GAUDI2_QUEUE_ID_PDMA_0_0: + case GAUDI2_QUEUE_ID_PDMA_0_1: + case GAUDI2_QUEUE_ID_PDMA_0_2: + case GAUDI2_QUEUE_ID_PDMA_0_3: + base = mmPDMA0_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_PDMA_0_0; + break; + case GAUDI2_QUEUE_ID_PDMA_1_0: + case GAUDI2_QUEUE_ID_PDMA_1_1: + case GAUDI2_QUEUE_ID_PDMA_1_2: + case GAUDI2_QUEUE_ID_PDMA_1_3: + base = mmPDMA1_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_PDMA_1_0; + break; + case GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0: + case GAUDI2_QUEUE_ID_DCORE0_EDMA_0_1: + case GAUDI2_QUEUE_ID_DCORE0_EDMA_0_2: + case GAUDI2_QUEUE_ID_DCORE0_EDMA_0_3: + base = mmDCORE0_EDMA0_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0; + break; + case GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0: + case GAUDI2_QUEUE_ID_DCORE0_EDMA_1_1: + case GAUDI2_QUEUE_ID_DCORE0_EDMA_1_2: + case GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3: + base = mmDCORE0_EDMA1_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0; + break; + case GAUDI2_QUEUE_ID_DCORE0_TPC_0_0: + case GAUDI2_QUEUE_ID_DCORE0_TPC_0_1: + case GAUDI2_QUEUE_ID_DCORE0_TPC_0_2: + case GAUDI2_QUEUE_ID_DCORE0_TPC_0_3: + base = mmDCORE0_TPC0_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE0_TPC_0_0; + break; + case GAUDI2_QUEUE_ID_DCORE0_TPC_1_0: + case GAUDI2_QUEUE_ID_DCORE0_TPC_1_1: + case GAUDI2_QUEUE_ID_DCORE0_TPC_1_2: + case GAUDI2_QUEUE_ID_DCORE0_TPC_1_3: + base = mmDCORE0_TPC1_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE0_TPC_1_0; + break; + case GAUDI2_QUEUE_ID_DCORE0_TPC_2_0: + case GAUDI2_QUEUE_ID_DCORE0_TPC_2_1: + case GAUDI2_QUEUE_ID_DCORE0_TPC_2_2: + case GAUDI2_QUEUE_ID_DCORE0_TPC_2_3: + base = mmDCORE0_TPC2_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE0_TPC_2_0; + break; + case GAUDI2_QUEUE_ID_DCORE0_TPC_3_0: + case GAUDI2_QUEUE_ID_DCORE0_TPC_3_1: + case GAUDI2_QUEUE_ID_DCORE0_TPC_3_2: + case GAUDI2_QUEUE_ID_DCORE0_TPC_3_3: + base = mmDCORE0_TPC3_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE0_TPC_3_0; + break; + case GAUDI2_QUEUE_ID_DCORE0_TPC_4_0: + case GAUDI2_QUEUE_ID_DCORE0_TPC_4_1: + case GAUDI2_QUEUE_ID_DCORE0_TPC_4_2: + case GAUDI2_QUEUE_ID_DCORE0_TPC_4_3: + base = mmDCORE0_TPC4_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE0_TPC_4_0; + break; + case GAUDI2_QUEUE_ID_DCORE0_TPC_5_0: + case GAUDI2_QUEUE_ID_DCORE0_TPC_5_1: + case GAUDI2_QUEUE_ID_DCORE0_TPC_5_2: + case GAUDI2_QUEUE_ID_DCORE0_TPC_5_3: + base = mmDCORE0_TPC5_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE0_TPC_5_0; + break; + case GAUDI2_QUEUE_ID_DCORE0_TPC_6_0: + case GAUDI2_QUEUE_ID_DCORE0_TPC_6_1: + case GAUDI2_QUEUE_ID_DCORE0_TPC_6_2: + case GAUDI2_QUEUE_ID_DCORE0_TPC_6_3: + base = mmDCORE0_TPC6_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE0_TPC_5_0; + break; + case GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0: + case GAUDI2_QUEUE_ID_DCORE1_EDMA_0_1: + case GAUDI2_QUEUE_ID_DCORE1_EDMA_0_2: + case GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3: + base = mmDCORE1_EDMA0_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0; + break; + case GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0: + case GAUDI2_QUEUE_ID_DCORE1_EDMA_1_1: + case GAUDI2_QUEUE_ID_DCORE1_EDMA_1_2: + case GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3: + base = mmDCORE1_EDMA1_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0; + break; + case GAUDI2_QUEUE_ID_DCORE1_TPC_0_0: + case GAUDI2_QUEUE_ID_DCORE1_TPC_0_1: + case GAUDI2_QUEUE_ID_DCORE1_TPC_0_2: + case GAUDI2_QUEUE_ID_DCORE1_TPC_0_3: + base = mmDCORE1_TPC0_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE1_TPC_0_0; + break; + case GAUDI2_QUEUE_ID_DCORE1_TPC_1_0: + case GAUDI2_QUEUE_ID_DCORE1_TPC_1_1: + case GAUDI2_QUEUE_ID_DCORE1_TPC_1_2: + case GAUDI2_QUEUE_ID_DCORE1_TPC_1_3: + base = mmDCORE1_TPC1_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE1_TPC_1_0; + break; + case GAUDI2_QUEUE_ID_DCORE1_TPC_2_0: + case GAUDI2_QUEUE_ID_DCORE1_TPC_2_1: + case GAUDI2_QUEUE_ID_DCORE1_TPC_2_2: + case GAUDI2_QUEUE_ID_DCORE1_TPC_2_3: + base = mmDCORE1_TPC2_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE1_TPC_2_0; + break; + case GAUDI2_QUEUE_ID_DCORE1_TPC_3_0: + case GAUDI2_QUEUE_ID_DCORE1_TPC_3_1: + case GAUDI2_QUEUE_ID_DCORE1_TPC_3_2: + case GAUDI2_QUEUE_ID_DCORE1_TPC_3_3: + base = mmDCORE1_TPC3_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE1_TPC_3_0; + break; + case GAUDI2_QUEUE_ID_DCORE1_TPC_4_0: + case GAUDI2_QUEUE_ID_DCORE1_TPC_4_1: + case GAUDI2_QUEUE_ID_DCORE1_TPC_4_2: + case GAUDI2_QUEUE_ID_DCORE1_TPC_4_3: + base = mmDCORE1_TPC4_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE1_TPC_4_0; + break; + case GAUDI2_QUEUE_ID_DCORE1_TPC_5_0: + case GAUDI2_QUEUE_ID_DCORE1_TPC_5_1: + case GAUDI2_QUEUE_ID_DCORE1_TPC_5_2: + case GAUDI2_QUEUE_ID_DCORE1_TPC_5_3: + base = mmDCORE1_TPC5_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE1_TPC_5_0; + break; + case GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0: + case GAUDI2_QUEUE_ID_DCORE2_EDMA_0_1: + case GAUDI2_QUEUE_ID_DCORE2_EDMA_0_2: + case GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3: + base = mmDCORE2_EDMA0_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0; + break; + case GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0: + case GAUDI2_QUEUE_ID_DCORE2_EDMA_1_1: + case GAUDI2_QUEUE_ID_DCORE2_EDMA_1_2: + case GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3: + base = mmDCORE2_EDMA1_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0; + break; + case GAUDI2_QUEUE_ID_DCORE2_TPC_0_0: + case GAUDI2_QUEUE_ID_DCORE2_TPC_0_1: + case GAUDI2_QUEUE_ID_DCORE2_TPC_0_2: + case GAUDI2_QUEUE_ID_DCORE2_TPC_0_3: + base = mmDCORE2_TPC0_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE2_TPC_0_0; + break; + case GAUDI2_QUEUE_ID_DCORE2_TPC_1_0: + case GAUDI2_QUEUE_ID_DCORE2_TPC_1_1: + case GAUDI2_QUEUE_ID_DCORE2_TPC_1_2: + case GAUDI2_QUEUE_ID_DCORE2_TPC_1_3: + base = mmDCORE2_TPC1_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE2_TPC_1_0; + break; + case GAUDI2_QUEUE_ID_DCORE2_TPC_2_0: + case GAUDI2_QUEUE_ID_DCORE2_TPC_2_1: + case GAUDI2_QUEUE_ID_DCORE2_TPC_2_2: + case GAUDI2_QUEUE_ID_DCORE2_TPC_2_3: + base = mmDCORE2_TPC2_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE2_TPC_2_0; + break; + case GAUDI2_QUEUE_ID_DCORE2_TPC_3_0: + case GAUDI2_QUEUE_ID_DCORE2_TPC_3_1: + case GAUDI2_QUEUE_ID_DCORE2_TPC_3_2: + case GAUDI2_QUEUE_ID_DCORE2_TPC_3_3: + base = mmDCORE2_TPC3_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE2_TPC_3_0; + break; + case GAUDI2_QUEUE_ID_DCORE2_TPC_4_0: + case GAUDI2_QUEUE_ID_DCORE2_TPC_4_1: + case GAUDI2_QUEUE_ID_DCORE2_TPC_4_2: + case GAUDI2_QUEUE_ID_DCORE2_TPC_4_3: + base = mmDCORE2_TPC4_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE2_TPC_4_0; + break; + case GAUDI2_QUEUE_ID_DCORE2_TPC_5_0: + case GAUDI2_QUEUE_ID_DCORE2_TPC_5_1: + case GAUDI2_QUEUE_ID_DCORE2_TPC_5_2: + case GAUDI2_QUEUE_ID_DCORE2_TPC_5_3: + base = mmDCORE2_TPC5_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE2_TPC_5_0; + break; + case GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0: + case GAUDI2_QUEUE_ID_DCORE3_EDMA_0_1: + case GAUDI2_QUEUE_ID_DCORE3_EDMA_0_2: + case GAUDI2_QUEUE_ID_DCORE3_EDMA_0_3: + base = mmDCORE3_EDMA0_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0; + break; + case GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0: + case GAUDI2_QUEUE_ID_DCORE3_EDMA_1_1: + case GAUDI2_QUEUE_ID_DCORE3_EDMA_1_2: + case GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3: + base = mmDCORE3_EDMA1_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0; + break; + case GAUDI2_QUEUE_ID_DCORE3_TPC_0_0: + case GAUDI2_QUEUE_ID_DCORE3_TPC_0_1: + case GAUDI2_QUEUE_ID_DCORE3_TPC_0_2: + case GAUDI2_QUEUE_ID_DCORE3_TPC_0_3: + base = mmDCORE3_TPC0_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE3_TPC_0_0; + break; + case GAUDI2_QUEUE_ID_DCORE3_TPC_1_0: + case GAUDI2_QUEUE_ID_DCORE3_TPC_1_1: + case GAUDI2_QUEUE_ID_DCORE3_TPC_1_2: + case GAUDI2_QUEUE_ID_DCORE3_TPC_1_3: + base = mmDCORE3_TPC1_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE3_TPC_1_0; + break; + case GAUDI2_QUEUE_ID_DCORE3_TPC_2_0: + case GAUDI2_QUEUE_ID_DCORE3_TPC_2_1: + case GAUDI2_QUEUE_ID_DCORE3_TPC_2_2: + case GAUDI2_QUEUE_ID_DCORE3_TPC_2_3: + base = mmDCORE3_TPC2_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE3_TPC_2_0; + break; + case GAUDI2_QUEUE_ID_DCORE3_TPC_3_0: + case GAUDI2_QUEUE_ID_DCORE3_TPC_3_1: + case GAUDI2_QUEUE_ID_DCORE3_TPC_3_2: + case GAUDI2_QUEUE_ID_DCORE3_TPC_3_3: + base = mmDCORE3_TPC3_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE3_TPC_3_0; + break; + case GAUDI2_QUEUE_ID_DCORE3_TPC_4_0: + case GAUDI2_QUEUE_ID_DCORE3_TPC_4_1: + case GAUDI2_QUEUE_ID_DCORE3_TPC_4_2: + case GAUDI2_QUEUE_ID_DCORE3_TPC_4_3: + base = mmDCORE3_TPC4_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE3_TPC_4_0; + break; + case GAUDI2_QUEUE_ID_DCORE3_TPC_5_0: + case GAUDI2_QUEUE_ID_DCORE3_TPC_5_1: + case GAUDI2_QUEUE_ID_DCORE3_TPC_5_2: + case GAUDI2_QUEUE_ID_DCORE3_TPC_5_3: + base = mmDCORE3_TPC5_QM_BASE; + pqIdx = qid - GAUDI2_QUEUE_ID_DCORE3_TPC_5_0; + break; + case GAUDI2_QUEUE_ID_CPU_PQ: assert(0 && "QID GAUDI2_QUEUE_ID_CPU_PQ mustn't be used"); break; + default: assert(0 && "Unknown QID"); + } +} + +unsigned Gaudi2Device::GetQidSize() const { return GAUDI2_QUEUE_ID_SIZE; } + +unsigned Gaudi2Device::GetDMAInQid() const { return GAUDI2_QUEUE_ID_PDMA_0_0; } + +unsigned Gaudi2Device::GetDMAOutQid() const { return GAUDI2_QUEUE_ID_PDMA_1_0; } + +unsigned Gaudi2Device::GetQmanFenceOffset(unsigned fenceIdx, unsigned streamId) const +{ + unsigned offset; + switch (fenceIdx) + { + case 0: + offset = (unsigned)offsetof(gaudi2::block_qman, cp_fence0_rdata[streamId]); + break; + case 1: + offset = (unsigned)offsetof(gaudi2::block_qman, cp_fence1_rdata[streamId]); + break; + case 2: + offset = (unsigned)offsetof(gaudi2::block_qman, cp_fence2_rdata[streamId]); + break; + case 3: + offset = (unsigned)offsetof(gaudi2::block_qman, cp_fence3_rdata[streamId]); + break; + default: + assert(0 && "invalid fence idx"); + offset = (unsigned)offsetof(gaudi2::block_qman, cp_fence0_rdata[streamId]); + break; + } + return offset; +} + +uint64_t Gaudi2Device::GetSyncMngrVarAddr(std::string varName, unsigned idx) const +{ + unsigned offset = 0; + uint64_t addr = 0; + if (varName != "sob_obj") + { + idx += GetMonitorObjectBaseIndex(); + assert(idx < c_monitorObjNr && "invalid monitor index"); + } + if (varName == "mon_pay_addrl") + { + offset = (unsigned)offsetof(gaudi2::block_sob_objs, mon_pay_addrl[idx]); + addr = c_syncObjectsBaseAddr + offset; + assert(addr > 0x1000007FFC108000 && addr < 0x1000007FFC10A000); + } + else if (varName == "mon_pay_addrh") + { + offset = (unsigned)offsetof(gaudi2::block_sob_objs, mon_pay_addrh[idx]); + addr = c_syncObjectsBaseAddr + offset; + assert(addr > 0x1000007FFC10A000 && addr < 0x1000007FFC10C000); + } + else if (varName == "mon_pay_data") + { + offset = (unsigned)offsetof(gaudi2::block_sob_objs, mon_pay_data[idx]); + addr = c_syncObjectsBaseAddr + offset; + assert(addr > 0x1000007FFC10C000 && addr < 0x1000007FFC10E000); + } + else if (varName == "mon_cfg") + { + offset = (unsigned)offsetof(gaudi2::block_sob_objs, mon_config[idx]); + addr = c_syncObjectsBaseAddr + offset; + } + + else if (varName == "mon_arm") + { + offset = (unsigned)offsetof(gaudi2::block_sob_objs, mon_arm[idx]); + addr = c_syncObjectsBaseAddr + offset; + assert(addr > 0x1000007FFC10E000 && addr < 0x1000007FFC110000); + } + else if (varName == "sob_obj") + { + assert(idx < c_syncObjNr && "invalid sync object index"); + offset = (unsigned)offsetof(gaudi2::block_sob_objs, sob_obj[idx]); + addr = c_syncObjectsBaseAddr + offset; + assert(addr > 0x1000007FFC100000 && addr < 0x1000007FFC108000); + } + else + { + assert(0 && "invalid var name"); + } + return addr; +} + +unsigned Gaudi2Device::GetDmaDownVarOffset(std::string varName) const +{ + unsigned offset = 0; + if (varName == "wr_comp_addr_lo") + { + offset = (unsigned)offsetof(gaudi2::block_dma_core, ctx.wr_comp_addr_lo); + } + else if (varName == "wr_comp_addr_hi") + { + offset = (unsigned)offsetof(block_dma_core, ctx.wr_comp_addr_hi); + } + else if (varName == "wr_comp_wdata") + { + offset = (unsigned)offsetof(block_dma_core, ctx.wr_comp_wdata); + } + else + { + assert(0 && "invalid var name"); + } + offset += mmPDMA0_CORE_BASE & 0xffff; + return offset; +} + +void Gaudi2Device::GetTpcTabOffset(int TabIdx, uint32_t* baseAddrLow, uint32_t* baseAddrHigh) const +{ + switch (TabIdx) + { + case 0: // 256b special functions + *baseAddrLow = + c_tpcCfgBlockOffset + (unsigned)offsetof(block_tpc, lut_func256_base_addr_lo); + *baseAddrHigh = + c_tpcCfgBlockOffset + (unsigned)offsetof(block_tpc, lut_func256_base_addr_hi); + break; + case 1: // 128b special functions + *baseAddrLow = + c_tpcCfgBlockOffset + (unsigned)offsetof(block_tpc, lut_func128_base_addr_lo); + *baseAddrHigh = + c_tpcCfgBlockOffset + (unsigned)offsetof(block_tpc, lut_func128_base_addr_hi); + break; + case 2: // 64b special functions + *baseAddrLow = c_tpcCfgBlockOffset + (unsigned)offsetof(block_tpc, lut_func64_base_addr_lo); + *baseAddrHigh = + c_tpcCfgBlockOffset + (unsigned)offsetof(block_tpc, lut_func64_base_addr_hi); + break; + case 3: // 32b special functions + *baseAddrLow = c_tpcCfgBlockOffset + (unsigned)offsetof(block_tpc, lut_func32_base_addr_lo); + *baseAddrHigh = + c_tpcCfgBlockOffset + (unsigned)offsetof(block_tpc, lut_func32_base_addr_hi); + break; + default: + assert(0); + } + return; +} + +unsigned Gaudi2Device::GetTpcCfgVarOffset(std::string varName) const +{ + unsigned offset = 0; + if (varName == "qm_tensor_0") + { + offset = (unsigned)offsetof(block_tpc, qm_tensor_0); + } + else if (varName == "sm_base_address_high") + { + offset = (unsigned)offsetof(block_tpc, sm_base_address_high); + } + else if (varName == "tpc_cmd") + { + offset = (unsigned)offsetof(block_tpc, tpc_cmd); + } + else if (varName == "tpc_execute") + { + offset = (unsigned)offsetof(block_tpc, tpc_execute); + } + else if (varName == "icache_base_adderess_low") + { + offset = (unsigned)offsetof(block_tpc, icache_base_adderess_low); + } + else if (varName == "icache_base_adderess_high") + { + offset = (unsigned)offsetof(block_tpc, icache_base_adderess_high); + } + else + { + assert(0 && "invalid var name"); + } + return c_tpcCfgBlockOffset + offset; +} + +unsigned Gaudi2Device::GetMonArmRawVal(uint8_t mask, uint8_t sid, unsigned sod, unsigned sop) const +{ + sob_objs::reg_mon_arm monArm; + memset(&monArm, 0, sizeof(sob_objs::reg_mon_arm)); + monArm.mask = mask; + monArm.sid = sid; + monArm.sod = sod; + monArm.sop = sop; + + return monArm._raw; +} + +unsigned Gaudi2Device::GetMonCfgRawVal(unsigned msbSid) const +{ + sob_objs::reg_mon_config monCfg; + memset(&monCfg, 0, sizeof(sob_objs::reg_mon_config)); + monCfg.msb_sid = msbSid; + + return monCfg._raw; +} +std::shared_ptr<::CPCommand::CpDma> Gaudi2Device::GenCpDma(uint64_t src, uint32_t size) const +{ + std::shared_ptr<::CPCommand::CpDma> pCommand; + pCommand = std::make_shared(src, size); + return pCommand; +} + +std::shared_ptr<::CPCommand::Fence> Gaudi2Device::GenFence(unsigned id, uint8_t targetVal, + unsigned decVal) const +{ + std::shared_ptr<::CPCommand::Fence> pCommand; + pCommand = std::make_shared(id, targetVal, decVal); + return pCommand; +} + +std::shared_ptr<::CPCommand::LinDma> Gaudi2Device::GenLinDma(uint64_t dst, uint64_t src, + uint32_t tsize, unsigned dmaDir, + uint16_t ctxId, bool wrComp) const +{ + // dmaDir not required for Gaudi, only for Goya + std::shared_ptr<::CPCommand::LinDma> pCommand; + pCommand = std::make_shared(dst, src, tsize, 0, wrComp); + pCommand->m_ctxId = ctxId; + return pCommand; +} + +std::shared_ptr<::CPCommand::MsgLong> Gaudi2Device::GenMsgLong(uint64_t addr, uint32_t value, bool mb, + bool rb, bool eb) const +{ + std::shared_ptr<::CPCommand::MsgLong> pCommand; + pCommand = std::make_shared(addr, value, mb, eb); + return pCommand; +} + +std::shared_ptr<::CPCommand::WReg32> Gaudi2Device::GenWReg32(uint16_t offset, uint32_t value, bool mb, + bool rb, bool eb) const +{ + std::shared_ptr<::CPCommand::WReg32> pCommand; + pCommand = std::make_shared(offset, value, mb, eb); + return pCommand; +} + +std::shared_ptr<::CPCommand::WRegBulk> Gaudi2Device::GenWRegBulk(uint16_t offset, uint32_t* values, + unsigned numValues) const +{ + std::shared_ptr<::CPCommand::WRegBulk> pCommand; + pCommand = std::make_shared(offset, values, numValues); + return pCommand; +} + +size_t Gaudi2Device::GetTpcDescSize() const { return sizeof(Gaudi2TpcDesc); } + +void Gaudi2Device::WriteSrf(HWAbstractionLayer::TpcDescHandle tpcDesc, const uint32_t* params, + unsigned paramsNr) const +{ + memcpy(&(((Gaudi2TpcDesc*)(tpcDesc))->m_desc.srf[0]), params, paramsNr * sizeof(uint32_t)); +} + +void Gaudi2Device::WriteKernelCfg(HWAbstractionLayer::TpcDescHandle tpcDesc, uint32_t smallVlm) const +{ + ((Gaudi2TpcDesc*)(tpcDesc))->m_desc.kernel_config.small_vlm = smallVlm; + ((Gaudi2TpcDesc*)(tpcDesc))->m_desc.kernel_config.aso_evict_l0 = 1; + // TODO: load actual count. + ((Gaudi2TpcDesc*)(tpcDesc))->m_desc.kernel_config.num_valid_srfs = 32; + + // Don't change rate limiter, setting default values. + ((Gaudi2TpcDesc*)(tpcDesc))->m_desc.kernel_config.rd_rate_limit_rst_token = 0x8; + ((Gaudi2TpcDesc*)(tpcDesc))->m_desc.kernel_config.wr_rate_limit_rst_token = 0x6; + ((Gaudi2TpcDesc*)(tpcDesc))->m_desc.kernel_config.irf_32bit_compatibility = 0x1; +} + +void Gaudi2Device::WriteKernelAddr(HWAbstractionLayer::TpcDescHandle tpcDesc, + uint64_t kernelAddr) const +{ + ((Gaudi2TpcDesc*)(tpcDesc))->m_desc.kernel_base_address_low._raw = + (uint32_t)(kernelAddr & 0xffffffff); + ((Gaudi2TpcDesc*)(tpcDesc))->m_desc.kernel_base_address_high._raw = (uint32_t)(kernelAddr >> 32); +} + +void Gaudi2Device::WriteTensorDesc(HWAbstractionLayer::TpcDescHandle tpcDesc, + TensorDescriptor& tensorDesc, unsigned tensorId) const +{ + memcpy(&(((Gaudi2TpcDesc*)(tpcDesc))->m_tensors[tensorId]), &tensorDesc, + sizeof(TensorDescriptor)); +} + +void Gaudi2Device::WriteTpcJobDesc(HWAbstractionLayer::TpcDescHandle tpcDesc, + const IndexSpace& partition, uint32_t soAddr, + uint32_t soMsg, bool updatePrintfAddr, + int printfTensorIdx) const +{ + // load IRF0/1 + ((Gaudi2TpcDesc*)(tpcDesc))->m_desc.tid_size_dim_0.v = partition.size[0]; + ((Gaudi2TpcDesc*)(tpcDesc))->m_desc.tid_size_dim_1.v = partition.size[1]; + ((Gaudi2TpcDesc*)(tpcDesc))->m_desc.tid_size_dim_2.v = partition.size[2]; + ((Gaudi2TpcDesc*)(tpcDesc))->m_desc.tid_size_dim_3.v = partition.size[3]; + ((Gaudi2TpcDesc*)(tpcDesc))->m_desc.tid_size_dim_4.v = partition.size[4]; + + ((Gaudi2TpcDesc*)(tpcDesc))->m_desc.tid_base_dim_0.v = partition.offset[0]; + ((Gaudi2TpcDesc*)(tpcDesc))->m_desc.tid_base_dim_1.v = partition.offset[1]; + ((Gaudi2TpcDesc*)(tpcDesc))->m_desc.tid_base_dim_2.v = partition.offset[2]; + ((Gaudi2TpcDesc*)(tpcDesc))->m_desc.tid_base_dim_3.v = partition.offset[3]; + ((Gaudi2TpcDesc*)(tpcDesc))->m_desc.tid_base_dim_4.v = partition.offset[4]; + + ((Gaudi2TpcDesc*)(tpcDesc))->m_so.addr.v = soAddr; + ((Gaudi2TpcDesc*)(tpcDesc))->m_so.message._raw = soMsg; + +} + +uint32_t Gaudi2Device::GenTpcCmd() const +{ + gaudi2::tpc::reg_tpc_cmd command; + memset(&command, 0, sizeof(command)); + command.icache_invalidate = 1; + command.dcache_invalidate = 1; + command.lcache_invalidate = 1; + command.tcache_invalidate = 1; + command.icache_prefetch_64kb = 0; + return command._raw; +} + +uint32_t Gaudi2Device::GetTpcTensorConfig() const { + struct gaudi2::tpc_tensor::reg_tensor_config config; + config._raw = 0; + config.data_type = TensorDataType::TensorDT_FP32; + config.valid_dim_mask = 0xF; + config.last_dim = 3; + return config._raw; +} +} // namespace gaudi2 diff --git a/synapse_backend/low_level_driver/gaudi2/gaudi2_device.h b/synapse_backend/low_level_driver/gaudi2/gaudi2_device.h new file mode 100644 index 0000000..bd95167 --- /dev/null +++ b/synapse_backend/low_level_driver/gaudi2/gaudi2_device.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: MIT + * + * Copyright 2016-2021 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#pragma once + +#include "hw_abstraction_layer.h" +#include "synapse_common_types.h" +namespace gaudi2 +{ +class Gaudi2Device : public HWAbstractionLayer +{ +public: + Gaudi2Device() {} + virtual ~Gaudi2Device() {} + + virtual synDeviceType getDeviceType() const override {return synDeviceGaudi2;} + virtual unsigned GetTensorSizeFromDesc(TensorDescriptor& desc) const override; + virtual unsigned GetTensorSizeFromDesc(TensorDescriptor& desc0, TensorDescriptor& desc1) const override; + + virtual unsigned GetSpecialFuncTabNr() const override; + virtual void GetSpecialFuncTabSizes(uint32_t* sizes, unsigned sizesLen) const override; + virtual void CopySpecialFuncTab( + std::vector>& specialFunctionCoefficients) const override; + + virtual int GetDmaUpSyncObjectIndex() const override; + virtual int GetDmaDownSyncObjectIndex() const override; + virtual int GetMonitorObjectBaseIndex() const override; + virtual uint64_t GetSyncManagerBaseAddr() const override; + virtual uint64_t GetDmaUpSyncObjectAddr() const override; + virtual uint64_t GetDmaDownSyncObjectAddr() const override; + + virtual unsigned GetTPCNr() const override; + virtual unsigned GetTPCQueueId(unsigned tpcId) const override; + virtual unsigned GetSyncObjectGroupSize() const override; + + virtual void Qid2Qman(unsigned qid, uint64_t& base, unsigned& pqIdx) const override; + virtual unsigned GetQidSize() const override; + virtual unsigned GetDMAInQid() const override; + virtual unsigned GetDMAOutQid() const override; + virtual unsigned GetQmanFenceOffset(unsigned fenceIdx, unsigned streamId) const override; + virtual uint64_t GetSyncMngrVarAddr(std::string varName, unsigned idx) const override; + virtual unsigned GetDmaDownVarOffset(std::string varName) const override; + virtual unsigned GetTpcCfgVarOffset(std::string varName) const override; + virtual unsigned GetMonArmRawVal(uint8_t mask, uint8_t sid, unsigned sod, unsigned sop) const override; + virtual unsigned GetMonCfgRawVal(unsigned msbSid) const override; + virtual void GetTpcTabOffset(int TabIdx, uint32_t* baseAddrLow, uint32_t* baseAddrHigh) const override; + + virtual std::shared_ptr GenWReg32(uint16_t offset, uint32_t value, bool mb = false, bool rb = false, bool eb = false) const override; + virtual std::shared_ptr GenWRegBulk(uint16_t offset, uint32_t* values, unsigned numValues) const override; + virtual std::shared_ptr GenMsgLong(uint64_t addr, uint32_t value, bool mb = false, bool rb = false, bool eb = false) const override; + virtual std::shared_ptr GenFence(unsigned id, uint8_t targetVal, unsigned decVal) const override; + virtual std::shared_ptr GenLinDma(uint64_t dst, uint64_t src, uint32_t tsize, unsigned dmaDir, uint16_t ctxId = 0, bool wrComp = false) const override; + virtual std::shared_ptr GenCpDma(uint64_t src, uint32_t size) const override; + + virtual size_t GetTpcDescSize() const override; + virtual void WriteSrf(TpcDescHandle tpcDesc, const uint32_t* params, unsigned paramsNr) const override; + virtual void WriteKernelCfg(TpcDescHandle tpcDesc, uint32_t smallVlm) const override; + virtual void WriteKernelAddr(TpcDescHandle tpcDesc, uint64_t kernelAddr) const override; + virtual void WriteTensorDesc(TpcDescHandle tpcDesc, TensorDescriptor& tensorDesc, unsigned tensorId) const override; + virtual void WriteTpcJobDesc(TpcDescHandle tpcDesc, const IndexSpace& partition, uint32_t soAddr, uint32_t soMsg, bool updatePrintfAddr, int printfTensorIdx) const override; + virtual uint32_t GenTpcCmd() const override; + virtual uint32_t GetTpcTensorConfig() const override; + + virtual bool isMmuEnabled() const override {return true;} + virtual bool shouldConfigureMonCfg() const override {return true;} + +private: + Gaudi2Device(const Gaudi2Device& other) = delete; + Gaudi2Device& operator=(const Gaudi2Device& other) = delete; + + static const unsigned c_tpcNr; + static const unsigned c_syncObjNr; + static const unsigned c_monitorObjNr; + static const unsigned c_syncObjectGroupSize; + static const int c_dmaDownSyncObjectIndex; + static const int c_dmaUpSyncObjectIndex; + static const int c_monitorObjectBaseIndex; + static const uint64_t c_syncManagerBase; + static const uint64_t c_syncObjectsBaseAddr; + static const unsigned c_dmaCoreBlockOffset; + static const unsigned c_tpcCfgBlockOffset; + + static constexpr uint64_t GetSyncObjectAddress(int synObjIndex); + int getAlignedFirstAvailableSOB() const; + +}; + + +} //namespace gaudi2 diff --git a/synapse_backend/low_level_driver/gaudi2/gaudi2_packet_gen.cpp b/synapse_backend/low_level_driver/gaudi2/gaudi2_packet_gen.cpp new file mode 100644 index 0000000..fdbe686 --- /dev/null +++ b/synapse_backend/low_level_driver/gaudi2/gaudi2_packet_gen.cpp @@ -0,0 +1,243 @@ +/* SPDX-License-Identifier: MIT + * + * Copyright 2016-2021 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#include "gaudi2_packet_gen.h" +#include "../../external_includes/gaudi2/gaudi2_packets.h" +namespace gaudi2 +{ +unsigned CPCommand::NopGen6::GetSize() const { return sizeof(packet_nop); } +unsigned CPCommand::StopGen6::GetSize() const { return sizeof(packet_stop); } +unsigned CPCommand::WReg32Gen6::GetSize() const { return sizeof(packet_wreg32); } +unsigned CPCommand::WRegBulkGen6::GetSize() const +{ + return sizeof(packet_wreg_bulk) + (m_numValues * sizeof(uint64_t)); +} +unsigned CPCommand::MsgLongGen6::GetSize() const { return sizeof(packet_msg_long); } +unsigned CPCommand::MsgShortGen6::GetSize() const { return sizeof(packet_msg_short); } +unsigned CPCommand::MsgProtGen6::GetSize() const { return sizeof(packet_msg_prot); } +unsigned CPCommand::FenceGen6::GetSize() const { return sizeof(packet_fence); } +unsigned CPCommand::LinDmaGen6::GetSize() const { return sizeof(packet_lin_dma); } +unsigned CPCommand::RepeatGen6::GetSize() const { return sizeof(packet_repeat); } +unsigned CPCommand::WaitGen6::GetSize() const { return sizeof(packet_wait); } +unsigned CPCommand::LoadAndExecGen6::GetSize() const { return sizeof(packet_load_and_exe); } +unsigned CPCommand::CpDmaGen6::GetSize() const { return sizeof(packet_cp_dma); } +unsigned CPCommand::ArbPointGen6::GetSize() const { return sizeof(packet_arb_point); } + +::CPCommand::Command* CPCommand::NopGen6::Clone() const { return new NopGen6(*this); } +::CPCommand::Command* CPCommand::StopGen6::Clone() const { return new StopGen6(*this); } +::CPCommand::Command* CPCommand::WReg32Gen6::Clone() const { return new WReg32Gen6(*this); } +::CPCommand::Command* CPCommand::WRegBulkGen6::Clone() const { return new WRegBulkGen6(*this); } +::CPCommand::Command* CPCommand::MsgLongGen6::Clone() const { return new MsgLongGen6(*this); } +::CPCommand::Command* CPCommand::MsgShortGen6::Clone() const { return new MsgShortGen6(*this); } +::CPCommand::Command* CPCommand::MsgProtGen6::Clone() const { return new MsgProtGen6(*this); } +::CPCommand::Command* CPCommand::FenceGen6::Clone() const { return new FenceGen6(*this); } +::CPCommand::Command* CPCommand::LinDmaGen6::Clone() const { return new LinDmaGen6(*this); } +::CPCommand::Command* CPCommand::RepeatGen6::Clone() const { return new RepeatGen6(*this); } +::CPCommand::Command* CPCommand::WaitGen6::Clone() const { return new WaitGen6(*this); } +::CPCommand::Command* CPCommand::LoadAndExecGen6::Clone() const { return new LoadAndExecGen6(*this); } +::CPCommand::Command* CPCommand::CpDmaGen6::Clone() const { return new CpDmaGen6(*this); } +::CPCommand::Command* CPCommand::ArbPointGen6::Clone() const { return new ArbPointGen6(*this); } + +void CPCommand::NopGen6::Serialize(void** buff) const +{ + memset(*buff, 0, sizeof(packet_nop)); + ((packet_nop*)(*buff))->opcode = PACKET_NOP; + ((packet_nop*)(*buff))->eng_barrier = m_eb; + ((packet_nop*)(*buff))->swtc = m_swtc; + ((packet_nop*)(*buff))->msg_barrier = m_mb; + (*(uint8_t**)buff) += GetSize(); +} + +void CPCommand::StopGen6::Serialize(void** buff) const +{ + memset(*buff, 0, sizeof(packet_stop)); + ((packet_stop*)(*buff))->opcode = PACKET_STOP; + ((packet_stop*)(*buff))->eng_barrier = m_eb; + ((packet_stop*)(*buff))->swtc = m_swtc; + ((packet_stop*)(*buff))->msg_barrier = m_mb; + (*(uint8_t**)buff) += GetSize(); +} + +void CPCommand::WReg32Gen6::Serialize(void** buff) const +{ + memset(*buff, 0, sizeof(packet_wreg32)); + ((packet_wreg32*)(*buff))->opcode = PACKET_WREG_32; + ((packet_wreg32*)(*buff))->eng_barrier = m_eb; + ((packet_wreg32*)(*buff))->swtc = m_swtc; + ((packet_wreg32*)(*buff))->msg_barrier = m_mb; + ((packet_wreg32*)(*buff))->pred = m_pred; + ((packet_wreg32*)(*buff))->reg_offset = m_offset; + ((packet_wreg32*)(*buff))->value = m_value; + ((packet_wreg32*)(*buff))->reg = 0x0; + (*(uint8_t**)buff) += GetSize(); +} + +void CPCommand::WRegBulkGen6::Serialize(void** buff) const +{ + memset(*buff, 0, sizeof(packet_wreg_bulk)); + ((packet_wreg_bulk*)(*buff))->opcode = PACKET_WREG_BULK; + ((packet_wreg_bulk*)(*buff))->eng_barrier = m_eb; + ((packet_wreg_bulk*)(*buff))->swtc = m_swtc; + ((packet_wreg_bulk*)(*buff))->msg_barrier = m_mb; + ((packet_wreg_bulk*)(*buff))->size64 = m_numValues; + ((packet_wreg_bulk*)(*buff))->pred = m_pred; + ((packet_wreg_bulk*)(*buff))->reg_offset = m_offset; + memcpy(((packet_wreg_bulk*)(*buff))->values, m_values, m_numValues * sizeof(uint64_t)); + (*(uint8_t**)buff) += GetSize(); +} + +void CPCommand::MsgLongGen6::Serialize(void** buff) const +{ + memset(*buff, 0, sizeof(packet_msg_long)); + ((packet_msg_long*)(*buff))->opcode = PACKET_MSG_LONG; + ((packet_msg_long*)(*buff))->eng_barrier = m_eb; + ((packet_msg_long*)(*buff))->swtc = m_swtc; + ((packet_msg_long*)(*buff))->msg_barrier = m_mb; + ((packet_msg_long*)(*buff))->pred = m_pred; + ((packet_msg_long*)(*buff))->weakly_ordered = m_weaklyOrdered; + ((packet_msg_long*)(*buff))->no_snoop = m_noSnoop; + ((packet_msg_long*)(*buff))->op = m_op; + ((packet_msg_long*)(*buff))->value = m_value; + ((packet_msg_long*)(*buff))->addr = m_addr; + (*(uint8_t**)buff) += GetSize(); +} + +void CPCommand::MsgShortGen6::Serialize(void** buff) const +{ + memset(*buff, 0, sizeof(packet_msg_short)); + ((packet_msg_short*)(*buff))->opcode = PACKET_MSG_SHORT; + ((packet_msg_short*)(*buff))->eng_barrier = m_eb; + ((packet_msg_short*)(*buff))->swtc = m_swtc; + ((packet_msg_short*)(*buff))->msg_barrier = m_mb; + ((packet_msg_short*)(*buff))->msg_addr_offset = m_offset; + ((packet_msg_short*)(*buff))->weakly_ordered = m_weaklyOrdered; + ((packet_msg_short*)(*buff))->no_snoop = m_noSnoop; + ((packet_msg_short*)(*buff))->op = m_op; + ((packet_msg_short*)(*buff))->value = m_value; + (*(uint8_t**)buff) += GetSize(); +} + +void CPCommand::MsgProtGen6::Serialize(void** buff) const +{ + memset(*buff, 0, sizeof(packet_msg_prot)); + ((packet_msg_prot*)(*buff))->opcode = PACKET_MSG_PROT; + ((packet_msg_prot*)(*buff))->eng_barrier = m_eb; + ((packet_msg_prot*)(*buff))->swtc = m_swtc; + ((packet_msg_prot*)(*buff))->msg_barrier = m_mb; + ((packet_msg_prot*)(*buff))->pred = m_pred; + ((packet_msg_prot*)(*buff))->weakly_ordered = m_weaklyOrdered; + ((packet_msg_prot*)(*buff))->no_snoop = m_noSnoop; + ((packet_msg_prot*)(*buff))->op = m_op; + ((packet_msg_prot*)(*buff))->value = m_value; + ((packet_msg_prot*)(*buff))->addr = m_addr; + (*(uint8_t**)buff) += GetSize(); +} + +void CPCommand::FenceGen6::Serialize(void** buff) const +{ + memset(*buff, 0, sizeof(packet_fence)); + ((packet_fence*)(*buff))->opcode = PACKET_FENCE; + ((packet_fence*)(*buff))->eng_barrier = m_eb; + ((packet_fence*)(*buff))->swtc = m_swtc; + ((packet_fence*)(*buff))->msg_barrier = m_mb; + ((packet_fence*)(*buff))->pred = m_pred; + ((packet_fence*)(*buff))->dec_val = m_decVal; + ((packet_fence*)(*buff))->target_val = m_targetVal; + ((packet_fence*)(*buff))->id = m_id; + (*(uint8_t**)buff) += GetSize(); +} + +void CPCommand::LinDmaGen6::Serialize(void** buff) const +{ + memset(*buff, 0, sizeof(packet_lin_dma)); + ((packet_lin_dma*)(*buff))->wrcomp = m_wrComp; + ((packet_lin_dma*)(*buff))->endian = 0; + ((packet_lin_dma*)(*buff))->memset = m_memset; + ((packet_lin_dma*)(*buff))->bf16 = 0; + ((packet_lin_dma*)(*buff))->fp16 = 0; + ((packet_lin_dma*)(*buff))->context_id_inc = 0; + ((packet_lin_dma*)(*buff))->add_offset_0 = 0; + ((packet_lin_dma*)(*buff))->opcode = PACKET_LIN_DMA; + ((packet_lin_dma*)(*buff))->eng_barrier = m_eb; + ((packet_lin_dma*)(*buff))->swtc = m_swtc; + ((packet_lin_dma*)(*buff))->msg_barrier = m_mb; + + ((packet_lin_dma*)(*buff))->tsize = m_tsize; + ((packet_lin_dma*)(*buff))->src_addr = m_src; + ((packet_lin_dma*)(*buff))->dst_addr = m_dst; + + (*(uint8_t**)buff) += GetSize(); +} + +void CPCommand::RepeatGen6::Serialize(void** buff) const +{ + memset(*buff, 0, sizeof(packet_repeat)); + ((packet_repeat*)(*buff))->opcode = PACKET_REPEAT; + ((packet_repeat*)(*buff))->eng_barrier = m_eb; + ((packet_repeat*)(*buff))->msg_barrier = m_mb; + ((packet_repeat*)(*buff))->sore = m_sore; + ((packet_repeat*)(*buff))->outer = m_o; + ((packet_repeat*)(*buff))->pred = m_pred; + ((packet_repeat*)(*buff))->jmp_ptr = m_jumpPtr; + (*(uint8_t**)buff) += GetSize(); +} + +void CPCommand::WaitGen6::Serialize(void** buff) const +{ + memset(*buff, 0, sizeof(packet_wait)); + ((packet_wait*)(*buff))->opcode = PACKET_WAIT; + ((packet_wait*)(*buff))->eng_barrier = m_eb; + ((packet_wait*)(*buff))->msg_barrier = m_mb; + ((packet_wait*)(*buff))->num_cycles_to_wait = m_cycles; + ((packet_wait*)(*buff))->inc_val = m_incVal; + ((packet_wait*)(*buff))->id = m_id; + (*(uint8_t**)buff) += GetSize(); +} + +void CPCommand::LoadAndExecGen6::Serialize(void** buff) const +{ + memset(*buff, 0, sizeof(packet_load_and_exe)); + ((packet_load_and_exe*)(*buff))->opcode = PACKET_LOAD_AND_EXE; + ((packet_load_and_exe*)(*buff))->eng_barrier = m_eb; + ((packet_load_and_exe*)(*buff))->swtc = m_swtc; + ((packet_load_and_exe*)(*buff))->msg_barrier = m_mb; + ((packet_load_and_exe*)(*buff))->dst = m_dest; + ((packet_load_and_exe*)(*buff))->load = m_load; + ((packet_load_and_exe*)(*buff))->exe = m_exec; + ((packet_load_and_exe*)(*buff))->etype = m_eType; + ((packet_load_and_exe*)(*buff))->pred = m_pred; + ((packet_load_and_exe*)(*buff))->pmap = 0; + (*(uint8_t**)buff) += GetSize(); +} + +void CPCommand::CpDmaGen6::Serialize(void** buff) const +{ + memset(*buff, 0, sizeof(packet_cp_dma)); + ((packet_cp_dma*)(*buff))->opcode = PACKET_CP_DMA; + ((packet_cp_dma*)(*buff))->eng_barrier = 0x0; + ((packet_cp_dma*)(*buff))->msg_barrier = m_mb; + ((packet_cp_dma*)(*buff))->tsize = m_tSize; + ((packet_cp_dma*)(*buff))->src_addr = m_src; + ((packet_cp_dma*)(*buff))->pred = m_pred; + ((packet_cp_dma*)(*buff))->upper_cp = 0x0; + (*(uint8_t**)buff) += GetSize(); +} + +void CPCommand::ArbPointGen6::Serialize(void** buff) const +{ + memset(*buff, 0, sizeof(packet_arb_point)); + ((packet_arb_point*)(*buff))->opcode = PACKET_ARB_POINT; + ((packet_arb_point*)(*buff))->eng_barrier = 0; + ((packet_arb_point*)(*buff))->msg_barrier = 0; + ((packet_arb_point*)(*buff))->priority = m_prio; + ((packet_arb_point*)(*buff))->rls = m_release; + ((packet_arb_point*)(*buff))->cfg = 0x0; + ((packet_arb_point*)(*buff))->pred = m_pred; + (*(uint8_t**)buff) += GetSize(); +} + +} \ No newline at end of file diff --git a/synapse_backend/low_level_driver/gaudi2/gaudi2_packet_gen.h b/synapse_backend/low_level_driver/gaudi2/gaudi2_packet_gen.h new file mode 100644 index 0000000..3ad7715 --- /dev/null +++ b/synapse_backend/low_level_driver/gaudi2/gaudi2_packet_gen.h @@ -0,0 +1,221 @@ +/* SPDX-License-Identifier: MIT + * + * Copyright 2016-2021 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +#pragma once + +#include "../program.h" + +namespace gaudi2 +{ +namespace CPCommand +{ + class NopGen6 : public ::CPCommand::Nop + { + public: + NopGen6(bool mb = true, bool eb = true) : Nop(mb, eb) {}; + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_swtc = false; + }; + + class StopGen6 : public ::CPCommand::Stop + { + public: + StopGen6() : Stop() {}; + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_swtc = false; + }; + + class WReg32Gen6 : public ::CPCommand::WReg32 + { + public: + WReg32Gen6(uint16_t offset, uint32_t value, bool mb = true, bool eb = true) : + WReg32(offset, value, mb, eb) {} + WReg32Gen6() : WReg32() {}; + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_swtc = false; + }; + + class WRegBulkGen6 : public ::CPCommand::WRegBulk + { + public: + WRegBulkGen6() : WRegBulk() {}; + + WRegBulkGen6(uint16_t offset, uint64_t* values, unsigned numValues) : + WRegBulk(offset, values, numValues) {} + + // wregbulk writes in 64-bit words , need to divide num of iteartion by 2. + WRegBulkGen6(uint16_t offset, uint32_t* values, unsigned numValues) : + WRegBulk(offset, (uint64_t*)values, numValues/2) {} + + + WRegBulkGen6(uint16_t offset, std::list::const_iterator &begin, std::list::const_iterator &end) : + WRegBulk(offset, begin, end) {} + + WRegBulkGen6(uint16_t offset, std::list &list) : + WRegBulk(offset, list) {} + + WRegBulkGen6(uint16_t offset, std::list &list) : + WRegBulk(offset, list) {} + + WRegBulkGen6(const WRegBulkGen6 &other) : + WRegBulk(other), m_swtc(other.m_swtc) {} + + virtual ~WRegBulkGen6() {} + + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_swtc = false; + }; + + class MsgLongGen6 : public ::CPCommand::MsgLong + { + public: + MsgLongGen6(uint64_t addr, uint32_t value, bool mb = true, bool eb = true) : + MsgLong(addr, value, mb, eb) {} + + MsgLongGen6() : MsgLong() {} + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_swtc = false; + }; + + class MsgShortGen6 : public ::CPCommand::MsgShort + { + public: + MsgShortGen6(unsigned base, uint16_t offset, uint32_t value) : + MsgShort(base, offset, value) {} + MsgShortGen6() : MsgShort(0, 0, 0) {} + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_swtc = false; + }; + + class MsgProtGen6 : public ::CPCommand::MsgProt + { + public: + MsgProtGen6(uint64_t addr, uint32_t value, bool mb = true, bool eb = true) : + MsgProt(addr, value, mb, eb) {} + + MsgProtGen6() : MsgProt(0, 0) {} + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_swtc = false; + }; + + class FenceGen6 : public ::CPCommand::Fence + { + public: + FenceGen6(unsigned id, uint8_t targetVal, unsigned decVal, bool mb = true, bool eb = true) + : Fence(id, targetVal, decVal, mb, eb) {} + + FenceGen6() : Fence() {} + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_swtc = false; + }; + + class LinDmaGen6 : public ::CPCommand::LinDma + { + public: + LinDmaGen6(uint64_t dst, uint64_t src, uint32_t tsize, unsigned dmaDir, bool wrComp = 0) : + LinDma(dst, src, tsize, dmaDir, wrComp) {} + + LinDmaGen6(const LinDmaGen6& other) : LinDma(other), m_swtc(other.m_swtc) {} + + LinDmaGen6() : LinDma() {}; + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_swtc = false; + }; + + class RepeatGen6 : public ::CPCommand::Repeat + { + public: + RepeatGen6(uint16_t jumpPtr = 0) : Repeat(jumpPtr) {} + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_swtc = false; + }; + + class WaitGen6 : public ::CPCommand::Wait + { + public: + WaitGen6(uint32_t cycles, unsigned incVal, unsigned id) : + Wait(cycles, incVal, id) {} + + WaitGen6() : Wait(0, 0, 0) {}; + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_swtc = false; + }; + + class LoadAndExecGen6 : public ::CPCommand::LoadAndExec + { + public: + LoadAndExecGen6() : LoadAndExec() {} + + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_swtc = false; + }; + + class CpDmaGen6 : public ::CPCommand::CpDma + { + public: + CpDmaGen6(uint64_t src, uint32_t size) : CpDma(src, size) {} + + CpDmaGen6() : CpDma() {} + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_swtc = false; + }; + + class ArbPointGen6 : public ::CPCommand::ArbPoint + { + public: + ArbPointGen6(uint8_t prio) : + ArbPoint(prio) {} + + ArbPointGen6() : ArbPoint() {} + virtual unsigned GetSize() const; + virtual void Serialize(void **buff) const; + virtual Command *Clone() const; + private: + bool m_swtc = false; + }; +}; + +} // namespace gaudi2 \ No newline at end of file diff --git a/synapse_backend/low_level_driver/gaudi_packet_gen.h b/synapse_backend/low_level_driver/gaudi_packet_gen.h deleted file mode 100644 index cdd6abb..0000000 --- a/synapse_backend/low_level_driver/gaudi_packet_gen.h +++ /dev/null @@ -1,141 +0,0 @@ -/* SPDX-License-Identifier: MIT - * - * Copyright 2016-2021 HabanaLabs, Ltd. - * All Rights Reserved. - * - */ - -#pragma once - -#include "program.h" - -namespace CPCommand -{ - class NopGen2 : public Nop - { - public: - using Nop::Nop; - virtual unsigned GetSize() const; - virtual void Serialize(void **buff) const; - virtual Command *Clone() const; - }; - - class StopGen2 : public Stop - { - public: - using Stop::Stop; - virtual unsigned GetSize() const; - virtual void Serialize(void **buff) const; - virtual Command *Clone() const; - }; - - class WReg32Gen2 : public WReg32 - { - public: - using WReg32::WReg32; - virtual unsigned GetSize() const; - virtual void Serialize(void **buff) const; - virtual Command *Clone() const; - }; - - class WRegBulkGen2 : public WRegBulk - { - public: - using WRegBulk::WRegBulk; - virtual ~WRegBulkGen2() {} - - virtual unsigned GetSize() const; - virtual void Serialize(void **buff) const; - virtual Command *Clone() const; - }; - - class MsgLongGen2 : public MsgLong - { - public: - using MsgLong::MsgLong; - virtual unsigned GetSize() const; - virtual void Serialize(void **buff) const; - virtual Command *Clone() const; - }; - - class MsgShortGen2 : public MsgShort - { - public: - using MsgShort::MsgShort; - virtual unsigned GetSize() const; - virtual void Serialize(void **buff) const; - virtual Command *Clone() const; - }; - - class MsgProtGen2 : public MsgProt - { - public: - using MsgProt::MsgProt; - virtual unsigned GetSize() const; - virtual void Serialize(void **buff) const; - virtual Command *Clone() const; - }; - - class FenceGen2 : public Fence - { - public: - using Fence::Fence; - virtual unsigned GetSize() const; - virtual void Serialize(void **buff) const; - virtual Command *Clone() const; - }; - - class LinDmaGen2 : public LinDma - { - public: - using LinDma::LinDma; - virtual unsigned GetSize() const; - virtual void Serialize(void **buff) const; - virtual Command *Clone() const; - }; - - class RepeatGen2 : public Repeat - { - public: - using Repeat::Repeat; - virtual unsigned GetSize() const; - virtual void Serialize(void **buff) const; - virtual Command *Clone() const; - }; - - class WaitGen2 : public Wait - { - public: - using Wait::Wait; - virtual unsigned GetSize() const; - virtual void Serialize(void **buff) const; - virtual Command *Clone() const; - }; - - class LoadAndExecGen2 : public LoadAndExec - { - public: - using LoadAndExec::LoadAndExec; - virtual unsigned GetSize() const; - virtual void Serialize(void **buff) const; - virtual Command *Clone() const; - }; - - class CpDmaGen2 : public CpDma - { - public: - using CpDma::CpDma; - virtual unsigned GetSize() const; - virtual void Serialize(void **buff) const; - virtual Command *Clone() const; - }; - - class ArbPointGen2 : public ArbPoint - { - public: - using ArbPoint::ArbPoint; - virtual unsigned GetSize() const; - virtual void Serialize(void **buff) const; - virtual Command *Clone() const; - }; -}; diff --git a/synapse_backend/low_level_driver/hw_abstraction_layer.h b/synapse_backend/low_level_driver/hw_abstraction_layer.h index b949e2e..88c635a 100644 --- a/synapse_backend/low_level_driver/hw_abstraction_layer.h +++ b/synapse_backend/low_level_driver/hw_abstraction_layer.h @@ -14,6 +14,7 @@ #include "TensorDescriptor.h" #include "program.h" #include "index_space.h" +#include "synapse_common_types.h" class HWAbstractionLayer { @@ -21,8 +22,9 @@ class HWAbstractionLayer HWAbstractionLayer() {} virtual ~HWAbstractionLayer() {} - virtual unsigned GetTensorSizeFromDesc(TensorDescriptorGaudi& desc) const = 0; - virtual unsigned GetTensorSizeFromDesc(TensorDescriptorGaudi& desc0, TensorDescriptorGaudi& desc1) const = 0; + virtual synDeviceType getDeviceType() const = 0; + virtual unsigned GetTensorSizeFromDesc(TensorDescriptor& desc) const = 0; + virtual unsigned GetTensorSizeFromDesc(TensorDescriptor& desc0, TensorDescriptor& desc1) const = 0; virtual unsigned GetSpecialFuncTabNr() const = 0; virtual void GetSpecialFuncTabSizes(uint32_t* sizes, unsigned sizesLen) const = 0; virtual void CopySpecialFuncTab( @@ -47,7 +49,8 @@ class HWAbstractionLayer virtual uint64_t GetSyncMngrVarAddr(std::string varName, unsigned idx) const = 0; virtual unsigned GetDmaDownVarOffset(std::string varName) const = 0; virtual unsigned GetTpcCfgVarOffset(std::string varName) const = 0; - virtual unsigned GetMonArmRawVal(unsigned mask, unsigned sid, unsigned sod, unsigned sop) const = 0; + virtual unsigned GetMonArmRawVal(uint8_t mask, uint8_t sid, unsigned sod, unsigned sop) const = 0; + virtual unsigned GetMonCfgRawVal(unsigned msbSid) const {return 0;} virtual void GetTpcTabOffset(int TabIdx, uint32_t* baseAddrLow, uint32_t* baseAddrHigh) const = 0; virtual std::shared_ptr GenWReg32(uint16_t offset, uint32_t value, bool mb = false, bool rb = false, bool eb = false) const = 0; @@ -63,9 +66,13 @@ class HWAbstractionLayer virtual void WriteSrf(TpcDescHandle tpcDesc, const uint32_t* params, unsigned paramsNr) const = 0; virtual void WriteKernelCfg(TpcDescHandle tpcDesc, uint32_t smallVlm) const = 0; virtual void WriteKernelAddr(TpcDescHandle tpcDesc, uint64_t kernelAddr) const = 0; - virtual void WriteTensorDesc(TpcDescHandle tpcDesc, TensorDescriptorGaudi& tensorDesc, unsigned tensorId) const = 0; - virtual void WriteTpcJobDesc(TpcDescHandle tpcDesc, const IndexSpace& partition, uint32_t contextId, uint32_t soAddr, uint32_t soMsg, uint32_t soIdx, bool updatePrintfAddr, int printfTensorIdx) const = 0; + virtual void WriteTensorDesc(TpcDescHandle tpcDesc, TensorDescriptor& tensorDesc, unsigned tensorId) const = 0; + virtual void WriteTpcJobDesc(TpcDescHandle tpcDesc, const IndexSpace& partition, uint32_t soAddr, uint32_t soMsg, bool updatePrintfAddr, int printfTensorIdx) const = 0; + virtual uint32_t GenTpcCmd() const = 0; + virtual uint32_t GetTpcTensorConfig() const = 0; + virtual bool isMmuEnabled() const = 0; + virtual bool shouldConfigureMonCfg() const = 0; void SetSmInfo(int firstAvailSob, int firstAvailMon) { m_firstAvailMonitor = firstAvailMon; diff --git a/synapse_backend/low_level_driver/launcher.cpp b/synapse_backend/low_level_driver/launcher.cpp index 9b3571e..8ad59be 100644 --- a/synapse_backend/low_level_driver/launcher.cpp +++ b/synapse_backend/low_level_driver/launcher.cpp @@ -6,12 +6,13 @@ */ +#include "gaudi2/asic_reg/gaudi2_blocks.h" +#include "program.h" #undef NDEBUG #include #include #include #include -#include #include #include #include @@ -182,12 +183,14 @@ void TestLauncher::ExecuteProgram(Device* device, const unsigned stream, unsigned dmaOutBuffSize = outputBuffers->size() * pLinDma->GetSize(); - dmaInBuffSize += pMsgLong->GetSize(); // reset input sync object - dmaInBuffSize += - CountBits(syncInfo->outputSOSel) * pMsgLong->GetSize(); // reset output sync object - std::shared_ptr pFence = device->GetHal()->GenFence(0, 0, 0); dmaOutBuffSize += 4 * pMsgLong->GetSize(); // arm the monitor + + if (device->GetHal()->shouldConfigureMonCfg()) + { + dmaOutBuffSize += pMsgLong->GetSize(); // arm the monitor - mon_config + } + dmaOutBuffSize += pFence->GetSize(); // fence dmaOutBuffSize += pMsgLong->GetSize(); // reset input sync object dmaOutBuffSize += @@ -217,60 +220,24 @@ void TestLauncher::ExecuteProgram(Device* device, const unsigned stream, assert(dmaInHostPtr != nullptr && "dmaInHostPtr is null!"); uint8_t* dmaInPtr = ((uint8_t*)dmaInHostPtr); - // reset input so - { - uint64_t addr = device->GetHal()->GetDmaDownSyncObjectAddr(); - std::shared_ptr pMsgLong = device->GetHal()->GenMsgLong(addr, 0); - pMsgLong->Serialize((void**)&dmaInPtr); - } - - // reset output so - static const unsigned c_so_group_size = device->GetHal()->GetSyncObjectGroupSize(); - for (unsigned k = 0; k < c_so_group_size; k++) - { - if (syncInfo->outputSOSel & (1 << k)) - { - unsigned soIdx = device->GetHal()->GetDmaUpSyncObjectIndex() + k; - uint64_t addr = device->GetHal()->GetSyncMngrVarAddr("sob_obj", soIdx); - std::shared_ptr pMsgLong = device->GetHal()->GenMsgLong(addr, 0); - pMsgLong->Serialize((void**)&dmaInPtr); - } - } - - // INFO: temporarily removing ARB_POINT packet from DMA down/up - /* - // arb request - if (arbitration && arbitration->enable) - { - packet_arb_point * ptr = (packet_arb_point*)dmaInPtr; - ptr->eng_barrier = 0; - ptr->msg_barrier = 0; - ptr->reg_barrier = 0; - ptr->opcode = PACKET_ARB_POINT; - ptr->pred = 0; - ptr->priority = arbitration->prio; - ptr->rls = 0; - dmaInPtr += sizeof(packet_arb_point); - } - */ - // dma in { uint64_t syncObj = device->GetHal()->GetSyncMngrVarAddr( "sob_obj", device->GetHal()->GetDmaDownSyncObjectIndex()); - // TODO : add support for multiple streams + uint16_t offset = device->GetHal()->GetDmaDownVarOffset("wr_comp_addr_lo"); std::shared_ptr pMsg1 = device->GetHal()->GenWReg32( - device->GetHal()->GetDmaDownVarOffset("wr_comp_addr_lo"), (uint32_t)syncObj); + offset, (uint32_t)syncObj); pMsg1->Serialize((void**)&dmaInPtr); + offset = device->GetHal()->GetDmaDownVarOffset("wr_comp_addr_hi"); std::shared_ptr pMsg2 = device->GetHal()->GenWReg32( - device->GetHal()->GetDmaDownVarOffset("wr_comp_addr_hi"), - (uint32_t)(syncObj >> 32)); + offset, (uint32_t)(syncObj >> 32)); pMsg2->Serialize((void**)&dmaInPtr); + offset = device->GetHal()->GetDmaDownVarOffset("wr_comp_wdata"); std::shared_ptr pMsg3 = device->GetHal()->GenWReg32( - device->GetHal()->GetDmaDownVarOffset("wr_comp_wdata"), 1, true, true, true); + offset, 1, true, true, true); pMsg3->Serialize((void**)&dmaInPtr); unsigned bufferCtr = 0; @@ -314,75 +281,17 @@ void TestLauncher::ExecuteProgram(Device* device, const unsigned stream, wkldsList.push_back(inputWkld); // step 4 - prepare output buffer - unsigned outQId = 0; - unsigned dmaOutQid = device->GetHal()->GetDMAOutQid(); - switch (stream) - { - case 0: - outQId = dmaOutQid; - break; - case 1: - outQId = dmaOutQid + 1; - break; - case 2: - outQId = dmaOutQid + 2; - break; - case 3: - outQId = dmaOutQid + 3; - break; - default: - assert(0); - } + unsigned dmaOutQid = device->GetHal()->GetDMAOutQid(); unsigned junk; uint64_t qmBase; - device->GetHal()->Qid2Qman(outQId, qmBase, junk); + device->GetHal()->Qid2Qman(dmaOutQid + stream, qmBase, junk); assert(dmaOutHostPtr != nullptr && "dmaOutHostPtr is null!"); uint8_t* dmaOutPtr = ((uint8_t*)dmaOutHostPtr); + uint64_t fenceAddr = qmBase + device->GetHal()->GetQmanFenceOffset(0, stream); - // mon arm - addr low - { - uint64_t fenceAddr = qmBase + device->GetHal()->GetQmanFenceOffset(0, stream); - uint64_t monArmAddr = device->GetHal()->GetSyncMngrVarAddr("mon_pay_addrl", outQId); - std::shared_ptr pMsgLong = - device->GetHal()->GenMsgLong(monArmAddr, (uint32_t)fenceAddr); - pMsgLong->Serialize((void**)&dmaOutPtr); - } - - // mon arm - addr high - { - uint64_t fenceAddr = qmBase + device->GetHal()->GetQmanFenceOffset(0, stream); - uint64_t monArmAddr = device->GetHal()->GetSyncMngrVarAddr("mon_pay_addrh", outQId); - std::shared_ptr pMsgLong = - device->GetHal()->GenMsgLong(monArmAddr, (uint32_t)(fenceAddr >> 32)); - pMsgLong->Serialize((void**)&dmaOutPtr); - } - - // mon arm - value - { - uint64_t monArmAddr = device->GetHal()->GetSyncMngrVarAddr("mon_pay_data", outQId); - std::shared_ptr pMsgLong = device->GetHal()->GenMsgLong(monArmAddr, 1); - pMsgLong->Serialize((void**)&dmaOutPtr); - } - - // mon arm - arm - { - uint64_t monArmAddr = device->GetHal()->GetSyncMngrVarAddr("mon_arm", outQId); - uint32_t monArmVal = device->GetHal()->GetMonArmRawVal(~(syncInfo->outputSOSel), // mask - syncInfo->outputSOIdx, // sid - syncInfo->outputSOTarget, // sod - 0); // sop - std::shared_ptr pMsgLong = - device->GetHal()->GenMsgLong(monArmAddr, monArmVal); - pMsgLong->Serialize((void**)&dmaOutPtr); - } - - // fence - { - std::shared_ptr pFence = device->GetHal()->GenFence(0, 1, 1); - pFence->Serialize((void**)&dmaOutPtr); - } + addMonitorForNode(device, stream, syncInfo, dmaOutQid + stream, fenceAddr, &dmaOutPtr, nullptr, true); // dma unsigned dmaDir; @@ -403,22 +312,18 @@ void TestLauncher::ExecuteProgram(Device* device, const unsigned stream, } // reset output so - for (unsigned k = 0; k < c_so_group_size; k++) - { - if (syncInfo->outputSOSel & (1 << k)) - { - unsigned soIdx = device->GetHal()->GetDmaUpSyncObjectIndex() + k; - uint64_t addr = device->GetHal()->GetSyncMngrVarAddr("sob_obj", soIdx); - std::shared_ptr pMsgLong = device->GetHal()->GenMsgLong(addr, 0); - pMsgLong->Serialize((void**)&dmaOutPtr); - } + { + uint64_t addr = device->GetHal()->GetDmaUpSyncObjectAddr(); + std::shared_ptr pMsgLong = + device->GetHal()->GenMsgLong(addr, 0); + pMsgLong->Serialize((void**)&dmaOutPtr); } assert(((uint64_t)dmaOutPtr - (uint64_t)dmaOutHostPtr) == dmaOutBuffSize); Device::QueueWkld outputWkld; outputWkld.buffer = dmaOutHandle; outputWkld.size = dmaOutBuffSize; - outputWkld.qid = outQId; + outputWkld.qid = dmaOutQid + stream; outputWkld.flags = dmaOutFlags; wkldsList.push_back(outputWkld); @@ -498,7 +403,7 @@ void TestLauncher::CreateAndExecuteProgram(SynMemoryAllocator* memAlloc, Device* programBuffer.hostVirtAddr = addressOut; DownloadProgram2Device(device, stream, &programBuffer); - + ResetSoObjsInDevice(device, syncInfo, stream); ExecuteProgram(device, stream, &devicePrograms, syncInfo, inputBuffers, outputBuffers); @@ -519,49 +424,177 @@ void TestLauncher::AddInputFenceSequence(Device* device, CPProgram& prog, unsigned stream; unsigned qid = prog.GetQId(); device->GetHal()->Qid2Qman(qid, qmanBase, stream); - uint64_t fenceAddr; - switch (stream) + uint64_t fenceAddr = qmanBase + device->GetHal()->GetQmanFenceOffset(stream, Device::c_streams_num); + SyncInfo syncInfo {syncObjectGroup /*idx*/, 1 /*sel*/, 1 /*target*/}; + addMonitorForNode(device, stream, &syncInfo, qid, fenceAddr, nullptr, &prog, true); + +} +void TestLauncher::ResetSoObjsInDevice(Device *device, const SyncInfo* syncInfo, + unsigned stream) +{ Device::Handle cmdBuffHandle; + void *hostAddr; + unsigned cmdBuffFlags; + std::shared_ptr dummyMsgLong = + device->GetHal()->GenMsgLong(0, 0); + + unsigned cmdBuffSize = dummyMsgLong->GetSize(); // reset input sync object + cmdBuffSize += CountBits(syncInfo->outputSOSel) * + dummyMsgLong->GetSize(); // reset output sync object + device->GetCB(cmdBuffSize, cmdBuffHandle, hostAddr, cmdBuffFlags); + + // reset input so + { + std::shared_ptr pMsgLong; + uint64_t addr = device->GetHal()->GetDmaDownSyncObjectAddr(); + pMsgLong = device->GetHal()->GenMsgLong(addr, 0); + pMsgLong->Serialize(&hostAddr); + } + + // reset output so + static const unsigned c_so_group_size = + device->GetHal()->GetSyncObjectGroupSize(); + for (unsigned k = 0; k < c_so_group_size; k++) { + if (syncInfo->outputSOSel & (1 << k)) { + unsigned soIdx = device->GetHal()->GetDmaUpSyncObjectIndex() + k; + uint64_t addr = device->GetHal()->GetSyncMngrVarAddr("sob_obj", soIdx); + std::shared_ptr pMsgLong = + device->GetHal()->GenMsgLong(addr, 0); + pMsgLong->Serialize((void **)&hostAddr); + } + } + Device::QueueWkld wkld; + unsigned dmaInQid = device->GetHal()->GetDMAInQid(); + switch (stream) { + case 0: + wkld.qid = dmaInQid; + break; + case 1: + wkld.qid = dmaInQid + 1; + break; + case 2: + wkld.qid = dmaInQid + 2; + break; + case 3: + wkld.qid = dmaInQid + 3; + break; + default: + assert(0); + } + wkld.buffer = cmdBuffHandle; + wkld.size = cmdBuffSize; + wkld.flags = cmdBuffFlags; + + std::list wkldsList = {}; + wkldsList.push_back(wkld); + + Device::Handle submitHandle; + std::list setupList; + device->SubmitWklds(setupList, wkldsList, false, submitHandle); + device->Wait(submitHandle); + device->ReleaseCB(cmdBuffHandle); +} + + +void TestLauncher::addMonitorForNode(Device* device, + unsigned stream, + const SyncInfo* syncInfo, + uint32_t outMonitorIdx, + uint64_t fenceAddr, + uint8_t** CBPtr, + CPProgram* prog, + bool addFence) +{ + assert(CBPtr != nullptr || prog != nullptr); + bool addToProg = (prog != nullptr); + // mon arm - addr low { - case 0: - fenceAddr = qmanBase + device->GetHal()->GetQmanFenceOffset(0, Device::c_streams_num); - break; - case 1: - fenceAddr = qmanBase + device->GetHal()->GetQmanFenceOffset(1, Device::c_streams_num); - break; - case 2: - fenceAddr = qmanBase + device->GetHal()->GetQmanFenceOffset(2, Device::c_streams_num); - break; - case 3: - fenceAddr = qmanBase + device->GetHal()->GetQmanFenceOffset(3, Device::c_streams_num); - break; - default: - assert(0); + uint64_t monArmAddr = device->GetHal()->GetSyncMngrVarAddr("mon_pay_addrl", outMonitorIdx); + std::shared_ptr pMsgLong = + device->GetHal()->GenMsgLong(monArmAddr, (uint32_t)fenceAddr); + if (addToProg) + { + prog->AddCommandsBack(*pMsgLong); + } + else + { + pMsgLong->Serialize((void**)CBPtr); + } } - std::shared_ptr pMsgLong1 = device->GetHal()->GenMsgLong( - device->GetHal()->GetSyncMngrVarAddr("mon_pay_addrl", qid), // addr - (uint32_t)fenceAddr); // value - prog.AddCommandsBack(*pMsgLong1); - - std::shared_ptr pMsgLong2 = device->GetHal()->GenMsgLong( - device->GetHal()->GetSyncMngrVarAddr("mon_pay_addrh", qid), // addr - (uint32_t)(fenceAddr >> 32)); // value - prog.AddCommandsBack(*pMsgLong2); - - std::shared_ptr pMsgLong3 = device->GetHal()->GenMsgLong( - device->GetHal()->GetSyncMngrVarAddr("mon_pay_data", qid), // addr - 1); // value - prog.AddCommandsBack(*pMsgLong3); - - std::shared_ptr pMsgLong4 = - device->GetHal()->GenMsgLong(device->GetHal()->GetSyncMngrVarAddr("mon_arm", qid), // addr - device->GetHal()->GetMonArmRawVal( // value - 254, // mask // ~(1) in 8 bit - syncObjectGroup, // sid - 1, // sod - 0)); // sop - prog.AddCommandsBack(*pMsgLong4); - - std::shared_ptr pFence = device->GetHal()->GenFence(stream, 1, 1); - prog.AddCommandsBack(*pFence); + // mon arm - addr high + { + uint64_t monArmAddr = device->GetHal()->GetSyncMngrVarAddr("mon_pay_addrh", outMonitorIdx); + std::shared_ptr pMsgLong = + device->GetHal()->GenMsgLong(monArmAddr, (uint32_t)(fenceAddr >> 32)); + if (addToProg) + { + prog->AddCommandsBack(*pMsgLong); + } + else + { + pMsgLong->Serialize((void**)CBPtr); + } + } + + // mon arm - value + { + uint64_t monArmAddr = device->GetHal()->GetSyncMngrVarAddr("mon_pay_data", outMonitorIdx); + std::shared_ptr pMsgLong = device->GetHal()->GenMsgLong(monArmAddr, 1); + if (addToProg) + { + prog->AddCommandsBack(*pMsgLong); + } + else + { + pMsgLong->Serialize((void**)CBPtr); + } + } + + if(device->GetHal()->shouldConfigureMonCfg()) + { + uint64_t monCfgAddr = device->GetHal()->GetSyncMngrVarAddr("mon_cfg", outMonitorIdx); + uint32_t monCfgVal = device->GetHal()->GetMonCfgRawVal(syncInfo->outputSOIdx >> 8); // msb + std::shared_ptr pMsgLong = + device->GetHal()->GenMsgLong(monCfgAddr, monCfgVal); + if (addToProg) + { + prog->AddCommandsBack(*pMsgLong); + } + else + { + pMsgLong->Serialize((void**)CBPtr); + } + } + + // mon arm - arm + { + static constexpr unsigned equal_or_great = 0; + uint64_t monArmAddr = device->GetHal()->GetSyncMngrVarAddr("mon_arm", outMonitorIdx); + uint32_t monArmVal = device->GetHal()->GetMonArmRawVal(~(uint8_t)(syncInfo->outputSOSel), // mask + syncInfo->outputSOIdx, // sid + syncInfo->outputSOTarget, // sod + equal_or_great); // sop + std::shared_ptr pMsgLong = + device->GetHal()->GenMsgLong(monArmAddr, monArmVal); + if (addToProg) + { + prog->AddCommandsBack(*pMsgLong); + } + else + { + pMsgLong->Serialize((void**)CBPtr); + } + } + if (addFence) + { + std::shared_ptr pFence = device->GetHal()->GenFence(0, 1, 1); + if (addToProg) + { + prog->AddCommandsBack(*pFence); + } + else + { + pFence->Serialize((void**)CBPtr); + } + } } diff --git a/synapse_backend/low_level_driver/launcher.h b/synapse_backend/low_level_driver/launcher.h index d6252c1..bff6304 100644 --- a/synapse_backend/low_level_driver/launcher.h +++ b/synapse_backend/low_level_driver/launcher.h @@ -96,19 +96,27 @@ class TestLauncher DeviceMemory_t memSpace); private: - static void GetProgBuffSizeAndOffsets( - Device *device, - const std::list *programs, - std::list *offsets, - unsigned *size); - static void PrepareProgBuff( - Device *device, - const unsigned stream, - const uint64_t deviceAddr, - const std::list *programs, - const std::list *offsets, - const unsigned bufferSize, - std::list *devicePrograms, - void *progBuff); + static void ResetSoObjsInDevice(Device *device, const SyncInfo* syncInfo, + unsigned stream); + static void + GetProgBuffSizeAndOffsets(Device *device, + const std::list *programs, + std::list *offsets, unsigned *size); + static void PrepareProgBuff(Device *device, const unsigned stream, + const uint64_t deviceAddr, + const std::list *programs, + const std::list *offsets, + const unsigned bufferSize, + std::list *devicePrograms, + void *progBuff); + static void addMonitorForNode(Device* device, + unsigned stream, + const SyncInfo* syncInfo, + uint32_t outMonitorIdx, + uint64_t fenceAddr, + uint8_t** CBPtr, + CPProgram* prog, + bool addFence); + }; diff --git a/synapse_backend/low_level_driver/program.h b/synapse_backend/low_level_driver/program.h index 820b0fa..f78432d 100644 --- a/synapse_backend/low_level_driver/program.h +++ b/synapse_backend/low_level_driver/program.h @@ -6,6 +6,7 @@ */ #pragma once +#include #include #include #include @@ -18,8 +19,8 @@ namespace CPCommand class Command { public: - Command(bool mb = true, bool rb = true, bool eb = true) - : m_mb(mb), m_rb(rb), m_eb(eb) {} + Command(bool mb = true, bool eb = true) + : m_mb(mb), m_eb(eb) {} virtual ~Command() {} @@ -28,7 +29,6 @@ namespace CPCommand virtual Command *Clone() const = 0; bool m_mb; - bool m_rb; bool m_eb; }; @@ -36,7 +36,7 @@ namespace CPCommand class Nop : public Command { public: - Nop(bool mb = true, bool rb = true, bool eb = true) : Command(mb, rb, eb) {}; + Nop(bool mb = true, bool eb = true) : Command(mb, eb) {}; virtual unsigned GetSize() const = 0; virtual void Serialize(void **buff) const = 0; @@ -60,8 +60,8 @@ namespace CPCommand uint32_t m_value; uint8_t m_pred; - WReg32(uint16_t offset, uint32_t value, bool mb = true, bool rb = true, bool eb = true) : - Command(mb, rb, eb), m_offset(offset), m_value(value), m_pred(0) {}; + WReg32(uint16_t offset, uint32_t value, bool mb = true, bool eb = true) : + Command(mb, eb), m_offset(offset), m_value(value), m_pred(0) {}; WReg32() : WReg32(0, 0) {}; virtual unsigned GetSize() const = 0; @@ -79,16 +79,13 @@ namespace CPCommand WRegBulk() : Command(), m_offset(0), m_values(0), m_pred(0), m_numValues(0), m_freeValues(0) {}; - WRegBulk(uint16_t offset, uint64_t *values, unsigned numValues) : + WRegBulk(uint16_t offset, uint64_t* values, unsigned numValues) : Command(), m_offset(offset), m_pred(0), m_numValues(numValues), m_freeValues(1) { m_values = (uint64_t*)malloc(m_numValues * sizeof(uint64_t)); memcpy(m_values, values, m_numValues * sizeof(uint64_t)); } - WRegBulk(uint16_t offset, uint32_t *values, unsigned numValues) : - WRegBulk(offset, (uint64_t*)values, numValues / 2) {} - WRegBulk(uint16_t offset, std::list::const_iterator &begin, std::list::const_iterator &end) : Command(), m_offset(offset), m_pred(0),m_numValues(0), m_freeValues(1) { @@ -116,7 +113,7 @@ namespace CPCommand } WRegBulk(const WRegBulk &other) : - Command(other.m_mb, other.m_rb, other.m_eb), m_offset(other.m_offset), + Command(other.m_mb, other.m_eb), m_offset(other.m_offset), m_pred(other.m_pred),m_numValues(other.m_numValues), m_freeValues(1) { m_values = (uint64_t*)malloc(m_numValues * sizeof(uint64_t)); @@ -147,8 +144,8 @@ namespace CPCommand bool m_weaklyOrdered; - MsgLong(uint64_t addr, uint32_t value, bool mb = true, bool rb = true, bool eb = true) : - Command(mb, rb, eb), m_addr(addr), m_value(value), m_pred(0), + MsgLong(uint64_t addr, uint32_t value, bool mb = true, bool eb = true) : + Command(mb, eb), m_addr(addr), m_value(value), m_pred(0), m_op(0), m_noSnoop(0), m_weaklyOrdered(0) {} MsgLong() : MsgLong(0, 0) {} @@ -190,8 +187,8 @@ namespace CPCommand bool m_noSnoop; bool m_weaklyOrdered; - MsgProt(uint64_t addr, uint32_t value, bool mb = true, bool rb = true, bool eb = true) : - Command(mb, rb, eb), m_addr(addr), m_value(value), m_pred(0), + MsgProt(uint64_t addr, uint32_t value, bool mb = true, bool eb = true) : + Command(mb, eb), m_addr(addr), m_value(value), m_pred(0), m_op(0), m_noSnoop(0), m_weaklyOrdered(0) {} MsgProt() : MsgProt(0, 0) {} @@ -209,8 +206,8 @@ namespace CPCommand unsigned m_id; uint8_t m_pred; - Fence(unsigned id, uint8_t targetVal, unsigned decVal, bool mb = true, bool rb = true, bool eb = true) - : Command(mb, rb, eb), m_decVal(decVal), m_targetVal(targetVal), m_id(id), m_pred(0) {} + Fence(unsigned id, uint8_t targetVal, unsigned decVal, bool mb = true, bool eb = true) + : Command(mb, eb), m_decVal(decVal), m_targetVal(targetVal), m_id(id), m_pred(0) {} Fence() : Fence(0, 0, 0) {} diff --git a/synapse_backend/runner/SpecialFuncCoefficientsGen2.cpp b/synapse_backend/runner/SpecialFuncCoefficientsGen2.cpp index 5f704d7..08a2cab 100644 --- a/synapse_backend/runner/SpecialFuncCoefficientsGen2.cpp +++ b/synapse_backend/runner/SpecialFuncCoefficientsGen2.cpp @@ -8,7 +8,7 @@ #include #include #include "SpecialFuncCoefficients.h" -#include "SpecialFuncCoefficients_defGen2.h" +#include "gaudi/SpecialFuncCoefficients_defGen2.h" using namespace std; namespace tpc_gaudi { diff --git a/synapse_backend/runner/SpecialFuncCoefficientsGen6.cpp b/synapse_backend/runner/SpecialFuncCoefficientsGen6.cpp new file mode 100644 index 0000000..e8b7837 --- /dev/null +++ b/synapse_backend/runner/SpecialFuncCoefficientsGen6.cpp @@ -0,0 +1,6237 @@ +/***************************************************************************** + * Copyright (C) 2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + * Unauthorized copying of this file, via any medium is strictly prohibited. + * Proprietary and confidential. + ****************************************************************************** + */ + +#include +#include +#include "SpecialFuncCoefficients.h" +#include "gaudi2/SpecialFuncCoefficients_defGen6.h" +using namespace std; + +// clang-format off + +namespace tpc_gaudi2 { + +// FP32 + +//log2_default_coeffs_m7_zero_exp +// followed by log2_default_coeffs_m7_nonzero_exp +float log2_coeffs_fp32[3 * 256] = // C0, C1, C2 +{ 1.4426950216, -0.7213352919, 0.4767034054, 1.4370887280, -0.7138869762, 0.4684575796, +1.4315400124, -0.7065676451, 0.4604130983, 1.4260480404, -0.6993738413, 0.4525636435, +1.4206118584, -0.6923028231, 0.4449031353, 1.4152303934, -0.6853513718, 0.4374254942, +1.4099026918, -0.6785168648, 0.4301253557, 1.4046280384, -0.6717963219, 0.4229969978, +1.3994054794, -0.6651872396, 0.4160354137, 1.3942340612, -0.6586868763, 0.4092354774, +1.3891130686, -0.6522927284, 0.4025923014, 1.3840415478, -0.6460024118, 0.3961013556, +1.3790189028, -0.6398135424, 0.3897579908, 1.3740440607, -0.6337237358, 0.3835577965, +1.3691165447, -0.6277308464, 0.3774968386, 1.3642354012, -0.6218326092, 0.3715709448, +1.3594000340, -0.6160269976, 0.3657763004, 1.3546096087, -0.6103118658, 0.3601089716, +1.3498635292, -0.6046853065, 0.3545655012, 1.3451610804, -0.5991452932, 0.3491423130, +1.3405015469, -0.5936901569, 0.3438361883, 1.3358843327, -0.5883178711, 0.3386436701, +1.3313087225, -0.5830266476, 0.3335616589, 1.3267742395, -0.5778149366, 0.3285871744, +1.3222800493, -0.5726808310, 0.3237172365, 1.3178257942, -0.5676229000, 0.3189491034, +1.3134106398, -0.5626394749, 0.3142797947, 1.3090342283, -0.5577288866, 0.3097069263, +1.3046958447, -0.5528898239, 0.3052278757, 1.3003950119, -0.5481207371, 0.3008399010, +1.2961311340, -0.5434203148, 0.2965409756, 1.2919038534, -0.5387868881, 0.2923284769, +1.2877123356, -0.5342193842, 0.2882003784, 1.2835563421, -0.5297163725, 0.2841544151, +1.2794352770, -0.5252765417, 0.2801883221, 1.2753486633, -0.5208986998, 0.2763003111, +1.2712960243, -0.5165815353, 0.2724882364, 1.2672768831, -0.5123240948, 0.2687501907, +1.2632907629, -0.5081249475, 0.2650845051, 1.2593371868, -0.5039830208, 0.2614890337, +1.2554157972, -0.4998973608, 0.2579623461, 1.2515259981, -0.4958667755, 0.2545025349, +1.2476676702, -0.4918903112, 0.2511081696, 1.2438400984, -0.4879667759, 0.2477774620, +1.2400429249, -0.4840953350, 0.2445089817, 1.2362757921, -0.4802749157, 0.2413011789, +1.2325384617, -0.4765046835, 0.2381526232, 1.2288302183, -0.4727836847, 0.2350617647, +1.2251509428, -0.4691108465, 0.2320275307, 1.2215001583, -0.4654854536, 0.2290482521, +1.2178776264, -0.4619066715, 0.2261229753, 1.2142827511, -0.4583735466, 0.2232501507, +1.2107152939, -0.4548853636, 0.2204287052, 1.2071750164, -0.4514411688, 0.2176574469, +1.2036613226, -0.4480403662, 0.2149351835, 1.2001742125, -0.4446821213, 0.2122608423, +1.1967130899, -0.4413655996, 0.2096332312, 1.1932777166, -0.4380900860, 0.2070513964, +1.1898677349, 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-0.3701508045, 0.1565093994, +1.1149197817, -0.3677053452, 0.1547988653, 1.1120566130, -0.3652867079, 0.1531147957, +1.1092121601, -0.3628942966, 0.1514563560, 1.1063863039, -0.3605278730, 0.1498230696, +1.1035788059, -0.3581868410, 0.1482145786, 1.1007894278, -0.3558710814, 0.1466304064, +1.0980181694, -0.3535799980, 0.1450699568, 1.0952646732, -0.3513132334, 0.1435327530, +1.0925288200, -0.3490705490, 0.1420185566, 1.0898103714, -0.3468515873, 0.1405266523, +1.0871092081, -0.3446558714, 0.1390568018, 1.0844249725, -0.3424831629, 0.1376085281, +1.0817577839, -0.3403331041, 0.1361814737, 1.0791072845, -0.3382052183, 0.1347751617, +1.0764732361, -0.3360993862, 0.1333892345, 1.0738556385, -0.3340152502, 0.1320233345, +1.0712541342, -0.3319523335, 0.1306769848, 1.0686687231, -0.3299105167, 0.1293499470, +1.0660991669, -0.3278894424, 0.1280418634, 1.0635453463, -0.3258888721, 0.1267523766, +1.0610071421, -0.3239083290, 0.1254810095, 1.0584841967, -0.3219478130, 0.1242275238, +1.0559766293, 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0.7630759478, -0.2009750605, 0.9248125553, 0.7599357367, -0.1993277073, +0.9307373762, 0.7568212748, -0.1977005005, 0.9366379976, 0.7537322044, -0.1960932016, +0.9425145388, 0.7506682873, -0.1945054531, 0.9483672380, 0.7476291656, -0.1929368973, +0.9541963339, 0.7446144819, -0.1913871765, 0.9600019455, 0.7416241169, -0.1898560524, +0.9657843113, 0.7386577129, -0.1883432865, 0.9715435505, 0.7357147932, -0.1868485212, +0.9772799015, 0.7327953577, -0.1853713989, 0.9829936028, 0.7298989296, -0.1839118004, +0.9886846542, 0.7270252705, -0.1824693680, 0.9943534136, 0.7241742611, -0.1810438633 }; + +// ========== GL pow2 poly2 approximation (m = 6) =================== + +float pow2_coeffs_fp32[3*64] = // C0, C1, C2 +{ 1.0000000000, 0.6931395531, 0.2415316105, 1.0108892918, 0.7006872892, 0.2441617250, +1.0218971968, 0.7083172798, 0.2468204498, 1.0330249071, 0.7160303593, 0.2495082617, +1.0442737341, 0.7238274813, 0.2522251606, 1.0556452274, 0.7317093611, 0.2549717426, +1.0671404600, 0.7396771908, 0.2577481270, 1.0787608624, 0.7477318048, 0.2605549097, +1.0905077457, 0.7558740377, 0.2633920908, 1.1023825407, 0.7641049623, 0.2662602663, +1.1143867970, 0.7724255323, 0.2691596746, 1.1265215874, 0.7808367014, 0.2720906734, +1.1387887001, 0.7893394232, 0.2750535011, 1.1511892080, 0.7979347706, 0.2780486345, +1.1637248993, 0.8066236973, 0.2810764313, 1.1763969660, 0.8154072762, 0.2841371298, +1.1892070770, 0.8242864609, 0.2872312069, 1.2021567822, 0.8332623243, 0.2903589010, +1.2152473927, 0.8423359394, 0.2935206890, 1.2284805775, 0.8515083790, 0.2967169285, +1.2418577671, 0.8607807159, 0.2999479771, 1.2553807497, 0.8701540232, 0.3032141924, +1.2690509558, 0.8796293736, 0.3065159321, 1.2828700542, 0.8892079592, 0.3098536730, +1.2968395948, 0.8988907337, 0.3132277727, 1.3109612465, 0.9086790085, 0.3166385889, +1.3252366781, 0.9185738564, 0.3200865984, 1.3396675587, 0.9285764694, 0.3235721588, +1.3542555571, 0.9386880398, 0.3270956278, 1.3690024614, 0.9489096403, 0.3306573629, +1.3839099407, 0.9592425823, 0.3342580795, 1.3989796638, 0.9696880579, 0.3378978968, +1.4142135382, 0.9802472591, 0.3415772915, 1.4296133518, 0.9909214973, 0.3452968597, +1.4451807737, 1.0017119646, 0.3490569592, 1.4609178305, 1.0126198530, 0.3528578281, +1.4768261909, 1.0236465931, 0.3567003012, 1.4929077625, 1.0347933769, 0.3605844975, +1.5091644526, 1.0460615158, 0.3645110130, 1.5255981684, 1.0574523211, 0.3684802055, +1.5422108173, 1.0689672232, 0.3724926710, 1.5590044260, 1.0806075335, 0.3765488863, +1.5759809017, 1.0923745632, 0.3806492090, 1.5931421518, 1.1042697430, 0.3847942352, +1.6104903221, 1.1162945032, 0.3889844418, 1.6280274391, 1.1284501553, 0.3932201862, +1.6457555294, 1.1407381296, 0.3975020647, 1.6636766195, 1.1531599760, 0.4018305540, +1.6817928553, 1.1657171249, 0.4062062502, 1.7001063824, 1.1784108877, 0.4106295109, +1.7186193466, 1.1912429333, 0.4151009321, 1.7373338938, 1.2042146921, 0.4196211100, +1.7562521696, 1.2173278332, 0.4241905212, 1.7753765583, 1.2305836678, 0.4288096428, +1.7947090864, 1.2439837456, 0.4334790707, 1.8142521381, 1.2575298548, 0.4381992817, +1.8340080976, 1.2712235451, 0.4429709911, 1.8539791107, 1.2850662470, 0.4477946758, +1.8741676807, 1.2990596294, 0.4526708126, 1.8945759535, 1.3132054806, 0.4576001167, +1.9152065516, 1.3275053501, 0.4625829458, 1.9360618591, 1.3419609070, 0.4676202536, +1.9571441412, 1.3565739393, 0.4727122784, 1.9784560204, 1.3713461161, 0.4778597355 }; + + +float recip_coeffs_fp32[3*128] = // C0, C1, C2 +{ 1.0000000000, -0.9999661446, 0.9883909225, 0.9922480583, -0.9845234156, 0.9656698704, +0.9846153259, -0.9694355726, 0.9436399937, 0.9770991802, -0.9546920061, 0.9222751856, +0.9696969986, -0.9402822256, 0.9015504122, 0.9624060392, -0.9261962175, 0.8814419508, +0.9552239180, -0.9124244452, 0.8619271517, 0.9481481314, -0.8989574909, 0.8429841995, +0.9411764145, -0.8857865334, 0.8245922327, 0.9343065023, -0.8729028702, 0.8067314625, +0.9275362492, -0.8602983952, 0.7893828154, 0.9208632708, -0.8479648829, 0.7725280523, +0.9142856598, -0.8358947039, 0.7561497688, 0.9078013897, -0.8240803480, 0.7402311563, +0.9014084339, -0.8125147820, 0.7247563601, 0.8951048851, -0.8011909723, 0.7097097635, +0.8888888359, -0.7901022434, 0.6950769424, 0.8827586174, -0.7792421579, 0.6808435917, +0.8767123222, -0.7686043978, 0.6669962406, 0.8707482815, -0.7581831217, 0.6535217762, +0.8648648262, -0.7479722500, 0.6404079199, 0.8590604067, -0.7379662991, 0.6276426315, +0.8533333540, -0.7281597853, 0.6152142286, 0.8476821184, -0.7185474634, 0.6031119823, +0.8421052694, -0.7091242075, 0.5913249254, 0.8366012573, -0.6998851299, 0.5798431635, +0.8311687708, -0.6908254623, 0.5686566830, 0.8258064985, -0.6819405556, 0.5577560663, +0.8205127716, -0.6732258797, 0.5471323729, 0.8152866364, -0.6646772623, 0.5367767811, +0.8101265430, -0.6562904119, 0.5266808271, 0.8050314188, -0.6480613947, 0.5168365240, +0.7999999523, -0.6399860382, 0.5072360039, 0.7950310707, -0.6320607662, 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0.1287354231, +0.5039370060, -0.2539503574, 0.1272238493, 0.5019607544, -0.2519624233, 0.1257358789 }; + + +// rqsrt FP32 (m=7, even and odd exp) +// rqsrt FP32 (m=7, even and odd exp) +// rsqrt_default_coeffs_m7_12 followed by rsqrt_default_coeffs_m7_24 +float rsqrt_coeffs_fp32[3 * 256] = // C0, C1, C2 +{ 1.0000000000, -0.4999893904, 0.3713679314, 0.9961165190, -0.4941869974, 0.3642400503, +0.9922778606, -0.4884959459, 0.3573021889, 0.9884833097, -0.4829133749, 0.3505480289, +0.9847319126, -0.4774363041, 0.3439712524, 0.9810229540, -0.4720618725, 0.3375658989, +0.9773555994, -0.4667876959, 0.3313263655, 0.9737290144, -0.4616109133, 0.3252470493, +0.9701424837, -0.4565290213, 0.3193227053, 0.9665952921, -0.4515398741, 0.3135484457, +0.9630868435, -0.4466408491, 0.3079192638, 0.9596161842, -0.4418296814, 0.3024306297, +0.9561828375, -0.4371044636, 0.2970778942, 0.9527860880, -0.4324626923, 0.2918570042, +0.9494253397, -0.4279025793, 0.2867635489, 0.9460998774, -0.4234220982, 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0.0218588114, +0.5656853914, -0.0905089378, 0.0215872526, 0.5642764568, -0.0898343325, 0.0213204622, +0.5628780127, -0.0891680717, 0.0210582018, 0.5614899397, -0.0885100365, 0.0208004713, +0.5601119995, -0.0878599882, 0.0205470324, 0.5587441921, -0.0872179270, 0.0202980042, +0.5573863983, -0.0865836143, 0.0200531483, 0.5560383797, -0.0859569311, 0.0198124647, +0.5547001362, -0.0853377581, 0.0195757151, 0.5533715487, -0.0847260952, 0.0193430185, +0.5520524979, -0.0841215849, 0.0191140175, 0.5507427454, -0.0835243464, 0.0188889503, +0.5494422913, -0.0829340219, 0.0186674595, 0.5481510162, -0.0823507309, 0.0184496641, +0.5468686819, -0.0817741156, 0.0182354450, 0.5455955267, -0.0812042952, 0.0180245638, +0.5443310738, -0.0806410313, 0.0178171396, 0.5430754423, -0.0800842047, 0.0176130533, +0.5418283939, -0.0795338154, 0.0174121857, 0.5405899286, -0.0789897442, 0.0172146559, +0.5393599272, -0.0784517527, 0.0170201063, 0.5381382704, -0.0779199600, 0.0168286562, +0.5369248390, -0.0773940086, 0.0166401863, 0.5357196331, -0.0768740177, 0.0164546967, +0.5345225334, -0.0763598680, 0.0162720680, 0.5333333015, -0.0758513212, 0.0160923004, +0.5321520567, -0.0753484964, 0.0159152746, 0.5309786797, -0.0748511553, 0.0157408714, +0.5298129320, -0.0743591785, 0.0155692101, 0.5286549330, -0.0738726854, 0.0154001713, +0.5275043249, -0.0733914375, 0.0152337551, 0.5263613462, -0.0729154348, 0.0150697231, +0.5252257586, -0.0724444389, 0.0149081945, 0.5240974426, -0.0719785690, 0.0147490501, +0.5229763985, -0.0715177059, 0.0145924091, 0.5218625069, -0.0710617304, 0.0144379139, +0.5207556486, -0.0706105232, 0.0142858028, 0.5196558237, -0.0701640844, 0.0141359568, +0.5185630322, -0.0697222948, 0.0139882565, 0.5174770355, -0.0692851543, 0.0138427019, +0.5163978338, -0.0688526630, 0.0136991739, 0.5153253078, -0.0684245825, 0.0135577917, +0.5142594576, -0.0680007935, 0.0134184361, 0.5132002831, -0.0675815344, 0.0132811069, +0.5121475458, -0.0671664476, 0.0131458044, 0.5111012459, -0.0667556524, 0.0130122900, +0.5100613832, -0.0663490295, 0.0128806829, 0.5090278387, -0.0659465790, 0.0127509832, +0.5080004930, -0.0655480623, 0.0126230717, 0.5069793463, -0.0651535988, 0.0124970675, +0.5059643984, -0.0647630692, 0.0123726130, 0.5049555302, -0.0643764734, 0.0122500658, +0.5039526224, -0.0639935732, 0.0121290684, 0.5029556751, -0.0636146069, 0.0120098591, +0.5019646883, -0.0632393360, 0.0118921995, 0.5009794235, -0.0628676414, 0.0117762089 }; + + +// SQRT FP32 +// sqrt_default_coeffs_m6_12 followed by sqrt_default_coeffs_m6_24 +float sqrt_coeffs_fp32[3*128] = // C0, C1, C2 +{ 1.0000000000, 0.4999915361, -0.1235522032, 1.0077822208, 0.4961308241, -0.1207334995, +1.0155048370, 0.4923580885, -0.1180204153, 1.0231691599, 0.4886702299, -0.1154073477, +1.0307763815, 0.4850640297, -0.1128894091, 1.0383279324, 0.4815363884, -0.1104617119, +1.0458250046, 0.4780846834, -0.1081197262, 1.0532686710, 0.4747061729, -0.1058593988, +1.0606601238, 0.4713982344, -0.1036766768, 1.0680004358, 0.4681584835, -0.1015679836, +1.0752906799, 0.4649846554, -0.0995298624, 1.0825318098, 0.4618744850, -0.0975589752, +1.0897247791, 0.4588259459, -0.0956522226, 1.0968705416, 0.4558370113, -0.0938068628, +1.1039701700, 0.4529056549, -0.0920200348, 1.1110242605, 0.4500302076, -0.0902892351, +1.1180340052, 0.4472087622, -0.0886120796, 1.1250000000, 0.4444397688, -0.0869860649, +1.1319231987, 0.4417215586, -0.0854092836, 1.1388041973, 0.4390525818, -0.0838795900, +1.1456439495, 0.4364315271, -0.0823949575, 1.1524430513, 0.4338567257, -0.0809537172, +1.1592023373, 0.4313269854, -0.0795538425, 1.1659224033, 0.4288411140, -0.0781940222, +1.1726039648, 0.4263975620, -0.0768723488, 1.1792476177, 0.4239953756, -0.0755876303, +1.1858540773, 0.4216333628, -0.0743381977, 1.1924240589, 0.4193104506, -0.0731228590, +1.1989579201, 0.4170254469, -0.0719403028, 1.2054563761, 0.4147773981, -0.0707892179, +1.2119200230, 0.4125652313, -0.0696685314, 1.2183493376, 0.4103882313, -0.0685771704, +1.2247449160, 0.4082452059, -0.0675139427, 1.2311072350, 0.4061354399, -0.0664778948, +1.2374368906, 0.4040580988, -0.0654681921, 1.2437342405, 0.4020122290, -0.0644836426, +1.2500000000, 0.3999972343, -0.0635236502, 1.2562344074, 0.3980121613, -0.0625871420, +1.2624381781, 0.3960564137, -0.0616734028, 1.2686114311, 0.3941291571, -0.0607818365, +1.2747548819, 0.3922297955, -0.0599113703, 1.2808688879, 0.3903576136, -0.0590615273, +1.2869538069, 0.3885118961, -0.0582317114, 1.2930101156, 0.3866922855, -0.0574209690, +1.2990380526, 0.3848978281, -0.0566290617, 1.3050383329, 0.3831282854, -0.0558550358, +1.3110110760, 0.3813828230, -0.0550985336, 1.3169567585, 0.3796610832, -0.0543589592, +1.3228756189, 0.3779623508, -0.0536357164, 1.3287682533, 0.3762862682, -0.0529284477, +1.3346347809, 0.3746323586, -0.0522365570, 1.3404756784, 0.3729999065, -0.0515596867, +1.3462911844, 0.3713887930, -0.0508972406, 1.3520817757, 0.3697983027, -0.0502488613, +1.3578475714, 0.3682279587, -0.0496141911, 1.3635890484, 0.3666776419, -0.0489926338, +1.3693064451, 0.3651466370, -0.0483840704, 1.3750000000, 0.3636345863, -0.0477879047, +1.3806700706, 0.3621412516, -0.0472040176, 1.3863170147, 0.3606661558, -0.0466318130, +1.3919410706, 0.3592089415, -0.0460710526, 1.3975424767, 0.3577692509, -0.0455214977, +1.4031214714, 0.3563467264, -0.0449827909, 1.4086784124, 0.3549410105, -0.0444546938, +1.4142135382, 0.3535474539, -0.0436823368, 1.4252192974, 0.3508174419, -0.0426857471, +1.4361406565, 0.3481497765, -0.0417264700, 1.4469796419, 0.3455420732, -0.0408027172, +1.4577380419, 0.3429920673, -0.0399124622, 1.4684175253, 0.3404976130, -0.0390540361, +1.4790199995, 0.3380569220, -0.0382261276, 1.4895468950, 0.3356679678, -0.0374269485, +1.5000000000, 0.3333288431, -0.0366551876, 1.5103807449, 0.3310379982, -0.0359096527, +1.5206906796, 0.3287937641, -0.0351891518, 1.5309311152, 0.3265945911, -0.0344922543, +1.5411034822, 0.3244389296, -0.0338181257, 1.5512092113, 0.3223254681, -0.0331656933, +1.5612494946, 0.3202526569, -0.0325340033, 1.5712256432, 0.3182194233, -0.0319221020, +1.5811388493, 0.3162243366, -0.0313290358, 1.5909903049, 0.3142663240, -0.0307542086, +1.6007810831, 0.3123443127, -0.0301967859, 1.6105123758, 0.3104571104, -0.0296559334, +1.6201851368, 0.3086036444, -0.0291310549, 1.6298005581, 0.3067830801, -0.0286214352, +1.6393595934, 0.3049942255, -0.0281265974, 1.6488631964, 0.3032364845, -0.0276457071, +1.6583124399, 0.3015086651, -0.0271785259, 1.6677080393, 0.2998100519, -0.0267242193, +1.6770509481, 0.2981398106, -0.0262825489, 1.6863422394, 0.2964972258, -0.0258527994, +1.6955825090, 0.2948814631, -0.0254347324, 1.7047727108, 0.2932919264, -0.0250277519, +1.7139136791, 0.2917276621, -0.0246316195, 1.7230061293, 0.2901883125, -0.0242457390, +1.7320507765, 0.2886729240, -0.0238697529, 1.7410485744, 0.2871811390, -0.0235035419, +1.7500000000, 0.2857122421, -0.0231465101, 1.7589058876, 0.2842656374, -0.0227984190, +1.7677669525, 0.2828407288, -0.0224590302, 1.7765837908, 0.2814370394, -0.0221278667, +1.7853571177, 0.2800540924, -0.0218048096, 1.7940875292, 0.2786914110, -0.0214896202, +1.8027756214, 0.2773482800, -0.0211818218, 1.8114221096, 0.2760244608, -0.0208814144, +1.8200274706, 0.2747194767, -0.0205880404, 1.8285923004, 0.2734327316, -0.0203013420, +1.8371173143, 0.2721638680, -0.0200213194, 1.8456028700, 0.2709126472, -0.0197477341, +1.8540496826, 0.2696783543, -0.0194802284, 1.8624581099, 0.2684608698, -0.0192188025, +1.8708287477, 0.2672597170, -0.0189630985, 1.8791620731, 0.2660745382, -0.0187129974, +1.8874585629, 0.2649050951, -0.0184683800, 1.8957188129, 0.2637507915, -0.0182291269, +1.9039433002, 0.2626115084, -0.0179948807, 1.9121322632, 0.2614868879, -0.0177656412, +1.9202864170, 0.2603765726, -0.0175412893, 1.9284061193, 0.2592802048, -0.0173214674, +1.9364917278, 0.2581976652, -0.0171062946, 1.9445436001, 0.2571284771, -0.0168956518, +1.9525624514, 0.2560725212, -0.0166891813, 1.9605484009, 0.2550295591, -0.0164868832, +1.9685019255, 0.2539991140, -0.0162886381, 1.9764235020, 0.2529810667, -0.0160943270, +1.9843134880, 0.2519751787, -0.0159038305, 1.9921722412, 0.2509812117, -0.0157171488 }; + +// Tanh FP32 +// tanhx_default_coeffs2_01 (tanh(x)/x on [0, 1]) then +// tanh_default_coeffs2_12 then +// tanh_default_coeffs2_24 then +// tanh_default_coeffs2_48 + +float tanh_coeffs_fp32[3*256] = //C0, C1, C2 +{ 1.0000000000, -0.0000004768, -0.3332743645, 0.9999185801, -0.0104162693, -0.3328828812, +0.9996745586, -0.0208197832, -0.3321070671, 0.9992681742, -0.0311989784, -0.3309412003, +0.9986999035, -0.0415418148, -0.3293853998, 0.9979704618, -0.0518360138, -0.3274627924, +0.9970805645, -0.0620701313, -0.3251537085, 0.9960314035, -0.0722321272, -0.3224887848, +0.9948240519, -0.0823107958, -0.3194595575, 0.9934599400, -0.0922948122, -0.3160820007, +0.9919407368, -0.1021732092, -0.3123673201, 0.9902679920, -0.1119354963, -0.3083165884, +0.9884437323, -0.1215711832, -0.3039528131, 0.9864699841, -0.1310704947, -0.2992765903, +0.9843490124, -0.1404236555, -0.2943137884, 0.9820830822, -0.1496216059, -0.2890707254, +0.9796746969, -0.1586556435, -0.2835583687, 0.9771264791, -0.1675174236, -0.2777937651, +0.9744411707, -0.1761990786, -0.2717927694, 0.9716217518, -0.1846932173, -0.2655715942, +0.9686712027, -0.1929929256, -0.2591465712, 0.9655923843, -0.2010917664, -0.2525355816, +0.9623887539, -0.2089838982, -0.2457501888, 0.9590634108, -0.2166639566, -0.2388041019, +0.9556196928, -0.2241269350, -0.2317200899, 0.9520611763, -0.2313685417, -0.2245080471, +0.9483913183, -0.2383847237, -0.2171947956, 0.9446135759, -0.2451722622, -0.2097854614, +0.9407315254, -0.2517281771, -0.2023022175, 0.9367489815, -0.2580502033, -0.1947520971, +0.9326694012, -0.2641363144, -0.1871581078, 0.9284965992, -0.2699850798, -0.1795344353, +0.9242343307, -0.2755955458, -0.1718945503, 0.9198862314, -0.2809672356, -0.1642494202, +0.9154560566, -0.2861000299, -0.1566145420, 0.9109475613, -0.2909941673, -0.1490094662, +0.9063644409, -0.2956506014, -0.1414327621, 0.9017103910, -0.3000702858, -0.1339080334, +0.8969891071, -0.3042547703, -0.1264433861, 0.8922042847, -0.3082059622, -0.1190465689, +0.8873596191, -0.3119260073, -0.1117306948, 0.8824584484, -0.3154174089, -0.1045058966, +0.8775045872, -0.3186830282, -0.0973776579, 0.8725014925, -0.3217258453, -0.0903611183, +0.8674525023, -0.3245493174, -0.0834573507, 0.8623610735, -0.3271570206, -0.0766738653, +0.8572305441, -0.3295527697, -0.0700170994, 0.8520642519, -0.3317404985, -0.0634979010, +0.8468652964, -0.3337244987, -0.0571156740, 0.8416368961, -0.3355090618, -0.0508797169, +0.8363821507, -0.3370987177, -0.0447931290, 0.8311041594, -0.3384981155, -0.0388590097, +0.8258056641, -0.3397120237, -0.0330797434, 0.8204896450, -0.3407453299, -0.0274559259, +0.8151587248, -0.3416029215, -0.0219926834, 0.8098158836, -0.3422898054, -0.0166913271, +0.8044635057, -0.3428109884, -0.0115562677, 0.7991043329, -0.3431717157, -0.0065784454, +0.7937407494, -0.3433768749, -0.0017732382, 0.7883750200, -0.3434318304, 0.0028746128, +0.7830096483, -0.3433415890, 0.0073572397, 0.7776467800, -0.3431112766, 0.0116755962, +0.7722884417, -0.3427460194, 0.0158325434, 0.7669370174, -0.3422508240, 0.0198251009, +0.7615941763, 0.4199600220, -0.3174098730, 0.7680785656, 0.4100407362, -0.3124781847, +0.7744091749, 0.4002757072, -0.3074805737, 0.7805885077, 0.3906668425, -0.3024270535, +0.7866188288, 0.3812158108, -0.2973269224, 0.7925027609, 0.3719242811, -0.2921890020, +0.7982428074, 0.3627933264, -0.2870219946, 0.8038413525, 0.3538239002, -0.2818338871, +0.8093011379, 0.3450164795, -0.2766324282, 0.8146244287, 0.3363717794, -0.2714250088, +0.8198139668, 0.3278896809, -0.2662185431, 0.8248723745, 0.3195704222, -0.2610194683, +0.8298019171, 0.3114136457, -0.2558339834, 0.8346053362, 0.3034188747, -0.2506679296, +0.8392850161, 0.2955855131, -0.2455266714, 0.8438436985, 0.2879129648, -0.2404153347, +0.8482836485, 0.2804000378, -0.2353385687, 0.8526074886, 0.2730457783, -0.2303007841, +0.8568176031, 0.2658489943, -0.2253060341, 0.8609164953, 0.2588083744, -0.2203582525, +0.8649066687, 0.2519222498, -0.2154606581, 0.8687903881, 0.2451891899, -0.2106165886, +0.8725700378, 0.2386076450, -0.2058289051, 0.8762480021, 0.2321755886, -0.2011002302, +0.8798266649, 0.2258913517, -0.1964330673, 0.8833082914, 0.2197530270, -0.1918294430, +0.8866951466, 0.2137584686, -0.1872912645, 0.8899893761, 0.2079057693, -0.1828203201, +0.8931933641, 0.2021929026, -0.1784180403, 0.8963090181, 0.1966174841, -0.1740858555, +0.8993387222, 0.1911774874, -0.1698246002, 0.9022845030, 0.1858706474, -0.1656354666, +0.9051482677, 0.1806946993, -0.1615191698, 0.9079321623, 0.1756473780, -0.1574761868, +0.9106382132, 0.1707264185, -0.1535071135, 0.9132684469, 0.1659295559, -0.1496123075, +0.9158245325, 0.1612542868, -0.1457917690, 0.9183086157, 0.1566984653, -0.1420457363, +0.9207223654, 0.1522597075, -0.1383742094, 0.9230675697, 0.1479357481, -0.1347768307, +0.9253462553, 0.1437240839, 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0.9999989913148257,2.0145825227562218e-6,-1.895930736181713e-6,0.9999991098384055,1.777863052450431e-6,-1.673153527367253e-6, + 0.9999992144351088,1.5689587917693268e-6,-1.4765529113243865e-6,0.9999993067413848,1.3846014117657902e-6,-1.303053803748557e-6, + 0.9999993882013944,1.2219065568968099e-6,-1.1499411334942588e-6,0.9999994600896062,1.078328819401828e-6,-1.014819437969358e-6, + 0.9999995235307347,9.51621904310801e-7,-8.955751519535445e-7,0.9999995795173374,8.398034281777209e-7,-7.903423751222791e-7, + 0.9999996289253434,7.411239685877437e-7,-6.974748590604199e-7,0.9999996725277578,6.54039626303923e-7,-6.155193101058801e-7, + 0.9999997110067551,5.771879673570432e-7,-5.431939513292875e-7,0.9999997449643522,5.09366613829617e-7,-4.793670641129786e-7} + ; + +// ========== GL sin and cos poly2 approximations (m = 6) =================== +// sinx_default_coeffs2_01 (sin(x)/x on [0, 1]) followed by +// cos_default_coeffs2_01 + +float sincos_coeffs_fp32[3 * 128] = // C0, C1, C2 +{ 1.0000000000, 0.0000000000, -0.1666648388, 0.9999593496, -0.0052082539, -0.1666419506, +0.9998372793, -0.0104157925, -0.1665916443, 0.9996337891, -0.0156217813, -0.1665184498, +0.9993491173, -0.0208255053, -0.1664193869, 0.9989830256, -0.0260261297, -0.1662989855, +0.9985357523, -0.0312230587, -0.1661468744, 0.9980074167, -0.0364152193, -0.1659829617, +0.9973978996, -0.0416022539, -0.1657814980, 0.9967073202, -0.0467830896, -0.1655626297, +0.9959359169, -0.0519570112, -0.1653236151, 0.9950838089, -0.0571234226, -0.1650542021, +0.9941508770, -0.0622814894, -0.1647593975, 0.9931375980, -0.0674303770, -0.1644445658, +0.9920438528, -0.0725693703, -0.1641073227, 0.9908698797, -0.0776977539, -0.1637454033, +0.9896157980, -0.0828148127, -0.1633566618, 0.9882819653, -0.0879197121, -0.1629469395, +0.9868685007, -0.0930118561, -0.1625065804, 0.9853755236, -0.0980902910, -0.1620492935, +0.9838032722, -0.1031544209, -0.1615658998, 0.9821519852, -0.1082034111, -0.1610625982, +0.9804220200, -0.1132366657, -0.1605306864, 0.9786134958, -0.1182533503, -0.1599767208, +0.9767267704, -0.1232527494, -0.1593998671, 0.9747619629, -0.1282341480, -0.1587996483, +0.9727195501, -0.1331967115, -0.1581830978, 0.9705997705, -0.1381399632, -0.1575347185, +0.9684028625, -0.1430629492, -0.1568700075, 0.9661291838, -0.1479651928, -0.1561738253, +0.9637790918, -0.1528457403, -0.1554619074, 0.9613529444, -0.1577039957, -0.1547274590, +0.9588510990, -0.1625392437, -0.1539713144, 0.9562737942, -0.1673508883, -0.1531870365, +0.9536215067, -0.1721380949, -0.1523840427, 0.9508947134, -0.1769001484, -0.1515637636, +0.9480936527, -0.1816365719, -0.1507132053, 0.9452188015, -0.1863464117, -0.1498500109, +0.9422705173, -0.1910291910, -0.1489615440, 0.9392493963, -0.1956841946, -0.1480506659, +0.9361556768, -0.2003108263, -0.1471130848, 0.9329898357, -0.2049082518, -0.1461601257, +0.9297524691, -0.2094758749, -0.1451878548, 0.9264440536, -0.2140130997, -0.1441930532, +0.9230648279, -0.2185192108, -0.1431802511, 0.9196155071, -0.2229936123, -0.1421468258, +0.9160965681, -0.2274357080, -0.1410903931, 0.9125084877, -0.2318447828, -0.1400165558, +0.9088516235, -0.2362203598, -0.1389162540, 0.9051268101, -0.2405616045, -0.1378034353, +0.9013344049, -0.2448680401, -0.1366695166, 0.8974750042, -0.2491390705, -0.1355142593, +0.8935490847, -0.2533739805, -0.1343450546, 0.8895573616, -0.2575722933, -0.1331547499, +0.8855003119, -0.2617334127, -0.1319440603, 0.8813785315, -0.2658567429, -0.1307140589, +0.8771926165, -0.2699416876, -0.1294665337, 0.8729431629, -0.2739876509, -0.1282032728, +0.8686307669, -0.2779940367, -0.1269270182, 0.8642561436, -0.2819604874, -0.1256251335, +0.8598198891, -0.2858862877, -0.1243087053, 0.8553224802, -0.2897709608, -0.1229740381, +0.8507648706, -0.2936139107, -0.1216250658, 0.8461474180, -0.2974146605, -0.1202591658, +1.0000000000, -0.0000001192, -0.4999834299, 0.9998779297, -0.0156248808, -0.4998588562, +0.9995117188, -0.0312458277, -0.4996122122, 0.9989016056, -0.0468590260, -0.4992513657, +0.9980474710, -0.0624608994, -0.4987611771, 0.9969497919, -0.0780475140, -0.4981498718, +0.9956086874, -0.0936150551, -0.4974181652, 0.9940245152, -0.1091597080, -0.4965672493, +0.9921976328, -0.1246777773, -0.4955908060, 0.9901286364, -0.1401653290, -0.4944984913, +0.9878177643, -0.1556186676, -0.4932849407, 0.9852658510, -0.1710340977, -0.4919457436, +0.9824733734, -0.1864076853, -0.4904919863, 0.9794409275, -0.2017358541, -0.4889127016, +0.9761694670, -0.2170146704, -0.4872205257, 0.9726597071, -0.2322405577, -0.4854061604, +0.9689124823, -0.2474098206, -0.4834684134, 0.9649286270, -0.2625185251, -0.4814227819, +0.9607092142, -0.2775632143, -0.4792548418, 0.9562553167, -0.2925401926, -0.4769665003, +0.9515680075, -0.3074456453, -0.4745686054, 0.9466482401, -0.3222761154, -0.4720498323, +0.9414974451, -0.3370279074, -0.4694159031, 0.9361168146, -0.3516974449, -0.4666656256, +0.9305076599, -0.3662810326, -0.4638071060, 0.9246712923, -0.3807752132, -0.4608343840, +0.9186091423, -0.3951765299, -0.4577429295, 0.9123227596, -0.4094812870, -0.4545449018, +0.9058136940, -0.4236861467, -0.4512314796, 0.8990834951, -0.4377874136, -0.4478178024, +0.8921337128, -0.4517819881, -0.4442828894, 0.8849661350, -0.4656661749, -0.4406453371, +0.8775825500, -0.4794366360, -0.4369027615, 0.8699847460, -0.4930901527, -0.4330469370, +0.8621745110, -0.5066231489, -0.4290943146, 0.8541537523, -0.5200325251, -0.4250327349, +0.8459244967, -0.5333150625, -0.4208598137, 0.8374887705, -0.5464671850, -0.4165978432, +0.8288484812, -0.5594860315, -0.4122253656, 0.8200058937, -0.5723682642, -0.4077538252, +0.8109631538, -0.5851107836, -0.4031811953, 0.8017224073, -0.5977104902, -0.3985080719, +0.7922859192, -0.6101641655, -0.3937445879, 0.7826559544, -0.6224689484, -0.3888804913, +0.7728350163, -0.6346217394, -0.3839230537, 0.7628252506, -0.6466195583, -0.3788743019, +0.7526293993, -0.6584595442, -0.3737312555, 0.7422497272, -0.6701388359, -0.3684930801, +0.7316888571, -0.6816544533, -0.3631694317, 0.7209494114, -0.6930036545, -0.3577570915, +0.7100338936, -0.7041836977, -0.3522555828, 0.6989450455, -0.7151918411, -0.3466669321, +0.6876856089, -0.7260253429, -0.3409961462, 0.6762582064, -0.7366816998, -0.3352354765, +0.6646656990, -0.7471580505, -0.3294029236, 0.6529110670, -0.7574521303, -0.3234812021, +0.6409969330, -0.7675611973, -0.3174864054, 0.6289262772, -0.7774828672, -0.3114144802, +0.6167020798, -0.7872147560, -0.3052647114, 0.6043273211, -0.7967544794, -0.2990390062, +0.5918051004, -0.8060996532, -0.2927424908, 0.5791383982, -0.8152480125, -0.2863755226, +0.5663301945, -0.8241974115, -0.2799340487, 0.5533838272, -0.8329455853, -0.2734248638 }; + + + + +////// BF16 ////// + + // ========== bf16 log2 linear approximation on [1, 2] =================== + +uint16_t log2_bf16_linear_coeffs_m3[2*2*(1 << m3_val)] = // C2, C1, C0 +{ +//zero +16313, 48938, +16302, 48914, +16293, 48896, +16285, 48868, +16278, 48840, +16271, 48820, +16266, 48804, +16261, 48788, +//non zero + 0, 16302, +15920, 16284, +16036, 16269, +16108, 16257, +16150, 16236, +16180, 16218, +16206, 16204, +16232, 16190 +}; + +uint16_t log2_bf16_linear_coeffs_m4[2*2*(1 << m4_val)] = // C2, C1, C0 +{ +//zero +16313, 48946, +16307, 48932, +16302, 48920, +16297, 48910, +16293, 48900, +16289, 48888, +16285, 48872, +16281, 48860, +16278, 48848, +16275, 48836, +16271, 48824, +16269, 48816, +16266, 48808, +16263, 48800, +16261, 48792, +16258, 48784, +//non zero + 0, 16307, +15792, 16297, +15920, 16288, +16000, 16280, +16036, 16272, +16072, 16265, +16108, 16259, +16134, 16252, +16150, 16242, +16164, 16232, +16180, 16224, +16194, 16214, +16206, 16208, +16220, 16200, +16232, 16194, +16244, 16188 +}; + +uint16_t log2_bf16_linear_coeffs_interleaved_m5[2*4*(1 << m5_val)] = // C2, C1, C0 +{ + //non zero //zero //0.75-1 + 0, 16310, 16313, 48948, 00000, 00000, 00000, 00000, + 15680, 16304, 16310, 48942, 00000, 00000, 00000, 00000, + 15792, 16299, 16307, 48936, 00000, 00000, 00000, 00000, + 15880, 16294, 16305, 48928, 00000, 00000, 00000, 00000, + 15920, 16290, 16302, 48922, 00000, 00000, 00000, 00000, + 15960, 16286, 16300, 48918, 00000, 00000, 00000, 00000, + 16000, 16281, 16297, 48912, 00000, 00000, 00000, 00000, + 16020, 16278, 16295, 48908, 00000, 00000, 00000, 00000, + 16036, 16274, 16293, 48902, 00000, 00000, 00000, 00000, + 16056, 16270, 16291, 48898, 00000, 00000, 00000, 00000, + 16072, 16267, 16289, 48892, 00000, 00000, 00000, 00000, + 16092, 16264, 16287, 48884, 00000, 00000, 00000, 00000, + 16108, 16261, 16285, 48876, 00000, 00000, 00000, 00000, + 16124, 16258, 16283, 48868, 00000, 00000, 00000, 00000, + 16134, 16254, 16281, 48864, 00000, 00000, 00000, 00000, + 16142, 16248, 16279, 48856, 00000, 00000, 00000, 00000, + 16150, 16244, 16278, 48852, 16340, 49029, 00000, 00000, + 16158, 16238, 16276, 48844, 16338, 49026, 00000, 00000, + 16164, 16234, 16275, 48840, 16336, 49020, 00000, 00000, + 16172, 16230, 16273, 48832, 16334, 49014, 00000, 00000, + 16180, 16226, 16271, 48828, 16332, 49008, 00000, 00000, + 16186, 16220, 16270, 48824, 16331, 49002, 00000, 00000, + 16194, 16216, 16269, 48820, 16329, 48996, 00000, 00000, + 16200, 16212, 16267, 48816, 16327, 48992, 00000, 00000, + 16206, 16210, 16266, 48808, 16325, 48986, 00000, 00000, + 16214, 16206, 16264, 48804, 16324, 48980, 00000, 00000, + 16220, 16202, 16263, 48800, 16322, 48976, 00000, 00000, + 16226, 16198, 16262, 48800, 16320, 48972, 00000, 00000, + 16232, 16196, 16261, 48796, 16319, 48968, 00000, 00000, + 16238, 16192, 16259, 48792, 16317, 48962, 00000, 00000, + 16244, 16190, 16258, 48788, 16316, 48958, 00000, 00000, + 16250, 16186, 16257, 48784, 16314, 48954, 00000, 00000 +}; + +uint16_t log2_bf16_linear_coeffs_m5[2*2*(1 << m5_val)] = // C2, C1, C0 +{ +//zero +16313, 48948, +16310, 48942, +16307, 48936, +16305, 48928, +16302, 48922, +16300, 48918, +16297, 48912, +16295, 48908, +16293, 48902, +16291, 48898, +16289, 48892, +16287, 48884, +16285, 48876, +16283, 48868, +16281, 48864, +16279, 48856, +16278, 48852, +16276, 48844, +16275, 48840, +16273, 48832, +16271, 48828, +16270, 48824, +16269, 48820, +16267, 48816, +16266, 48808, +16264, 48804, +16263, 48800, +16262, 48800, +16261, 48796, +16259, 48792, +16258, 48788, +16257, 48784, +//non zero + 0, 16310, +15680, 16304, +15792, 16299, +15880, 16294, +15920, 16290, +15960, 16286, +16000, 16281, +16020, 16278, +16036, 16274, +16056, 16270, +16072, 16267, +16092, 16264, +16108, 16261, +16124, 16258, +16134, 16254, +16142, 16248, +16150, 16244, +16158, 16238, +16164, 16234, +16172, 16230, +16180, 16226, +16186, 16220, +16194, 16216, +16200, 16212, +16206, 16210, +16214, 16206, +16220, 16202, +16226, 16198, +16232, 16196, +16238, 16192, +16244, 16190, +16250, 16186 +}; +uint16_t log2_bf16_linear_gaudi2_coeffs_m5[3*2*(1 << m5_val)] = // C2, C1, C0 +{ + //non zero + 0, 16310, + 15680, 16304, + 15792, 16299, + 15880, 16294, + 15920, 16290, + 15960, 16286, + 16000, 16281, + 16020, 16278, + 16036, 16274, + 16056, 16270, + 16072, 16267, + 16092, 16264, + 16108, 16261, + 16124, 16258, + 16134, 16254, + 16142, 16248, + 16150, 16244, + 16158, 16238, + 16164, 16234, + 16172, 16230, + 16180, 16226, + 16186, 16220, + 16194, 16216, + 16200, 16212, + 16206, 16210, + 16214, 16206, + 16220, 16202, + 16226, 16198, + 16232, 16196, + 16238, 16192, + 16244, 16190, + 16250, 16186, +//zero +16313, 48948, +16310, 48942, +16307, 48936, +16305, 48928, +16302, 48922, +16300, 48918, +16297, 48912, +16295, 48908, +16293, 48902, +16291, 48898, +16289, 48892, +16287, 48884, +16285, 48876, +16283, 48868, +16281, 48864, +16279, 48856, +16278, 48852, +16276, 48844, +16275, 48840, +16273, 48832, +16271, 48828, +16270, 48824, +16269, 48820, +16267, 48816, +16266, 48808, +16264, 48804, +16263, 48800, +16262, 48800, +16261, 48796, +16259, 48792, +16258, 48788, +16257, 48784, +//0.75-1 +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +16340, 49029, +16338, 49026, +16336, 49020, +16334, 49014, +16332, 49008, +16331, 49002, +16329, 48996, +16327, 48992, +16325, 48986, +16324, 48980, +16322, 48976, +16320, 48972, +16319, 48968, +16317, 48962, +16316, 48958, +16314, 48954 +}; + +uint16_t log2_bf16_linear_coeffs_m6[2*2*(1 << m6_val)] = // C2, C1, C0 +{ +//zero +16313, 48950, +16311, 48948, +16310, 48944, +16308, 48940, +16307, 48936, +16306, 48934, +16305, 48930, +16303, 48928, +16302, 48924, +16301, 48922, +16300, 48918, +16298, 48916, +16297, 48914, +16296, 48910, +16295, 48908, +16294, 48906, +16293, 48904, +16292, 48902, +16291, 48900, +16290, 48898, +16289, 48892, +16288, 48888, +16287, 48884, +16286, 48884, +16285, 48880, +16284, 48876, +16283, 48872, +16282, 48868, +16281, 48864, +16280, 48860, +16279, 48856, +16279, 48856, +16278, 48852, +16277, 48848, +16276, 48844, +16275, 48844, +16275, 48840, +16274, 48836, +16273, 48836, +16272, 48832, +16271, 48828, +16271, 48828, +16270, 48824, +16269, 48824, +16269, 48820, +16268, 48816, +16267, 48816, +16266, 48812, +16266, 48812, +16265, 48808, +16264, 48808, +16264, 48804, +16263, 48804, +16263, 48800, +16262, 48800, +16261, 48796, +16261, 48796, +16260, 48792, +16259, 48792, +16259, 48792, +16258, 48788, +16258, 48788, +16257, 48784, +16257, 48784, +//non zero + 0, 16311, +15552, 16308, +15680, 16306, +15744, 16303, +15792, 16301, +15840, 16298, +15880, 16296, +15896, 16293, +15920, 16291, +15936, 16289, +15960, 16287, +15976, 16285, +16000, 16282, +16008, 16280, +16020, 16279, +16028, 16277, +16036, 16275, +16048, 16273, +16056, 16271, +16064, 16270, +16072, 16268, +16080, 16266, +16092, 16265, +16100, 16263, +16108, 16262, +16116, 16260, +16124, 16259, +16130, 16257, +16134, 16256, +16138, 16252, +16142, 16250, +16146, 16248, +16150, 16244, +16154, 16242, +16158, 16240, +16162, 16238, +16164, 16236, +16168, 16232, +16172, 16230, +16176, 16228, +16180, 16226, +16182, 16224, +16186, 16222, +16190, 16220, +16194, 16218, +16196, 16216, +16200, 16214, +16204, 16212, +16206, 16210, +16210, 16208, +16214, 16206, +16216, 16204, +16220, 16202, +16222, 16202, +16226, 16200, +16230, 16198, +16232, 16196, +16236, 16194, +16238, 16192, +16242, 16192, +16244, 16190, +16248, 16188, +16250, 16186, +16254, 16186 +}; + + // ========== bf16 log2 poly2 approximation on [1, 2] =================== + +uint16_t log2_bf16_poly2_coeffs_m3[2*3*(1 << m3_val)] = // C2, C1, C0 +{ +//zero +16313, 48952, 16088, +16302, 48926, 16040, +16293, 48904, 16004, +16285, 48880, 15960, +16278, 48852, 15920, +16271, 48832, 15896, +16266, 48812, 15872, +16261, 48796, 15840, +//non zero + 0, 16312, 48932, +15920, 16292, 48900, +16036, 16275, 48856, +16108, 16262, 48820, +16150, 16246, 48792, +16180, 16228, 48768, +16206, 16210, 48736, +16232, 16196, 48712 +}; + +uint16_t log2_bf16_poly2_coeffs_m4[2*3*(1 << m4_val)] = // C2, C1, C0 +{ +//zero +16313, 48952, 16100, +16307, 48938, 16072, +16302, 48926, 16048, +16297, 48914, 16028, +16293, 48904, 16012, +16289, 48896, 16000, +16285, 48880, 15968, +16281, 48864, 15952, +16278, 48852, 15928, +16275, 48840, 15912, +16271, 48832, 15896, +16269, 48820, 15888, +16266, 48812, 15872, +16263, 48804, 15856, +16261, 48796, 15840, +16258, 48788, 15824, +//non zero + 0, 16313, 48942, +15792, 16302, 48922, +15920, 16292, 48906, +16000, 16283, 48888, +16036, 16276, 48864, +16072, 16269, 48844, +16108, 16262, 48828, +16134, 16256, 48812, +16150, 16246, 48796, +16164, 16236, 48784, +16180, 16228, 48776, +16194, 16218, 48760, +16206, 16210, 48744, +16220, 16204, 48728, +16232, 16196, 48712, +16244, 16190, 48704 +}; + +uint16_t log2_bf16_poly2_coeffs_m5[2*3*(1 << m5_val)] = // C2, C1, C0 +{ +//zero +16313, 48952, 16108, +16310, 48946, 16096, +16307, 48938, 16080, +16305, 48932, 16068, +16302, 48926, 16056, +16300, 48920, 16044, +16297, 48914, 16036, +16295, 48910, 16024, +16293, 48904, 16016, +16291, 48900, 16008, +16289, 48896, 16000, +16287, 48888, 15992, +16285, 48880, 15976, +16283, 48872, 15968, +16281, 48864, 15952, +16279, 48860, 15944, +16278, 48852, 15936, +16276, 48848, 15928, +16275, 48840, 15920, +16273, 48836, 15912, +16271, 48832, 15904, +16270, 48824, 15896, +16269, 48820, 15888, +16267, 48816, 15888, +16266, 48812, 15880, +16264, 48808, 15872, +16263, 48804, 15872, +16262, 48800, 15856, +16261, 48796, 15840, +16259, 48792, 15840, +16258, 48788, 15824, +16257, 48784, 15824, +//non zero + 0, 16313, 48948, +15680, 16307, 48936, +15792, 16302, 48926, +15880, 16297, 48918, +15920, 16292, 48910, +15960, 16288, 48902, +16000, 16283, 48896, +16020, 16280, 48884, +16036, 16276, 48872, +16056, 16272, 48860, +16072, 16269, 48848, +16092, 16265, 48840, +16108, 16262, 48832, +16124, 16259, 48824, +16134, 16256, 48816, +16142, 16252, 48808, +16150, 16246, 48800, +16158, 16242, 48796, +16164, 16236, 48788, +16172, 16232, 48784, +16180, 16228, 48776, +16186, 16222, 48772, +16194, 16218, 48768, +16200, 16214, 48760, +16206, 16212, 48752, +16214, 16208, 48744, +16220, 16204, 48736, +16226, 16200, 48728, +16232, 16196, 48720, +16238, 16194, 48712, +16244, 16190, 48704, +16250, 16188, 48696 +}; + +uint16_t log2_bf16_poly2_coeffs_m6[2*3*(1 << m6_val)] = // C2, C1, C0 +{ +//zero +16313, 48952, 16112, +16311, 48948, 16104, +16310, 48946, 16096, +16308, 48942, 16092, +16307, 48938, 16084, +16306, 48934, 16076, +16305, 48932, 16068, +16303, 48928, 16064, +16302, 48926, 16056, +16301, 48922, 16052, +16300, 48920, 16048, +16298, 48918, 16040, +16297, 48914, 16036, +16296, 48912, 16032, +16295, 48910, 16028, +16294, 48908, 16024, +16293, 48904, 16020, +16292, 48902, 16016, +16291, 48900, 16012, +16290, 48898, 16008, +16289, 48896, 16004, +16288, 48892, 16000, +16287, 48888, 15992, +16286, 48884, 15984, +16285, 48880, 15984, +16284, 48876, 15976, +16283, 48872, 15968, +16282, 48868, 15960, +16281, 48864, 15960, +16280, 48864, 15952, +16279, 48860, 15944, +16279, 48856, 15944, +16278, 48852, 15936, +16277, 48852, 15936, +16276, 48848, 15928, +16275, 48844, 15928, +16275, 48840, 15920, +16274, 48840, 15920, +16273, 48836, 15912, +16272, 48832, 15912, +16271, 48832, 15904, +16271, 48828, 15904, +16270, 48824, 15896, +16269, 48824, 15896, +16269, 48820, 15888, +16268, 48820, 15888, +16267, 48816, 15888, +16266, 48816, 15880, +16266, 48812, 15880, +16265, 48808, 15880, +16264, 48808, 15872, +16264, 48804, 15872, +16263, 48804, 15872, +16263, 48800, 15856, +16262, 48800, 15856, +16261, 48800, 15856, +16261, 48796, 15840, +16260, 48796, 15840, +16259, 48792, 15840, +16259, 48792, 15840, +16258, 48788, 15824, +16258, 48788, 15824, +16257, 48784, 15824, +16257, 48784, 15824, +//non zero + 0, 16313, 48950, +15552, 16310, 48944, +15680, 16307, 48940, +15744, 16304, 48934, +15792, 16302, 48930, +15840, 16299, 48924, +15880, 16297, 48920, +15896, 16294, 48916, +15920, 16292, 48912, +15936, 16290, 48908, +15960, 16288, 48904, +15976, 16286, 48900, +16000, 16284, 48898, +16008, 16281, 48892, +16020, 16280, 48884, +16028, 16278, 48880, +16036, 16276, 48872, +16048, 16274, 48868, +16056, 16272, 48864, +16064, 16270, 48856, +16072, 16269, 48852, +16080, 16267, 48848, +16092, 16265, 48844, +16100, 16264, 48836, +16108, 16262, 48832, +16116, 16261, 48828, +16124, 16259, 48824, +16130, 16258, 48820, +16134, 16256, 48816, +16138, 16254, 48812, +16142, 16252, 48808, +16146, 16248, 48804, +16150, 16246, 48804, +16154, 16244, 48800, +16158, 16242, 48796, +16162, 16238, 48792, +16164, 16236, 48788, +16168, 16234, 48788, +16172, 16232, 48784, +16176, 16230, 48780, +16180, 16228, 48780, +16182, 16226, 48776, +16186, 16222, 48772, +16190, 16220, 48772, +16194, 16218, 48768, +16196, 16216, 48768, +16200, 16214, 48760, +16204, 16212, 48752, +16206, 16212, 48752, +16210, 16210, 48744, +16214, 16208, 48744, +16216, 16206, 48736, +16220, 16204, 48736, +16222, 16202, 48728, +16226, 16200, 48728, +16230, 16198, 48720, +16232, 16196, 48720, +16236, 16196, 48720, +16238, 16194, 48712, +16242, 16192, 48712, +16244, 16190, 48704, +16248, 16190, 48704, +16250, 16188, 48704, +16254, 16186, 48696 +}; + +////// BF16 ////// +uint16_t exp_ftable_bf16[2 * 4 * (1 << m5_val)] = // val , val -128 +{ + 0x3ef9, 0x3f80, 0x3f80, 0x3efb, 0x3f80, 0x3f80, 0x3f80, 0x3f80, + 0x3f80, 0x3f80, 0x3f80, 0x3f80, 0x3f02, 0x3f80, 0x3f03, 0x3f80, + 0x3f80, 0x3f05, 0x3f80, 0x3f80, 0x3f06, 0x3f80, 0x3f80, 0x3f08, + 0x3f80, 0x3f80, 0x3f0a, 0x3f80, 0x3f80, 0x3f0b, 0x3f80, 0x3f0c, + 0x3f0d, 0x3f80, 0x3f0e, 0x3f0e, 0x3f80, 0x3f10, 0x3f80, 0x3f80, + 0x3f11, 0x3f12, 0x3f80, 0x3f13, 0x3f80, 0x3f80, 0x3f15, 0x3f80, + 0x3f80, 0x3f16, 0x3f80, 0x3f80, 0x3f18, 0x3f80, 0x3f80, 0x3f1a, + 0x3f80, 0x3f1b, 0x3f1c, 0x3f1e, 0x3f1f, 0x3f20, 0x3f21, 0x3f23, + 0x3f24, 0x3f25, 0x3f27, 0x3f28, 0x3f29, 0x3f2b, 0x3f2c, 0x3f2d, + 0x3f2f, 0x3f30, 0x3f31, 0x3f33, 0x3f34, 0x3f36, 0x3f37, 0x3f38, + 0x3f3a, 0x3f3b, 0x3f3d, 0x3f3e, 0x3f40, 0x3f41, 0x3f43, 0x3f44, + 0x3f46, 0x3f47, 0x3f49, 0x3f4b, 0x3f4c, 0x3f4e, 0x3f4f, 0x3f51, + 0x3f53, 0x3f54, 0x3f56, 0x3f58, 0x3f59, 0x3f5b, 0x3f5d, 0x3f5e, + 0x3f60, 0x3f62, 0x3f64, 0x3f65, 0x3f67, 0x3f69, 0x3f6b, 0x3f6d, + 0x3f6f, 0x3f70, 0x3f72, 0x3f74, 0x3f76, 0x3f78, 0x3f7a, 0x3f7c, + 0x3f7e, 0x3f80, 0x3f81, 0x3f82, 0x3f83, 0x3f84, 0x3f85, 0x3f86, + 0x3f87, 0x3f88, 0x3f89, 0x3f8a, 0x3f8b, 0x3f8d, 0x3f8e, 0x3f8f, + 0x3f90, 0x3f91, 0x3f92, 0x3f93, 0x3f94, 0x3f96, 0x3f97, 0x3f98, + 0x3f99, 0x3f9a, 0x3f9c, 0x3f9d, 0x3f9e, 0x3f9f, 0x3fa1, 0x3fa2, + 0x3fa3, 0x3fa4, 0x3fa6, 0x3fa7, 0x3fa8, 0x3faa, 0x3fab, 0x3fac, + 0x3fae, 0x3faf, 0x3fb0, 0x3fb2, 0x3fb3, 0x3fb5, 0x3fb6, 0x3fb7, + 0x3fb9, 0x3fba, 0x3fbc, 0x3fbd, 0x3fbf, 0x3fc0, 0x3fc2, 0x3fc3, + 0x3fc5, 0x3fc6, 0x3fc8, 0x3fc9, 0x3fcb, 0x3fcd, 0x3fce, 0x3fd0, + 0x3fd1, 0x3fd3, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 +}; + + // ========== float log2(x) linear approximation for [0.75, 1.0] =================== + +uint16_t log2m1_bf16_linear_coeffs_m4_01p[2*(1 << m4_val)] = // C2, C1, C0 +{ +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +48852, 16364, +48792, 16347, +48712, 16332, +48576, 16319 +}; + +uint16_t log2m1_bf16_linear_coeffs_m5_01p[2*(1 << m5_val)] = // C2, C1, C0 +{ +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +48852, 16369, +48824, 16360, +48792, 16351, +48760, 16343, +48712, 16335, +48656, 16328, +48576, 16322, +48448, 16316 +}; + +uint16_t log2m1_bf16_linear_coeffs_m6_01p[2*(1 << m6_val)] = // C2, C1, C0 +{ +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +48852, 16372, +48836, 16367, +48824, 16362, +48808, 16357, +48792, 16353, +48780, 16349, +48760, 16345, +48736, 16341, +48712, 16337, +48680, 16334, +48656, 16330, +48624, 16327, +48576, 16323, +48528, 16320, +48448, 16317, +48320, 16314 +}; + + // ========== bf16 log2(x) poly2 approximation for 0.75, 1.0] =================== + +uint16_t log2m1_bf16_poly2_coeffs_m4_01p[3*(1 << m4_val)] = // C2, C1, C0 +{ +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +48852, 16374, 49047, +48792, 16355, 49026, +48712, 16339, 48994, +48576, 16325, 48964 +}; + +uint16_t log2m1_bf16_poly2_coeffs_m5_01p[3*(1 << m5_val)] = // C2, C1, C0 +{ +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +48852, 16374, 49054, +48824, 16364, 49041, +48792, 16355, 49031, +48760, 16347, 49018, +48712, 16339, 49000, +48656, 16332, 48986, +48576, 16325, 48972, +48448, 16319, 48958 +}; + +uint16_t log2m1_bf16_poly2_coeffs_m6_01p[3*(1 << m6_val)] = // C2, C1, C0 +{ +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +48852, 16374, 49057, +48836, 16369, 49050, +48824, 16364, 49044, +48808, 16360, 49039, +48792, 16355, 49033, +48780, 16351, 49028, +48760, 16347, 49022, +48736, 16343, 49014, +48712, 16339, 49004, +48680, 16335, 48996, +48656, 16332, 48990, +48624, 16328, 48982, +48576, 16325, 48974, +48528, 16322, 48968, +48448, 16319, 48962, +48320, 16316, 48956 +}; + + // ========== bf16 log2(x)/(x - 1.0) linear approximation for 0.0, 1.0] =================== + +uint16_t log2m1_bf16_linear_coeffs_m4_01f[2*(1 << m4_val)] = // C2, C1, C0 +{ +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +16340, 49024, +16332, 49000, +16325, 48978, +16319, 48960 +}; + +uint16_t log2m1_bf16_linear_coeffs_m5_01f[2*(1 << m5_val)] = // C2, C1, C0 +{ +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +16340, 49027, +16336, 49018, +16332, 49006, +16329, 48994, +16325, 48984, +16322, 48974, +16319, 48964, +16316, 48956 +}; + +uint16_t log2m1_bf16_linear_coeffs_m6_01f[2 * (1 << m6_val)] = // C2, C1, C0 +{ +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +00000, 00000, +16340, 49029, +16338, 49026, +16336, 49020, +16334, 49014, +16332, 49008, +16331, 49002, +16329, 48996, +16327, 48992, +16325, 48986, +16324, 48980, +16322, 48976, +16320, 48972, +16319, 48968, +16317, 48962, +16316, 48958, +16314, 48954 +}; + + // ========== bf16 log2(x)/(x - 1.0) poly2 approximation for 0.0, 1.0] =================== + +uint16_t log2m1_bf16_poly2_coeffs_m4_01f[3*(1 << m4_val)] = // C2, C1, C0 +{ +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +16340, 49031, 16214, +16332, 49010, 16180, +16325, 48988, 16154, +16319, 48968, 16132 +}; + +uint16_t log2m1_bf16_poly2_coeffs_m5_01f[3*(1 << m5_val)] = // C2, C1, C0 +{ +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +16340, 49031, 16224, +16336, 49024, 16204, +16332, 49010, 16188, +16329, 49000, 16172, +16325, 48988, 16160, +16322, 48978, 16148, +16319, 48970, 16138, +16316, 48960, 16128 +}; + +uint16_t log2m1_bf16_poly2_coeffs_m6_01f[3*(1 << m6_val)] = // C2, C1, C0 +{ +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +00000, 00000, 00000, +16340, 49031, 16228, +16338, 49027, 16218, +16336, 49024, 16210, +16334, 49018, 16200, +16332, 49010, 16192, +16331, 49004, 16184, +16329, 49000, 16176, +16327, 48994, 16170, +16325, 48988, 16162, +16324, 48984, 16156, +16322, 48978, 16150, +16320, 48974, 16146, +16319, 48970, 16140, +16317, 48964, 16134, +16316, 48960, 16130, +16314, 48956, 16124 +}; + + // ======= reduced bf16 log2(x)/(x - 1.0) linear approximation for 0.0, 1.0] w/o zeroes ======= + +// reduced m4 table - no zeroes +uint16_t log2m1_bf16_linear_coeffs_m4_0_075[2 * (( 1 << m4_val) >> 2)] = // C2, C1, C0 +{ +16340, 49024, +16332, 49000, +16325, 48978, +16319, 48960 +}; + +// reduced m5 table - no zeroes +uint16_t log2m1_bf16_linear_coeffs_m5_0_075[2 * (( 1 << m5_val) >> 2)] = // C2, C1, C0 +{ +16340, 49027, +16336, 49018, +16332, 49006, +16329, 48994, +16325, 48984, +16322, 48974, +16319, 48964, +16316, 48956 +}; + +// reduced m6 table - no zeroes +uint16_t log2m1_bf16_linear_coeffs_m6_0_075[2 * ((1 << m6_val) >> 2)] = // C2, C1, C0 +{ +16340, 49029, +16338, 49026, +16336, 49020, +16334, 49014, +16332, 49008, +16331, 49002, +16329, 48996, +16327, 48992, +16325, 48986, +16324, 48980, +16322, 48976, +16320, 48972, +16319, 48968, +16317, 48962, +16316, 48958, +16314, 48954 +}; + + // --------reduced bf16 log2(x)/(x - 1.0) poly2 approximation for 0.0, 1.0] w/o zeroes------- + +uint16_t log2m1_bf16_poly2_coeffs_m4_0_075[3 * ((1 << m4_val) >> 2)] = // C2, C1, C0 +{ +16340, 49031, 16214, +16332, 49010, 16180, +16325, 48988, 16154, +16319, 48968, 16132 +}; + + +uint16_t log2m1_bf16_poly2_coeffs_m5_0_075[3 * ((1 << m5_val) >> 2)] = // C2, C1, C0 +{ +16340, 49031, 16224, +16336, 49024, 16204, +16332, 49010, 16188, +16329, 49000, 16172, +16325, 48988, 16160, +16322, 48978, 16148, +16319, 48970, 16138, +16316, 48960, 16128 +}; + +uint16_t log2m1_bf16_poly2_coeffs_m6_0_075[3 * ((1 << m6_val) >> 2)] = // C2, C1, C0 +{ +16340, 49031, 16228, +16338, 49027, 16218, +16336, 49024, 16210, +16334, 49018, 16200, +16332, 49010, 16192, +16331, 49004, 16184, +16329, 49000, 16176, +16327, 48994, 16170, +16325, 48988, 16162, +16324, 48984, 16156, +16322, 48978, 16150, +16320, 48974, 16146, +16319, 48970, 16140, +16317, 48964, 16134, +16316, 48960, 16130, +16314, 48956, 16124 +}; + + +// ========== GL log2 poly2 approximation (m = 3) =================== + +// log2 zero_exp followed by non_zero exp + +uint16_t log2_coeffs_bf16[3*16] = +{ + 0x3dc5u, 0xb9c0u, 0x36bcu, + 0x3d70u, 0xb8eau, 0x353cu, + 0x3d27u, 0xb844u, 0x3428u, + 0x3ce7u, 0xb77cu, 0x32c0u, + 0x3caeu, 0xb6a4u, 0x3198u, + 0x3c7cu, 0xb5f4u, 0x30b0u, + 0x3c4eu, 0xb560u, 0x2ff0u, + 0x3c25u, 0xb4e0u, 0x2ec0u, + 0x0000u, 0x3dc2u, 0xb920u, + 0x3170u, 0x3d1fu, 0xb81au, + 0x3528u, 0x3c9cu, 0xb6b4u, + 0x3758u, 0x3c31u, 0xb598u, + 0x38aeu, 0x3bb0u, 0xb4bcu, + 0x399au, 0x3b18u, 0xb410u, + 0x3a76u, 0x3a96u, 0xb308u, + 0x3b42u, 0x3a26u, 0xb228u +}; + +// ========== GL pow2 poly2 approximation (m = 2) =================== + +uint16_t pow2_coeffs_bf16[3 * 4] = // C2, C1, C0 +{ + 16256, 16176, 16008, + 16280, 16210, 16032, + 16309, 16250, 16060, + 16343, 16277, 16096 +}; + +// ========== bf16 recip const approximation (m = 7) =================== + +uint16_t recip_bf16_scalar_coeffs_m7[1 << 7] = // C2, C1, C0 +{ +16256, +16254, +16252, +16250, +16248, +16246, +16245, +16243, +16241, +16239, +16237, +16236, +16234, +16232, +16231, +16229, +16228, +16226, +16224, +16223, +16221, +16220, +16218, +16217, +16216, +16214, +16213, +16211, +16210, +16209, +16207, +16206, +16205, +16204, +16202, +16201, +16200, +16199, +16197, +16196, +16195, +16194, +16193, +16192, +16191, +16189, +16188, +16187, +16186, +16185, +16184, +16183, +16182, +16181, +16180, +16179, +16178, +16177, +16176, +16175, +16174, +16173, +16172, +16172, +16171, +16170, +16169, +16168, +16167, +16166, +16165, +16165, +16164, +16163, +16162, +16161, +16161, +16160, +16159, +16158, +16158, +16157, +16156, +16155, +16155, +16154, +16153, +16152, +16152, +16151, +16150, +16150, +16149, +16148, +16148, +16147, +16146, +16146, +16145, +16144, +16144, +16143, +16142, +16142, +16141, +16141, +16140, +16139, +16139, +16138, +16138, +16137, +16137, +16136, +16135, +16135, +16134, +16134, +16133, +16133, +16132, +16132, +16131, +16131, +16130, +16130, +16129, +16129 +}; + + // ========== bf16 recip linear approximation (m = 2) =================== + +uint16_t recip_bf16_linear_coeffs_m2[2*(1 << 2)] = // C1, C0 +{ + 16254, 48972, + 16204, 48904, + 16170, 48836, + 16146, 48788 +}; + +uint16_t recip_bf16_linear_coeffs_m3[2*(1 << 3)] = // C1, C0 +{ + 16256, 48996, + 16228, 48950, + 16204, 48916, + 16186, 48888, + 16170, 48852, + 16158, 48820, + 16146, 48796, + 16136, 48776 +}; + +uint16_t recip_bf16_linear_coeffs_m4[2*(1 << 4)] = // C1, C0 +{ + 16256, 49008, + 16240, 48982, + 16228, 48960, + 16216, 48940, + 16204, 48924, + 16194, 48910, + 16186, 48898, + 16178, 48876, + 16170, 48860, + 16164, 48840, + 16158, 48828, + 16152, 48812, + 16146, 48800, + 16142, 48792, + 16136, 48780, + 16132, 48772 +}; + +// ========== GL recip poly2 approximations (m = 3) =================== +uint16_t recip_bf16_poly2_coeffs_m2[3*(1 << 2)] = // C0, C1, C2 +{ + 16256, 49018, 16182, + 16204, 48930, 16072, + 16170, 48864, 15984, + 16146, 48804, 15904 +}; + +uint16_t recip_bf16_poly2_coeffs_m3[3*(1 << 3)] = // C0, C1, C2 +{ + 16256, 49022, 16214, + 16228, 48970, 16154, + 16204, 48932, 16100, + 16186, 48902, 16044, + 16170, 48868, 16008, + 16158, 48832, 15960, + 16146, 48808, 15920, + 16136, 48784, 15888 +}; + +uint16_t recip_bf16_poly2_coeffs_m4[3*(1 << 4)] = // C0, C1, C2 +{ + 16256, 49024, 16234, + 16240, 48994, 16196, + 16228, 48970, 16166, + 16216, 48950, 16142, + 16204, 48932, 16116, + 16196, 48916, 16084, + 16186, 48904, 16056, + 16178, 48888, 16032, + 16170, 48868, 16016, + 16164, 48848, 16000, + 16158, 48832, 15968, + 16152, 48820, 15944, + 16146, 48808, 15928, + 16142, 48796, 15904, + 16136, 48784, 15888, + 16132, 48776, 15880 +}; + +uint16_t recip_coeffs_bf16[8*3] = +{ + 0x3c00u, 0xbbf2u, 0x3ab2u, + 0x3b1cu, 0xba48u, 0x38ccu, + 0x3a66u, 0xb918u, 0x3718u, + 0x39d2u, 0xb836u, 0x3568u, + 0x3956u, 0xb718u, 0x3434u, + 0x38ecu, 0xb60cu, 0x32a8u, + 0x3892u, 0xb538u, 0x3160u, + 0x3844u, 0xb48cu, 0x3068u +}; + +// M.Wiktor imp. SW-41220: +uint16_t recip_coeffs_c0_bf16[128] = +{ + 16256,16254,16252,16250,16248,16246,16245, + 16243,16241,16239,16237,16236,16234,16232, + 16231,16229,16228,16226,16224,16223,16221, + 16220,16218,16217,16216,16214,16213,16211, + 16210,16209,16207,16206,16205,16204,16202, + 16201,16200,16199,16197,16196,16195,16194, + 16193,16192,16191,16189,16188,16187,16186, + 16185,16184,16183,16182,16181,16180,16179, + 16178,16177,16176,16175,16174,16173,16172, + 16172,16171,16170,16169,16168,16167,16166, + 16165,16165,16164,16163,16162,16161,16161, + 16160,16159,16158,16158,16157,16156,16155, + 16155,16154,16153,16152,16152,16151,16150, + 16150,16149,16148,16148,16147,16146,16146, + 16145,16144,16144,16143,16142,16142,16141, + 16141,16140,16139,16139,16138,16138,16137, + 16137,16136,16135,16135,16134,16134,16133, + 16133,16132,16132,16131,16131,16130,16130, + 16129,16129 +}; +// ========== GL rsqrt poly2 approximations (m = 3) =================== +// rsqrt_default_coeffs_m3_12 followed by rsqrt_default_coeffs_m3_24 +#if 0 +uint16_t rsqrt_coeffs_bf16[3*16] = +{ + 0x3c00u, 0xb7f8u, 0x352cu, + 0x3b8au, 0xb6acu, 0x33d8u, + 0x3b28u, 0xb5b4u, 0x3218u, + 0x3ad2u, 0xb4f4u, 0x30d8u, + 0x3a88u, 0xb458u, 0x2fe0u, + 0x3a46u, 0xb3b8u, 0x2e80u, + 0x3a0cu, 0xb2e8u, 0x2d70u, + 0x39d8u, 0xb238u, 0x2ca0u, + + 0x39a8u, 0xb1a0u, 0x2b60u, + 0x3956u, 0xb0b8u, 0x2980u, + 0x3910u, 0xb008u, 0x2840u, + 0x38d2u, 0xaf00u, 0x26c0u, + 0x389eu, 0xae20u, 0x2580u, + 0x3870u, 0xad70u, 0x2480u, + 0x3846u, 0xace0u, 0x2380u, + 0x3822u, 0xac60u, 0x2280u +}; +#else + uint16_t rsqrt_coeffs_bf16[2*16] = +{ + 16256u, 48876u, + 16242u, 48840u, + 16228u, 48812u, + 16218u, 48788u, + 16208u, 48772u, + 16200u, 48744u, + 16194u, 48720u, + 16186u, 48704u, + + 16180u, 48680u, + 16170u, 48656u, + 16162u, 48624u, + 16154u, 48592u, + 16148u, 48576u, + 16142u, 48544u, + 16136u, 48528u, + 16132u, 48512u +}; +#endif + +uint16_t rsqrt_bf16_const_coeffs_m6[1 << 7] = // C2, C1, C0 coeffs_12 followed by coeffs_24 +{ + // ========== bf16 rsqrt const approximation for [1.0, 2.0] (m = 6) =================== + 16256, + 16254, + 16252, + 16250, + 16248, + 16247, + 16245, + 16243, + 16241, + 16240, + 16238, + 16236, + 16235, + 16233, + 16232, + 16230, + 16229, + 16228, + 16226, + 16225, + 16223, + 16222, + 16221, + 16220, + 16218, + 16217, + 16216, + 16215, + 16214, + 16212, + 16211, + 16210, + 16209, + 16208, + 16207, + 16206, + 16205, + 16204, + 16203, + 16202, + 16201, + 16200, + 16199, + 16198, + 16197, + 16196, + 16195, + 16194, + 16194, + 16193, + 16192, + 16191, + 16190, + 16189, + 16189, + 16188, + 16187, + 16186, + 16185, + 16185, + 16184, + 16183, + 16182, + 16182, +// ========== bf16 rsqrt const approximation for [2.0, 4.0] (m = 6) =================== + 16180, + 16178, + 16178, + 16176, + 16174, + 16174, + 16172, + 16172, + 16170, + 16168, + 16168, + 16166, + 16166, + 16164, + 16164, + 16162, + 16162, + 16160, + 16160, + 16158, + 16158, + 16156, + 16156, + 16154, + 16154, + 16154, + 16152, + 16152, + 16150, + 16150, + 16148, + 16148, + 16148, + 16146, + 16146, + 16146, + 16144, + 16144, + 16144, + 16142, + 16142, + 16140, + 16140, + 16140, + 16140, + 16138, + 16138, + 16138, + 16136, + 16136, + 16136, + 16134, + 16134, + 16134, + 16134, + 16132, + 16132, + 16132, + 16130, + 16130, + 16130, + 16130, + 16128, + 16128 +}; + + +uint16_t rsqrt_bf16_linear_coeffs_m2[2 * (1 << 3)] = // C1, C0 +{ + // ========== bf16 rsqrt linear approximation for [1.0, 2.0] (m = 2) =================== + 16256, 48856, + 16228, 48800, + 16208, 48760, + 16194, 48712, +// ========== bf16 rsqrt linear approximation for [2.0, 4.0] (m = 2) =================== + 16180, 48664, + 16162, 48608, + 16148, 48560, + 16136, 48528 +}; +uint16_t rsqrt_bf16_linear_coeffs_m3[2 * (1 << 4)] = // C1, C0 +{ + 16256, 48876, + 16242, 48840, + 16228, 48812, + 16218, 48788, + 16208, 48772, + 16200, 48744, + 16194, 48720, + 16186, 48704, + + 16180, 48680, + 16170, 48656, + 16162, 48624, + 16154, 48592, + 16148, 48576, + 16142, 48544, + 16136, 48528, + 16132, 48512 +}; + +uint16_t rsqrt_bf16_linear_coeffs_m4[2 * (1 << 5)] = // C1, C0 +{ + 16256, 48884, + 16248, 48864, + 16242, 48844, + 16234, 48832, + 16228, 48816, + 16224, 48804, + 16218, 48792, + 16214, 48784, + 16210, 48776, + 16204, 48768, + 16200, 48752, + 16198, 48736, + 16194, 48728, + 16190, 48720, + 16186, 48704, + 16184, 48696, + + 16180, 48688, + 16176, 48672, + 16170, 48656, + 16166, 48648, + 16162, 48640, + 16158, 48624, + 16154, 48608, + 16150, 48592, + 16148, 48576, + 16144, 48560, + 16142, 48560, + 16140, 48544, + 16136, 48544, + 16134, 48528, + 16132, 48528, + 16130, 48512 +}; + + + +uint16_t rsqrt_bf16_poly2_coeffs_m2[3 * (1 << 3)] = // C2, C1, C0 +{ + // ========== bf16 rsqrt poly2 approximation for [1.0, 2.0] (m = 2) =================== + 16256, 48892, 16016, + 16228, 48820, 15920, + 16210, 48780, 15840, + 16194, 48728, 15776, + // ========== bf16 rsqrt poly2 approximation for [2.0, 4.0] (m = 2) =================== + 16182, 48688, 15680, + 16162, 48640, 15616, + 16148, 48576, 15552, + 16136, 48544, 15488 +}; + +uint16_t rsqrt_bf16_poly2_coeffs_m3[3 * (1 << 4)] = // C2, C1, C0 +{ + 16256, 48896, 16036, + 16242, 48852, 15992, + 16228, 48824, 15936, + 16218, 48800, 15896, + 16210, 48780, 15872, + 16200, 48760, 15824, + 16194, 48736, 15792, + 16186, 48712, 15760, + + 16182, 48696, 15712, + 16170, 48664, 15680, + 16162, 48640, 15616, + 16154, 48608, 15552, + 16148, 48576, 15552, + 16142, 48560, 15488, + 16136, 48544, 15488, + 16132, 48528, 15488, +}; + +uint16_t rsqrt_bf16_poly2_coeffs_m4[3 * (1 << 5)] = // C2, C1, C0 +{ + 16256, 48896, 16048, + 16248, 48872, 16024, + 16242, 48856, 16004, + 16234, 48836, 15976, + 16228, 48824, 15952, + 16224, 48812, 15928, + 16218, 48800, 15904, + 16214, 48788, 15888, + 16210, 48780, 15880, + 16204, 48772, 15856, + 16200, 48760, 15840, + 16198, 48744, 15808, + 16194, 48736, 15792, + 16190, 48720, 15776, + 16186, 48712, 15776, + 16184, 48704, 15760, + + 16182, 48696, 15744, + 16176, 48680, 15712, + 16170, 48664, 15680, + 16166, 48648, 15648, + 16162, 48640, 15648, + 16158, 48624, 15616, + 16154, 48608, 15616, + 16150, 48592, 15552, + 16148, 48576, 15552, + 16144, 48576, 15552, + 16142, 48560, 15488, + 16140, 48544, 15488, + 16136, 48544, 15488, + 16134, 48528, 15488, + 16132, 48528, 15488, + 16130, 48512, 15488, +}; + + // ========== bf16 sqrt const approximation for [1.0, 4.0] (m = 6) =================== + +uint16_t sqrt_bf16_const_coeffs_m6[1 << 7] = // C2, C1, C0 coeffs_12 followed by coeffs_24 +{ + // ========== bf16 sqrt const approximation for [1.0, 2.0] (m = 6) =================== +16256, +16257, +16258, +16259, +16260, +16261, +16262, +16263, +16264, +16265, +16266, +16267, +16268, +16269, +16270, +16271, +16272, +16272, +16273, +16274, +16275, +16276, +16277, +16278, +16279, +16279, +16280, +16281, +16282, +16283, +16284, +16284, +16285, +16286, +16287, +16288, +16288, +16289, +16290, +16291, +16292, +16292, +16293, +16294, +16295, +16295, +16296, +16297, +16298, +16298, +16299, +16300, +16301, +16301, +16302, +16303, +16304, +16304, +16305, +16306, +16307, +16307, +16308, +16309, +// ========== bf16 sqrt const approximation for [2.0, 4.0] (m = 6) =================== +16310, +16311, +16313, +16314, +16315, +16317, +16318, +16319, +16321, +16322, +16323, +16325, +16326, +16327, +16328, +16330, +16331, +16332, +16334, +16335, +16336, +16337, +16338, +16340, +16341, +16342, +16343, +16344, +16346, +16347, +16348, +16349, +16350, +16351, +16353, +16354, +16355, +16356, +16357, +16358, +16359, +16360, +16362, +16363, +16364, +16365, +16366, +16367, +16368, +16369, +16370, +16371, +16372, +16373, +16374, +16375, +16376, +16377, +16378, +16379, +16380, +16381, +16382, +16383 +}; + + // ========== bf16 sqrt linear approximation for [1.0, 4.0] (m = 2-4) =================== + +uint16_t sqrt_bf16_linear_coeffs_m2[2*2*(1 << 2)] = // C1, C0 coeffs_12 followed by coeffs_24 +{ + // ========== bf16 sqrt linear approximation for [1.0, 2.0] (m = 2) =================== +16256, 16112, +16271, 16092, +16285, 16072, +16297, 16060, + // ========== bf16 sqrt linear approximation for [2.0, 4.0] (m = 2) =================== +16309, 16044, +16330, 16028, +16350, 16016, +16368, 16004 +}; + +uint16_t sqrt_bf16_linear_coeffs_m3[2*2*(1 << 3)] = // C1, C0 coeffs_12 followed by coeffs_24 +{ + // ========== bf16 sqrt linear approximation for [1.0, 2.0] (m = 3) =================== +16256, 16120, +16264, 16108, +16271, 16096, +16278, 16084, +16285, 16076, +16291, 16068, +16297, 16064, +16303, 16056, + // ========== bf16 sqrt linear approximation for [2.0, 4.0] (m = 3) =================== +16309, 16048, +16320, 16040, +16330, 16032, +16340, 16024, +16350, 16016, +16359, 16012, +16367, 16008, +16376, 16004 +}; + +uint16_t sqrt_bf16_linear_coeffs_m4[2*2*(1 << 4)] = // C1, C0 coeffs_12 followed by coeffs_24 +{ + // ========== bf16 sqrt linear approximation for [1.0, 2.0] (m = 4) =================== +16256, 16124, +16260, 16116, +16264, 16112, +16267, 16104, +16271, 16100, +16275, 16092, +16278, 16088, +16281, 16084, +16285, 16080, +16288, 16076, +16291, 16072, +16294, 16068, +16297, 16064, +16300, 16060, +16303, 16056, +16306, 16056, + // ========== bf16 sqrt linear approximation for [2.0, 4.0] (m = 4) =================== +16309, 16052, +16315, 16044, +16320, 16040, +16325, 16036, +16330, 16032, +16335, 16028, +16340, 16024, +16345, 16020, +16350, 16020, +16354, 16016, +16359, 16012, +16363, 16012, +16367, 16008, +16372, 16004, +16376, 16004, +16380, 16000 +}; + + // ========== bf16 sqrt poly2 approximation for [1.0, 4.0] (m = 2-4) =================== + +uint16_t sqrt_bf16_poly2_coeffs_m2[2*3*(1 << 2)] = // C2, C1, C0 coeffs_12 followed by coeffs_24 +{ + // ========== bf16 sqrt poly2 approximation for [1.0, 2.0] (m = 2) =================== +16256, 16128, 48592, +16271, 16100, 48544, +16285, 16080, 48512, +16297, 16064, 48448, + // ========== bf16 sqrt poly2 approximation for [2.0, 4.0] (m = 2) =================== +16309, 16052, 48416, +16330, 16032, 48384, +16350, 16020, 48320, +16367, 16008, 48256 +}; + +uint16_t sqrt_bf16_poly2_coeffs_m3[2*3*(1 << 3)] = // C2, C1, C0 coeffs_12 followed by coeffs_24 +{ + // ========== bf16 sqrt poly2 approximation for [1.0, 2.0] (m = 3) =================== +16256, 16128, 48624, +16264, 16112, 48576, +16271, 16100, 48560, +16278, 16092, 48528, +16285, 16080, 48512, +16291, 16072, 48480, +16297, 16064, 48480, +16303, 16060, 48448, + // ========== bf16 sqrt poly2 approximation for [2.0, 4.0] (m = 3) =================== +16309, 16052, 48416, +16320, 16044, 48384, +16330, 16032, 48384, +16340, 16028, 48320, +16350, 16020, 48320, +16359, 16012, 48320, +16367, 16008, 48256, +16376, 16004, 48256 +}; + +uint16_t sqrt_bf16_poly2_coeffs_m4[2*3*(1 << 4)] = // C2, C1, C0 coeffs_12 followed by coeffs_24 +{ + // ========== bf16 sqrt poly2 approximation for [1.0, 2.0] (m = 4) =================== +16256, 16128, 48624, +16260, 16120, 48608, +16264, 16112, 48592, +16267, 16108, 48576, +16271, 16100, 48560, +16275, 16096, 48544, +16278, 16092, 48544, +16281, 16084, 48528, +16285, 16080, 48512, +16288, 16076, 48512, +16291, 16072, 48512, +16294, 16068, 48480, +16297, 16064, 48480, +16300, 16064, 48448, +16303, 16060, 48448, +16306, 16056, 48448, + // ========== bf16 sqrt poly2 approximation for [2.0, 4.0] (m = 4) =================== +16309, 16052, 48416, +16315, 16048, 48416, +16320, 16044, 48416, +16325, 16040, 48384, +16330, 16032, 48384, +16335, 16028, 48384, +16340, 16028, 48320, +16345, 16024, 48320, +16350, 16020, 48320, +16354, 16016, 48320, +16359, 16012, 48320, +16363, 16012, 48320, +16367, 16008, 48256, +16372, 16008, 48256, +16376, 16004, 48256, +16380, 16004, 48256 +}; + +// ========== GL sqrt poly2 approximations (m = 2) =================== +// sqrt_default_coeffs_m2_12 followed by sqrt_default_coeffs_m2_24 +uint16_t sqrt_coeffs_bf16[3*8] = +{ + 0x3c00u, 0x37f8u, 0xaec0u, + 0x3c79u, 0x3724u, 0xad00u, + 0x3ce6u, 0x3684u, 0xabc0u, + 0x3d4bu, 0x360cu, 0xaa40u, + 0x3da8u, 0x35a4u, 0xa8c0u, + 0x3e53u, 0x350cu, 0xa700u, + 0x3eeeu, 0x349cu, 0xa580u, + 0x3f7cu, 0x3444u, 0xa480u +}; + + // ========== bf16 tanhx linear approximation on [0, 1] =================== +// // ========== bf16 tanh linear approximation on [0, 1] =================== + // ========== bf16 tanh linear approximation on [1, 2] =================== + // ========== bf16 tanh linear approximation on [2, 4] =================== +uint16_t tanh_bf16_linear_coeffs_m2[3*2*(1 << 2)] = // C2, C1, C0 +{ +16256, 48544, +16252, 48736, +16236, 48800, +16216, 48816, + +/* + 0, 16250, +16000, 16222, +16112, 16178, +16164, 16130, +*/ + +16196, 16048, +16218, 15976, +16232, 15896, +16242, 15808, + +16248, 15680, +16252, 15488, +16254, 15360, +16256, 0 +}; + +uint16_t tanh_bf16_linear_coeffs_m3[3*2*(1 << 3)] = // C2, C1, C0 +{ +16256, 48416, +16254, 48640, +16250, 48712, +16244, 48768, +16236, 48792, +16228, 48804, +16216, 48812, +16206, 48816, + +/* + 0, 16254, +15872, 16246, +15992, 16232, +16056, 16212, +16108, 16190, +16142, 16164, +16162, 16140, +16180, 16108, +*/ + +16196, 16068, +16208, 16032, +16218, 16000, +16226, 15952, +16232, 15912, +16236, 15872, +16242, 15824, +16244, 15776, + +16246, 15712, +16250, 15616, +16252, 15552, +16254, 15488, +16254, 15360, +16256, 15360, +16256, 0, +16256, 0 +}; + +uint16_t tanh_bf16_linear_coeffs_m4[3*2*(1 << 4)] = // C2, C1, C0 +{ +16256, 48320, +16256, 48512, +16254, 48592, +16254, 48656, +16250, 48696, +16248, 48728, +16244, 48752, +16240, 48776, +16236, 48788, +16232, 48796, +16228, 48804, +16222, 48808, +16216, 48812, +16212, 48816, +16206, 48816, +16200, 48816, + +/* + 0, 16256, +15744, 16254, +15872, 16250, +15936, 16244, +15992, 16236, +16028, 16228, +16056, 16218, +16084, 16208, +16108, 16196, +16130, 16184, +16142, 16172, +16152, 16158, +16162, 16146, +16172, 16134, +16180, 16120, +16188, 16096, +*/ + +16196, 16076, +16202, 16056, +16208, 16040, +16212, 16024, +16218, 16008, +16222, 15992, +16226, 15960, +16228, 15936, +16232, 15920, +16234, 15904, +16236, 15880, +16240, 15856, +16242, 15840, +16242, 15808, +16244, 15792, +16246, 15776, + +16246, 15744, +16248, 15680, +16250, 15648, +16252, 15616, +16252, 15552, +16254, 15488, +16254, 15488, +16254, 15360, +16254, 15360, +16256, 15360, +16256, 15360, +16256, 15360, +16256, 0, +16256, 0, +16256, 0, +16256, 0 +}; + + // ========== bf16 tanhx poly2 approximation on [0, 1] =================== +// // ========== bf16 tanh poly2 approximation on [0, 1] =================== + // ========== bf16 tanh poly2 approximation on [1, 2] =================== + // ========== bf16 tanh poly2 approximation on [2, 4] =================== +uint16_t tanh_bf16_poly2_coeffs_m2[3*3*(1 << 2)] = // C2, C1, C0 +{ +16256, 0, 48804, +16250, 48680, 48752, +16236, 48784, 48624, +16216, 48812, 48256, + +/* + 0, 16257, 48624, +15992, 16242, 48800, +16108, 16202, 48836, +16162, 16152, 48820, +*/ + +16194, 16084, 48784, +16218, 16012, 48712, +16232, 15928, 48648, +16240, 15840, 48560, + +16246, 15760, 48448, +16252, 15552, 48256, +16254, 15360, 48128, +16256, 0, 0 +}; + +uint16_t tanh_bf16_poly2_coeffs_m3[3*3*(1 << 3)] = // C2, C1, C0 +{ +16256, 0, 48808, +16254, 48560, 48796, +16250, 48672, 48776, +16244, 48744, 48720, +16236, 48780, 48664, +16228, 48800, 48560, +16216, 48812, 48416, +16206, 48816, 15360, + +/* + 0, 16256, 48512, +15872, 16252, 48696, +15992, 16242, 48780, +16056, 16224, 48816, +16108, 16202, 48832, +16142, 16178, 48836, +16162, 16152, 48828, +16180, 16128, 48812, +*/ + +16194, 16088, 48792, +16208, 16048, 48772, +16218, 16016, 48736, +16226, 15976, 48696, +16232, 15928, 48664, +16236, 15888, 48624, +16240, 15856, 48576, +16244, 15792, 48544, + +16246, 15760, 48480, +16250, 15648, 48384, +16252, 15552, 48320, +16254, 15488, 48256, +16254, 15360, 48128, +16256, 15360, 48128, +16256, 0, 0, +16256, 0, 0 +}; + +uint16_t tanh_bf16_poly2_coeffs_m4[3*3*(1 << 4)] = // C2, C1, C0 +{ +16256, 0, 48812, +16256, 48416, 48808, +16254, 48560, 48800, +16254, 48640, 48792, +16250, 48672, 48780, +16248, 48712, 48768, +16244, 48744, 48736, +16240, 48768, 48704, +16236, 48780, 48680, +16232, 48792, 48648, +16228, 48800, 48592, +16222, 48808, 48528, +16216, 48812, 48448, +16212, 48816, 48320, +16206, 48816, 48128, +16200, 48816, 15488, + +/* + 0, 16256, 48384, +15744, 16256, 48576, +15872, 16252, 48664, +15936, 16248, 48720, +15992, 16240, 48768, +16028, 16232, 48792, +16056, 16224, 48808, +16084, 16212, 48820, +16108, 16202, 48832, +16130, 16190, 48836, +16142, 16178, 48836, +16152, 16164, 48836, +16162, 16152, 48832, +16172, 16140, 48824, +16180, 16130, 48816, +16188, 16108, 48808, +*/ + +16194, 16088, 48800, +16202, 16068, 48788, +16208, 16048, 48776, +16212, 16032, 48768, +16218, 16016, 48744, +16222, 16000, 48728, +16226, 15976, 48704, +16228, 15952, 48688, +16232, 15928, 48672, +16234, 15912, 48656, +16236, 15888, 48640, +16240, 15872, 48608, +16240, 15856, 48592, +16242, 15824, 48576, +16244, 15792, 48544, +16246, 15776, 48528, + +16246, 15760, 48512, +16248, 15712, 48448, +16250, 15680, 48416, +16252, 15616, 48384, +16252, 15552, 48320, +16254, 15552, 48256, +16254, 15488, 48256, +16254, 15488, 48128, +16254, 15360, 48128, +16256, 15360, 48128, +16256, 15360, 48128, +16256, 15360, 48128, +16256, 0, 0, +16256, 0, 0, +16256, 0, 0, +16256, 0, 0 +}; + +// tanh +// tanhx_default_coeffs_m4_01 followed by +// tanh_default_coeffs_m4_12 followed by +// tanh_default_coeffs_m4_24 followed by +// tanh_default_coeffs_m4_48 + +uint16_t tanh_coeffs_bf16[3 * 64] = +{ + 0x3c00u, 0x0000u, 0xb550u, + 0x3bfeu, 0xa960u, 0xb538u, + 0x3bf6u, 0xad40u, 0xb508u, + 0x3be8u, 0xafd0u, 0xb4c0u, + 0x3bd6u, 0xb118u, 0xb464u, + 0x3bc0u, 0xb230u, 0xb3f8u, + 0x3ba6u, 0xb330u, 0xb310u, + 0x3b86u, 0xb408u, 0xb220u, + 0x3b64u, 0xb46cu, 0xb120u, + 0x3b40u, 0xb4bcu, 0xb028u, + 0x3b1au, 0xb500u, 0xae70u, + 0x3af0u, 0xb534u, 0xacb0u, + 0x3ac6u, 0xb558u, 0xaa20u, + 0x3a9cu, 0xb570u, 0xa640u, + 0x3a70u, 0xb57cu, 0x9c00u, + 0x3a44u, 0xb580u, 0x2300u, + 0x3a18u, 0x36b8u, 0xb4f4u, + 0x3a4au, 0x3618u, 0xb4a4u, + 0x3a7au, 0x3584u, 0xb44cu, + 0x3aa4u, 0x34fcu, 0xb3f0u, + 0x3acau, 0x347cu, 0xb348u, + 0x3aecu, 0x3408u, 0xb2a8u, + 0x3b0au, 0x3338u, 0xb210u, + 0x3b26u, 0x3278u, 0xb180u, + 0x3b3eu, 0x31c8u, 0xb0f8u, + 0x3b54u, 0x3128u, 0xb080u, + 0x3b68u, 0x3098u, 0xb008u, + 0x3b78u, 0x3018u, 0xaf40u, + 0x3b88u, 0x2f40u, 0xae80u, + 0x3b96u, 0x2e70u, 0xadd0u, + 0x3ba2u, 0x2dc0u, 0xad30u, + 0x3bacu, 0x2d10u, 0xaca0u, + 0x3bb6u, 0x2c80u, 0xabc0u, + 0x3bc6u, 0x2b20u, 0xaa20u, + 0x3bd4u, 0x2980u, 0xa8e0u, + 0x3bdcu, 0x2860u, 0xa780u, + 0x3be4u, 0x26c0u, 0xa600u, + 0x3beau, 0x2540u, 0xa4c0u, + 0x3bf0u, 0x2440u, 0xa380u, + 0x3bf4u, 0x2280u, 0xa180u, + 0x3bf6u, 0x2100u, 0xa080u, + 0x3bf8u, 0x2000u, 0x9f00u, + 0x3bfau, 0x1e00u, 0x9d00u, + 0x3bfcu, 0x1d00u, 0x9c00u, + 0x3bfcu, 0x1c00u, 0x9a00u, + 0x3bfeu, 0x1a00u, 0x9a00u, + 0x3bfeu, 0x1800u, 0x9800u, + 0x3bfeu, 0x1800u, 0x9800u, + 0x3bfeu, 0x1400u, 0x9400u, + 0x3c00u, 0x1400u, 0x9400u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u +}; + +// bf16 uint16 coefficients for approximation sinx,cos on all intervals + +uint16_t sincos_bf16_scalar_coeffs_m7[2*(1 << m7_val)] = // C2, C1, C0 +{ +//sinx +16256, +16256, +16256, +16256, +16256, +16256, +16256, +16256, +16256, +16256, +16256, +16256, +16256, +16256, +16256, +16256, +16256, +16256, +16256, +16256, +16254, +16254, +16254, +16254, +16254, +16254, +16254, +16254, +16254, +16254, +16254, +16254, +16254, +16254, +16252, +16252, +16252, +16252, +16252, +16252, +16252, +16252, +16252, +16252, +16250, +16250, +16250, +16250, +16250, +16250, +16250, +16250, +16248, +16248, +16248, +16248, +16248, +16248, +16248, +16246, +16246, +16246, +16246, +16246, +16246, +16244, +16244, +16244, +16244, +16244, +16244, +16242, +16242, +16242, +16242, +16242, +16242, +16240, +16240, +16240, +16240, +16240, +16238, +16238, +16238, +16238, +16236, +16236, +16236, +16236, +16236, +16234, +16234, +16234, +16234, +16232, +16232, +16232, +16232, +16230, +16230, +16230, +16230, +16230, +16228, +16228, +16228, +16226, +16226, +16226, +16226, +16224, +16224, +16224, +16224, +16222, +16222, +16222, +16220, +16220, +16220, +16220, +16218, +16218, +16218, +16216, +16216, +16216, +//cos +16256, +16256, +16256, +16256, +16256, +16256, +16256, +16256, +16256, +16256, +16256, +16254, +16254, +16254, +16254, +16254, +16254, +16254, +16254, +16254, +16252, +16252, +16252, +16252, +16252, +16250, +16250, +16250, +16250, +16250, +16248, +16248, +16248, +16248, +16246, +16246, +16246, +16246, +16244, +16244, +16244, +16242, +16242, +16242, +16240, +16240, +16240, +16238, +16238, +16238, +16236, +16236, +16234, +16234, +16234, +16232, +16232, +16230, +16230, +16228, +16228, +16228, +16226, +16226, +16224, +16224, +16222, +16222, +16220, +16220, +16218, +16218, +16216, +16214, +16214, +16212, +16212, +16210, +16210, +16208, +16208, +16206, +16204, +16204, +16202, +16200, +16200, +16198, +16198, +16196, +16194, +16194, +16192, +16190, +16190, +16188, +16186, +16186, +16184, +16182, +16182, +16180, +16178, +16176, +16176, +16174, +16172, +16170, +16170, +16168, +16166, +16164, +16164, +16162, +16160, +16158, +16158, +16156, +16154, +16152, +16150, +16150, +16148, +16146, +16144, +16142, +16140, +16140 +}; + +uint16_t sincos_bf16_linear_coeffs_m2[2*2 * (1 << m2_val)] = // C2, C1, C0 +{ +//sinx +16256, 48416, +16254, 48640, +16246, 48720, +16232, 48780, +//cos +16257, 48640, +16250, 48828, +16226, 48918, +16188, 48964 +}; + + +uint16_t sincos_bf16_linear_coeffs_m3[2*2 * (1 << m3_val)] = // C2, C1, C0 +{ +//sinx +16256, 48320, +16256, 48512, +16254, 48592, +16250, 48656, +16246, 48696, +16240, 48736, +16232, 48768, +16224, 48788, +//cos +16256, 48512, +16254, 48704, +16248, 48796, +16238, 48856, +16224, 48904, +16208, 48930, +16188, 48954, +16164, 48974 +}; + +uint16_t sincos_bf16_linear_coeffs_m4[2*2 * (1 << m4_val)] = // C2, C1, C0 +{ +//sinx +16256, 48128, +16256, 48384, +16256, 48480, +16254, 48528, +16254, 48576, +16252, 48608, +16250, 48648, +16248, 48672, +16246, 48688, +16242, 48704, +16240, 48728, +16236, 48744, +16232, 48760, +16228, 48776, +16224, 48784, +16220, 48792, +//cos +16256, 48384, +16256, 48576, +16254, 48672, +16252, 48736, +16248, 48784, +16244, 48812, +16238, 48844, +16232, 48872, +16224, 48898, +16216, 48912, +16208, 48924, +16198, 48936, +16188, 48948, +16176, 48960, +16164, 48970, +16152, 48980 +}; + +uint16_t sincos_bf16_linear_coeffs_m5[2*2 * (1 << m5_val)] = // C2, C1, C0 +{ +//sinx +16256, 48128, +16256, 48256, +16256, 48320, +16256, 48416, +16256, 48448, +16254, 48480, +16254, 48528, +16254, 48544, +16254, 48560, +16252, 48592, +16252, 48608, +16250, 48624, +16250, 48640, +16250, 48656, +16248, 48664, +16246, 48672, +16246, 48680, +16244, 48696, +16242, 48704, +16242, 48712, +16240, 48720, +16238, 48728, +16236, 48744, +16234, 48752, +16232, 48760, +16230, 48768, +16228, 48772, +16226, 48776, +16224, 48780, +16222, 48784, +16220, 48788, +16218, 48792, +//cos +16256, 48256, +16256, 48448, +16256, 48544, +16254, 48608, +16254, 48656, +16252, 48688, +16252, 48720, +16250, 48752, +16248, 48776, +16246, 48788, +16244, 48804, +16242, 48820, +16238, 48836, +16236, 48848, +16232, 48864, +16228, 48880, +16224, 48892, +16220, 48902, +16216, 48908, +16212, 48914, +16208, 48922, +16202, 48928, +16198, 48934, +16192, 48940, +16188, 48946, +16182, 48952, +16176, 48956, +16170, 48962, +16164, 48968, +16158, 48972, +16152, 48976, +16144, 48982 +}; + +uint16_t sincos_bf16_linear_coeffs_m6[2 * 2 * (1 << m6_val)] = // C2, C1, C0 +{ +//sinx +16256, 0, +16256, 48128, +16256, 48256, +16256, 48256, +16256, 48320, +16256, 48384, +16256, 48384, +16256, 48416, +16256, 48448, +16256, 48448, +16254, 48480, +16254, 48512, +16254, 48512, +16254, 48528, +16254, 48544, +16254, 48544, +16254, 48560, +16254, 48576, +16252, 48576, +16252, 48592, +16252, 48608, +16252, 48608, +16250, 48624, +16250, 48624, +16250, 48640, +16250, 48648, +16250, 48648, +16248, 48656, +16248, 48664, +16248, 48664, +16246, 48672, +16246, 48672, +16246, 48680, +16244, 48688, +16244, 48688, +16244, 48696, +16242, 48704, +16242, 48704, +16242, 48712, +16240, 48712, +16240, 48720, +16238, 48728, +16238, 48728, +16238, 48736, +16236, 48736, +16236, 48744, +16234, 48744, +16234, 48752, +16232, 48760, +16232, 48760, +16230, 48768, +16230, 48768, +16228, 48772, +16228, 48772, +16226, 48776, +16226, 48776, +16224, 48780, +16224, 48780, +16222, 48784, +16222, 48784, +16220, 48788, +16218, 48788, +16218, 48792, +16216, 48792, +//cos +16256, 48128, +16256, 48320, +16256, 48416, +16256, 48480, +16256, 48528, +16256, 48560, +16254, 48592, +16254, 48624, +16254, 48648, +16254, 48664, +16252, 48680, +16252, 48696, +16252, 48712, +16250, 48728, +16250, 48744, +16250, 48760, +16248, 48772, +16248, 48780, +16246, 48784, +16244, 48792, +16244, 48800, +16242, 48808, +16242, 48816, +16240, 48824, +16238, 48832, +16236, 48840, +16236, 48844, +16234, 48852, +16232, 48860, +16230, 48868, +16228, 48876, +16226, 48880, +16224, 48888, +16222, 48896, +16220, 48900, +16218, 48902, +16216, 48906, +16214, 48910, +16212, 48912, +16210, 48916, +16208, 48920, +16206, 48922, +16202, 48926, +16200, 48928, +16198, 48932, +16196, 48936, +16192, 48938, +16190, 48942, +16188, 48944, +16184, 48946, +16182, 48950, +16178, 48952, +16176, 48956, +16174, 48958, +16170, 48960, +16168, 48964, +16164, 48966, +16162, 48968, +16158, 48970, +16154, 48974, +16152, 48976, +16148, 48978, +16144, 48980, +16142, 48982 +}; + +uint16_t sincos_bf16_poly2_coeffs_m2[2 * 3 * (1 << m2_val)] = // C2, C1, C0 +{ +//sinx +16256, 0, 48680, +16254, 48560, 48672, +16246, 48680, 48664, +16232, 48752, 48648, +//cos +16256, 0, 48892, +16248, 48768, 48876, +16224, 48888, 48848, +16188, 48944, 48804 +}; + +uint16_t sincos_bf16_poly2_coeffs_m3[2 * 3 * (1 << m3_val)] = // C2, C1, C0 +{ +//sinx +16256, 0, 48680, +16256, 48416, 48680, +16254, 48560, 48680, +16250, 48640, 48672, +16246, 48680, 48664, +16240, 48720, 48656, +16232, 48752, 48648, +16224, 48780, 48640, +//cos +16256, 0, 48896, +16254, 48640, 48892, +16248, 48768, 48884, +16238, 48828, 48872, +16224, 48884, 48856, +16208, 48918, 48836, +16188, 48942, 48816, +16164, 48964, 48792 +}; + +uint16_t sincos_bf16_poly2_coeffs_m4[2 * 3 * (1 << m4_val)] = // C2, C1, C0 +{ +//sinx +16256, 0, 48680, +16256, 48320, 48680, +16256, 48416, 48680, +16254, 48512, 48680, +16254, 48560, 48680, +16252, 48592, 48680, +16250, 48640, 48672, +16248, 48656, 48672, +16246, 48680, 48672, +16242, 48696, 48664, +16240, 48720, 48664, +16236, 48736, 48656, +16232, 48752, 48656, +16228, 48768, 48648, +16224, 48780, 48640, +16220, 48788, 48640, +//cos +16256, 0, 48896, +16256, 48512, 48896, +16254, 48640, 48892, +16252, 48704, 48888, +16248, 48768, 48884, +16244, 48796, 48880, +16238, 48828, 48876, +16232, 48856, 48868, +16224, 48884, 48860, +16216, 48904, 48852, +16208, 48918, 48844, +16198, 48930, 48832, +16188, 48942, 48820, +16176, 48954, 48812, +16164, 48964, 48796, +16152, 48974, 48784 +}; + +uint16_t sincos_bf16_poly2_coeffs_m5[2 * 3 * (1 << m5_val)] = // C2, C1, C0 +{ +//sinx +16256, 0, 48680, +16256, 48128, 48680, +16256, 48320, 48680, +16256, 48384, 48680, +16256, 48416, 48680, +16254, 48480, 48680, +16254, 48512, 48680, +16254, 48528, 48680, +16254, 48560, 48680, +16252, 48576, 48680, +16252, 48592, 48680, +16250, 48608, 48680, +16250, 48640, 48672, +16250, 48648, 48672, +16248, 48656, 48672, +16246, 48672, 48672, +16246, 48680, 48672, +16244, 48688, 48664, +16242, 48696, 48664, +16242, 48704, 48664, +16240, 48720, 48664, +16238, 48728, 48664, +16236, 48736, 48656, +16234, 48744, 48656, +16232, 48752, 48656, +16230, 48760, 48648, +16228, 48768, 48648, +16226, 48776, 48648, +16224, 48780, 48640, +16222, 48784, 48640, +16220, 48788, 48640, +16218, 48792, 48624, +//cos +16256, 0, 48896, +16256, 48384, 48896, +16256, 48512, 48896, +16254, 48576, 48896, +16254, 48640, 48892, +16252, 48672, 48892, +16252, 48704, 48892, +16250, 48736, 48888, +16248, 48768, 48888, +16246, 48784, 48884, +16244, 48796, 48884, +16242, 48812, 48880, +16238, 48828, 48876, +16236, 48844, 48872, +16232, 48856, 48872, +16228, 48872, 48868, +16224, 48884, 48864, +16220, 48898, 48860, +16216, 48904, 48856, +16212, 48912, 48848, +16208, 48918, 48844, +16202, 48924, 48840, +16198, 48930, 48836, +16192, 48936, 48832, +16188, 48942, 48824, +16182, 48948, 48820, +16176, 48954, 48812, +16170, 48960, 48808, +16164, 48964, 48800, +16158, 48970, 48796, +16152, 48974, 48788, +16144, 48980, 48780 +}; + +uint16_t sincos_bf16_poly2_coeffs_m6[2 * 3 * (1 << m6_val)] = // C2, C1, C0 +{ +//sinx +16256, 0, 48680, +16256, 48128, 48680, +16256, 48128, 48680, +16256, 48256, 48680, +16256, 48320, 48680, +16256, 48320, 48680, +16256, 48384, 48680, +16256, 48416, 48680, +16256, 48416, 48680, +16256, 48448, 48680, +16254, 48480, 48680, +16254, 48480, 48680, +16254, 48512, 48680, +16254, 48528, 48680, +16254, 48528, 48680, +16254, 48544, 48680, +16254, 48560, 48680, +16254, 48560, 48680, +16252, 48576, 48680, +16252, 48592, 48680, +16252, 48592, 48680, +16252, 48608, 48680, +16250, 48608, 48680, +16250, 48624, 48672, +16250, 48640, 48672, +16250, 48640, 48672, +16250, 48648, 48672, +16248, 48656, 48672, +16248, 48656, 48672, +16248, 48664, 48672, +16246, 48672, 48672, +16246, 48672, 48672, +16246, 48680, 48672, +16244, 48680, 48672, +16244, 48688, 48672, +16244, 48696, 48664, +16242, 48696, 48664, +16242, 48704, 48664, +16242, 48704, 48664, +16240, 48712, 48664, +16240, 48720, 48664, +16238, 48720, 48664, +16238, 48728, 48664, +16238, 48728, 48656, +16236, 48736, 48656, +16236, 48744, 48656, +16234, 48744, 48656, +16234, 48752, 48656, +16232, 48752, 48656, +16232, 48760, 48656, +16230, 48760, 48648, +16230, 48768, 48648, +16228, 48768, 48648, +16228, 48772, 48648, +16226, 48776, 48648, +16226, 48776, 48648, +16224, 48780, 48648, +16224, 48780, 48640, +16222, 48784, 48640, +16222, 48784, 48640, +16220, 48788, 48640, +16218, 48788, 48640, +16218, 48792, 48640, +16216, 48792, 48624, +//cos +16256, 0, 48896, +16256, 48256, 48896, +16256, 48384, 48896, +16256, 48448, 48896, +16256, 48512, 48896, +16256, 48544, 48896, +16254, 48576, 48896, +16254, 48608, 48896, +16254, 48640, 48892, +16254, 48656, 48892, +16252, 48672, 48892, +16252, 48688, 48892, +16252, 48704, 48892, +16250, 48720, 48892, +16250, 48736, 48888, +16250, 48752, 48888, +16248, 48768, 48888, +16248, 48776, 48888, +16246, 48784, 48884, +16244, 48788, 48884, +16244, 48796, 48884, +16242, 48804, 48880, +16242, 48812, 48880, +16240, 48820, 48880, +16238, 48828, 48876, +16236, 48836, 48876, +16236, 48844, 48876, +16234, 48848, 48872, +16232, 48856, 48872, +16230, 48864, 48868, +16228, 48872, 48868, +16226, 48880, 48864, +16224, 48884, 48864, +16222, 48892, 48860, +16220, 48898, 48860, +16218, 48902, 48856, +16216, 48904, 48856, +16214, 48908, 48852, +16212, 48912, 48852, +16210, 48914, 48848, +16208, 48918, 48848, +16206, 48922, 48844, +16202, 48924, 48840, +16200, 48928, 48840, +16198, 48930, 48836, +16196, 48934, 48832, +16192, 48936, 48832, +16190, 48940, 48828, +16188, 48942, 48824, +16184, 48946, 48824, +16182, 48948, 48820, +16178, 48952, 48816, +16176, 48954, 48816, +16174, 48956, 48812, +16170, 48960, 48808, +16168, 48962, 48804, +16164, 48964, 48804, +16162, 48968, 48800, +16158, 48970, 48796, +16154, 48972, 48792, +16152, 48974, 48788, +16148, 48976, 48788, +16144, 48978, 48784, +16142, 48982, 48780 +}; + +// sincos +// sinx_default_coeffs_m4_01 followed by +// cos_default_coeffs_m4_01 +uint16_t sincos_coeffs_bf16[3 * 32] = +{ + 0x3c00u, 0x0000u, 0xb158u, + 0x3bfeu, 0xa540u, 0xb1f8u, + 0x3bfau, 0xa960u, 0xb088u, + 0x3bf4u, 0xac00u, 0xb0d8u, + 0x3beau, 0xad50u, 0xb0d8u, + 0x3bdeu, 0xaea0u, 0xb070u, + 0x3bd0u, 0xafe0u, 0xb190u, + 0x3bc0u, 0xb098u, 0xb008u, + 0x3bacu, 0xb130u, 0xb1d8u, + 0x3b96u, 0xb1d0u, 0xb0d8u, + 0x3b7eu, 0xb268u, 0xb100u, + 0x3b62u, 0xb300u, 0xb028u, + 0x3b46u, 0xb390u, 0xb048u, + 0x3b26u, 0xb410u, 0xae80u, + 0x3b04u, 0xb450u, 0xb108u, + 0x3ae0u, 0xb494u, 0xaf10u, + 0x3c00u, 0x0000u, 0xb800u, + 0x3bfcu, 0xac00u, 0xb7f4u, + 0x3bf0u, 0xb000u, 0xb7a0u, + 0x3bdcu, 0xb1f8u, 0xb7c4u, + 0x3bc0u, 0xb3e8u, 0xb810u, + 0x3b9cu, 0xb4ecu, 0xb778u, + 0x3b72u, 0xb5dcu, 0xb790u, + 0x3b40u, 0xb6c8u, 0xb728u, + 0x3b06u, 0xb7acu, 0xb704u, + 0x3ac4u, 0xb844u, 0xb6f0u, + 0x3a7cu, 0xb8aeu, 0xb6b4u, + 0x3a2eu, 0xb914u, 0xb61cu, + 0x39dau, 0xb974u, 0xb5f0u, + 0x3980u, 0xb9d0u, 0xb508u, + 0x3920u, 0xba24u, 0xb530u, + 0x38bcu, 0xba74u, 0xb444u +}; + + +////// FP16 ////// + + +// ========== GL log2 poly2 approximation (m = 3) =================== + +// log2 zero_exp followed by non_zero exp + +uint16_t log2_coeffs_fp16[3 * 16] = +{ + 0x3dc5u, 0xb9c0u, 0x36bcu, + 0x3d70u, 0xb8eau, 0x353cu, + 0x3d27u, 0xb844u, 0x3428u, + 0x3ce7u, 0xb77cu, 0x32c0u, + 0x3caeu, 0xb6a4u, 0x3198u, + 0x3c7cu, 0xb5f4u, 0x30b0u, + 0x3c4eu, 0xb560u, 0x2ff0u, + 0x3c25u, 0xb4e0u, 0x2ec0u, + 0x0000u, 0x3dc2u, 0xb920u, + 0x3170u, 0x3d1fu, 0xb81au, + 0x3528u, 0x3c9cu, 0xb6b4u, + 0x3758u, 0x3c31u, 0xb598u, + 0x38aeu, 0x3bb0u, 0xb4bcu, + 0x399au, 0x3b18u, 0xb410u, + 0x3a76u, 0x3a96u, 0xb308u, + 0x3b42u, 0x3a26u, 0xb228u +}; + +// ========== GL pow2 poly2 approximation (m = 2) =================== + +uint16_t pow2_coeffs_fp16[3 * 4] = +{ + 0x3c00u, 0x3988u, 0x3430u, + 0x3cc2u, 0x3a94u, 0x34fcu, + 0x3da8u, 0x3bd2u, 0x35f0u, + 0x3ebau, 0x3ca6u, 0x3710u +}; + +// ========== GL recip poly2 approximations (m = 3) =================== + +uint16_t recip_coeffs_fp16[8 * 3] = +{ + 0x3c00u, 0xbbf2u, 0x3ab2u, + 0x3b1cu, 0xba48u, 0x38ccu, + 0x3a66u, 0xb918u, 0x3718u, + 0x39d2u, 0xb836u, 0x3568u, + 0x3956u, 0xb718u, 0x3434u, + 0x38ecu, 0xb60cu, 0x32a8u, + 0x3892u, 0xb538u, 0x3160u, + 0x3844u, 0xb48cu, 0x3068u +}; + +// ========== GL rsqrt poly2 approximations (m = 3) =================== +// rsqrt_default_coeffs_m3_12 followed by rsqrt_default_coeffs_m3_24 +uint16_t rsqrt_coeffs_fp16[3 * 16] = +{ + 0x3c00u, 0xb7f8u, 0x352cu, + 0x3b8au, 0xb6acu, 0x33d8u, + 0x3b28u, 0xb5b4u, 0x3218u, + 0x3ad2u, 0xb4f4u, 0x30d8u, + 0x3a88u, 0xb458u, 0x2fe0u, + 0x3a46u, 0xb3b8u, 0x2e80u, + 0x3a0cu, 0xb2e8u, 0x2d70u, + 0x39d8u, 0xb238u, 0x2ca0u, + 0x39a8u, 0xb1a0u, 0x2b60u, + 0x3956u, 0xb0b8u, 0x2980u, + 0x3910u, 0xb008u, 0x2840u, + 0x38d2u, 0xaf00u, 0x26c0u, + 0x389eu, 0xae20u, 0x2580u, + 0x3870u, 0xad70u, 0x2480u, + 0x3846u, 0xace0u, 0x2380u, + 0x3822u, 0xac60u, 0x2280u +}; + +// ========== GL sqrt poly2 approximations (m = 2) =================== +// sqrt_default_coeffs_m2_12 followed by sqrt_default_coeffs_m2_24 +uint16_t sqrt_coeffs_fp16[3 * 8] = +{ + 0x3c00u, 0x37f8u, 0xaec0u, + 0x3c79u, 0x3724u, 0xad00u, + 0x3ce6u, 0x3684u, 0xabc0u, + 0x3d4bu, 0x360cu, 0xaa40u, + 0x3da8u, 0x35a4u, 0xa8c0u, + 0x3e53u, 0x350cu, 0xa700u, + 0x3eeeu, 0x349cu, 0xa580u, + 0x3f7cu, 0x3444u, 0xa480u +}; + +// tanh +// tanhx_default_coeffs_m4_01 followed by +// tanh_default_coeffs_m4_12 followed by +// tanh_default_coeffs_m4_24 followed by +// tanh_default_coeffs_m4_48 + +uint16_t tanh_coeffs_fp16[3 * 64] = +{ + 0x3c00u, 0x0000u, 0xb550u, + 0x3bfeu, 0xa960u, 0xb538u, + 0x3bf6u, 0xad40u, 0xb508u, + 0x3be8u, 0xafd0u, 0xb4c0u, + 0x3bd6u, 0xb118u, 0xb464u, + 0x3bc0u, 0xb230u, 0xb3f8u, + 0x3ba6u, 0xb330u, 0xb310u, + 0x3b86u, 0xb408u, 0xb220u, + 0x3b64u, 0xb46cu, 0xb120u, + 0x3b40u, 0xb4bcu, 0xb028u, + 0x3b1au, 0xb500u, 0xae70u, + 0x3af0u, 0xb534u, 0xacb0u, + 0x3ac6u, 0xb558u, 0xaa20u, + 0x3a9cu, 0xb570u, 0xa640u, + 0x3a70u, 0xb57cu, 0x9c00u, + 0x3a44u, 0xb580u, 0x2300u, + 0x3a18u, 0x36b8u, 0xb4f4u, + 0x3a4au, 0x3618u, 0xb4a4u, + 0x3a7au, 0x3584u, 0xb44cu, + 0x3aa4u, 0x34fcu, 0xb3f0u, + 0x3acau, 0x347cu, 0xb348u, + 0x3aecu, 0x3408u, 0xb2a8u, + 0x3b0au, 0x3338u, 0xb210u, + 0x3b26u, 0x3278u, 0xb180u, + 0x3b3eu, 0x31c8u, 0xb0f8u, + 0x3b54u, 0x3128u, 0xb080u, + 0x3b68u, 0x3098u, 0xb008u, + 0x3b78u, 0x3018u, 0xaf40u, + 0x3b88u, 0x2f40u, 0xae80u, + 0x3b96u, 0x2e70u, 0xadd0u, + 0x3ba2u, 0x2dc0u, 0xad30u, + 0x3bacu, 0x2d10u, 0xaca0u, + 0x3bb6u, 0x2c80u, 0xabc0u, + 0x3bc6u, 0x2b20u, 0xaa20u, + 0x3bd4u, 0x2980u, 0xa8e0u, + 0x3bdcu, 0x2860u, 0xa780u, + 0x3be4u, 0x26c0u, 0xa600u, + 0x3beau, 0x2540u, 0xa4c0u, + 0x3bf0u, 0x2440u, 0xa380u, + 0x3bf4u, 0x2280u, 0xa180u, + 0x3bf6u, 0x2100u, 0xa080u, + 0x3bf8u, 0x2000u, 0x9f00u, + 0x3bfau, 0x1e00u, 0x9d00u, + 0x3bfcu, 0x1d00u, 0x9c00u, + 0x3bfcu, 0x1c00u, 0x9a00u, + 0x3bfeu, 0x1a00u, 0x9a00u, + 0x3bfeu, 0x1800u, 0x9800u, + 0x3bfeu, 0x1800u, 0x9800u, + 0x3bfeu, 0x1400u, 0x9400u, + 0x3c00u, 0x1400u, 0x9400u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u, + 0x3c00u, 0x0000u, 0x0000u +}; + +// sincos +// sinx_default_coeffs_m4_01 followed by +// cos_default_coeffs_m4_01 +uint16_t sincos_coeffs_fp16[3 * 32] = +{ + 0x3c00u, 0x0000u, 0xb158u, + 0x3bfeu, 0xa540u, 0xb1f8u, + 0x3bfau, 0xa960u, 0xb088u, + 0x3bf4u, 0xac00u, 0xb0d8u, + 0x3beau, 0xad50u, 0xb0d8u, + 0x3bdeu, 0xaea0u, 0xb070u, + 0x3bd0u, 0xafe0u, 0xb190u, + 0x3bc0u, 0xb098u, 0xb008u, + 0x3bacu, 0xb130u, 0xb1d8u, + 0x3b96u, 0xb1d0u, 0xb0d8u, + 0x3b7eu, 0xb268u, 0xb100u, + 0x3b62u, 0xb300u, 0xb028u, + 0x3b46u, 0xb390u, 0xb048u, + 0x3b26u, 0xb410u, 0xae80u, + 0x3b04u, 0xb450u, 0xb108u, + 0x3ae0u, 0xb494u, 0xaf10u, + 0x3c00u, 0x0000u, 0xb800u, + 0x3bfcu, 0xac00u, 0xb7f4u, + 0x3bf0u, 0xb000u, 0xb7a0u, + 0x3bdcu, 0xb1f8u, 0xb7c4u, + 0x3bc0u, 0xb3e8u, 0xb810u, + 0x3b9cu, 0xb4ecu, 0xb778u, + 0x3b72u, 0xb5dcu, 0xb790u, + 0x3b40u, 0xb6c8u, 0xb728u, + 0x3b06u, 0xb7acu, 0xb704u, + 0x3ac4u, 0xb844u, 0xb6f0u, + 0x3a7cu, 0xb8aeu, 0xb6b4u, + 0x3a2eu, 0xb914u, 0xb61cu, + 0x39dau, 0xb974u, 0xb5f0u, + 0x3980u, 0xb9d0u, 0xb508u, + 0x3920u, 0xba24u, 0xb530u, + 0x38bcu, 0xba74u, 0xb444u +}; + +// Tanh int16_t for 0-8: 64 intervals +uint16_t tanh_coeffs_int16_0_8[3 * 64] = { + 0x0u, 0x4030u, 0xf022u, 0xfeau, 0x3f2du, 0xd254u, 0x1f59u, 0x3c4au, 0xb9ceu, 0x2ddeu, 0x37ddu, 0xa8b2u, 0x3b27u, + 0x325eu, 0x9f9au, 0x46fdu, 0x2c50u, 0x9dc6u, 0x514du, 0x2626u, 0xa1aau, 0x5a1au, 0x203du, 0xa966u, 0x617cu, 0x1ad2u, + 0xb340u, 0x6797u, 0x1605u, 0xbdd6u, 0x6c95u, 0x11e3u, 0xc832u, 0x709eu, 0xe68u, 0xd1bcu, 0x73dcu, 0xb85u, 0xda28u, + 0x7672u, 0x929u, 0xe160u, 0x787fu, 0x741u, 0xe76eu, 0x7a1eu, 0x5b9u, 0xec68u, 0x7b65u, 0x480u, 0xf076u, 0x7c66u, + 0x389u, 0xf3bau, 0x7d30u, 0x2c5u, 0xf656u, 0x7dceu, 0x22bu, 0xf868u, 0x7e49u, 0x1b2u, 0xfa0cu, 0x7eaau, 0x153u, + 0xfb56u, 0x7ef5u, 0x109u, 0xfc5au, 0x7f30u, 0xceu, 0xfd26u, 0x7f5eu, 0xa1u, 0xfdc6u, 0x7f82u, 0x7eu, 0xfe44u, + 0x7f9eu, 0x62u, 0xfea6u, 0x7fb3u, 0x4cu, 0xfef2u, 0x7fc4u, 0x3cu, 0xff2eu, 0x7fd1u, 0x2eu, 0xff5cu, 0x7fdcu, + 0x24u, 0xff80u, 0x7fe4u, 0x1cu, 0xff9cu, 0x7feau, 0x16u, 0xffb2u, 0x7fefu, 0x11u, 0xffc4u, 0x7ff3u, 0xeu, + 0xffd0u, 0x7ff6u, 0xbu, 0xffdcu, 0x7ff8u, 0x8u, 0xffe4u, 0x7ffau, 0x7u, 0xffeau, 0x7ffbu, 0x5u, 0xffeeu, + 0x7ffcu, 0x4u, 0xfff2u, 0x7ffdu, 0x3u, 0xfff6u, 0x7ffeu, 0x3u, 0xfff8u, 0x7ffeu, 0x2u, 0xfffau, 0x7fffu, + 0x2u, 0xfffcu, 0x7fffu, 0x1u, 0xfffcu, 0x7fffu, 0x1u, 0xfffcu, 0x7fffu, 0x1u, 0xfffeu, 0x7fffu, 0x1u, + 0xfffeu, 0x7fffu, 0x1u, 0xfffeu, 0x7fffu, 0x1u, 0xfffeu, 0x7fffu, 0x0u, 0x0u, 0x7fffu, 0x0u, 0x0u, + 0x7fffu, 0x0u, 0x0u, 0x7fffu, 0x0u, 0x0u, 0x7fffu, 0x0u, 0x0u, 0x7fffu, 0x0u, 0x0u, 0x7fffu, + 0x0u, 0x0u, 0x7fffu, 0x0u, 0x0u, 0x7fffu, 0x0u, 0x0u, 0x7fffu, 0x0u, 0x0u, 0x7fffu, 0x0u, + 0x0u, 0x7fffu, 0x0u, 0x0u, 0x7fffu, 0x0u, 0x0u, 0x7fffu, 0x0u, 0x0u, +}; + +//int32_t qfC0_sigmoid = -15; +//int32_t qfC1_sigmoid = -16; +//int32_t qfC2_sigmoid = -19; +// Sigmoid int16_t for 0-8: 64 intervals +uint16_t sigmoid_coeffs_int16_0_8[3 * 64] = +{ + 0x4000u, 0x400cu, 0xf800u, + 0x43ffu, 0x3fccu, 0xe850u, + 0x47f5u, 0x3f0eu, 0xd950u, + 0x4bdcu, 0x3dd8u, 0xcb80u, + 0x4fadu, 0x3c32u, 0xbf30u, + 0x5360u, 0x3a2au, 0xb4a0u, + 0x56efu, 0x37ceu, 0xac10u, + 0x5a57u, 0x352cu, 0xa580u, + 0x5d93u, 0x3258u, 0xa100u, + 0x60a1u, 0x2f5eu, 0x9e60u, + 0x637fu, 0x2c50u, 0x9d80u, + 0x662bu, 0x293cu, 0x9e30u, + 0x68a6u, 0x262cu, 0xa030u, + 0x6af1u, 0x232eu, 0xa340u, + 0x6d0du, 0x2046u, 0xa720u, + 0x6efbu, 0x1d80u, 0xabb0u, + 0x70beu, 0x1adeu, 0xb0a0u, + 0x7258u, 0x1862u, 0xb5e0u, + 0x73ccu, 0x1612u, 0xbb30u, + 0x751bu, 0x13eau, 0xc080u, + 0x764au, 0x11eeu, 0xc5b0u, + 0x775bu, 0x101cu, 0xcab0u, + 0x784fu, 0xe72u, 0xcf70u, + 0x792au, 0xceeu, 0xd400u, + 0x79eeu, 0xb8eu, 0xd830u, + 0x7a9du, 0xa50u, 0xdc20u, + 0x7b39u, 0x930u, 0xdfb0u, + 0x7bc4u, 0x82eu, 0xe300u, + 0x7c40u, 0x746u, 0xe610u, + 0x7cadu, 0x678u, 0xe8d0u, + 0x7d0fu, 0x5beu, 0xeb40u, + 0x7d66u, 0x518u, 0xed80u, + 0x7db3u, 0x484u, 0xef90u, + 0x7df7u, 0x400u, 0xf160u, + 0x7e33u, 0x38cu, 0xf300u, + 0x7e69u, 0x324u, 0xf470u, + 0x7e98u, 0x2c8u, 0xf5c0u, + 0x7ec2u, 0x276u, 0xf6f0u, + 0x7ee7u, 0x22cu, 0xf7f0u, + 0x7f08u, 0x1ecu, 0xf8e0u, + 0x7f25u, 0x1b4u, 0xf9b0u, + 0x7f3eu, 0x180u, 0xfa60u, + 0x7f55u, 0x154u, 0xfb10u, + 0x7f69u, 0x12cu, 0xfba0u, + 0x7f7bu, 0x10au, 0xfc20u, + 0x7f8au, 0xeau, 0xfc90u, + 0x7f98u, 0xceu, 0xfd00u, + 0x7fa4u, 0xb6u, 0xfd50u, + 0x7fafu, 0xa2u, 0xfda0u, + 0x7fb8u, 0x8eu, 0xfdf0u, + 0x7fc1u, 0x7eu, 0xfe20u, + 0x7fc8u, 0x70u, 0xfe60u, + 0x7fcfu, 0x62u, 0xfe90u, + 0x7fd5u, 0x56u, 0xfec0u, + 0x7fdau, 0x4cu, 0xfee0u, + 0x7fdeu, 0x44u, 0xff00u, + 0x7fe2u, 0x3cu, 0xff20u, + 0x7fe6u, 0x34u, 0xff40u, + 0x7fe9u, 0x2eu, 0xff50u, + 0x7febu, 0x28u, 0xff60u, + 0x7feeu, 0x24u, 0xff80u, + 0x7ff0u, 0x20u, 0xff80u, + 0x7ff2u, 0x1cu, 0xff90u, + 0x7ff4u, 0x18u, 0xffa0u +}; + +//int32_t qfC0_exp = -15; +//int32_t qfC1_exp = -15; +//int32_t qfC2_exp = -16; +// int expX = -11 +// Exp(-x) int16_t for x in 0-16 (expX = -11): 64 intervals +uint16_t expminusx_coeffs_int16_0_16[3 * 64] = { + 0x7ffeu, 0x80adu, 0x712cu, + 0x63aeu, 0x9cd7u, 0x5823u, + 0x4da1u, 0xb2c6u, 0x44a9u, + 0x3c75u, 0xc3dbu, 0x357cu, + 0x2f16u, 0xd129u, 0x29a1u, + 0x24abu, 0xdb85u, 0x2079u, + 0x1c8fu, 0xe397u, 0x1943u, + 0x163eu, 0xe9e0u, 0x13a5u, + 0x1152u, 0xeec5u, 0xf49u, + 0xd7eu, 0xf295u, 0xbdeu, + 0xa81u, 0xf58cu, 0x958u, + 0x82fu, 0xf7dcu, 0x745u, + 0x65fu, 0xf9a9u, 0x5a9u, + 0x4f6u, 0xfb10u, 0x468u, + 0x3ddu, 0xfc28u, 0x362u, + 0x302u, 0xfd01u, 0x2b7u, + 0x258u, 0xfdabu, 0x213u, + 0x1d3u, 0xfe2fu, 0x19fu, + 0x16cu, 0xfe96u, 0x13fu, + 0x11bu, 0xfee6u, 0xfbu, + 0xddu, 0xff24u, 0xcfu, + 0xacu, 0xff55u, 0x97u, + 0x86u, 0xff7bu, 0x70u, + 0x68u, 0xff98u, 0x64u, + 0x51u, 0xffafu, 0x4eu, + 0x3fu, 0xffc1u, 0x3au, + 0x31u, 0xffcfu, 0x2bu, + 0x26u, 0xffdau, 0x1du, + 0x1eu, 0xffe2u, 0x23u, + 0x17u, 0xffe9u, 0x10u, + 0x12u, 0xffeeu, 0xfu, + 0xeu, 0xfff2u, 0xbu, + 0xbu, 0xfff5u, 0xcu, + 0x8u, 0xfff7u, 0x17u, + 0x7u, 0xfff9u, 0x12u, + 0x5u, 0xfffbu, 0xffffu, + 0x4u, 0xfffcu, 0x3u, + 0x3u, 0xfffdu, 0xffffu, + 0x3u, 0xfffeu, 0xfff4u, + 0x2u, 0xfffeu, 0x5u, + 0x2u, 0xffffu, 0xfff2u, + 0x1u, 0xffffu, 0xfffcu, + 0x1u, 0xffffu, 0x4u, + 0x1u, 0xffffu, 0xau, + 0x0u, 0xffffu, 0xfu, + 0x1u, 0x0u, 0xfff3u, + 0x0u, 0x0u, 0xfff6u, + 0x0u, 0x0u, 0xfff8u, + 0x0u, 0x0u, 0xfffau, + 0x0u, 0x0u, 0xfffbu, + 0x0u, 0x0u, 0xfffcu, + 0x0u, 0x0u, 0xfffdu, + 0x0u, 0x0u, 0xfffeu, + 0x0u, 0x0u, 0xfffeu, + 0x0u, 0x0u, 0xffffu, + 0x0u, 0x0u, 0xffffu, + 0x0u, 0x0u, 0xffffu, + 0x0u, 0x0u, 0xffffu, + 0x0u, 0x0u, 0xffffu, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, +}; + + + +//int32_t qfC0_recip = -15; +//int32_t qfC1_recip = -15; +//int32_t qfC2_recip = -15; +// int expX = -11 +// 1/x int16_t for x in 1-4: 64 intervals +// The intervals go from 0 to 4, but the intervals from 0 to 1 are zeros +uint16_t recip_coeffs_int16_1_4[3 * 64] = { + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x7fffu, 0x8041u, 0x74d9u, + 0x7878u, 0x8ed1u, 0x61edu, + 0x71c7u, 0x9b06u, 0x52e2u, + 0x6bcau, 0xa55cu, 0x46c4u, + 0x6666u, 0xae30u, 0x3ce6u, + 0x6186u, 0xb5c9u, 0x34c9u, + 0x5d17u, 0xbc5fu, 0x2e0eu, + 0x590bu, 0xc21eu, 0x286du, + 0x5555u, 0xc72au, 0x23abu, + 0x51ebu, 0xcb9eu, 0x1fa1u, + 0x4ec5u, 0xcf91u, 0x1c2eu, + 0x4bdau, 0xd315u, 0x1939u, + 0x4925u, 0xd63bu, 0x16aau, + 0x469fu, 0xd910u, 0x146du, + 0x4444u, 0xdb9du, 0x127cu, + 0x4210u, 0xddecu, 0x10c7u, + 0x4000u, 0xe004u, 0xf48u, + 0x3e0fu, 0xe1edu, 0xdf2u, + 0x3c3cu, 0xe3abu, 0xcc5u, + 0x3a84u, 0xe543u, 0xbb9u, + 0x38e4u, 0xe6bau, 0xac9u, + 0x375au, 0xe813u, 0x9f1u, + 0x35e5u, 0xe951u, 0x930u, + 0x3483u, 0xea77u, 0x882u, + 0x3333u, 0xeb87u, 0x7e4u, + 0x31f4u, 0xec83u, 0x757u, + 0x30c3u, 0xed6eu, 0x6d5u, + 0x2fa1u, 0xee48u, 0x660u, + 0x2e8cu, 0xef14u, 0x5f4u, + 0x2d83u, 0xefd3u, 0x590u, + 0x2c86u, 0xf085u, 0x536u, + 0x2b93u, 0xf12bu, 0x4e6u, + 0x2aabu, 0xf1c8u, 0x499u, + 0x29ccu, 0xf25bu, 0x453u, + 0x28f6u, 0xf2e5u, 0x413u, + 0x2828u, 0xf368u, 0x3d5u, + 0x2762u, 0xf3e2u, 0x3a1u, + 0x26a4u, 0xf456u, 0x36du, + 0x25edu, 0xf4c4u, 0x33du, + 0x253du, 0xf52bu, 0x312u, + 0x2492u, 0xf58eu, 0x2e7u, + 0x23eeu, 0xf5ebu, 0x2c1u, + 0x234fu, 0xf643u, 0x29eu, + 0x22b6u, 0xf697u, 0x27cu, + 0x2222u, 0xf6e6u, 0x25fu, + 0x2193u, 0xf732u, 0x241u, + 0x2108u, 0xf77au, 0x226u, + 0x2082u, 0xf7bfu, 0x20cu, +}; + +// uint8 sqrt values scaled by 16 - used for LOOKUP instruction test +uint8_t sqrt_coeffs_int8_scale_1_16[256] = {0, 16, 23, 28, 32, 36, 39, 42, 45, 48, 51, 53, 55, 58, 60, 62, 64, 66, 68, 70, 72, 73, 75, 77, 78, 80, 82, 83, 85, 86, 88, 89, 91, 92, 93, 95, 96, 97, 99, 100, 101, 102, 104, 105, 106, 107, 109, 110, 111, 112, 113, 114, 115, 116, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 148, 149, 150, 151, 152, 153, 153, 154, 155, 156, 157, 158, 158, 159, 160, 161, 162, 162, 163, 164, 165, 166, 166, 167, 168, 169, 169, 170, 171, 172, 172, 173, 174, 175, 175, 176, 177, 177, 178, 179, 180, 180, 181, 182, 182, 183, 184, 185, 185, 186, 187, 187, 188, 189, 189, 190, 191, 191, 192, 193, 193, 194, 195, 195, 196, 197, 197, 198, 199, 199, 200, 200, 201, 202, 202, 203, 204, 204, 205, 206, 206, 207, 207, 208, 209, 209, 210, 210, 211, 212, 212, 213, 213, 214, 215, 215, 216, 216, 217, 218, 218, 219, 219, 220, 221, 221, 222, 222, 223, 223, 224, 225, 225, 226, 226, 227, 227, 228, 229, 229, 230, 230, 231, 231, 232, 232, 233, 234, 234, 235, 235, 236, 236, 237, 237, 238, 238, 239, 239, 240, 241, 241, 242, 242, 243, 243, 244, 244, 245, 245, 246, 246, 247, 247, 248, 248, 249, 249, 250, 250, 251, 251, 252, 252, 253, 253, 254, 254, 255, 255}; +uint16_t square_coeffs_uint16[] = { 0,1,4,9,16,25,36,49,64,81,100,121,144,169,196,225,256,289,324,361,400,441,484,529,576,625,676,729,784,841,900,961,1024,1089,1156,1225,1296,1369,1444,1521,1600,1681,1764,1849,1936,2025,2116,2209,2304,2401,2500,2601,2704,2809,2916,3025,3136,3249,3364,3481,3600,3721,3844,3969,4096,4225,4356,4489,4624,4761,4900,5041,5184,5329,5476,5625,5776,5929,6084,6241,6400,6561,6724,6889,7056,7225,7396,7569,7744,7921,8100,8281,8464,8649,8836,9025,9216,9409,9604,9801,10000,10201,10404,10609,10816,11025,11236,11449,11664,11881,12100,12321,12544,12769,12996,13225,13456,13689,13924,14161,14400,14641,14884,15129,15376,15625,15876,16129,16384,16641,16900,17161,17424,17689,17956,18225,18496,18769,19044,19321,19600,19881,20164,20449,20736,21025,21316,21609,21904,22201,22500,22801,23104,23409,23716,24025,24336,24649,24964,25281,25600,25921,26244,26569,26896,27225,27556,27889,28224,28561,28900,29241,29584,29929,30276,30625,30976,31329,31684,32041,32400,32761,33124,33489,33856,34225,34596,34969,35344,35721,36100,36481,36864,37249,37636,38025,38416,38809,39204,39601,40000,40401,40804,41209,41616,42025,42436,42849,43264,43681,44100,44521,44944,45369,45796,46225,46656,47089,47524,47961,48400,48841,49284,49729,50176,50625,51076,51529,51984,52441,52900,53361,53824,54289,54756,55225,55696,56169,56644,57121,57600,58081,58564,59049,59536,60025,60516,61009,61504,62001,62500,63001,63504,64009,64516,65025 }; +uint32_t power4_coeffs_uint32[] = { 0,1,16,81,256,625,1296,2401,4096,6561,10000,14641,20736,28561,38416,50625,65536,83521,104976,130321,160000,194481,234256,279841,331776,390625,456976,531441,614656,707281,810000,923521,1048576,1185921,1336336,1500625,1679616,1874161,2085136,2313441,2560000,2825761,3111696,3418801,3748096,4100625,4477456,4879681,5308416,5764801,6250000,6765201,7311616,7890481,8503056,9150625,9834496,10556001,11316496,12117361,12960000,13845841,14776336,15752961,16777216,17850625,18974736,20151121,21381376,22667121,24010000,25411681,26873856,28398241,29986576,31640625,33362176,35153041,37015056,38950081,40960000,43046721,45212176,47458321,49787136,52200625,54700816,57289761,59969536,62742241,65610000,68574961,71639296,74805201,78074896,81450625,84934656,88529281,92236816,96059601,100000000,104060401,108243216,112550881,116985856,121550625,126247696,131079601,136048896,141158161,146410000,151807041,157351936,163047361,168896016,174900625,181063936,187388721,193877776,200533921,207360000,214358881,221533456,228886641,236421376,244140625,252047376,260144641,268435456,276922881,285610000,294499921,303595776,312900721,322417936,332150625,342102016,352275361,362673936,373301041,384160000,395254161,406586896,418161601,429981696,442050625,454371856,466948881,479785216,492884401,506250000,519885601,533794816,547981281,562448656,577200625,592240896,607573201,623201296,639128961,655360000,671898241,688747536,705911761,723394816,741200625,759333136,777796321,796594176,815730721,835210000,855036081,875213056,895745041,916636176,937890625,959512576,981506241,1003875856,1026625681,1049760000,1073283121,1097199376,1121513121,1146228736,1171350625,1196883216,1222830961,1249198336,1275989841,1303210000,1330863361,1358954496,1387488001,1416468496,1445900625,1475789056,1506138481,1536953616,1568239201,1600000000,1632240801,1664966416,1698181681,1731891456,1766100625,1800814096,1836036801,1871773696,1908029761,1944810000,1982119441,2019963136,2058346161,2097273616,2136750625,2176782336,2217373921,2258530576,2300257521,2342560000,2385443281,2428912656,2472973441,2517630976,2562890625,2608757776,2655237841,2702336256,2750058481,2798410000,2847396321,2897022976,2947295521,2998219536,3049800625,3102044416,3154956561,3208542736,3262808641,3317760000,3373402561,3429742096,3486784401,3544535296,3603000625,3662186256,3722098081,3782742016,3844124001,3906250000,3969126001,4032758016,4097152081,4162314256,4228250625 }; + +// C0, C1, C2 +// expC0 = -7, expC1 = -6, expC2 = -8 +int8_t tanh_coeffs_int8[] = { + 0 , 64, -16, + 16 , 63, -46, + 31 , 60, -70, + 46 , 56, -87, + 59 , 50, -96, + 71 , 44, -98, + 81 , 38, -94, + 90 , 32, -87, + 97 , 27, -77, + 104 , 22, -66, + 109 , 18, -56, + 113 , 14, -46, + 116 , 12, -38, + 118 , 9 , -31 , + 120 , 7 , -25 , + 122 , 6 , -20 , + 123 , 5 , -16 , + 124 , 4 , -12 , + 125 , 3 , -10 , + 126 , 2 , -8 , + 126 , 2 , -6 , + 127 , 1 , -5 , + 127 , 1 , -4 , + 127 , 1 , -3 , + 127 , 1 , -2 , + 127 , 0 , -2 , + 127 , 0 , -1 , + 127 , 0 , -1 , + 127 , 0 , -1 , + 127 , 0 , -1 , + 127 , 0 , -1 , + 127 , 0 , 0 +}; + +int8_t tanh_coeffs_int8_linear[] = { +// C0 (not used), C1 (used as C0), C2 (used as C1) +// Exponents: -7, -7 + 0, 0, 127, + 0, 16, 123, + 0, 31, 120, + 0, 46, 106, + 0, 59, 95 , + 0, 71, 82 , + 0, 81, 72 , + 0, 90, 59 , + 0, 97, 59 , + 0, 104, 39, + 0, 109, 32, + 0, 113, 23, + 0, 116, 21, + 0, 118, 24, + 0, 120, 13, + 0, 122, 10, + 0, 123, 8 , + 0, 124, 8 , + 0, 125, 8 , + 0, 126, 4 , + 0, 126, 3 , + 0, 127, 2 , + 0, 127, 2 , + 0, 127, 1 , + 0, 127, 1 , + 0, 127, 1 , + 0, 127, 1 , + 0, 127, 1 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 +}; + +int8_t sigmoid_coeffs_0_8_linear[] = +{ + // C0 (not used), C1 (used as C0), C2 (used as C1) + // Exponents: -7, -9 + 0, 64, 127, + 0, 68, 127, + 0, 72, 125, + 0, 76, 122, + 0, 80, 100, + 0, 83, 114, + 0, 87, 109, + 0, 90, 107, + 0, 94, 95 , + 0, 97, 92 , + 0, 99, 108, + 0, 102, 79 , + 0, 105, 63 , + 0, 107, 67 , + 0, 109, 64 , + 0, 111, 56 , + 0, 113, 51 , + 0, 114, 46 , + 0, 116, 31 , + 0, 117, 38 , + 0, 118, 34 , + 0, 119, 32 , + 0, 120, 32 , + 0, 121, 32 , + 0, 122, 22 , + 0, 123, 20 , + 0, 123, 32 , + 0, 124, 15 , + 0, 124, 14 , + 0, 125, 12 , + 0, 125, 11 , + 0, 125, 32 , + 0, 126, 9 , + 0, 126, 8 , + 0, 126, 7 , + 0, 126, 32 , + 0, 127, 5 , + 0, 127, 5 , + 0, 127, 4 , + 0, 127, 4 , + 0, 127, 3 , + 0, 127, 3 , + 0, 127, 3 , + 0, 127, 2 , + 0, 127, 2 , + 0, 127, 2 , + 0, 127, 2 , + 0, 127, 1 , + 0, 127, 1 , + 0, 127, 1 , + 0, 127, 1 , + 0, 127, 1 , + 0, 127, 1 , + 0, 127, 1 , + 0, 127, 1 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , + 0, 127, 0 , +}; + +int8_t exp_minusx_0_8_linear[] = { + // C0 (not used), C1 (used as C0), C2 (used as C1) + // Exponents: -7, -7 + 0, 127, -110, + 0, 113, -106, + 0, 100, -94 , + 0, 88 , -83 , + 0, 78 , -73 , + 0, 69 , -73 , + 0, 60 , -55 , + 0, 53 , -50 , + 0, 47 , -44 , + 0, 42 , -40 , + 0, 37 , -40 , + 0, 32 , -30 , + 0, 29 , -27 , + 0, 25 , -23 , + 0, 22 , -21 , + 0, 20 , -24 , + 0, 17 , -16 , + 0, 15 , -14 , + 0, 13 , -7 , + 0, 12 , -11 , + 0, 11 , -10 , + 0, 9 , -7 , + 0, 8 , -7 , + 0, 7 , -7 , + 0, 6 , -7 , + 0, 6 , -8 , + 0, 5 , -5 , + 0, 4 , -4 , + 0, 4 , -4 , + 0, 3 , -3 , + 0, 3 , -3 , + 0, 3 , -8 , + 0, 2 , -2 , + 0, 2 , -2 , + 0, 2 , -2 , + 0, 2 , -2 , + 0, 1 , -1 , + 0, 1 , -1 , + 0, 1 , -1 , + 0, 1 , -1 , + 0, 1 , -1 , + 0, 1 , -1 , + 0, 1 , -1 , + 0, 1 , -1 , + 0, 1 , -8 , + 0, 0, 0 , + 0, 0, 0 , + 0, 0, 0 , + 0, 0, 0 , + 0, 0, 0 , + 0, 0, 0 , + 0, 0, 0 , + 0, 0, 0 , + 0, 0, 0 , + 0, 0, 0 , + 0, 0, 0 , + 0, 0, 0 , + 0, 0, 0 , + 0, 0, 0 , + 0, 0, 0 , + 0, 0, 0 , + 0, 0, 0 , + 0, 0, 0 , + 0, 0, 0 +}; + +uint16_t expminusx_coeffs_int16_0_16_128_entries[3 * 64 * 2] = { + 0x7ffeu, 0x80adu, 0x712cu, + 0x63aeu, 0x9cd7u, 0x5823u, + 0x4da1u, 0xb2c6u, 0x44a9u, + 0x3c75u, 0xc3dbu, 0x357cu, + 0x2f16u, 0xd129u, 0x29a1u, + 0x24abu, 0xdb85u, 0x2079u, + 0x1c8fu, 0xe397u, 0x1943u, + 0x163eu, 0xe9e0u, 0x13a5u, + 0x1152u, 0xeec5u, 0xf49u, + 0xd7eu, 0xf295u, 0xbdeu, + 0xa81u, 0xf58cu, 0x958u, + 0x82fu, 0xf7dcu, 0x745u, + 0x65fu, 0xf9a9u, 0x5a9u, + 0x4f6u, 0xfb10u, 0x468u, + 0x3ddu, 0xfc28u, 0x362u, + 0x302u, 0xfd01u, 0x2b7u, + 0x258u, 0xfdabu, 0x213u, + 0x1d3u, 0xfe2fu, 0x19fu, + 0x16cu, 0xfe96u, 0x13fu, + 0x11bu, 0xfee6u, 0xfbu, + 0xddu, 0xff24u, 0xcfu, + 0xacu, 0xff55u, 0x97u, + 0x86u, 0xff7bu, 0x70u, + 0x68u, 0xff98u, 0x64u, + 0x51u, 0xffafu, 0x4eu, + 0x3fu, 0xffc1u, 0x3au, + 0x31u, 0xffcfu, 0x2bu, + 0x26u, 0xffdau, 0x1du, + 0x1eu, 0xffe2u, 0x23u, + 0x17u, 0xffe9u, 0x10u, + 0x12u, 0xffeeu, 0xfu, + 0xeu, 0xfff2u, 0xbu, + 0xbu, 0xfff5u, 0xcu, + 0x8u, 0xfff7u, 0x17u, + 0x7u, 0xfff9u, 0x12u, + 0x5u, 0xfffbu, 0xffffu, + 0x4u, 0xfffcu, 0x3u, + 0x3u, 0xfffdu, 0xffffu, + 0x3u, 0xfffeu, 0xfff4u, + 0x2u, 0xfffeu, 0x5u, + 0x2u, 0xffffu, 0xfff2u, + 0x1u, 0xffffu, 0xfffcu, + 0x1u, 0xffffu, 0x4u, + 0x1u, 0xffffu, 0xau, + 0x0u, 0xffffu, 0xfu, + 0x1u, 0x0u, 0xfff3u, + 0x0u, 0x0u, 0xfff6u, + 0x0u, 0x0u, 0xfff8u, + 0x0u, 0x0u, 0xfffau, + 0x0u, 0x0u, 0xfffbu, + 0x0u, 0x0u, 0xfffcu, + 0x0u, 0x0u, 0xfffdu, + 0x0u, 0x0u, 0xfffeu, + 0x0u, 0x0u, 0xfffeu, + 0x0u, 0x0u, 0xffffu, + 0x0u, 0x0u, 0xffffu, + 0x0u, 0x0u, 0xffffu, + 0x0u, 0x0u, 0xffffu, + 0x0u, 0x0u, 0xffffu, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, +// zero pad + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u, + 0x0u, 0x0u, 0x0u +}; + +int16_t gelu_minus_relu_coeffs_int16_0_4[3 * 64] = { + 0, -32766, 26050, -3892, -29500, 25862, -7376, -26260, 25498, -10460, -23070, 24892, -13148, -19956, 24172, + -15456, -16938, 23160, -17392, -14040, 22056, -18976, -11280, 20802, -20224, -8676, 19496, -21156, -6240, 18014, + -21796, -3986, 16536, -22164, -1920, 14916, -22288, -50, 13310, -22188, 1620, 11808, -21896, 3094, 10154, + -21428, 4370, 8644, -20816, 5454, 7214, -20076, 6354, 5804, -19240, 7078, 4474, -18320, 7636, 3258, + -17340, 8040, 2138, -16316, 8304, 1030, -15272, 8438, 150, -14216, 8458, -648, -13164, 8378, -1378, + -12128, 8210, -1932, -11116, 7968, -2356, -10140, 7668, -2858, -9204, 7316, -3050, -8312, 6930, -3366, + -7472, 6514, -3400, -6684, 6084, -3580, -5952, 5642, -3502, -5272, 5200, -3466, -4652, 4764, -3454, + -4080, 4336, -3254, -3564, 3924, -3100, -3100, 3532, -3028, -2680, 3158, -2738, -2308, 2810, -2622, + -1976, 2484, -2344, -1684, 2186, -2250, -1428, 1910, -1950, -1204, 1662, -1844, -1012, 1436, -1594, + -844, 1234, -1394, -704, 1056, -1316, -580, 896, -1068, -476, 758, -1000, -388, 636, -826, + -316, 532, -776, -256, 440, -566, -204, 364, -550, -164, 298, -436, -132, 242, -314, + -104, 196, -268, -80, 158, -242, -64, 126, -182, -48, 100, -144, -36, 80, -188, + -28, 62, -106, -20, 48, -70, -16, 38, -112, -12, 28, -14}; + +uint16_t gelu_coeffs_fp16[3 * 64] = { + 0x849au, 0x8d83u, 0x9265u, + 0x8820u, 0x90bau, 0x94d1u, + 0x8b2fu, 0x93d6u, 0x97b6u, + 0x8e19u, 0x9656u, 0x99edu, + 0x910cu, 0x98fdu, 0x9c64u, + 0x9413u, 0x9ba2u, 0x9e60u, + 0x966du, 0x9db9u, 0xa077u, + 0x98f3u, 0xa02du, 0xa21bu, + 0x9b73u, 0xa1f3u, 0xa412u, + 0x9d7cu, 0xa424u, 0xa548u, + 0x9fe9u, 0xa5a1u, 0xa6aau, + 0xa195u, 0xa77cu, 0xa818u, + 0xa3b9u, 0xa8ddu, 0xa8e1u, + 0xa53du, 0xaa2eu, 0xa9a3u, + 0xa6f7u, 0xabacu, 0xaa4au, + 0xa88bu, 0xaca7u, 0xaabfu, + 0xa9d0u, 0xad83u, 0xaae5u, + 0xab4cu, 0xae5cu, 0xaa9cu, + 0xac7eu, 0xaf23u, 0xa9c3u, + 0xad6du, 0xafc5u, 0xa83eu, + 0xae6du, 0xb015u, 0xa3c2u, + 0xaf75u, 0xb01cu, 0x20d3u, + 0xb03cu, 0xafd2u, 0x2933u, + 0xb0b2u, 0xaee0u, 0x2d01u, + 0xb115u, 0xad49u, 0x2fbfu, + 0xb158u, 0xa9f5u, 0x315eu, + 0xb171u, 0x15ebu, 0x32e9u, + 0xb152u, 0x2bdeu, 0x3437u, + 0xb0f0u, 0x3041u, 0x34ecu, + 0xb03fu, 0x32dfu, 0x3586u, + 0xae6cu, 0x34e1u, 0x35fcu, + 0xab34u, 0x366au, 0x363au, + 0x0u, 0x3800u, 0x3661u, + 0x2c66u, 0x38cbu, 0x3647u, + 0x30cau, 0x3990u, 0x35fdu, + 0x33c1u, 0x3a48u, 0x3586u, + 0x3588u, 0x3af0u, 0x34ecu, + 0x3757u, 0x3b82u, 0x3438u, + 0x38a4u, 0x3bfdu, 0x32ebu, + 0x39aau, 0x3c30u, 0x315fu, + 0x3abbu, 0x3c55u, 0x2fc1u, + 0x3bd3u, 0x3c6eu, 0x2d03u, + 0x3c79u, 0x3c7du, 0x2936u, + 0x3d09u, 0x3c83u, 0x20e2u, + 0x3d99u, 0x3c83u, 0xa3b7u, + 0x3e29u, 0x3c7cu, 0xa83cu, + 0x3eb8u, 0x3c72u, 0xa9c2u, + 0x3f46u, 0x3c66u, 0xaa9bu, + 0x3fd2u, 0x3c58u, 0xaae5u, + 0x402eu, 0x3c4au, 0xaabfu, + 0x4072u, 0x3c3du, 0xaa4bu, + 0x40b6u, 0x3c31u, 0xa9a4u, + 0x40f8u, 0x3c27u, 0xa8e2u, + 0x413au, 0x3c1eu, 0xa818u, + 0x417cu, 0x3c17u, 0xa6acu, + 0x41bdu, 0x3c11u, 0xa549u, + 0x41feu, 0x3c0cu, 0xa413u, + 0x423fu, 0x3c08u, 0xa21du, + 0x427fu, 0x3c06u, 0xa077u, + 0x42bfu, 0x3c04u, 0x9e5au, + 0x4300u, 0x3c02u, 0x9c65u, + 0x4340u, 0x3c02u, 0x99eau, + 0x4380u, 0x3c01u, 0x97beu, + 0x43c0u, 0x3c01u, 0x94ecu//, + // 0x4400u, 0x3c00u, 0x9213u +}; + +/* REDUCTION OPS TABLES */ +uint32_t reduction_shuffle_tab_32[3*64] = +{ + /* SHUFFLE 1 */ /* SHUFFLE 2 */ /* SHUFFLE 3 */ + /* DG0 */ /* DG0 */ /* DG0 */ + /* G0 */ /* G0 */ /* G0 */ + /* 1 -> 0 */ 0x81818181, /* 2 -> 0 */ 0x82828282, /* 4 -> 0 */ 0x84848484, + /* 0 -> 1 */ 0x80808080, /* 2 -> 1 */ 0x82828282, /* 4 -> 1 */ 0x84848484, + /* 3 -> 2 */ 0x83838383, /* 0 -> 2 */ 0x80808080, /* 4 -> 2 */ 0x84848484, + /* 2 -> 3 */ 0x82828282, /* 0 -> 3 */ 0x80808080, /* 4 -> 3 */ 0x84848484, + /* 5 -> 4 */ 0x85858585, /* 6 -> 4 */ 0x86868686, /* 0 -> 4 */ 0x80808080, + /* 4 -> 5 */ 0x84848484, /* 6 -> 5 */ 0x86868686, /* 0 -> 5 */ 0x80808080, + /* 7 -> 6 */ 0x87878787, /* 4 -> 6 */ 0x84848484, /* 0 -> 6 */ 0x80808080, + /* 6 -> 7 */ 0x86868686, /* 4 -> 7 */ 0x84848484, /* 0 -> 7 */ 0x80808080, + /* G1 */ /* G1 */ /* G1 */ + /* 1 -> 0 */ 0xA1A1A1A1, /* 2 -> 0 */ 0xA2A2A2A2, /* 4 -> 0 */ 0xA4A4A4A4, + /* 0 -> 1 */ 0xA0A0A0A0, /* 2 -> 1 */ 0xA2A2A2A2, /* 4 -> 1 */ 0xA4A4A4A4, + /* 3 -> 2 */ 0xA3A3A3A3, /* 0 -> 2 */ 0xA0A0A0A0, /* 4 -> 2 */ 0xA4A4A4A4, + /* 2 -> 3 */ 0xA2A2A2A2, /* 0 -> 3 */ 0xA0A0A0A0, /* 4 -> 3 */ 0xA4A4A4A4, + /* 5 -> 4 */ 0xA5A5A5A5, /* 6 -> 4 */ 0xA6A6A6A6, /* 0 -> 4 */ 0xA0A0A0A0, + /* 4 -> 5 */ 0xA4A4A4A4, /* 6 -> 5 */ 0xA6A6A6A6, /* 0 -> 5 */ 0xA0A0A0A0, + /* 7 -> 6 */ 0xA7A7A7A7, /* 4 -> 6 */ 0xA4A4A4A4, /* 0 -> 6 */ 0xA0A0A0A0, + /* 6 -> 7 */ 0xA6A6A6A6, /* 4 -> 7 */ 0xA4A4A4A4, /* 0 -> 7 */ 0xA0A0A0A0, + /* DG1 */ /* DG1 */ /* DG1 */ + /* G0 */ /* G0 */ /* G0 */ + /* 1 -> 0 */ 0x81818181, /* 2 -> 0 */ 0x82828282, /* 4 -> 0 */ 0x84848484, + /* 0 -> 1 */ 0x80808080, /* 2 -> 1 */ 0x82828282, /* 4 -> 1 */ 0x84848484, + /* 3 -> 2 */ 0x83838383, /* 0 -> 2 */ 0x80808080, /* 4 -> 2 */ 0x84848484, + /* 2 -> 3 */ 0x82828282, /* 0 -> 3 */ 0x80808080, /* 4 -> 3 */ 0x84848484, + /* 5 -> 4 */ 0x85858585, /* 6 -> 4 */ 0x86868686, /* 0 -> 4 */ 0x80808080, + /* 4 -> 5 */ 0x84848484, /* 6 -> 5 */ 0x86868686, /* 0 -> 5 */ 0x80808080, + /* 7 -> 6 */ 0x87878787, /* 4 -> 6 */ 0x84848484, /* 0 -> 6 */ 0x80808080, + /* 6 -> 7 */ 0x86868686, /* 4 -> 7 */ 0x84848484, /* 0 -> 7 */ 0x80808080, + /* G1 */ /* G1 */ /* G1 */ + /* 1 -> 0 */ 0xA1A1A1A1, /* 2 -> 0 */ 0xA2A2A2A2, /* 4 -> 0 */ 0xA4A4A4A4, + /* 0 -> 1 */ 0xA0A0A0A0, /* 2 -> 1 */ 0xA2A2A2A2, /* 4 -> 1 */ 0xA4A4A4A4, + /* 3 -> 2 */ 0xA3A3A3A3, /* 0 -> 2 */ 0xA0A0A0A0, /* 4 -> 2 */ 0xA4A4A4A4, + /* 2 -> 3 */ 0xA2A2A2A2, /* 0 -> 3 */ 0xA0A0A0A0, /* 4 -> 3 */ 0xA4A4A4A4, + /* 5 -> 4 */ 0xA5A5A5A5, /* 6 -> 4 */ 0xA6A6A6A6, /* 0 -> 4 */ 0xA0A0A0A0, + /* 4 -> 5 */ 0xA4A4A4A4, /* 6 -> 5 */ 0xA6A6A6A6, /* 0 -> 5 */ 0xA0A0A0A0, + /* 7 -> 6 */ 0xA7A7A7A7, /* 4 -> 6 */ 0xA4A4A4A4, /* 0 -> 6 */ 0xA0A0A0A0, + /* 6 -> 7 */ 0xA6A6A6A6, /* 4 -> 7 */ 0xA4A4A4A4, /* 0 -> 7 */ 0xA0A0A0A0, + /* DG2 */ /* DG2 */ /* DG2 */ + /* G0 */ /* G0 */ /* G0 */ + /* 1 -> 0 */ 0x81818181, /* 2 -> 0 */ 0x82828282, /* 4 -> 0 */ 0x84848484, + /* 0 -> 1 */ 0x80808080, /* 2 -> 1 */ 0x82828282, /* 4 -> 1 */ 0x84848484, + /* 3 -> 2 */ 0x83838383, /* 0 -> 2 */ 0x80808080, /* 4 -> 2 */ 0x84848484, + /* 2 -> 3 */ 0x82828282, /* 0 -> 3 */ 0x80808080, /* 4 -> 3 */ 0x84848484, + /* 5 -> 4 */ 0x85858585, /* 6 -> 4 */ 0x86868686, /* 0 -> 4 */ 0x80808080, + /* 4 -> 5 */ 0x84848484, /* 6 -> 5 */ 0x86868686, /* 0 -> 5 */ 0x80808080, + /* 7 -> 6 */ 0x87878787, /* 4 -> 6 */ 0x84848484, /* 0 -> 6 */ 0x80808080, + /* 6 -> 7 */ 0x86868686, /* 4 -> 7 */ 0x84848484, /* 0 -> 7 */ 0x80808080, + /* G1 */ /* G1 */ /* G1 */ + /* 1 -> 0 */ 0xA1A1A1A1, /* 2 -> 0 */ 0xA2A2A2A2, /* 4 -> 0 */ 0xA4A4A4A4, + /* 0 -> 1 */ 0xA0A0A0A0, /* 2 -> 1 */ 0xA2A2A2A2, /* 4 -> 1 */ 0xA4A4A4A4, + /* 3 -> 2 */ 0xA3A3A3A3, /* 0 -> 2 */ 0xA0A0A0A0, /* 4 -> 2 */ 0xA4A4A4A4, + /* 2 -> 3 */ 0xA2A2A2A2, /* 0 -> 3 */ 0xA0A0A0A0, /* 4 -> 3 */ 0xA4A4A4A4, + /* 5 -> 4 */ 0xA5A5A5A5, /* 6 -> 4 */ 0xA6A6A6A6, /* 0 -> 4 */ 0xA0A0A0A0, + /* 4 -> 5 */ 0xA4A4A4A4, /* 6 -> 5 */ 0xA6A6A6A6, /* 0 -> 5 */ 0xA0A0A0A0, + /* 7 -> 6 */ 0xA7A7A7A7, /* 4 -> 6 */ 0xA4A4A4A4, /* 0 -> 6 */ 0xA0A0A0A0, + /* 6 -> 7 */ 0xA6A6A6A6, /* 4 -> 7 */ 0xA4A4A4A4, /* 0 -> 7 */ 0xA0A0A0A0, + /* DG3 */ /* DG3 */ /* DG3 */ + /* G0 */ /* G0 */ /* G0 */ + /* 1 -> 0 */ 0x81818181, /* 2 -> 0 */ 0x82828282, /* 4 -> 0 */ 0x84848484, + /* 0 -> 1 */ 0x80808080, /* 2 -> 1 */ 0x82828282, /* 4 -> 1 */ 0x84848484, + /* 3 -> 2 */ 0x83838383, /* 0 -> 2 */ 0x80808080, /* 4 -> 2 */ 0x84848484, + /* 2 -> 3 */ 0x82828282, /* 0 -> 3 */ 0x80808080, /* 4 -> 3 */ 0x84848484, + /* 5 -> 4 */ 0x85858585, /* 6 -> 4 */ 0x86868686, /* 0 -> 4 */ 0x80808080, + /* 4 -> 5 */ 0x84848484, /* 6 -> 5 */ 0x86868686, /* 0 -> 5 */ 0x80808080, + /* 7 -> 6 */ 0x87878787, /* 4 -> 6 */ 0x84848484, /* 0 -> 6 */ 0x80808080, + /* 6 -> 7 */ 0x86868686, /* 4 -> 7 */ 0x84848484, /* 0 -> 7 */ 0x80808080, + /* G1 */ /* G1 */ /* G1 */ + /* 1 -> 0 */ 0xA1A1A1A1, /* 2 -> 0 */ 0xA2A2A2A2, /* 4 -> 0 */ 0xA4A4A4A4, + /* 0 -> 1 */ 0xA0A0A0A0, /* 2 -> 1 */ 0xA2A2A2A2, /* 4 -> 1 */ 0xA4A4A4A4, + /* 3 -> 2 */ 0xA3A3A3A3, /* 0 -> 2 */ 0xA0A0A0A0, /* 4 -> 2 */ 0xA4A4A4A4, + /* 2 -> 3 */ 0xA2A2A2A2, /* 0 -> 3 */ 0xA0A0A0A0, /* 4 -> 3 */ 0xA4A4A4A4, + /* 5 -> 4 */ 0xA5A5A5A5, /* 6 -> 4 */ 0xA6A6A6A6, /* 0 -> 4 */ 0xA0A0A0A0, + /* 4 -> 5 */ 0xA4A4A4A4, /* 6 -> 5 */ 0xA6A6A6A6, /* 0 -> 5 */ 0xA0A0A0A0, + /* 7 -> 6 */ 0xA7A7A7A7, /* 4 -> 6 */ 0xA4A4A4A4, /* 0 -> 6 */ 0xA0A0A0A0, + /* 6 -> 7 */ 0xA6A6A6A6, /* 4 -> 7 */ 0xA4A4A4A4, /* 0 -> 7 */ 0xA0A0A0A0, +}; + +// Format the permutation argument for the shuffle instruction. +constexpr uint8_t SHUFFLE_EL_F32(uint8_t n) +{ + return n | ((n > 7) << 5) | 0x80; +} + +// Concatanate four u8 permutation arguments into 1 u32. +constexpr uint32_t SH_EL(uint8_t n) { + return ((uint32_t)SHUFFLE_EL_F32(n)) | + ((uint32_t)SHUFFLE_EL_F32(n) << 8) | + ((uint32_t)SHUFFLE_EL_F32(n) << 16) | + ((uint32_t)SHUFFLE_EL_F32(n) << 24); +} + +// From tpc_kernels/src/shuffle_tab.cpp, `f128_shuffle_table`. +// Used in `swizzle` LTO intrinsic, which is used in the fuser. +uint32_t swizzle_shuffle_tab_32[3*64] = +{ +// not used backward reorder combine + 0x0, SH_EL(0), 0x0, + 0x0, SH_EL(2), 0x0, + 0x0, SH_EL(4), 0x0, + 0x0, SH_EL(6), 0x0, + 0x0, SH_EL(1), SH_EL(0), + 0x0, SH_EL(3), SH_EL(1), + 0x0, SH_EL(5), SH_EL(2), + 0x0, SH_EL(7), SH_EL(3), + 0x0, SH_EL(8), SH_EL(12), + 0x0, SH_EL(10), SH_EL(13), + 0x0, SH_EL(12), SH_EL(14), + 0x0, SH_EL(14), SH_EL(15), + 0x0, SH_EL(9), 0x20202020, + 0x0, SH_EL(11), 0x20202020, + 0x0, SH_EL(13), 0x20202020, + 0x0, SH_EL(15), 0x20202020, + + 0x0, SH_EL(0), 0x0, + 0x0, SH_EL(2), 0x0, + 0x0, SH_EL(4), 0x0, + 0x0, SH_EL(6), 0x0, + 0x0, SH_EL(1), SH_EL(0), + 0x0, SH_EL(3), SH_EL(1), + 0x0, SH_EL(5), SH_EL(2), + 0x0, SH_EL(7), SH_EL(3), + 0x0, SH_EL(8), SH_EL(12), + 0x0, SH_EL(10), SH_EL(13), + 0x0, SH_EL(12), SH_EL(14), + 0x0, SH_EL(14), SH_EL(15), + 0x0, SH_EL(9), 0x20202020, + 0x0, SH_EL(11), 0x20202020, + 0x0, SH_EL(13), 0x20202020, + 0x0, SH_EL(15), 0x20202020, + + 0x0, SH_EL(0), 0x0, + 0x0, SH_EL(2), 0x0, + 0x0, SH_EL(4), 0x0, + 0x0, SH_EL(6), 0x0, + 0x0, SH_EL(1), SH_EL(0), + 0x0, SH_EL(3), SH_EL(1), + 0x0, SH_EL(5), SH_EL(2), + 0x0, SH_EL(7), SH_EL(3), + 0x0, SH_EL(8), SH_EL(12), + 0x0, SH_EL(10), SH_EL(13), + 0x0, SH_EL(12), SH_EL(14), + 0x0, SH_EL(14), SH_EL(15), + 0x0, SH_EL(9), 0x20202020, + 0x0, SH_EL(11), 0x20202020, + 0x0, SH_EL(13), 0x20202020, + 0x0, SH_EL(15), 0x20202020, + + 0x0, SH_EL(0), 0x0, + 0x0, SH_EL(2), 0x0, + 0x0, SH_EL(4), 0x0, + 0x0, SH_EL(6), 0x0, + 0x0, SH_EL(1), SH_EL(0), + 0x0, SH_EL(3), SH_EL(1), + 0x0, SH_EL(5), SH_EL(2), + 0x0, SH_EL(7), SH_EL(3), + 0x0, SH_EL(8), SH_EL(12), + 0x0, SH_EL(10), SH_EL(13), + 0x0, SH_EL(12), SH_EL(14), + 0x0, SH_EL(14), SH_EL(15), + 0x0, SH_EL(9), 0x20202020, + 0x0, SH_EL(11), 0x20202020, + 0x0, SH_EL(13), 0x20202020, + 0x0, SH_EL(15), 0x20202020 +}; + +uint32_t reduction_shuffle_tab_16[3*128] = +{ + /* NOT USED */ /* SHUFFLE 1 */ /* SHUFFLE 2 */ + /* DG0 */ /* DG0 */ + /* G0 */ /* G0 */ + 0x0, /* 0 <-> 1 */ 0x80808181, /* 2 -> 0, 1 */ 0x82828282, + 0x0, /* 2 <-> 3 */ 0x82828383, /* 0 -> 2, 3 */ 0x80808080, + 0x0, /* 4 <-> 5 */ 0x84848585, /* 6 -> 4, 5 */ 0x86868686, + 0x0, /* 6 <-> 7 */ 0x86868787, /* 4 -> 6, 7 */ 0x84848484, + 0x0, /* 8 <-> 9 */ 0x88888989, /* 10 -> 8, 9 */ 0x8A8A8A8A, + 0x0, /* 10 <-> 11 */ 0x8A8A8B8B, /* 8 -> 10, 11 */ 0x88888888, + 0x0, /* 12 <-> 13 */ 0x8C8C8D8D, /* 14 -> 12, 13 */ 0x8E8E8E8E, + 0x0, /* 14 <-> 15 */ 0x8E8E8F8F, /* 12 -> 14, 15 */ 0x8C8C8C8C, + /* G1 */ /* G1 */ + 0x0, /* 0 <-> 1 */ 0xA0A0A1A1, /* 2 -> 0, 1 */ 0xA2A2A2A2, + 0x0, /* 2 <-> 3 */ 0xA2A2A3A3, /* 0 -> 2, 3 */ 0xA0A0A0A0, + 0x0, /* 4 <-> 5 */ 0xA4A4A5A5, /* 6 -> 4, 5 */ 0xA6A6A6A6, + 0x0, /* 6 <-> 7 */ 0xA6A6A7A7, /* 4 -> 6, 7 */ 0xA4A4A4A4, + 0x0, /* 8 <-> 9 */ 0xA8A8A9A9, /* 10 -> 8, 9 */ 0xAAAAAAAA, + 0x0, /* 10 <-> 11 */ 0xAAAAABAB, /* 8 -> 10, 11 */ 0xA8A8A8A8, + 0x0, /* 12 <-> 13 */ 0xACACADAD, /* 14 -> 12, 13 */ 0xAEAEAEAE, + 0x0, /* 14 <-> 15 */ 0xAEAEAFAF, /* 12 -> 14, 15 */ 0xACACACAC, + /* DG1 */ /* DG1 */ + /* G0 */ /* G0 */ + 0x0, /* 0 <-> 1 */ 0x80808181, /* 2 -> 0, 1 */ 0x82828282, + 0x0, /* 2 <-> 3 */ 0x82828383, /* 0 -> 2, 3 */ 0x80808080, + 0x0, /* 4 <-> 5 */ 0x84848585, /* 6 -> 4, 5 */ 0x86868686, + 0x0, /* 6 <-> 7 */ 0x86868787, /* 4 -> 6, 7 */ 0x84848484, + 0x0, /* 8 <-> 9 */ 0x88888989, /* 10 -> 8, 9 */ 0x8A8A8A8A, + 0x0, /* 10 <-> 11 */ 0x8A8A8B8B, /* 8 -> 10, 11 */ 0x88888888, + 0x0, /* 12 <-> 13 */ 0x8C8C8D8D, /* 14 -> 12, 13 */ 0x8E8E8E8E, + 0x0, /* 14 <-> 15 */ 0x8E8E8F8F, /* 12 -> 14, 15 */ 0x8C8C8C8C, + /* G1 */ /* G1 */ + 0x0, /* 0 <-> 1 */ 0xA0A0A1A1, /* 2 -> 0, 1 */ 0xA2A2A2A2, + 0x0, /* 2 <-> 3 */ 0xA2A2A3A3, /* 0 -> 2, 3 */ 0xA0A0A0A0, + 0x0, /* 4 <-> 5 */ 0xA4A4A5A5, /* 6 -> 4, 5 */ 0xA6A6A6A6, + 0x0, /* 6 <-> 7 */ 0xA6A6A7A7, /* 4 -> 6, 7 */ 0xA4A4A4A4, + 0x0, /* 8 <-> 9 */ 0xA8A8A9A9, /* 10 -> 8, 9 */ 0xAAAAAAAA, + 0x0, /* 10 <-> 11 */ 0xAAAAABAB, /* 8 -> 10, 11 */ 0xA8A8A8A8, + 0x0, /* 12 <-> 13 */ 0xACACADAD, /* 14 -> 12, 13 */ 0xAEAEAEAE, + 0x0, /* 14 <-> 15 */ 0xAEAEAFAF, /* 12 -> 14, 15 */ 0xACACACAC, + /* DG2 */ /* DG2 */ + /* G0 */ /* G0 */ + 0x0, /* 0 <-> 1 */ 0x80808181, /* 2 -> 0, 1 */ 0x82828282, + 0x0, /* 2 <-> 3 */ 0x82828383, /* 0 -> 2, 3 */ 0x80808080, + 0x0, /* 4 <-> 5 */ 0x84848585, /* 6 -> 4, 5 */ 0x86868686, + 0x0, /* 6 <-> 7 */ 0x86868787, /* 4 -> 6, 7 */ 0x84848484, + 0x0, /* 8 <-> 9 */ 0x88888989, /* 10 -> 8, 9 */ 0x8A8A8A8A, + 0x0, /* 10 <-> 11 */ 0x8A8A8B8B, /* 8 -> 10, 11 */ 0x88888888, + 0x0, /* 12 <-> 13 */ 0x8C8C8D8D, /* 14 -> 12, 13 */ 0x8E8E8E8E, + 0x0, /* 14 <-> 15 */ 0x8E8E8F8F, /* 12 -> 14, 15 */ 0x8C8C8C8C, + /* G1 */ /* G1 */ + 0x0, /* 0 <-> 1 */ 0xA0A0A1A1, /* 2 -> 0, 1 */ 0xA2A2A2A2, + 0x0, /* 2 <-> 3 */ 0xA2A2A3A3, /* 0 -> 2, 3 */ 0xA0A0A0A0, + 0x0, /* 4 <-> 5 */ 0xA4A4A5A5, /* 6 -> 4, 5 */ 0xA6A6A6A6, + 0x0, /* 6 <-> 7 */ 0xA6A6A7A7, /* 4 -> 6, 7 */ 0xA4A4A4A4, + 0x0, /* 8 <-> 9 */ 0xA8A8A9A9, /* 10 -> 8, 9 */ 0xAAAAAAAA, + 0x0, /* 10 <-> 11 */ 0xAAAAABAB, /* 8 -> 10, 11 */ 0xA8A8A8A8, + 0x0, /* 12 <-> 13 */ 0xACACADAD, /* 14 -> 12, 13 */ 0xAEAEAEAE, + 0x0, /* 14 <-> 15 */ 0xAEAEAFAF, /* 12 -> 14, 15 */ 0xACACACAC, + /* DG3 */ /* DG3 */ + /* G0 */ /* G0 */ + 0x0, /* 0 <-> 1 */ 0x80808181, /* 2 -> 0, 1 */ 0x82828282, + 0x0, /* 2 <-> 3 */ 0x82828383, /* 0 -> 2, 3 */ 0x80808080, + 0x0, /* 4 <-> 5 */ 0x84848585, /* 6 -> 4, 5 */ 0x86868686, + 0x0, /* 6 <-> 7 */ 0x86868787, /* 4 -> 6, 7 */ 0x84848484, + 0x0, /* 8 <-> 9 */ 0x88888989, /* 10 -> 8, 9 */ 0x8A8A8A8A, + 0x0, /* 10 <-> 11 */ 0x8A8A8B8B, /* 8 -> 10, 11 */ 0x88888888, + 0x0, /* 12 <-> 13 */ 0x8C8C8D8D, /* 14 -> 12, 13 */ 0x8E8E8E8E, + 0x0, /* 14 <-> 15 */ 0x8E8E8F8F, /* 12 -> 14, 15 */ 0x8C8C8C8C, + /* G1 */ /* G1 */ + 0x0, /* 0 <-> 1 */ 0xA0A0A1A1, /* 2 -> 0, 1 */ 0xA2A2A2A2, + 0x0, /* 2 <-> 3 */ 0xA2A2A3A3, /* 0 -> 2, 3 */ 0xA0A0A0A0, + 0x0, /* 4 <-> 5 */ 0xA4A4A5A5, /* 6 -> 4, 5 */ 0xA6A6A6A6, + 0x0, /* 6 <-> 7 */ 0xA6A6A7A7, /* 4 -> 6, 7 */ 0xA4A4A4A4, + 0x0, /* 8 <-> 9 */ 0xA8A8A9A9, /* 10 -> 8, 9 */ 0xAAAAAAAA, + 0x0, /* 10 <-> 11 */ 0xAAAAABAB, /* 8 -> 10, 11 */ 0xA8A8A8A8, + 0x0, /* 12 <-> 13 */ 0xACACADAD, /* 14 -> 12, 13 */ 0xAEAEAEAE, + 0x0, /* 14 <-> 15 */ 0xAEAEAFAF, /* 12 -> 14, 15 */ 0xACACACAC, + /* NOT USED */ /* SHUFFLE 3 */ /* SHUFFLE 4 */ + /* DG0 */ /* DG0 */ + /* G0 */ /* G0 */ + 0x0, /* 4 -> 0, 1 */ 0x84848484, /* 8 -> 0, 1 */ 0x88888888, + 0x0, /* 4 -> 2, 3 */ 0x84848484, /* 8 -> 2, 3 */ 0x88888888, + 0x0, /* 0 -> 4, 5 */ 0x80808080, /* 8 -> 4, 5 */ 0x88888888, + 0x0, /* 0 -> 6, 7 */ 0x80808080, /* 8 -> 6, 7 */ 0x88888888, + 0x0, /* 12 -> 8, 9 */ 0x8C8C8C8C, /* 0 -> 8, 9 */ 0x80808080, + 0x0, /* 12 -> 10, 11 */ 0x8C8C8C8C, /* 0 -> 10, 11 */ 0x80808080, + 0x0, /* 8 -> 12, 13 */ 0x88888888, /* 0 -> 12, 13 */ 0x80808080, + 0x0, /* 8 -> 14, 15 */ 0x88888888, /* 0 -> 14, 15 */ 0x80808080, + /* G1 */ /* G1 */ + 0x0, /* 4 -> 0, 1 */ 0xA4A4A4A4, /* 8 -> 0, 1 */ 0xA8A8A8A8, + 0x0, /* 4 -> 2, 3 */ 0xA4A4A4A4, /* 8 -> 2, 3 */ 0xA8A8A8A8, + 0x0, /* 0 -> 4, 5 */ 0xA0A0A0A0, /* 8 -> 4, 5 */ 0xA8A8A8A8, + 0x0, /* 0 -> 6, 7 */ 0xA0A0A0A0, /* 8 -> 6, 7 */ 0xA8A8A8A8, + 0x0, /* 12 -> 8, 9 */ 0xACACACAC, /* 0 -> 8, 9 */ 0xA0A0A0A0, + 0x0, /* 12 -> 10, 11 */ 0xACACACAC, /* 0 -> 10, 11 */ 0xA0A0A0A0, + 0x0, /* 8 -> 12, 13 */ 0xA8A8A8A8, /* 0 -> 12, 13 */ 0xA0A0A0A0, + 0x0, /* 8 -> 14, 15 */ 0xA8A8A8A8, /* 0 -> 14, 15 */ 0xA0A0A0A0, + /* DG1 */ /* DG1 */ + /* G0 */ /* G0 */ + 0x0, /* 4 -> 0, 1 */ 0x84848484, /* 8 -> 0, 1 */ 0x88888888, + 0x0, /* 4 -> 2, 3 */ 0x84848484, /* 8 -> 2, 3 */ 0x88888888, + 0x0, /* 0 -> 4, 5 */ 0x80808080, /* 8 -> 4, 5 */ 0x88888888, + 0x0, /* 0 -> 6, 7 */ 0x80808080, /* 8 -> 6, 7 */ 0x88888888, + 0x0, /* 12 -> 8, 9 */ 0x8C8C8C8C, /* 0 -> 8, 9 */ 0x80808080, + 0x0, /* 12 -> 10, 11 */ 0x8C8C8C8C, /* 0 -> 10, 11 */ 0x80808080, + 0x0, /* 8 -> 12, 13 */ 0x88888888, /* 0 -> 12, 13 */ 0x80808080, + 0x0, /* 8 -> 14, 15 */ 0x88888888, /* 0 -> 14, 15 */ 0x80808080, + /* G1 */ /* G1 */ + 0x0, /* 4 -> 0, 1 */ 0xA4A4A4A4, /* 8 -> 0, 1 */ 0xA8A8A8A8, + 0x0, /* 4 -> 2, 3 */ 0xA4A4A4A4, /* 8 -> 2, 3 */ 0xA8A8A8A8, + 0x0, /* 0 -> 4, 5 */ 0xA0A0A0A0, /* 8 -> 4, 5 */ 0xA8A8A8A8, + 0x0, /* 0 -> 6, 7 */ 0xA0A0A0A0, /* 8 -> 6, 7 */ 0xA8A8A8A8, + 0x0, /* 12 -> 8, 9 */ 0xACACACAC, /* 0 -> 8, 9 */ 0xA0A0A0A0, + 0x0, /* 12 -> 10, 11 */ 0xACACACAC, /* 0 -> 10, 11 */ 0xA0A0A0A0, + 0x0, /* 8 -> 12, 13 */ 0xA8A8A8A8, /* 0 -> 12, 13 */ 0xA0A0A0A0, + 0x0, /* 8 -> 14, 15 */ 0xA8A8A8A8, /* 0 -> 14, 15 */ 0xA0A0A0A0, + /* DG2 */ /* DG2 */ + /* G0 */ /* G0 */ + 0x0, /* 4 -> 0, 1 */ 0x84848484, /* 8 -> 0, 1 */ 0x88888888, + 0x0, /* 4 -> 2, 3 */ 0x84848484, /* 8 -> 2, 3 */ 0x88888888, + 0x0, /* 0 -> 4, 5 */ 0x80808080, /* 8 -> 4, 5 */ 0x88888888, + 0x0, /* 0 -> 6, 7 */ 0x80808080, /* 8 -> 6, 7 */ 0x88888888, + 0x0, /* 12 -> 8, 9 */ 0x8C8C8C8C, /* 0 -> 8, 9 */ 0x80808080, + 0x0, /* 12 -> 10, 11 */ 0x8C8C8C8C, /* 0 -> 10, 11 */ 0x80808080, + 0x0, /* 8 -> 12, 13 */ 0x88888888, /* 0 -> 12, 13 */ 0x80808080, + 0x0, /* 8 -> 14, 15 */ 0x88888888, /* 0 -> 14, 15 */ 0x80808080, + /* G1 */ /* G1 */ + 0x0, /* 4 -> 0, 1 */ 0xA4A4A4A4, /* 8 -> 0, 1 */ 0xA8A8A8A8, + 0x0, /* 4 -> 2, 3 */ 0xA4A4A4A4, /* 8 -> 2, 3 */ 0xA8A8A8A8, + 0x0, /* 0 -> 4, 5 */ 0xA0A0A0A0, /* 8 -> 4, 5 */ 0xA8A8A8A8, + 0x0, /* 0 -> 6, 7 */ 0xA0A0A0A0, /* 8 -> 6, 7 */ 0xA8A8A8A8, + 0x0, /* 12 -> 8, 9 */ 0xACACACAC, /* 0 -> 8, 9 */ 0xA0A0A0A0, + 0x0, /* 12 -> 10, 11 */ 0xACACACAC, /* 0 -> 10, 11 */ 0xA0A0A0A0, + 0x0, /* 8 -> 12, 13 */ 0xA8A8A8A8, /* 0 -> 12, 13 */ 0xA0A0A0A0, + 0x0, /* 8 -> 14, 15 */ 0xA8A8A8A8, /* 0 -> 14, 15 */ 0xA0A0A0A0, + /* DG3 */ /* DG3 */ + /* G0 */ /* G0 */ + 0x0, /* 4 -> 0, 1 */ 0x84848484, /* 8 -> 0, 1 */ 0x88888888, + 0x0, /* 4 -> 2, 3 */ 0x84848484, /* 8 -> 2, 3 */ 0x88888888, + 0x0, /* 0 -> 4, 5 */ 0x80808080, /* 8 -> 4, 5 */ 0x88888888, + 0x0, /* 0 -> 6, 7 */ 0x80808080, /* 8 -> 6, 7 */ 0x88888888, + 0x0, /* 12 -> 8, 9 */ 0x8C8C8C8C, /* 0 -> 8, 9 */ 0x80808080, + 0x0, /* 12 -> 10, 11 */ 0x8C8C8C8C, /* 0 -> 10, 11 */ 0x80808080, + 0x0, /* 8 -> 12, 13 */ 0x88888888, /* 0 -> 12, 13 */ 0x80808080, + 0x0, /* 8 -> 14, 15 */ 0x88888888, /* 0 -> 14, 15 */ 0x80808080, + /* G1 */ /* G1 */ + 0x0, /* 4 -> 0, 1 */ 0xA4A4A4A4, /* 8 -> 0, 1 */ 0xA8A8A8A8, + 0x0, /* 4 -> 2, 3 */ 0xA4A4A4A4, /* 8 -> 2, 3 */ 0xA8A8A8A8, + 0x0, /* 0 -> 4, 5 */ 0xA0A0A0A0, /* 8 -> 4, 5 */ 0xA8A8A8A8, + 0x0, /* 0 -> 6, 7 */ 0xA0A0A0A0, /* 8 -> 6, 7 */ 0xA8A8A8A8, + 0x0, /* 12 -> 8, 9 */ 0xACACACAC, /* 0 -> 8, 9 */ 0xA0A0A0A0, + 0x0, /* 12 -> 10, 11 */ 0xACACACAC, /* 0 -> 10, 11 */ 0xA0A0A0A0, + 0x0, /* 8 -> 12, 13 */ 0xA8A8A8A8, /* 0 -> 12, 13 */ 0xA0A0A0A0, + 0x0, /* 8 -> 14, 15 */ 0xA8A8A8A8, /* 0 -> 14, 15 */ 0xA0A0A0A0, +}; + +uint32_t reduction_shuffle_tab_8[3*128] = +{ + /* SHUFFLE 1 */ /* SHUFFLE 2 */ /* SHUFFLE 3 */ + /* DG0 */ /* DG0 */ /* DG0 */ + /* G0 */ /* G0 */ /* G0 */ + /* 0 <-> 1, 2 <-> 3 */ 0x82838081, /* 2 -> 0, 1, 0 -> 2, 3 */ 0x80808282, /* 4 -> 0, 1, 2, 3 */ 0x84848484, + /* 4 <-> 5, 6 <-> 7 */ 0x86878485, /* 6 -> 4, 5, 4 -> 6, 7 */ 0x84848686, /* 0 -> 4, 5, 6, 7 */ 0x80808080, + /* 8 <-> 9, 10 <-> 11 */ 0x8A8B8889, /* 10 -> 8, 9, 8 -> 10, 11 */ 0x88888A8A, /* 12 -> 8, 9, 10, 11 */ 0x8C8C8C8C, + /* 12 <-> 13, 14 <-> 15 */ 0x8E8F8C8D, /* 14 -> 12, 13, 12 -> 14, 15 */ 0x8C8C8E8E, /* 8 -> 12, 13, 14, 15 */ 0x88888888, + /* 16 <-> 17, 18 <-> 19 */ 0x92939091, /* 18 -> 16, 17, 16 -> 18, 19 */ 0x90909292, /* 20 -> 16, 17, 18, 19 */ 0x94949494, + /* 20 <-> 21, 22 <-> 23 */ 0x96979495, /* 22 -> 20, 21, 20 -> 22, 23 */ 0x94949696, /* 16 -> 20, 21, 22, 23 */ 0x90909090, + /* 24 <-> 25, 26 <-> 27 */ 0x9A9B9899, /* 26 -> 24, 25, 24 -> 26, 27 */ 0x98989A9A, /* 28 -> 24, 25, 26, 27 */ 0x9C9C9C9C, + /* 28 <-> 29, 30 <-> 31 */ 0x9E9F9C9D, /* 30 -> 28, 29, 28 -> 30, 31 */ 0x9C9C9E9E, /* 24 -> 28, 29, 30, 31 */ 0x98989898, + /* G1 */ /* G1 */ /* G1 */ + /* 0 <-> 1, 2 <-> 3 */ 0xA2A3A0A1, /* 2 -> 0, 1, 0 -> 2, 3 */ 0xA0A0A2A2, /* 4 -> 0, 1, 2, 3 */ 0xA4A4A4A4, + /* 4 <-> 5, 6 <-> 7 */ 0xA6A7A4A5, /* 6 -> 4, 5, 4 -> 6, 7 */ 0xA4A4A6A6, /* 0 -> 4, 5, 6, 7 */ 0xA0A0A0A0, + /* 8 <-> 9, 10 <-> 11 */ 0xAAABA8A9, /* 10 -> 8, 9, 8 -> 10, 11 */ 0xA8A8AAAA, /* 12 -> 8, 9, 10, 11 */ 0xACACACAC, + /* 12 <-> 13, 14 <-> 15 */ 0xAEAFACAD, /* 14 -> 12, 13, 12 -> 14, 15 */ 0xACACAEAE, /* 8 -> 12, 13, 14, 15 */ 0xA8A8A8A8, + /* 16 <-> 17, 18 <-> 19 */ 0xB2B3B0B1, /* 18 -> 16, 17, 16 -> 18, 19 */ 0x90909292, /* 20 -> 16, 17, 18, 19 */ 0xB4B4B4B4, + /* 20 <-> 21, 22 <-> 23 */ 0xB6B7B4B5, /* 22 -> 20, 21, 20 -> 22, 23 */ 0x94949696, /* 16 -> 20, 21, 22, 23 */ 0xB0B0B0B0, + /* 24 <-> 25, 26 <-> 27 */ 0xBABBB8B9, /* 26 -> 24, 25, 24 -> 26, 27 */ 0x98989A9A, /* 28 -> 24, 25, 26, 27 */ 0xBCBCBCBC, + /* 28 <-> 29, 30 <-> 31 */ 0xBEBFBCBD, /* 30 -> 28, 29, 28 -> 30, 31 */ 0x9C9C9E9E, /* 24 -> 28, 29, 30, 31 */ 0xB8B8B8B8, + /* DG1 */ /* DG1 */ /* DG1 */ + /* G0 */ /* G0 */ /* G0 */ + /* 0 <-> 1, 2 <-> 3 */ 0x82838081, /* 2 -> 0, 1, 0 -> 2, 3 */ 0x80808282, /* 4 -> 0, 1, 2, 3 */ 0x84848484, + /* 4 <-> 5, 6 <-> 7 */ 0x86878485, /* 6 -> 4, 5, 4 -> 6, 7 */ 0x84848686, /* 0 -> 4, 5, 6, 7 */ 0x80808080, + /* 8 <-> 9, 10 <-> 11 */ 0x8A8B8889, /* 10 -> 8, 9, 8 -> 10, 11 */ 0x88888A8A, /* 12 -> 8, 9, 10, 11 */ 0x8C8C8C8C, + /* 12 <-> 13, 14 <-> 15 */ 0x8E8F8C8D, /* 14 -> 12, 13, 12 -> 14, 15 */ 0x8C8C8E8E, /* 8 -> 12, 13, 14, 15 */ 0x88888888, + /* 16 <-> 17, 18 <-> 19 */ 0x92939091, /* 18 -> 16, 17, 16 -> 18, 19 */ 0x90909292, /* 20 -> 16, 17, 18, 19 */ 0x94949494, + /* 20 <-> 21, 22 <-> 23 */ 0x96979495, /* 22 -> 20, 21, 20 -> 22, 23 */ 0x94949696, /* 16 -> 20, 21, 22, 23 */ 0x90909090, + /* 24 <-> 25, 26 <-> 27 */ 0x9A9B9899, /* 26 -> 24, 25, 24 -> 26, 27 */ 0x98989A9A, /* 28 -> 24, 25, 26, 27 */ 0x9C9C9C9C, + /* 28 <-> 29, 30 <-> 31 */ 0x9E9F9C9D, /* 30 -> 28, 29, 28 -> 30, 31 */ 0x9C9C9E9E, /* 24 -> 28, 29, 30, 31 */ 0x98989898, + /* G1 */ /* G1 */ /* G1 */ + /* 0 <-> 1, 2 <-> 3 */ 0xA2A3A0A1, /* 2 -> 0, 1, 0 -> 2, 3 */ 0xA0A0A2A2, /* 4 -> 0, 1, 2, 3 */ 0xA4A4A4A4, + /* 4 <-> 5, 6 <-> 7 */ 0xA6A7A4A5, /* 6 -> 4, 5, 4 -> 6, 7 */ 0xA4A4A6A6, /* 0 -> 4, 5, 6, 7 */ 0xA0A0A0A0, + /* 8 <-> 9, 10 <-> 11 */ 0xAAABA8A9, /* 10 -> 8, 9, 8 -> 10, 11 */ 0xA8A8AAAA, /* 12 -> 8, 9, 10, 11 */ 0xACACACAC, + /* 12 <-> 13, 14 <-> 15 */ 0xAEAFACAD, /* 14 -> 12, 13, 12 -> 14, 15 */ 0xACACAEAE, /* 8 -> 12, 13, 14, 15 */ 0xA8A8A8A8, + /* 16 <-> 17, 18 <-> 19 */ 0xB2B3B0B1, /* 18 -> 16, 17, 16 -> 18, 19 */ 0x90909292, /* 20 -> 16, 17, 18, 19 */ 0xB4B4B4B4, + /* 20 <-> 21, 22 <-> 23 */ 0xB6B7B4B5, /* 22 -> 20, 21, 20 -> 22, 23 */ 0x94949696, /* 16 -> 20, 21, 22, 23 */ 0xB0B0B0B0, + /* 24 <-> 25, 26 <-> 27 */ 0xBABBB8B9, /* 26 -> 24, 25, 24 -> 26, 27 */ 0x98989A9A, /* 28 -> 24, 25, 26, 27 */ 0xBCBCBCBC, + /* 28 <-> 29, 30 <-> 31 */ 0xBEBFBCBD, /* 30 -> 28, 29, 28 -> 30, 31 */ 0x9C9C9E9E, /* 24 -> 28, 29, 30, 31 */ 0xB8B8B8B8, + /* DG2 */ /* DG2 */ /* DG2 */ + /* G0 */ /* G0 */ /* G0 */ + /* 0 <-> 1, 2 <-> 3 */ 0x82838081, /* 2 -> 0, 1, 0 -> 2, 3 */ 0x80808282, /* 4 -> 0, 1, 2, 3 */ 0x84848484, + /* 4 <-> 5, 6 <-> 7 */ 0x86878485, /* 6 -> 4, 5, 4 -> 6, 7 */ 0x84848686, /* 0 -> 4, 5, 6, 7 */ 0x80808080, + /* 8 <-> 9, 10 <-> 11 */ 0x8A8B8889, /* 10 -> 8, 9, 8 -> 10, 11 */ 0x88888A8A, /* 12 -> 8, 9, 10, 11 */ 0x8C8C8C8C, + /* 12 <-> 13, 14 <-> 15 */ 0x8E8F8C8D, /* 14 -> 12, 13, 12 -> 14, 15 */ 0x8C8C8E8E, /* 8 -> 12, 13, 14, 15 */ 0x88888888, + /* 16 <-> 17, 18 <-> 19 */ 0x92939091, /* 18 -> 16, 17, 16 -> 18, 19 */ 0x90909292, /* 20 -> 16, 17, 18, 19 */ 0x94949494, + /* 20 <-> 21, 22 <-> 23 */ 0x96979495, /* 22 -> 20, 21, 20 -> 22, 23 */ 0x94949696, /* 16 -> 20, 21, 22, 23 */ 0x90909090, + /* 24 <-> 25, 26 <-> 27 */ 0x9A9B9899, /* 26 -> 24, 25, 24 -> 26, 27 */ 0x98989A9A, /* 28 -> 24, 25, 26, 27 */ 0x9C9C9C9C, + /* 28 <-> 29, 30 <-> 31 */ 0x9E9F9C9D, /* 30 -> 28, 29, 28 -> 30, 31 */ 0x9C9C9E9E, /* 24 -> 28, 29, 30, 31 */ 0x98989898, + /* G1 */ /* G1 */ /* G1 */ + /* 0 <-> 1, 2 <-> 3 */ 0xA2A3A0A1, /* 2 -> 0, 1, 0 -> 2, 3 */ 0xA0A0A2A2, /* 4 -> 0, 1, 2, 3 */ 0xA4A4A4A4, + /* 4 <-> 5, 6 <-> 7 */ 0xA6A7A4A5, /* 6 -> 4, 5, 4 -> 6, 7 */ 0xA4A4A6A6, /* 0 -> 4, 5, 6, 7 */ 0xA0A0A0A0, + /* 8 <-> 9, 10 <-> 11 */ 0xAAABA8A9, /* 10 -> 8, 9, 8 -> 10, 11 */ 0xA8A8AAAA, /* 12 -> 8, 9, 10, 11 */ 0xACACACAC, + /* 12 <-> 13, 14 <-> 15 */ 0xAEAFACAD, /* 14 -> 12, 13, 12 -> 14, 15 */ 0xACACAEAE, /* 8 -> 12, 13, 14, 15 */ 0xA8A8A8A8, + /* 16 <-> 17, 18 <-> 19 */ 0xB2B3B0B1, /* 18 -> 16, 17, 16 -> 18, 19 */ 0x90909292, /* 20 -> 16, 17, 18, 19 */ 0xB4B4B4B4, + /* 20 <-> 21, 22 <-> 23 */ 0xB6B7B4B5, /* 22 -> 20, 21, 20 -> 22, 23 */ 0x94949696, /* 16 -> 20, 21, 22, 23 */ 0xB0B0B0B0, + /* 24 <-> 25, 26 <-> 27 */ 0xBABBB8B9, /* 26 -> 24, 25, 24 -> 26, 27 */ 0x98989A9A, /* 28 -> 24, 25, 26, 27 */ 0xBCBCBCBC, + /* 28 <-> 29, 30 <-> 31 */ 0xBEBFBCBD, /* 30 -> 28, 29, 28 -> 30, 31 */ 0x9C9C9E9E, /* 24 -> 28, 29, 30, 31 */ 0xB8B8B8B8, + /* DG3 */ /* DG3 */ /* DG3 */ + /* G0 */ /* G0 */ /* G0 */ + /* 0 <-> 1, 2 <-> 3 */ 0x82838081, /* 2 -> 0, 1, 0 -> 2, 3 */ 0x80808282, /* 4 -> 0, 1, 2, 3 */ 0x84848484, + /* 4 <-> 5, 6 <-> 7 */ 0x86878485, /* 6 -> 4, 5, 4 -> 6, 7 */ 0x84848686, /* 0 -> 4, 5, 6, 7 */ 0x80808080, + /* 8 <-> 9, 10 <-> 11 */ 0x8A8B8889, /* 10 -> 8, 9, 8 -> 10, 11 */ 0x88888A8A, /* 12 -> 8, 9, 10, 11 */ 0x8C8C8C8C, + /* 12 <-> 13, 14 <-> 15 */ 0x8E8F8C8D, /* 14 -> 12, 13, 12 -> 14, 15 */ 0x8C8C8E8E, /* 8 -> 12, 13, 14, 15 */ 0x88888888, + /* 16 <-> 17, 18 <-> 19 */ 0x92939091, /* 18 -> 16, 17, 16 -> 18, 19 */ 0x90909292, /* 20 -> 16, 17, 18, 19 */ 0x94949494, + /* 20 <-> 21, 22 <-> 23 */ 0x96979495, /* 22 -> 20, 21, 20 -> 22, 23 */ 0x94949696, /* 16 -> 20, 21, 22, 23 */ 0x90909090, + /* 24 <-> 25, 26 <-> 27 */ 0x9A9B9899, /* 26 -> 24, 25, 24 -> 26, 27 */ 0x98989A9A, /* 28 -> 24, 25, 26, 27 */ 0x9C9C9C9C, + /* 28 <-> 29, 30 <-> 31 */ 0x9E9F9C9D, /* 30 -> 28, 29, 28 -> 30, 31 */ 0x9C9C9E9E, /* 24 -> 28, 29, 30, 31 */ 0x98989898, + /* G1 */ /* G1 */ /* G1 */ + /* 0 <-> 1, 2 <-> 3 */ 0xA2A3A0A1, /* 2 -> 0, 1, 0 -> 2, 3 */ 0xA0A0A2A2, /* 4 -> 0, 1, 2, 3 */ 0xA4A4A4A4, + /* 4 <-> 5, 6 <-> 7 */ 0xA6A7A4A5, /* 6 -> 4, 5, 4 -> 6, 7 */ 0xA4A4A6A6, /* 0 -> 4, 5, 6, 7 */ 0xA0A0A0A0, + /* 8 <-> 9, 10 <-> 11 */ 0xAAABA8A9, /* 10 -> 8, 9, 8 -> 10, 11 */ 0xA8A8AAAA, /* 12 -> 8, 9, 10, 11 */ 0xACACACAC, + /* 12 <-> 13, 14 <-> 15 */ 0xAEAFACAD, /* 14 -> 12, 13, 12 -> 14, 15 */ 0xACACAEAE, /* 8 -> 12, 13, 14, 15 */ 0xA8A8A8A8, + /* 16 <-> 17, 18 <-> 19 */ 0xB2B3B0B1, /* 18 -> 16, 17, 16 -> 18, 19 */ 0x90909292, /* 20 -> 16, 17, 18, 19 */ 0xB4B4B4B4, + /* 20 <-> 21, 22 <-> 23 */ 0xB6B7B4B5, /* 22 -> 20, 21, 20 -> 22, 23 */ 0x94949696, /* 16 -> 20, 21, 22, 23 */ 0xB0B0B0B0, + /* 24 <-> 25, 26 <-> 27 */ 0xBABBB8B9, /* 26 -> 24, 25, 24 -> 26, 27 */ 0x98989A9A, /* 28 -> 24, 25, 26, 27 */ 0xBCBCBCBC, + /* 28 <-> 29, 30 <-> 31 */ 0xBEBFBCBD, /* 30 -> 28, 29, 28 -> 30, 31 */ 0x9C9C9E9E, /* 24 -> 28, 29, 30, 31 */ 0xB8B8B8B8, + /* NOT USED */ /* SHUFFLE 4 */ /* SHUFFLE 5 */ + /* DG0 */ /* DG0 */ + /* G0 */ /* G0 */ + 0x0, /* 8 -> 0, 1, 2, 3 */ 0x88888888, /* 16 -> 0, 1, 2, 3 */ 0x90909090, + 0x0, /* 8 -> 4, 5, 6, 7 */ 0x88888888, /* 16 -> 4, 5, 6, 7 */ 0x90909090, + 0x0, /* 0 -> 8, 9, 10, 11 */ 0x80808080, /* 16 -> 8, 9, 10, 11 */ 0x90909090, + 0x0, /* 0 -> 12, 13, 14, 15 */ 0x80808080, /* 16 -> 12, 13, 14, 15 */ 0x90909090, + 0x0, /* 24 -> 16, 17, 18, 19 */ 0x98989898, /* 0 -> 16, 17, 18, 19 */ 0x80808080, + 0x0, /* 24 -> 20, 21, 22, 23 */ 0x98989898, /* 0 -> 20, 21, 22, 23 */ 0x80808080, + 0x0, /* 16 -> 24, 25, 26, 27 */ 0x90909090, /* 0 -> 24, 25, 26, 27 */ 0x80808080, + 0x0, /* 16 -> 28, 29, 30, 31 */ 0x90909090, /* 0 -> 28, 29, 30, 31 */ 0x80808080, + /* G1 */ /* G1 */ + 0x0, /* 8 -> 0, 1, 2, 3 */ 0xA8A8A8A8, /* 16 -> 0, 1, 2, 3 */ 0xB0B0B0B0, + 0x0, /* 8 -> 4, 5, 6, 7 */ 0xA8A8A8A8, /* 16 -> 4, 5, 6, 7 */ 0xB0B0B0B0, + 0x0, /* 0 -> 8, 9, 10, 11 */ 0xA0A0A0A0, /* 16 -> 8, 9, 10, 11 */ 0xB0B0B0B0, + 0x0, /* 0 -> 12, 13, 14, 15 */ 0xA0A0A0A0, /* 16 -> 12, 13, 14, 15 */ 0xB0B0B0B0, + 0x0, /* 24 -> 16, 17, 18, 19 */ 0xB8B8B8B8, /* 0 -> 16, 17, 18, 19 */ 0xA0A0A0A0, + 0x0, /* 24 -> 20, 21, 22, 23 */ 0xB8B8B8B8, /* 0 -> 20, 21, 22, 23 */ 0xA0A0A0A0, + 0x0, /* 16 -> 24, 25, 26, 27 */ 0xB0B0B0B0, /* 0 -> 24, 25, 26, 27 */ 0xA0A0A0A0, + 0x0, /* 16 -> 28, 29, 30, 31 */ 0xB0B0B0B0, /* 0 -> 28, 29, 30, 31 */ 0xA0A0A0A0, + /* DG1 */ /* DG1 */ + /* G0 */ /* G0 */ + 0x0, /* 8 -> 0, 1, 2, 3 */ 0x88888888, /* 16 -> 0, 1, 2, 3 */ 0x90909090, + 0x0, /* 8 -> 4, 5, 6, 7 */ 0x88888888, /* 16 -> 4, 5, 6, 7 */ 0x90909090, + 0x0, /* 0 -> 8, 9, 10, 11 */ 0x80808080, /* 16 -> 8, 9, 10, 11 */ 0x90909090, + 0x0, /* 0 -> 12, 13, 14, 15 */ 0x80808080, /* 16 -> 12, 13, 14, 15 */ 0x90909090, + 0x0, /* 24 -> 16, 17, 18, 19 */ 0x98989898, /* 0 -> 16, 17, 18, 19 */ 0x80808080, + 0x0, /* 24 -> 20, 21, 22, 23 */ 0x98989898, /* 0 -> 20, 21, 22, 23 */ 0x80808080, + 0x0, /* 16 -> 24, 25, 26, 27 */ 0x90909090, /* 0 -> 24, 25, 26, 27 */ 0x80808080, + 0x0, /* 16 -> 28, 29, 30, 31 */ 0x90909090, /* 0 -> 28, 29, 30, 31 */ 0x80808080, + /* G1 */ /* G1 */ + 0x0, /* 8 -> 0, 1, 2, 3 */ 0xA8A8A8A8, /* 16 -> 0, 1, 2, 3 */ 0xB0B0B0B0, + 0x0, /* 8 -> 4, 5, 6, 7 */ 0xA8A8A8A8, /* 16 -> 4, 5, 6, 7 */ 0xB0B0B0B0, + 0x0, /* 0 -> 8, 9, 10, 11 */ 0xA0A0A0A0, /* 16 -> 8, 9, 10, 11 */ 0xB0B0B0B0, + 0x0, /* 0 -> 12, 13, 14, 15 */ 0xA0A0A0A0, /* 16 -> 12, 13, 14, 15 */ 0xB0B0B0B0, + 0x0, /* 24 -> 16, 17, 18, 19 */ 0xB8B8B8B8, /* 0 -> 16, 17, 18, 19 */ 0xA0A0A0A0, + 0x0, /* 24 -> 20, 21, 22, 23 */ 0xB8B8B8B8, /* 0 -> 20, 21, 22, 23 */ 0xA0A0A0A0, + 0x0, /* 16 -> 24, 25, 26, 27 */ 0xB0B0B0B0, /* 0 -> 24, 25, 26, 27 */ 0xA0A0A0A0, + 0x0, /* 16 -> 28, 29, 30, 31 */ 0xB0B0B0B0, /* 0 -> 28, 29, 30, 31 */ 0xA0A0A0A0, + /* DG2 */ /* DG2 */ + /* G0 */ /* G0 */ + 0x0, /* 8 -> 0, 1, 2, 3 */ 0x88888888, /* 16 -> 0, 1, 2, 3 */ 0x90909090, + 0x0, /* 8 -> 4, 5, 6, 7 */ 0x88888888, /* 16 -> 4, 5, 6, 7 */ 0x90909090, + 0x0, /* 0 -> 8, 9, 10, 11 */ 0x80808080, /* 16 -> 8, 9, 10, 11 */ 0x90909090, + 0x0, /* 0 -> 12, 13, 14, 15 */ 0x80808080, /* 16 -> 12, 13, 14, 15 */ 0x90909090, + 0x0, /* 24 -> 16, 17, 18, 19 */ 0x98989898, /* 0 -> 16, 17, 18, 19 */ 0x80808080, + 0x0, /* 24 -> 20, 21, 22, 23 */ 0x98989898, /* 0 -> 20, 21, 22, 23 */ 0x80808080, + 0x0, /* 16 -> 24, 25, 26, 27 */ 0x90909090, /* 0 -> 24, 25, 26, 27 */ 0x80808080, + 0x0, /* 16 -> 28, 29, 30, 31 */ 0x90909090, /* 0 -> 28, 29, 30, 31 */ 0x80808080, + /* G1 */ /* G1 */ + 0x0, /* 8 -> 0, 1, 2, 3 */ 0xA8A8A8A8, /* 16 -> 0, 1, 2, 3 */ 0xB0B0B0B0, + 0x0, /* 8 -> 4, 5, 6, 7 */ 0xA8A8A8A8, /* 16 -> 4, 5, 6, 7 */ 0xB0B0B0B0, + 0x0, /* 0 -> 8, 9, 10, 11 */ 0xA0A0A0A0, /* 16 -> 8, 9, 10, 11 */ 0xB0B0B0B0, + 0x0, /* 0 -> 12, 13, 14, 15 */ 0xA0A0A0A0, /* 16 -> 12, 13, 14, 15 */ 0xB0B0B0B0, + 0x0, /* 24 -> 16, 17, 18, 19 */ 0xB8B8B8B8, /* 0 -> 16, 17, 18, 19 */ 0xA0A0A0A0, + 0x0, /* 24 -> 20, 21, 22, 23 */ 0xB8B8B8B8, /* 0 -> 20, 21, 22, 23 */ 0xA0A0A0A0, + 0x0, /* 16 -> 24, 25, 26, 27 */ 0xB0B0B0B0, /* 0 -> 24, 25, 26, 27 */ 0xA0A0A0A0, + 0x0, /* 16 -> 28, 29, 30, 31 */ 0xB0B0B0B0, /* 0 -> 28, 29, 30, 31 */ 0xA0A0A0A0, + /* DG3 */ /* DG3 */ + /* G0 */ /* G0 */ + 0x0, /* 8 -> 0, 1, 2, 3 */ 0x88888888, /* 16 -> 0, 1, 2, 3 */ 0x90909090, + 0x0, /* 8 -> 4, 5, 6, 7 */ 0x88888888, /* 16 -> 4, 5, 6, 7 */ 0x90909090, + 0x0, /* 0 -> 8, 9, 10, 11 */ 0x80808080, /* 16 -> 8, 9, 10, 11 */ 0x90909090, + 0x0, /* 0 -> 12, 13, 14, 15 */ 0x80808080, /* 16 -> 12, 13, 14, 15 */ 0x90909090, + 0x0, /* 24 -> 16, 17, 18, 19 */ 0x98989898, /* 0 -> 16, 17, 18, 19 */ 0x80808080, + 0x0, /* 24 -> 20, 21, 22, 23 */ 0x98989898, /* 0 -> 20, 21, 22, 23 */ 0x80808080, + 0x0, /* 16 -> 24, 25, 26, 27 */ 0x90909090, /* 0 -> 24, 25, 26, 27 */ 0x80808080, + 0x0, /* 16 -> 28, 29, 30, 31 */ 0x90909090, /* 0 -> 28, 29, 30, 31 */ 0x80808080, + /* G1 */ /* G1 */ + 0x0, /* 8 -> 0, 1, 2, 3 */ 0xA8A8A8A8, /* 16 -> 0, 1, 2, 3 */ 0xB0B0B0B0, + 0x0, /* 8 -> 4, 5, 6, 7 */ 0xA8A8A8A8, /* 16 -> 4, 5, 6, 7 */ 0xB0B0B0B0, + 0x0, /* 0 -> 8, 9, 10, 11 */ 0xA0A0A0A0, /* 16 -> 8, 9, 10, 11 */ 0xB0B0B0B0, + 0x0, /* 0 -> 12, 13, 14, 15 */ 0xA0A0A0A0, /* 16 -> 12, 13, 14, 15 */ 0xB0B0B0B0, + 0x0, /* 24 -> 16, 17, 18, 19 */ 0xB8B8B8B8, /* 0 -> 16, 17, 18, 19 */ 0xA0A0A0A0, + 0x0, /* 24 -> 20, 21, 22, 23 */ 0xB8B8B8B8, /* 0 -> 20, 21, 22, 23 */ 0xA0A0A0A0, + 0x0, /* 16 -> 24, 25, 26, 27 */ 0xB0B0B0B0, /* 0 -> 24, 25, 26, 27 */ 0xA0A0A0A0, + 0x0, /* 16 -> 28, 29, 30, 31 */ 0xB0B0B0B0, /* 0 -> 28, 29, 30, 31 */ 0xA0A0A0A0, +}; + +uint8_t *getLUTStartAddressFromFuncID(uint32_t funcID, uint8_t* baseAddr, uint8_t lutPtr) +{ + uint32_t numEntriesID; + uint32_t indexInType; + uint32_t funcOffset; + uint8_t *addr; + if (lutPtr) + { + numEntriesID = funcID & 0x3; + indexInType = (funcID & 0x00FFFFFF) >> 2; //bits 23:2 + addr = baseAddr + (indexInType<<8); + } + else + { + numEntriesID = funcID >> SPECIAL_FUNC_NUM_ENTRIES_IN_FUNCID_OFFSET; + indexInType = funcID & ((1 << SPECIAL_FUNC_NUM_ENTRIES_IN_FUNCID_OFFSET) - 1); + switch (numEntriesID) + { + case 0: + funcOffset = SPECIAL_FUNCS_NUM_OF_CACHE_LINES_IN_FUNC_256 * CACHE_LINE_SIZE_IN_BYTES; + break; + case 1: + funcOffset = SPECIAL_FUNCS_NUM_OF_CACHE_LINES_IN_FUNC_128 * CACHE_LINE_SIZE_IN_BYTES; + break; + case 2: + funcOffset = SPECIAL_FUNCS_NUM_OF_CACHE_LINES_IN_FUNC_64 * CACHE_LINE_SIZE_IN_BYTES; + break; + case 3: + funcOffset = SPECIAL_FUNCS_NUM_OF_CACHE_LINES_IN_FUNC_32 * CACHE_LINE_SIZE_IN_BYTES; + break; + default: + assert(0); + funcOffset = UINT32_MAX; + } + + addr = baseAddr + (funcOffset * indexInType); + } + return addr; +} + +uint32_t getCoefAddrFromOffset(uint8_t offset, bool isLOOKUP, uint32_t elementSize) +{ + if (isLOOKUP) //Generic Lookup + { + // In case of 16b/32b lookups, the elements are conscutive. In case of int8_t, they are duplicated 4 times. + return (offset*sizeof(float)); + } + else if (elementSize==4) //32bit + { + //add 8 bytes at end of each cache line (which has 10 intervals) + uint8_t cacheLinePadding = 8*sizeof(uint8_t)*(offset/SPECIAL_FUNCS_NUM_OF_INTERVALS_IN_CACHE_LINE); + return (offset*SPECIAL_FUNC_BYTES_IN_ENTRY + cacheLinePadding); + } + else //16bit/8bit + { + return (offset*sizeof(uint16_t)); + } +} + +void addTableLookup(uint32_t funcID, uint8_t* baseAddr, uint8_t *tableAddr, uint32_t tableActualSizeInBytes, uint8_t elementSize, uint8_t lutPtr) +{ + uint8_t *targetAddr = getLUTStartAddressFromFuncID(funcID, baseAddr, lutPtr); + if (elementSize == 1) + { + // Duplicate each element 4 times + for (uint32_t itr = 0, targetItr = 0; itr < tableActualSizeInBytes; itr += elementSize, targetItr += sizeof(uint32_t)) + { + for (uint32_t elemItr = targetItr; elemItr < targetItr + sizeof(uint32_t); elemItr += elementSize) + { + memcpy(targetAddr + elemItr, tableAddr + itr, elementSize); + } + } + } + else + { + assert((elementSize == 2 || elementSize == 4) && "Unexpected elementSize"); + // In case elementSize is 2 or 4, copy the table as is + memcpy(targetAddr, tableAddr, tableActualSizeInBytes); + } +} + +void addTableLookupC0C1C2(uint32_t funcID, uint8_t* baseAddr, uint8_t *tableAddr, uint32_t tableActualSizeInBytes, uint8_t elementSize, uint8_t lutPtr) +{ + uint8_t *targetAddr = getLUTStartAddressFromFuncID(funcID, baseAddr, lutPtr); + + if (elementSize==sizeof(float)) + { + for (uint32_t itr = 0; itr < tableActualSizeInBytes; itr += elementSize) + { + // Cache line contains 10 intervals (of 3 coefficients) + 8 bytes of "garbage" + if ((itr>0) && (itr % (SPECIAL_FUNCS_NUM_OF_INTERVALS_IN_CACHE_LINE*SPECIAL_FUNC_BYTES_IN_ENTRY) == 0)) + { + targetAddr= targetAddr + SPECIAL_FUNCS_CACHE_LINE_PADDING; + } + + memcpy(targetAddr, tableAddr, elementSize); + tableAddr+=elementSize; + targetAddr+=elementSize; + } + } + else // 16/8 bits element + { + for (uint32_t itr = 0, target_itr = 0; itr < tableActualSizeInBytes; itr += elementSize, target_itr+=sizeof(uint32_t)) + { + // Cache line contains 10 intervals (of 3 coefficients) + 8 bytes of "garbage" + if ((target_itr>0) && (target_itr % (SPECIAL_FUNCS_NUM_OF_INTERVALS_IN_CACHE_LINE*SPECIAL_FUNC_BYTES_IN_ENTRY) == 0)) + { + targetAddr= targetAddr + SPECIAL_FUNCS_CACHE_LINE_PADDING; + } + + //duplicate data in memory + for (int j=0;j> &specialFunctionCoefficients) +{ + specialFunctionCoefficients[SPECIAL_FUNC_256_ENTRIES].resize(SPECIAL_FUNC256_SIZE_BYTES); + specialFunctionCoefficients[SPECIAL_FUNC_128_ENTRIES].resize(SPECIAL_FUNC128_SIZE_BYTES); + specialFunctionCoefficients[SPECIAL_FUNC_64_ENTRIES].resize(SPECIAL_FUNC64_SIZE_BYTES); + specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES].resize(SPECIAL_FUNC32_SIZE_BYTES); + + //256-intervals tables + addTableLookupC0C1C2(FUNC_ID_FP32_TANH, &specialFunctionCoefficients[SPECIAL_FUNC_256_ENTRIES][0], (uint8_t*)tanh_coeffs_fp32, sizeof(tanh_coeffs_fp32), sizeof(float), 0); + addTableLookupC0C1C2(FUNC_ID_FP32_RSQRT, &specialFunctionCoefficients[SPECIAL_FUNC_256_ENTRIES][0], (uint8_t*)rsqrt_coeffs_fp32, sizeof(rsqrt_coeffs_fp32), sizeof(float), 0); + addTableLookupC0C1C2(FUNC_ID_FP32_LOG2, &specialFunctionCoefficients[SPECIAL_FUNC_256_ENTRIES][0], (uint8_t*)log2_coeffs_fp32, sizeof(log2_coeffs_fp32), sizeof(float), 0); + addTableLookup_8bit(FUNC_ID_INT8_SQRT, &specialFunctionCoefficients[SPECIAL_FUNC_256_ENTRIES][0], (uint8_t*)sqrt_coeffs_int8_scale_1_16, sizeof(sqrt_coeffs_int8_scale_1_16), sizeof(int8_t), 0); + addTableLookup_16bit(FUNC_ID_UINT16_SQUARE, &specialFunctionCoefficients[SPECIAL_FUNC_256_ENTRIES][0], (uint8_t*)square_coeffs_uint16, sizeof(square_coeffs_uint16), sizeof(uint16_t), 0); + addTableLookup(FUNC_ID_UINT32_POWER4, &specialFunctionCoefficients[SPECIAL_FUNC_256_ENTRIES][0], (uint8_t*)power4_coeffs_uint32, sizeof(power4_coeffs_uint32), sizeof(uint32_t), 0); + addTableLookupC0C1C2(FUNC_ID_FP32_ERF, &specialFunctionCoefficients[SPECIAL_FUNC_256_ENTRIES][0], (uint8_t*)erf_coeffs_fp32, sizeof(erf_coeffs_fp32), sizeof(float), 0); + addTableLookupC0C1C2(FUNC_ID_FP32_IMP_TANH, &specialFunctionCoefficients[SPECIAL_FUNC_256_ENTRIES][0], (uint8_t*)tanh_imp_coeffs_fp32, sizeof(tanh_imp_coeffs_fp32), sizeof(float), 0); + + //128-intervals tables + addTableLookupC0C1C2(FUNC_ID_FP32_SQRT, &specialFunctionCoefficients[SPECIAL_FUNC_128_ENTRIES][0], (uint8_t*)sqrt_coeffs_fp32, sizeof(sqrt_coeffs_fp32), sizeof(float), 0); + addTableLookupC0C1C2(FUNC_ID_FP32_RCP, &specialFunctionCoefficients[SPECIAL_FUNC_128_ENTRIES][0], (uint8_t*)recip_coeffs_fp32, sizeof(recip_coeffs_fp32), sizeof(float), 0); + addTableLookupC0C1C2(FUNC_ID_FP32_SINCOS, &specialFunctionCoefficients[SPECIAL_FUNC_128_ENTRIES][0], (uint8_t*)sincos_coeffs_fp32, sizeof(sincos_coeffs_fp32), sizeof(float), 0); + addTableLookup(FUNC_ID_BF16_EXP, &specialFunctionCoefficients[SPECIAL_FUNC_128_ENTRIES][0], (uint8_t*)exp_ftable_bf16, sizeof(exp_ftable_bf16), sizeof(uint16_t),0); + addTableLookupC0C1C2(FUNC_ID_INT16_EXP_NEG_0_16_128ENTRIES, &specialFunctionCoefficients[SPECIAL_FUNC_128_ENTRIES][0], (uint8_t*)expminusx_coeffs_int16_0_16_128_entries, (sizeof(expminusx_coeffs_int16_0_16_128_entries)), sizeof(uint16_t), 0); + addTableLookupC0C1C2(FUNC_ID_REDUCTION_16, &specialFunctionCoefficients[SPECIAL_FUNC_128_ENTRIES][0], (uint8_t*)reduction_shuffle_tab_16, sizeof(reduction_shuffle_tab_16), sizeof(reduction_shuffle_tab_16[0]), 0); + addTableLookupC0C1C2(FUNC_ID_REDUCTION_8, &specialFunctionCoefficients[SPECIAL_FUNC_128_ENTRIES][0], (uint8_t*)reduction_shuffle_tab_8, sizeof(reduction_shuffle_tab_8), sizeof(reduction_shuffle_tab_8[0]), 0); + + //64-intervals tables + addTableLookupC0C1C2(FUNC_ID_FP32_POW2, &specialFunctionCoefficients[SPECIAL_FUNC_64_ENTRIES][0], (uint8_t*)pow2_coeffs_fp32, sizeof(pow2_coeffs_fp32), sizeof(float), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_BF16_TANH, FUNC_ID_BF16_TANH_C0, &specialFunctionCoefficients[SPECIAL_FUNC_64_ENTRIES][0], (uint8_t*)tanh_coeffs_bf16, sizeof(tanh_coeffs_bf16), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_INT16_TANH_0_8, FUNC_ID_INT16_TANH_0_8_C0, &specialFunctionCoefficients[SPECIAL_FUNC_64_ENTRIES][0], (uint8_t*)tanh_coeffs_int16_0_8, sizeof(tanh_coeffs_int16_0_8), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_INT16_SIGMOID_0_8, FUNC_ID_INT16_SIGMOID_0_8_C0, &specialFunctionCoefficients[SPECIAL_FUNC_64_ENTRIES][0], (uint8_t*)sigmoid_coeffs_int16_0_8, sizeof(sigmoid_coeffs_int16_0_8), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_INT16_EXP_NEG_0_16, FUNC_ID_INT16_EXP_NEG_0_16_C0, &specialFunctionCoefficients[SPECIAL_FUNC_64_ENTRIES][0], (uint8_t*)expminusx_coeffs_int16_0_16, sizeof(expminusx_coeffs_int16_0_16), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_INT16_RECIP_1_4, FUNC_ID_INT16_RECIP_1_4_C0, &specialFunctionCoefficients[SPECIAL_FUNC_64_ENTRIES][0], (uint8_t*)recip_coeffs_int16_1_4, sizeof(recip_coeffs_int16_1_4), sizeof(uint16_t), 0); + addTableLookupC0C1C2_8bit(FUNC_ID_INT8_TANH_0_8_LINEAR, FUNC_ID_INT8_TANH_0_8_LINEAR_C0, &specialFunctionCoefficients[SPECIAL_FUNC_64_ENTRIES][0], (uint8_t*)tanh_coeffs_int8_linear, sizeof(tanh_coeffs_int8_linear), sizeof(int8_t), 0); + addTableLookupC0C1C2_8bit(FUNC_ID_INT8_SIGMOID_0_8_LINEAR, FUNC_ID_INT8_SIGMOID_0_8_LINEAR_C0, &specialFunctionCoefficients[SPECIAL_FUNC_64_ENTRIES][0], (uint8_t*)sigmoid_coeffs_0_8_linear, sizeof(sigmoid_coeffs_0_8_linear), sizeof(int8_t), 0); + addTableLookupC0C1C2_8bit(FUNC_ID_INT8_EXP_NEG_0_8_LINEAR, FUNC_ID_UNUSED, &specialFunctionCoefficients[SPECIAL_FUNC_64_ENTRIES][0], (uint8_t*)exp_minusx_0_8_linear, sizeof(exp_minusx_0_8_linear), sizeof(int8_t), 0); + addTableLookup(FUNC_ID_INT16_GELU_MINUS_RELU_0_4, &specialFunctionCoefficients[SPECIAL_FUNC_64_ENTRIES][0], (uint8_t*)gelu_minus_relu_coeffs_int16_0_4, sizeof(gelu_minus_relu_coeffs_int16_0_4), sizeof(int16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_FP16_GELU, FUNC_ID_FP16_GELU_C0, &specialFunctionCoefficients[SPECIAL_FUNC_64_ENTRIES][0], (uint8_t*)gelu_coeffs_fp16, sizeof(gelu_coeffs_fp16), sizeof(uint16_t), 0); + addTableLookupC0C1C2(FUNC_ID_REDUCTION_32, &specialFunctionCoefficients[SPECIAL_FUNC_64_ENTRIES][0], (uint8_t*)reduction_shuffle_tab_32, sizeof(reduction_shuffle_tab_32), sizeof(reduction_shuffle_tab_32[0]), 0); + addTableLookupC0C1C2(FUNC_ID_SWIZZLE_32, &specialFunctionCoefficients[SPECIAL_FUNC_64_ENTRIES][0], (uint8_t*)swizzle_shuffle_tab_32, sizeof(swizzle_shuffle_tab_32), sizeof(swizzle_shuffle_tab_32[0]), 0); + + //32-intervals tables + addTableLookup(FUNC_ID_BF16_RSQRT, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)rsqrt_coeffs_bf16, sizeof(rsqrt_coeffs_bf16), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_BF16_LOG2, FUNC_ID_BF16_LOG2_C0, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)log2_coeffs_bf16, sizeof(log2_coeffs_bf16), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_BF16_SQRT, FUNC_ID_BF16_SQRT_C0, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)sqrt_coeffs_bf16, sizeof(sqrt_coeffs_bf16), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_BF16_RCP, FUNC_ID_BF16_RCP_C0, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)recip_coeffs_bf16, sizeof(recip_coeffs_bf16), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_BF16_SINCOS, FUNC_ID_BF16_SINCOS_C0, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)sincos_coeffs_bf16, sizeof(sincos_coeffs_bf16), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_BF16_POW2, FUNC_ID_BF16_POW2_C0, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)pow2_coeffs_bf16, sizeof(pow2_coeffs_bf16), sizeof(uint16_t), 0); + addTableLookupC0C1C2_8bit(FUNC_ID_INT8_TANH, FUNC_ID_INT8_TANH_C0, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)tanh_coeffs_int8, sizeof(tanh_coeffs_int8), sizeof(int8_t), 0); + + + addTableLookup(FUNC_ID_BF16_RCP_SCALAR_M7, &specialFunctionCoefficients[SPECIAL_FUNC_128_ENTRIES][0],(uint8_t*)recip_bf16_scalar_coeffs_m7, sizeof(recip_bf16_scalar_coeffs_m7), sizeof(uint16_t), 0); + addTableLookup(FUNC_ID_BF16_RCP_LINEAR_M2, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)recip_bf16_linear_coeffs_m2, sizeof(recip_bf16_linear_coeffs_m2), sizeof(uint16_t), 0); + addTableLookup(FUNC_ID_BF16_RCP_LINEAR_M3, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)recip_bf16_linear_coeffs_m3, sizeof(recip_bf16_linear_coeffs_m3), sizeof(uint16_t), 0); + addTableLookup(FUNC_ID_BF16_RCP_LINEAR_M4, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)recip_bf16_linear_coeffs_m4, sizeof(recip_bf16_linear_coeffs_m4), sizeof(uint16_t), 0); + + addTableLookupC0C1C2_16bit(FUNC_ID_BF16_RCP_POLY2_M2_C2C1,FUNC_ID_BF16_RCP_POLY2_M2_C0,&specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0],(uint8_t*)recip_bf16_poly2_coeffs_m2,sizeof(recip_bf16_poly2_coeffs_m2), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_BF16_RCP_POLY2_M3_C2C1,FUNC_ID_BF16_RCP_POLY2_M3_C0,&specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0],(uint8_t*)recip_bf16_poly2_coeffs_m3,sizeof(recip_bf16_poly2_coeffs_m3), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_BF16_RCP_POLY2_M4_C2C1,FUNC_ID_BF16_RCP_POLY2_M4_C0,&specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0],(uint8_t*)recip_bf16_poly2_coeffs_m4,sizeof(recip_bf16_poly2_coeffs_m4), sizeof(uint16_t), 0); + + addTableLookup(FUNC_ID_BF16_C0_RECIP, &specialFunctionCoefficients[SPECIAL_FUNC_64_ENTRIES][0], (uint8_t*)recip_coeffs_c0_bf16, sizeof(recip_coeffs_c0_bf16), sizeof(uint16_t), 0); + + addTableLookup(FUNC_ID_BF16_SQRT_SCALAR_M6, &specialFunctionCoefficients[SPECIAL_FUNC_64_ENTRIES][0], (uint8_t*)sqrt_bf16_const_coeffs_m6, sizeof(sqrt_bf16_const_coeffs_m6), sizeof(uint16_t), 0); + addTableLookup(FUNC_ID_BF16_SQRT_LINEAR_M2, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)sqrt_bf16_linear_coeffs_m2, sizeof(sqrt_bf16_linear_coeffs_m2), sizeof(uint16_t), 0); + addTableLookup(FUNC_ID_BF16_SQRT_LINEAR_M3, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)sqrt_bf16_linear_coeffs_m3, sizeof(sqrt_bf16_linear_coeffs_m3), sizeof(uint16_t), 0); + addTableLookup(FUNC_ID_BF16_SQRT_LINEAR_M4, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)sqrt_bf16_linear_coeffs_m4, sizeof(sqrt_bf16_linear_coeffs_m4), sizeof(uint16_t), 0); + + addTableLookupC0C1C2_16bit(FUNC_ID_BF16_SQRT_POLY2_M2_C2C1,FUNC_ID_BF16_SQRT_POLY2_M2_C0,&specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0],(uint8_t*)sqrt_bf16_poly2_coeffs_m2,sizeof(sqrt_bf16_poly2_coeffs_m2), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_BF16_SQRT_POLY2_M3_C2C1,FUNC_ID_BF16_SQRT_POLY2_M3_C0,&specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0],(uint8_t*)sqrt_bf16_poly2_coeffs_m3,sizeof(sqrt_bf16_poly2_coeffs_m3), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_BF16_SQRT_POLY2_M4_C2C1,FUNC_ID_BF16_SQRT_POLY2_M4_C0,&specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0],(uint8_t*)sqrt_bf16_poly2_coeffs_m4,sizeof(sqrt_bf16_poly2_coeffs_m4), sizeof(uint16_t), 0); + + addTableLookup(FUNC_ID_BF16_RSQRT_SCALAR_M6, &specialFunctionCoefficients[SPECIAL_FUNC_64_ENTRIES][0], (uint8_t*)rsqrt_bf16_const_coeffs_m6, sizeof(rsqrt_bf16_const_coeffs_m6), sizeof(uint16_t), 0); + addTableLookup(FUNC_ID_BF16_RSQRT_LINEAR_M2, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)rsqrt_bf16_linear_coeffs_m2, sizeof(rsqrt_bf16_linear_coeffs_m2), sizeof(uint16_t), 0); + addTableLookup(FUNC_ID_BF16_RSQRT_LINEAR_M3, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)rsqrt_bf16_linear_coeffs_m3, sizeof(rsqrt_bf16_linear_coeffs_m3), sizeof(uint16_t), 0); + addTableLookup(FUNC_ID_BF16_RSQRT_LINEAR_M4, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)rsqrt_bf16_linear_coeffs_m4, sizeof(rsqrt_bf16_linear_coeffs_m4), sizeof(uint16_t), 0); + + addTableLookupC0C1C2_16bit(FUNC_ID_BF16_RSQRT_POLY2_M2_C2C1, FUNC_ID_BF16_RSQRT_POLY2_M2_C0, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)rsqrt_bf16_poly2_coeffs_m2, sizeof(rsqrt_bf16_poly2_coeffs_m2), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_BF16_RSQRT_POLY2_M3_C2C1, FUNC_ID_BF16_RSQRT_POLY2_M3_C0, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)rsqrt_bf16_poly2_coeffs_m3, sizeof(rsqrt_bf16_poly2_coeffs_m3), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_BF16_RSQRT_POLY2_M4_C2C1, FUNC_ID_BF16_RSQRT_POLY2_M4_C0, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)rsqrt_bf16_poly2_coeffs_m4, sizeof(rsqrt_bf16_poly2_coeffs_m4), sizeof(uint16_t), 0); + + addTableLookup(FUNC_ID_BF16_TANH_LINEAR_M2, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)tanh_bf16_linear_coeffs_m2, sizeof(tanh_bf16_linear_coeffs_m2), sizeof(uint16_t), 0); + addTableLookup(FUNC_ID_BF16_TANH_LINEAR_M3, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)tanh_bf16_linear_coeffs_m3, sizeof(tanh_bf16_linear_coeffs_m3), sizeof(uint16_t), 0); + addTableLookup(FUNC_ID_BF16_TANH_LINEAR_M4, &specialFunctionCoefficients[SPECIAL_FUNC_64_ENTRIES][0], (uint8_t*)tanh_bf16_linear_coeffs_m4, sizeof(tanh_bf16_linear_coeffs_m4), sizeof(uint16_t), 0); + + addTableLookupC0C1C2_16bit(FUNC_ID_BF16_TANH_POLY2_M2_C2C1,FUNC_ID_BF16_TANH_POLY2_M2_C0,&specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0],(uint8_t*)tanh_bf16_poly2_coeffs_m2,sizeof(tanh_bf16_poly2_coeffs_m2), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_BF16_TANH_POLY2_M3_C2C1,FUNC_ID_BF16_TANH_POLY2_M3_C0,&specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0],(uint8_t*)tanh_bf16_poly2_coeffs_m3,sizeof(tanh_bf16_poly2_coeffs_m3), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_BF16_TANH_POLY2_M4_C2C1,FUNC_ID_BF16_TANH_POLY2_M4_C0,&specialFunctionCoefficients[SPECIAL_FUNC_64_ENTRIES][0],(uint8_t*)tanh_bf16_poly2_coeffs_m4,sizeof(tanh_bf16_poly2_coeffs_m4), sizeof(uint16_t), 0); + + addTableLookup(FUNC_ID_BF16_LOG2ML_LINEAR_M4_0_075, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)log2m1_bf16_linear_coeffs_m4_0_075, sizeof(log2m1_bf16_linear_coeffs_m4_0_075), sizeof(uint16_t), 0); + addTableLookup(FUNC_ID_BF16_LOG2_LINEAR_M5, &specialFunctionCoefficients[SPECIAL_FUNC_64_ENTRIES][0], (uint8_t*)log2_bf16_linear_coeffs_m5, sizeof(log2_bf16_linear_coeffs_m5), sizeof(uint16_t), 0); + addTableLookup(FUNC_ID_BF16_LOG2_LINEAR_INTERLEAVED_M5, &specialFunctionCoefficients[SPECIAL_FUNC_128_ENTRIES][0], (uint8_t*)log2_bf16_linear_coeffs_interleaved_m5, sizeof(log2_bf16_linear_coeffs_interleaved_m5), sizeof(uint16_t), 0); + addTableLookup(FUNC_ID_BF16_LOG2_LINEAR_GAUDI2_M5, &specialFunctionCoefficients[SPECIAL_FUNC_128_ENTRIES][0], (uint8_t*)log2_bf16_linear_gaudi2_coeffs_m5, sizeof(log2_bf16_linear_gaudi2_coeffs_m5), sizeof(uint16_t), 0); + + addTableLookup(FUNC_ID_BF16_SINCOS_SCALAR_M7, &specialFunctionCoefficients[SPECIAL_FUNC_128_ENTRIES][0],(uint8_t*)sincos_bf16_scalar_coeffs_m7, sizeof(sincos_bf16_scalar_coeffs_m7), sizeof(uint16_t), 0); + addTableLookup(FUNC_ID_BF16_SINCOS_LINEAR_M6, &specialFunctionCoefficients[SPECIAL_FUNC_128_ENTRIES][0],(uint8_t*)sincos_bf16_linear_coeffs_m6, sizeof(sincos_bf16_linear_coeffs_m6), sizeof(uint16_t), 0); + addTableLookup(FUNC_ID_BF16_SINCOS_LINEAR_M5, &specialFunctionCoefficients[SPECIAL_FUNC_64_ENTRIES][0],(uint8_t*)sincos_bf16_linear_coeffs_m5, sizeof(sincos_bf16_linear_coeffs_m5), sizeof(uint16_t), 0); + addTableLookup(FUNC_ID_BF16_SINCOS_LINEAR_M4, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0],(uint8_t*)sincos_bf16_linear_coeffs_m4, sizeof(sincos_bf16_linear_coeffs_m4), sizeof(uint16_t), 0); + addTableLookup(FUNC_ID_BF16_SINCOS_LINEAR_M3, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0],(uint8_t*)sincos_bf16_linear_coeffs_m3, sizeof(sincos_bf16_linear_coeffs_m3), sizeof(uint16_t), 0); + addTableLookup(FUNC_ID_BF16_SINCOS_LINEAR_M2, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0],(uint8_t*)sincos_bf16_linear_coeffs_m2, sizeof(sincos_bf16_linear_coeffs_m2), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_BF16_SINCOS_POLY2_M6_C2C1,FUNC_ID_BF16_SINCOS_POLY2_M6_C0,&specialFunctionCoefficients[SPECIAL_FUNC_128_ENTRIES][0],(uint8_t*)sincos_bf16_poly2_coeffs_m6, sizeof(sincos_bf16_poly2_coeffs_m6), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_BF16_SINCOS_POLY2_M5_C2C1,FUNC_ID_BF16_SINCOS_POLY2_M5_C0,&specialFunctionCoefficients[SPECIAL_FUNC_64_ENTRIES][0],(uint8_t*)sincos_bf16_poly2_coeffs_m5, sizeof(sincos_bf16_poly2_coeffs_m5), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_BF16_SINCOS_POLY2_M4_C2C1,FUNC_ID_BF16_SINCOS_POLY2_M4_C0,&specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0],(uint8_t*)sincos_bf16_poly2_coeffs_m4, sizeof(sincos_bf16_poly2_coeffs_m4), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_BF16_SINCOS_POLY2_M3_C2C1,FUNC_ID_BF16_SINCOS_POLY2_M3_C0,&specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0],(uint8_t*)sincos_bf16_poly2_coeffs_m3, sizeof(sincos_bf16_poly2_coeffs_m3), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_BF16_SINCOS_POLY2_M2_C2C1,FUNC_ID_BF16_SINCOS_POLY2_M2_C0,&specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0],(uint8_t*)sincos_bf16_poly2_coeffs_m2, sizeof(sincos_bf16_poly2_coeffs_m2), sizeof(uint16_t), 0); + + addTableLookupC0C1C2_16bit(FUNC_ID_FP16_RCP, FUNC_ID_FP16_RCP_C0, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)recip_coeffs_fp16, sizeof(recip_coeffs_fp16), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_FP16_TANH, FUNC_ID_FP16_TANH_C0, &specialFunctionCoefficients[SPECIAL_FUNC_64_ENTRIES][0], (uint8_t*)tanh_coeffs_fp16, sizeof(tanh_coeffs_fp16), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_FP16_LOG2, FUNC_ID_FP16_LOG2_C0, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)log2_coeffs_fp16, sizeof(log2_coeffs_fp16), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_FP16_SQRT, FUNC_ID_FP16_SQRT_C0, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)sqrt_coeffs_fp16, sizeof(sqrt_coeffs_fp16), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_FP16_RSQRT, FUNC_ID_FP16_RSQRT_C0, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)rsqrt_coeffs_fp16, sizeof(rsqrt_coeffs_fp16), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_FP16_SINCOS, FUNC_ID_FP16_SINCOS_C0, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)sincos_coeffs_fp16, sizeof(sincos_coeffs_fp16), sizeof(uint16_t), 0); + addTableLookupC0C1C2_16bit(FUNC_ID_FP16_POW2, FUNC_ID_FP16_POW2_C0, &specialFunctionCoefficients[SPECIAL_FUNC_32_ENTRIES][0], (uint8_t*)pow2_coeffs_fp16, sizeof(pow2_coeffs_fp16), sizeof(uint16_t), 0); +} + +// clang-format on + +} // namespace tpc_gaudi2 +// clang-format on diff --git a/synapse_backend/runner/TensorDescriptorGen2.cpp b/synapse_backend/runner/TensorDescriptorGen2.cpp index d154855..f40bc12 100644 --- a/synapse_backend/runner/TensorDescriptorGen2.cpp +++ b/synapse_backend/runner/TensorDescriptorGen2.cpp @@ -5,7 +5,7 @@ * */ -#include "TPC_IO_REG_SPACE_GEN2.h" +#include "gaudi/TPC_IO_REG_SPACE_GEN2.h" #include "TensorDescriptor.h" uint32_t gen2_TensorDescriptorElementSizeType(uint32_t configuration) @@ -65,4 +65,5 @@ uint32_t get_ElementSizeInBytesFromDataType(TensorDataType DataType) } return 0; } -} +} //namespace tpc_gaudi + diff --git a/synapse_backend/runner/TensorDescriptorGen6.cpp b/synapse_backend/runner/TensorDescriptorGen6.cpp new file mode 100644 index 0000000..2bb77f1 --- /dev/null +++ b/synapse_backend/runner/TensorDescriptorGen6.cpp @@ -0,0 +1,96 @@ +/***************************************************************************** + * Copyright (C) 2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + * Unauthorized copying of this file, via any medium is strictly prohibited. + * Proprietary and confidential. + ****************************************************************************** + */ + +#include "TensorDescriptor.h" +#include "gaudi2/TPC_IO_REG_SPACE_GEN6.h" + +uint32_t gen6_TensorDescriptorElementSizeType(uint32_t configuration) +{ + return ((configuration & KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK) >> + KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT); +} + +uint32_t gen6_TensorDescriptorValidDimMask(uint32_t configuration) +{ + return ((configuration & KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK) >> + KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT); +} + +uint32_t gen6_TensorDescriptorLastDim(uint32_t configuration) +{ + return ((configuration & KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK) >> + KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT); +} + +uint32_t gen6_TensorDescriptorLastDim64(uint32_t configuration) +{ + return ((configuration & KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM64_MASK) >> + KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM64_SHIFT); +} + +uint32_t gen6_TensorDescriptorL0CD(uint32_t configuration) +{ + return ((configuration & KERNEL_TENSOR_0_TENSOR_CONFIG_L0CD_MASK) >> KERNEL_TENSOR_0_TENSOR_CONFIG_L0CD_SHIFT); +} + +uint32_t gen6_get_TensorDescriptorRMW_set(uint32_t configuration) +{ + return ((configuration & KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_SET_MASK) >> + KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_SET_SHIFT); +} + +uint32_t gen6_get_TensorDescriptorRMW_op(uint32_t configuration) +{ + return ((configuration & KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_OP_MASK) >> KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_OP_SHIFT); +} + +namespace tpc_gaudi2 +{ +uint32_t TensorDescriptorConfiguration(uint32_t dataType, + uint32_t validDimMask, + uint32_t lastDim, + uint32_t rmwSel, + uint32_t rmwOp, + uint32_t dup_oob, + uint32_t l0cd, + uint32_t lastDim64, + uint32_t hw_pref_dis) +{ + return ( + ((dataType << KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT) & KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK) | + ((validDimMask << KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT) & + KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK) | + ((lastDim << KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT) & KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK) | + ((lastDim64 << KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM64_SHIFT) & + KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM64_MASK) | + ((l0cd << KERNEL_TENSOR_0_TENSOR_CONFIG_L0CD_SHIFT) & KERNEL_TENSOR_0_TENSOR_CONFIG_L0CD_MASK) | + ((hw_pref_dis << KERNEL_TENSOR_0_TENSOR_CONFIG_T_PREF_DIS_SHIFT) & + KERNEL_TENSOR_0_TENSOR_CONFIG_T_PREF_DIS_MASK) | + ((dup_oob << KERNEL_TENSOR_0_TENSOR_CONFIG_DUP_OOB_SHIFT) & KERNEL_TENSOR_0_TENSOR_CONFIG_DUP_OOB_MASK) | + ((rmwSel << KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_SET_SHIFT) & KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_SET_MASK) | + ((rmwOp << KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_OP_SHIFT) & KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_OP_MASK)); +} + +uint32_t get_ElementSizeInBytesFromDataType(TensorDataType DataType) +{ + switch (DataType) { + case TensorDT_INT8: + case TensorDT_UINT8: + case TensorDT_INT16: + case TensorDT_UINT16: + case TensorDT_BF16: + case TensorDT_FP16: return 2; + case TensorDT_INT32: + case TensorDT_UINT32: + case TensorDT_FP32: return 4; + default: assert(0 && "This is not a valid DataType"); break; + } + return 0; +} +} // namespace tpc_gaudi2 \ No newline at end of file diff --git a/synapse_backend/runner/thunk_runner.cpp b/synapse_backend/runner/thunk_runner.cpp index a36b2f7..10c5ce6 100644 --- a/synapse_backend/runner/thunk_runner.cpp +++ b/synapse_backend/runner/thunk_runner.cpp @@ -6,8 +6,6 @@ */ #include "runtime.h" -#include "asic_reg_structs/tpc_regs.h" -#include "gaudi_device.h" #include #include "index_space.h" #include @@ -80,7 +78,7 @@ void LoadSpecialFuncTab(std::list& inputBuffers, DeviceMemory_t memSpace } unsigned int -RunKernel(std::vector& descriptors, +RunKernel(std::vector& descriptors, const gcapi::HabanaKernelParams_t& gc_input, const gcapi::HabanaKernelInstantiation_t& gc_output, bool specialFunctionUsed, @@ -184,9 +182,6 @@ RunKernel(std::vector& descriptors, { unsigned j = i % tpcIds.size(); - // generates a unique context ID for each TPC for trace use. - uint32_t contextId = (uint32_t)0xab + tpcIds[j]; - uint32_t soAddr = (uint32_t)c_syncObjectAddr; // if this tpc id receives more then one descriptor - we write 0 to the sync object. uint32_t soMsg = 0x80000000; @@ -196,13 +191,11 @@ RunKernel(std::vector& descriptors, soMsg = 0x80000001; } - uint32_t soIdx = (uint32_t)c_syncObjectIndex; - // Explanation for (i == 0 ? 0 : s_printfIsUsed) : // in the first invocation there is no need to update the base address of the printf // tensor runner.m_device.GetHal()->WriteTpcJobDesc( - mainDesc, partition[i], contextId, soAddr, soMsg, soIdx, + mainDesc, partition[i], soAddr, soMsg, 0, 15); // write TPC descriptor to queue manager. @@ -229,32 +222,22 @@ RunKernel(std::vector& descriptors, baseAddrHigh, specialFuncTabAddresses[tabIdx] >> 32)); } } - // set SM_BASE_ADDRESS_HIGH - tpcProgram[activeTpcCount * qidx + j].AddCommandsBack( - *runner.m_device.GetHal()->GenWReg32( - runner.m_device.GetHal()->GetTpcCfgVarOffset("sm_base_address_high"), - (runner.m_device.GetHal()->GetSyncManagerBaseAddr() >> 32))); - // Invalidate ICache/DCache/LCache/TCache - tpc::reg_tpc_cmd command; - memset(&command, 0, sizeof(command)); - command.icache_invalidate = 1; - command.dcache_invalidate = 1; - command.lcache_invalidate = 1; - command.tcache_invalidate = 1; - command.icache_prefetch_64kb = 0; + uint32_t tpc_cmd = runner.m_device.GetHal()->GenTpcCmd(); bool msgBarrier = 0; bool regBarrier = 0; bool engBarrier = 1; // TPC cmd - tpcProgram[activeTpcCount * qidx + j].AddCommandsBack( - *runner.m_device.GetHal()->GenWReg32( - runner.m_device.GetHal()->GetTpcCfgVarOffset("tpc_cmd"), command._raw, - msgBarrier, regBarrier, engBarrier)); + auto pMsgLong_tpc_cmd = runner.m_device.GetHal()->GenWReg32( + runner.m_device.GetHal()->GetTpcCfgVarOffset("tpc_cmd"), //addr + tpc_cmd, //value + msgBarrier, regBarrier, engBarrier); + tpcProgram[activeTpcCount * qidx + j].AddCommandsBack(*pMsgLong_tpc_cmd); // TPC execute - tpcProgram[activeTpcCount * qidx + j].AddCommandsBack( - *runner.m_device.GetHal()->GenWReg32( - runner.m_device.GetHal()->GetTpcCfgVarOffset("tpc_execute"), 1)); + auto pMsgLong_tpc_exec = runner.m_device.GetHal()->GenWReg32( + runner.m_device.GetHal()->GetTpcCfgVarOffset("tpc_execute"), //addr + 1); // value + tpcProgram[activeTpcCount * qidx + j].AddCommandsBack(*pMsgLong_tpc_exec); } } @@ -281,4 +264,4 @@ RunKernel(std::vector& descriptors, free(mainDesc); return 0; -} \ No newline at end of file +} diff --git a/synapse_core/graph.h b/synapse_core/graph.h index 87cbd00..bf77a60 100644 --- a/synapse_core/graph.h +++ b/synapse_core/graph.h @@ -12,17 +12,21 @@ #include "tensor.h" #include "node.h" +#include "synapse_common_types.h" + class Graph { public: - Graph() : m_node(nullptr), m_nodeCount(0) {} + Graph(synDeviceType deviceType) : m_node(nullptr), m_nodeCount(0), m_deviceType(deviceType) {} ~Graph(); bool addNode(Node* node); const Node* getNode(); + synDeviceType getDeviceType() const {return m_deviceType;} private: Node* m_node; unsigned m_nodeCount; std::mutex m_mutex; + synDeviceType m_deviceType; }; diff --git a/synapse_core/kernel_db.cpp b/synapse_core/kernel_db.cpp index 2e46a81..c8d86f2 100644 --- a/synapse_core/kernel_db.cpp +++ b/synapse_core/kernel_db.cpp @@ -10,6 +10,7 @@ #include #include "kernel_db.h" #include "gc_interface.h" +#include "recipe.h" using namespace gcapi; @@ -37,9 +38,10 @@ void KernelDB::clear() } m_libEntry = nullptr; m_loadedKernels.clear(); + m_initalized = false; } -void KernelDB::init() +void KernelDB::init(synDeviceType deviceType) { std::lock_guard l(m_mutex); if (m_libHandle != nullptr) return; @@ -61,7 +63,7 @@ void KernelDB::init() gcapi::GlueCodeReturn_t ret; unsigned kernelCount = 0; - ret = nameFunc(nullptr, &kernelCount, gcapi::DEVICE_ID_GAUDI); + ret = nameFunc(nullptr, &kernelCount, deviceIdfromDeviceType(deviceType)); if (ret != gcapi::GLUE_SUCCESS) { return; @@ -75,7 +77,7 @@ void KernelDB::init() kernelNames[kernel] = new char[gcapi::MAX_NODE_NAME]; } - ret = nameFunc(kernelNames, &kernelCount, gcapi::DEVICE_ID_GAUDI); + ret = nameFunc(kernelNames, &kernelCount, deviceIdfromDeviceType(deviceType)); if (ret != gcapi::GLUE_SUCCESS) { for (unsigned i = 0; i < kernelCount; i++) @@ -92,6 +94,7 @@ void KernelDB::init() delete[] kernelNames[i]; } delete[] kernelNames; + m_initalized = true; } bool KernelDB::isKernelExist(const std::string &guid) const @@ -113,3 +116,7 @@ GlueCodeReturn_t KernelDB::GetKernelInstantiation(HabanaKernelParams_t* params, return m_libEntry(params, instance); } +bool KernelDB::initialized() { + std::lock_guard l(m_mutex); + return m_initalized; +} diff --git a/synapse_core/kernel_db.h b/synapse_core/kernel_db.h index 8610efb..e3bf0ae 100644 --- a/synapse_core/kernel_db.h +++ b/synapse_core/kernel_db.h @@ -10,6 +10,7 @@ #include #include #include "gc_interface.h" +#include "synapse_common_types.h" class KernelDB { @@ -21,7 +22,8 @@ class KernelDB KernelDB(); ~KernelDB(); - void init(); + void init(synDeviceType deviceType); + bool initialized(); void clear(); gcapi::GlueCodeReturn_t GetKernelInstantiation(gcapi::HabanaKernelParams_t* params, gcapi::HabanaKernelInstantiation_t* instance); @@ -33,5 +35,6 @@ class KernelDB std::unordered_set m_loadedKernels; libHandle m_libHandle; gcapi::pfnHabanaKernel m_libEntry; + bool m_initalized = false; }; diff --git a/synapse_core/recipe.cpp b/synapse_core/recipe.cpp index 23de56f..c91ba65 100644 --- a/synapse_core/recipe.cpp +++ b/synapse_core/recipe.cpp @@ -7,13 +7,25 @@ #include #include +#include "gaudi/gaudi_device.h" +#include "gaudi2/gaudi2_device.h" +#include "hw_abstraction_layer.h" #include "recipe.h" +#include "synapse_common_types.h" +#include "synapse_state.h" #include "tpc_elf_api.hpp" -Recipe::Recipe() : m_params(nullptr), m_paramSize(0), m_numInputs(0), m_numAuxTensors(0), m_firstAux(0), m_auxBuffer(nullptr), m_elfBuffer(nullptr) +Recipe::Recipe(const synDeviceType deviceType) { - memset(&m_kernelParams, 0, sizeof(m_kernelParams)); - memset(&m_kernelInstance, 0, sizeof(m_kernelInstance)); + switch(deviceType) + { + case synDeviceGaudi: + m_hal = std::make_shared(); + case synDeviceGaudi2: + m_hal = std::make_shared(); + default: + assert(0 && "unsupported device type"); + } } Recipe::~Recipe() @@ -47,7 +59,7 @@ void Recipe::Compile(Graph *g, KernelDB* db) } m_guid = node->GetGUID(); - SetKernelParams(); + SetKernelParams(g->getDeviceType()); gcapi::GlueCodeReturn_t ret = db->GetKernelInstantiation(&m_kernelParams, &m_kernelInstance); while (ret != gcapi::GLUE_SUCCESS) { @@ -116,7 +128,7 @@ void Recipe::PartitionIndexSpace() if (idxSpace.size[i] == 0) idxSpace.size[i] = 1; } - const unsigned nPartitions = 8; + const unsigned nPartitions = GetHal()->GetTPCNr(); curPartition.push_back(idxSpace); while (curPartition.size() < nPartitions) { @@ -142,17 +154,35 @@ void Recipe::PartitionIndexSpace() m_indexSpacePartition.insert(m_indexSpacePartition.end(), curPartition.begin(), curPartition.end()); } -void Recipe::SetKernelParams() +gcapi::DeviceId_t deviceIdfromDeviceType(synDeviceType deviceType) +{ + switch (deviceType) + { + case synDeviceGaudi: return gcapi::DEVICE_ID_GAUDI; + case synDeviceGaudi2: return gcapi::DEVICE_ID_GAUDI2; + + default: + { + assert(0); + return gcapi::DEVICE_ID_MAX; + } + } + + assert(0); + return gcapi::DEVICE_ID_MAX; +} + +void Recipe::SetKernelParams(synDeviceType deviceType) { m_kernelParams.NodeParams = m_params; m_kernelParams.NodeParamsSize = m_paramSize; m_kernelParams.kernelType = gcapi::KERNEL_TYPE_INFERENCE; - m_kernelParams.deviceId = gcapi::DEVICE_ID_GAUDI; + m_kernelParams.deviceId = deviceIdfromDeviceType(deviceType); m_kernelParams.apiVersion = 1; m_kernelParams.inputTensorNr = m_numInputs; m_kernelParams.outputTensorNr = m_tensors.size() - m_numInputs; m_kernelParams.debugFlags = 0; - m_kernelParams.maxAvailableTpc = 8; + m_kernelParams.maxAvailableTpc = GetHal()->GetTPCNr(); memcpy(m_kernelParams.nodeName, m_guid.c_str(), std::min(m_guid.size(), (size_t)gcapi::MAX_NODE_NAME)); for (unsigned i = 0; i < m_numInputs; ++i) @@ -236,4 +266,4 @@ void* Recipe::GetAuxHostPtr(unsigned int idx) { if (!IsTensorAux(idx)) return 0; return m_auxTensorData[idx - m_firstAux].first; -} \ No newline at end of file +} diff --git a/synapse_core/recipe.h b/synapse_core/recipe.h index d814491..7ef551e 100644 --- a/synapse_core/recipe.h +++ b/synapse_core/recipe.h @@ -10,14 +10,17 @@ #include #include #include "graph.h" +#include "hw_abstraction_layer.h" #include "node.h" #include "kernel_db.h" #include "index_space.h" +gcapi::DeviceId_t deviceIdfromDeviceType(synDeviceType deviceType); + class Recipe { public: - Recipe(); + Recipe(const synDeviceType deviceType); ~Recipe(); void Compile(Graph* g, KernelDB* db); @@ -37,7 +40,7 @@ class Recipe void* GetAuxHostPtr(unsigned idx); protected: - void SetKernelParams(); + void SetKernelParams(synDeviceType deviceType); void SetTensor(gcapi::Tensor_t* gTensor, Tensor* tensor); @@ -45,23 +48,24 @@ class Recipe void AllocateELFBuffer(); void PartitionIndexSpace(); - + std::shared_ptr GetHal() {return m_hal;} typedef std::pair AuxTensorData; private: std::vector m_tensors; std::string m_guid; - char* m_params; - unsigned m_paramSize; - unsigned m_numInputs; - unsigned m_numAuxTensors; - unsigned m_firstAux; - char* m_auxBuffer; - char* m_elfBuffer; - - std::vector m_auxTensorData; - std::vector m_indexSpacePartition; + char* m_params = nullptr; + unsigned m_paramSize = 0; + unsigned m_numInputs = 0; + unsigned m_numAuxTensors = 0; + unsigned m_firstAux = 0; + char* m_auxBuffer = nullptr; + char* m_elfBuffer = nullptr; - gcapi::HabanaKernelParams_t m_kernelParams; - gcapi::HabanaKernelInstantiation_t m_kernelInstance; + std::vector m_auxTensorData; + std::vector m_indexSpacePartition; + + gcapi::HabanaKernelParams_t m_kernelParams = {0}; + gcapi::HabanaKernelInstantiation_t m_kernelInstance = {{0}}; + std::shared_ptr m_hal = nullptr; }; diff --git a/synapse_core/synapse_core.cpp b/synapse_core/synapse_core.cpp index 225737a..4816c1f 100644 --- a/synapse_core/synapse_core.cpp +++ b/synapse_core/synapse_core.cpp @@ -7,6 +7,7 @@ #include #include "synapse_api.h" +#include "synapse_common_types.h" #include "synapse_state.h" #include "graph.h" #include "tensor.h" @@ -302,15 +303,23 @@ synStatus SYN_API_CALL synDeviceGetCount( uint32_t* pCount ) synStatus SYN_API_CALL synDeviceGetCountByDeviceType( uint32_t* pCount, const synDeviceType deviceType ) { - if ((deviceType != synDeviceGaudi)) return synInvalidArgument; - return synDeviceGetCount(pCount); + switch(deviceType) + { + case synDeviceGaudi: + case synDeviceGaudi2: + return synDeviceGetCount(pCount); + default: + return synInvalidArgument; + } } synStatus SYN_API_CALL synDeviceAcquireByDeviceType( synDeviceId* pDeviceId, const synDeviceType deviceType) { - if ((deviceType != synDeviceGaudi)) return synInvalidArgument; - return synDeviceAcquire(pDeviceId, ""); + bool ret = g_state.OpenDevice("", deviceType); + if (!ret) return synFail; + *pDeviceId = 0; + return synSuccess; } synStatus SYN_API_CALL synDeviceAcquireByModuleId( synDeviceId* pDeviceId, @@ -323,10 +332,7 @@ synStatus SYN_API_CALL synDeviceAcquire( synDeviceId* pDeviceId, const char* pciBus ) { if (pDeviceId == nullptr) return synInvalidArgument; - bool ret = g_state.OpenDevice(pciBus); - if (!ret) return synFail; - *pDeviceId = 0; - return synSuccess; + return synUnsupported; } synStatus SYN_API_CALL synDeviceSynchronize( const synDeviceId deviceId ) @@ -358,12 +364,23 @@ synStatus SYN_API_CALL synDeviceGetName( char* pName, const synDeviceId deviceId ) { static const char s_gaudiDeviceName[] = "Gaudi"; + static const char s_gaudi2DeviceName[] = "Gaudi2"; if (deviceId != 0) return synInvalidArgument; if (pName == nullptr) return synInvalidArgument; if (len < sizeof(s_gaudiDeviceName)) return synInvalidArgument; - memcpy(pName, s_gaudiDeviceName, sizeof(s_gaudiDeviceName)); + switch(g_state.getCurrentDeviceType()) + { + case synDeviceGaudi: + memcpy(pName, s_gaudiDeviceName, sizeof(s_gaudiDeviceName)); + break; + case synDeviceGaudi2: + memcpy(pName, s_gaudi2DeviceName, sizeof(s_gaudiDeviceName)); + break; + default: + return synInvalidArgument; + } return synSuccess; } @@ -528,8 +545,8 @@ synStatus SYN_API_CALL synGraphCompile( synRecipeHandle* pRecipeH Graph* g = (Graph*)graphHandle; if (g == nullptr) return synInvalidArgument; - Recipe* r = new Recipe(); - r->Compile(g, g_state.GetKernelDB()); + Recipe* r = new Recipe(g->getDeviceType()); + r->Compile(g, g_state.GetKernelDB(g->getDeviceType())); *pRecipeHandle = (synRecipeHandle)r; return synSuccess; } @@ -544,7 +561,8 @@ synStatus SYN_API_CALL synGraphCreate( synGraphHandle* pGraphHandle, switch (deviceType) { case synDeviceGaudi: - g = new Graph(); + case synDeviceGaudi2: + g = new Graph(deviceType); *pGraphHandle = (synGraphHandle)g; return synSuccess; @@ -768,7 +786,7 @@ synStatus SYN_API_CALL synDeviceGetAttribute( uint64_t* retVal, break; default: - return synDeviceTypeGetAttribute(retVal, deviceAttr, querySize, synDeviceGaudi); + return synDeviceTypeGetAttribute(retVal, deviceAttr, querySize, g_state.getCurrentDeviceType()); } return synSuccess; } @@ -779,7 +797,7 @@ synStatus SYN_API_CALL synDeviceTypeGetAttribute( uint64_t* retV const synDeviceType deviceType) { if (deviceAttr == nullptr) return synInvalidArgument; - if (deviceType != synDeviceGaudi) return synInvalidArgument; + if (deviceType != g_state.getCurrentDeviceType()) return synInvalidArgument; if (querySize < sizeof(uint64_t)) return synInvalidArgument; hlthunk_hw_ip_info info; diff --git a/synapse_core/synapse_state.cpp b/synapse_core/synapse_state.cpp index 75742c6..c85b9f0 100644 --- a/synapse_core/synapse_state.cpp +++ b/synapse_core/synapse_state.cpp @@ -6,10 +6,12 @@ */ #include "synapse_state.h" -#include "asic_reg_structs/tpc_tensor_regs.h" +#include "gaudi/gaudi_device.h" +#include "gaudi2/gaudi2_device.h" +#include "synapse_common_types.h" unsigned int -RunKernel(std::vector& descriptors, +RunKernel(std::vector& descriptors, const gcapi::HabanaKernelParams_t& gc_input, const gcapi::HabanaKernelInstantiation_t& gc_output, bool specialFunctionUsed, @@ -32,11 +34,6 @@ void SynapseState::Init() Stream::g_streamId = 0; - m_hal = new GaudiDevice(); - m_runner = new Runtime(m_hal); - - m_kernelDB.init(); - m_initialized = true; m_initMutex.unlock(); } @@ -59,24 +56,30 @@ void SynapseState::Destroy() m_d2hStream.Init(STREAM_TYPE_MAX); m_computeStream.Init(STREAM_TYPE_MAX); - for (const auto& it : m_mappedAddresses) + if (m_runner) { - m_runner->m_device.UnmapMemory(it.second); - } - m_mappedAddresses.clear(); - m_deviceAllocSizes.clear(); - m_freeDram = 0; + for (const auto& it : m_mappedAddresses) + { + m_runner->m_device.UnmapMemory(it.second); + } + m_mappedAddresses.clear(); + m_deviceAllocSizes.clear(); + m_freeDram = 0; - if (m_runner != nullptr) - { - if (m_hasDevice) + if (m_runner != nullptr) { - m_runner->m_device.CloseDevice(); + if (m_hasDevice) + { + m_runner->m_device.CloseDevice(); + } } + delete m_runner; + m_runner = nullptr; } - delete m_runner; - m_runner = nullptr; + delete m_hal; + m_hal = nullptr; + m_kernelDB.clear(); m_hasDevice = false; m_apiMutex.unlock(); @@ -125,20 +128,62 @@ void SynapseState::DestroyStream(synStreamHandle handle) pStream->Init(STREAM_TYPE_MAX); } -bool SynapseState::OpenDevice(const char *pciBusID) +hlthunk_device_name _getHlThunkDevice(synDeviceType deviceType) +{ + switch (deviceType) + { + case synDeviceGaudi: + return HLTHUNK_DEVICE_GAUDI; + case synDeviceGaudi2: + return HLTHUNK_DEVICE_GAUDI2; + default: + return HLTHUNK_DEVICE_INVALID; + } + + // Cannot reach here + return HLTHUNK_DEVICE_INVALID; +} + +bool SynapseState::OpenDevice(const char *pciBusID, const synDeviceType deviceType) { if (!m_initialized) return false; std::lock_guard l(m_apiMutex); if (m_hasDevice) return false; - m_hasDevice = m_runner->m_device.OpenDevice(pciBusID); + switch (deviceType) + { + case synDeviceGaudi: + m_hal = new gaudi::GaudiDevice(); + break; + case synDeviceGaudi2: + m_hal = new gaudi2::Gaudi2Device(); + break; + default: + return false; + } + + if (m_hal == nullptr) + { + assert(0); + return false; + } + + m_runner = new Runtime(m_hal); + + if (m_runner == nullptr) + { + assert(0); + return false; + } + + m_hasDevice = m_runner->m_device.OpenDevice(pciBusID, _getHlThunkDevice(deviceType)); if (m_hasDevice) { m_runner->m_device.GetHwIpInfo(m_cachedDeviceInfo); m_freeDram = m_cachedDeviceInfo.dram_size - s_stolenMemorySize; - m_memoryAlloc.Init(m_cachedDeviceInfo.dram_size, m_cachedDeviceInfo.dram_base_address); - m_sramAlloc.Init(m_cachedDeviceInfo.sram_size, m_cachedDeviceInfo.sram_base_address); + m_memoryAlloc.Init(&m_runner->m_device, m_runner->m_device.IsMmuEnabled(), m_cachedDeviceInfo.dram_size, m_cachedDeviceInfo.dram_base_address); + m_sramAlloc.Init(&m_runner->m_device, false, m_cachedDeviceInfo.sram_size, m_cachedDeviceInfo.sram_base_address); m_runner->SetDramAlloc(&m_memoryAlloc); m_runner->SetSramAlloc(&m_sramAlloc); } @@ -151,10 +196,9 @@ void SynapseState::CloseDevice() std::lock_guard l(m_apiMutex); if (!m_hasDevice) return; - + m_memoryAlloc.Deinit(); m_runner->m_device.CloseDevice(); m_hasDevice = false; - m_memoryAlloc.Deinit(); } void* SynapseState::HostAlloc(uint64_t size) @@ -316,10 +360,14 @@ bool SynapseState::Memcpy(synStreamHandle streamHandle, uint64_t src, uint32_t s return m_runner->m_device.CopyHostDevice(toDevice, it->second, devicePtr, size); } -KernelDB* SynapseState::GetKernelDB() +KernelDB* SynapseState::GetKernelDB(synDeviceType deviceType) { if (!m_initialized) return nullptr; std::lock_guard l(m_apiMutex); + if (!m_kernelDB.initialized()) + { + m_kernelDB.init(deviceType); + } return &m_kernelDB; } @@ -360,10 +408,10 @@ bool SynapseState::Launch(Stream *stream, Recipe *recipe, const synLaunchTensorI tensorBaseAddresses[name] = info.pTensorAddress; } - std::vector tensorDescs; + std::vector tensorDescs; for (unsigned i = 0; i < numTensors + recipe->GetNumAux(); ++i) { - TensorDescriptorGaudi t; + TensorDescriptor t; const Tensor* tensor = recipe->GetTensor(i); std::string name = tensor->GetName(); uint64_t baseAddress = 0; @@ -393,14 +441,8 @@ bool SynapseState::Launch(Stream *stream, Recipe *recipe, const synLaunchTensorI if (ret != synSuccess) return ret; } - struct tpc_tensor::reg_tensor_config config; - config._raw = 0; - config.last_dim = 3; - config.valid_dim_mask = 0xF; - config.data_type = 0x7; //FP32 - t.baseAddrUnion.baseAddr = baseAddress; - t.configuration = config._raw; + t.configuration = m_hal->GetTpcTensorConfig(); t.paddingValue = recipe->GetPaddingValue(i); unsigned stride = 1; for (unsigned dim = 0; dim < 5; ++dim) @@ -425,4 +467,9 @@ bool SynapseState::Launch(Stream *stream, Recipe *recipe, const synLaunchTensorI *m_runner); return (ret == 0); -} \ No newline at end of file +} +synDeviceType SynapseState::getCurrentDeviceType() const { + if (!m_hal) + return synDeviceType::synDeviceTypeInvalid; + return m_hal->getDeviceType(); +} diff --git a/synapse_core/synapse_state.h b/synapse_core/synapse_state.h index 011b973..7488c0e 100644 --- a/synapse_core/synapse_state.h +++ b/synapse_core/synapse_state.h @@ -11,14 +11,15 @@ #include "synapse_api.h" #include "stream.h" #include "node.h" +#include "synapse_api_types.h" +#include "synapse_common_types.h" #include "tensor.h" #include "heap_allocator.h" #include "kernel_db.h" #include "recipe.h" #include "runtime.h" -#include "gaudi_device.h" - +#include "hw_abstraction_layer.h" class SynapseState { @@ -34,7 +35,7 @@ class SynapseState void DestroyStream(synStreamHandle handle); - bool OpenDevice(const char* pciBusID); + bool OpenDevice(const char* pciBusID, const synDeviceType deviceType); void CloseDevice(); void* HostAlloc(uint64_t size); @@ -51,8 +52,8 @@ class SynapseState bool Launch(Stream* stream, Recipe* recipe, const synLaunchTensorInfo* launchTensorsInfo, unsigned numTensors); - KernelDB* GetKernelDB(); - + KernelDB* GetKernelDB(synDeviceType deviceType); + synDeviceType getCurrentDeviceType() const; static const uint64_t s_stolenMemorySize = 512ULL*1024ULL*1024ULL; //0.5GB static const uint64_t s_invalidDeviceAddr = std::numeric_limits::max(); diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index e8f016c..c8213c4 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -7,6 +7,7 @@ set(TARGET2 div_test) set (CMAKE_CXX_STANDARD 11) +set(CMAKE_CXX_FLAGS_DEBUG "-ggdb -O0") set(CMAKE_CXX_FLAGS_RELEASE "-O2 -DNDEBUG -fopenmp") set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fopenmp") @@ -21,8 +22,10 @@ else() message(FATAL_ERROR "Compiler does not support C++11") endif() -add_executable(${TARGET1} memcpy_test.cpp) -add_executable(${TARGET2} div_test.cpp) + +add_executable(${TARGET1} memcpy_test.cpp test_infra.cpp) +add_executable(${TARGET2} div_test.cpp test_infra.cpp) + set (INCLUDE_PATH ../external_includes/) target_link_libraries(${TARGET1} synapse_core) target_link_libraries(${TARGET2} synapse_core) diff --git a/tests/div_test.cpp b/tests/div_test.cpp index 3178f92..7809017 100644 --- a/tests/div_test.cpp +++ b/tests/div_test.cpp @@ -6,57 +6,15 @@ */ #include -#include - -float get_rand_between(float min, float max) -{ - float ret = (float)(std::rand() / (float)RAND_MAX); //[0, 1] - ret = ret * (max - min); //[0, Max+min] - return ret - min; //[min, max]; -} - - -void init_input_and_ref(float* a, float* b, float* ref, unsigned size) -{ - srand(2021); - for (unsigned i = 0; i < size; ++i) - { - a[i] = get_rand_between(-5.f, 5.f); - b[i] = get_rand_between(-5.f, 5.f); - ref[i] = a[i] / b[i]; - } -} - -void validate_output(float* output, float* ref) -{ - bool error = false; - const float eps = 1e-6; - float* pOutput = output; - float* pRef = ref; - for (unsigned b = 0; b < 1; ++b) - { - for (unsigned h = 0; h < 3; ++h) - { - for (unsigned w = 0; w < 3; ++w) - { - for (unsigned c = 0; c < 2; ++c) - { - if (std::abs(*pOutput - *pRef) > eps) - { - std::cout << "Error at [" << c << "," << w << "," << h << "," << b << "]: Output:" << *pOutput - << " Ref: " << *pRef << std::endl; - error = true; - } - ++pOutput; - ++pRef; - } - } - } - } - if (!error) - { - std::cout << "Comparison passed successfully" << std::endl; - } +#include "test_infra.h" + +void init_input_and_ref(float* a, float* b, float* ref, unsigned size) { + srand(2021); + for (unsigned i = 0; i < size; ++i) { + a[i] = HabanaTest::get_rand_between(-5.f, 5.f); + b[i] = HabanaTest::get_rand_between(-5.f, 5.f); + ref[i] = a[i] / b[i]; + } } int main(int argc, char* argv[]) @@ -72,10 +30,14 @@ int main(int argc, char* argv[]) return -1; } + HabanaTest::TestArguments args = HabanaTest::parseArguments(argc, argv); + + const synDeviceType deviceType = args.deviceType; + //// Model definition synGraphHandle graph; - status = synGraphCreate(&graph, synDeviceGaudi); + status = synGraphCreate(&graph, deviceType); if (status != synSuccess) { std::cout << "Failed to create graph" << std::endl; @@ -160,7 +122,7 @@ int main(int argc, char* argv[]) //// Execution synDeviceId devId; - status = synDeviceAcquireByDeviceType(&devId, synDeviceGaudi); + status = synDeviceAcquireByDeviceType(&devId, deviceType); if (status != synSuccess) { std::cout << "No available Gaudi devices!" << std::endl; @@ -350,7 +312,7 @@ int main(int argc, char* argv[]) } //Check results - validate_output(output, ref); + HabanaTest::validate_output(output, ref); synRecipeDestroy(recipe); synGraphDestroy(graph); diff --git a/tests/memcpy_test.cpp b/tests/memcpy_test.cpp index 0dab818..33530c2 100644 --- a/tests/memcpy_test.cpp +++ b/tests/memcpy_test.cpp @@ -7,16 +7,10 @@ #include #include +#include "test_infra.h" #include "synapse_api.h" -void random_init_buffer(float* buf, unsigned nElems) -{ - srand(2021); - for (unsigned i = 0; i < nElems; ++i) - { - buf[i] = (float)std::rand(); - } -} + int main(int argc, char* argv[]) { @@ -31,11 +25,14 @@ int main(int argc, char* argv[]) return -1; } + HabanaTest::TestArguments args = HabanaTest::parseArguments(argc, argv); + const unsigned bufferSizeElements = 1024; const unsigned bufferSizeBytes = bufferSizeElements * sizeof(float); synDeviceId devId; - status = synDeviceAcquireByDeviceType(&devId, synDeviceGaudi); + const synDeviceType deviceType = args.deviceType; + status = synDeviceAcquireByDeviceType(&devId, deviceType); if (status != synSuccess) { std::cout << "No available Gaudi devices!" << std::endl; @@ -57,7 +54,7 @@ int main(int argc, char* argv[]) return -1; } - random_init_buffer(input, bufferSizeElements); + HabanaTest::random_init_buffer(input, bufferSizeElements); //Set output to 0 so valgrind doesn't complain memset(output, 0, bufferSizeBytes); diff --git a/tests/test_infra.cpp b/tests/test_infra.cpp new file mode 100644 index 0000000..a944724 --- /dev/null +++ b/tests/test_infra.cpp @@ -0,0 +1,69 @@ +#include "test_infra.h" +#include "synapse_common_types.h" +#include +#include + +namespace HabanaTest +{ + +TestArguments parseArguments(int argc, char* argv[]) +{ + TestArguments args; + for (unsigned idx = 1; idx < argc; idx++) + { + std::string argStr(argv[idx]); + if(argStr.compare("-device") == 0) + { + idx++; + std::string deviceStr(argv[idx]); + if (deviceStr.compare("gaudi2") == 0) + { + args.deviceType = synDeviceGaudi2; + } + else if (deviceStr.compare("gaudi") == 0) + { + args.deviceType = synDeviceGaudi; + } + } + } + return args; +} + +void random_init_buffer(float *buf, unsigned nElems) { + srand(2021); + for (unsigned i = 0; i < nElems; ++i) { + buf[i] = (float)std::rand(); + } +} +float get_rand_between(float min, float max) { + float ret = (float)(std::rand() / (float)RAND_MAX); //[0, 1] + ret = ret * (max - min); //[0, Max+min] + return ret - min; //[min, max]; +} + +void validate_output(float *output, float *ref) { + bool error = false; + const float eps = 1e-6; + float *pOutput = output; + float *pRef = ref; + for (unsigned b = 0; b < 1; ++b) { + for (unsigned h = 0; h < 3; ++h) { + for (unsigned w = 0; w < 3; ++w) { + for (unsigned c = 0; c < 2; ++c) { + if (std::abs(*pOutput - *pRef) > eps) { + std::cout << "Error at [" << c << "," << w << "," << h << "," << b + << "]: Output:" << *pOutput << " Ref: " << *pRef + << std::endl; + error = true; + } + ++pOutput; + ++pRef; + } + } + } + } + if (!error) { + std::cout << "Comparison passed successfully" << std::endl; + } +} +} // namespace HabanaTest \ No newline at end of file diff --git a/tests/test_infra.h b/tests/test_infra.h new file mode 100644 index 0000000..6a406c7 --- /dev/null +++ b/tests/test_infra.h @@ -0,0 +1,24 @@ +#pragma once +#include "synapse_common_types.h" +#include +#include + +namespace HabanaTest +{ + +struct TestArguments +{ + synDeviceType deviceType = synDeviceGaudi; +}; + +TestArguments parseArguments(int argc, char* argv[]); + +void random_init_buffer(float *buf, unsigned nElems); + +float get_rand_between(float min, float max); + +void init_input_and_ref(float *a, float *b, float *ref, unsigned size); + +void validate_output(float *output, float *ref); + +} // namespace HabanaTest \ No newline at end of file diff --git a/tpc_kernels_db/CMakeLists.txt b/tpc_kernels_db/CMakeLists.txt index b76313d..c6d0eb8 100644 --- a/tpc_kernels_db/CMakeLists.txt +++ b/tpc_kernels_db/CMakeLists.txt @@ -25,9 +25,10 @@ endif() # Add TPC-C source files to be compiled by TPC Gaudi compiler and # linked into tpc_kernels executable. file(GLOB TPC_C_GAUDI_SOURCES_TO_EMBED ./kernels/gaudi/*.c) +file(GLOB TPC_C_GAUDI2_SOURCES_TO_EMBED ./kernels/gaudi2/*.c) # Generate a list of all TPC headers for compilation dependencies. -file(GLOB TPC_GAUDI_HEADERS ./kernels/gaudi/*.h) +file(GLOB TPC_GAUDI_HEADERS ./kernels/include/*.h) include_directories(../external_includes) diff --git a/tpc_kernels_db/kernels/gaudi/batch_norm_fwd_f32.c b/tpc_kernels_db/kernels/gaudi/batch_norm_fwd_f32.c index 7a28ecd..68b1dae 100644 --- a/tpc_kernels_db/kernels/gaudi/batch_norm_fwd_f32.c +++ b/tpc_kernels_db/kernels/gaudi/batch_norm_fwd_f32.c @@ -56,7 +56,7 @@ void main( int5 ofmCoords = { 0, 0, 0, 0, 0 }; int5 depthCoords = { depthStart, 0, 0, 0, 0 }; - float64 vN = v_f32_mov_s(N_reciprocal); + float64 vN = N_reciprocal; for (int d = depthStart; d < depthEnd; d += depthStep) { @@ -121,10 +121,10 @@ void main( tmp2 = x2 - mean_v; tmp3 = x3 - mean_v; - var_v_0 = v_f32_mac_b(tmp0, tmp0, var_v_0, (e_no_negation) << 1); - var_v_1 = v_f32_mac_b(tmp1, tmp1, var_v_1, (e_no_negation) << 1, w < widthEnd-1); - var_v_2 = v_f32_mac_b(tmp2, tmp2, var_v_2, (e_no_negation) << 1, w < widthEnd-2); - var_v_3 = v_f32_mac_b(tmp3, tmp3, var_v_3, (e_no_negation) << 1, w < widthEnd-3); + var_v_0 = v_f32_mac_b(tmp0, tmp0, var_v_0, e_no_negation << 1); + var_v_1 = v_f32_mac_b(tmp1, tmp1, var_v_1, e_no_negation << 1, w < widthEnd-1); + var_v_2 = v_f32_mac_b(tmp2, tmp2, var_v_2, e_no_negation << 1, w < widthEnd-2); + var_v_3 = v_f32_mac_b(tmp3, tmp3, var_v_3, e_no_negation << 1, w < widthEnd-3); } } } @@ -151,7 +151,7 @@ void main( float64 var_tmp = var_v + 1e-5; float64 istd = v_rsqrt_f32(var_tmp); float64 scale = gamma * istd; - float64 bias = v_f32_mac_b(scale, mean_v, beta, (e_with_negation) << 1); + float64 bias = v_f32_mac_b(scale, mean_v, beta, e_with_negation << 1); v_f32_st_tnsr(depthCoords, istd_tr, istd); v_f32_st_tnsr(depthCoords, mean_tr, mean_v); @@ -177,10 +177,10 @@ void main( x3 = v_f32_ld_tnsr_b(ifmCoords, ifm_tr); ifmCoords[width] += 1; // y = x * scale + bias - y0 = v_f32_mac_b(x0, scale, bias, (e_no_negation) << 1); - y1 = v_f32_mac_b(x1, scale, bias, (e_no_negation) << 1); - y2 = v_f32_mac_b(x2, scale, bias, (e_no_negation) << 1); - y3 = v_f32_mac_b(x3, scale, bias, (e_no_negation) << 1); + y0 = v_f32_mac_b(x0, scale, bias, e_no_negation << 1); + y1 = v_f32_mac_b(x1, scale, bias, e_no_negation << 1); + y2 = v_f32_mac_b(x2, scale, bias, e_no_negation << 1); + y3 = v_f32_mac_b(x3, scale, bias, e_no_negation << 1); v_f32_st_tnsr(ofmCoords, ofm_tr, y0); ofmCoords[width] += 1; v_f32_st_tnsr(ofmCoords, ofm_tr, y1); ofmCoords[width] += 1; diff --git a/tpc_kernels_db/kernels/gaudi/cast_bf16_to_f32.c b/tpc_kernels_db/kernels/gaudi/cast_bf16_to_f32.c index 48b21b4..29844c1 100644 --- a/tpc_kernels_db/kernels/gaudi/cast_bf16_to_f32.c +++ b/tpc_kernels_db/kernels/gaudi/cast_bf16_to_f32.c @@ -72,10 +72,10 @@ void main(tensor ifm, // Note: bfloat128 vector contains 4 dual groups and each dual group has 32 elements // Unpacks lower half of first group of all 4 dual gorups // 0..15, 32..47, 64..79, 96..111 - y.v1 = v_bf16_unpack_b(in, ((e_group_0) << 8) | ((e_every_second_element) << 9) | ((e_lower_half_group) << 10), y.v1); + y.v1 = v_bf16_unpack_b(in, e_group_0 << 8 | e_every_second_element << 9 | e_lower_half_group << 10, y.v1); // Unpacks lower half of second group of all 4 dual gorups // 16..31, 48..63, 80..95, 112..127 - y.v2 = v_bf16_unpack_b(in, ((e_group_1) << 8) | ((e_every_second_element) << 9) | ((e_lower_half_group) << 10), y.v2); + y.v2 = v_bf16_unpack_b(in, e_group_1 << 8 | e_every_second_element << 9 | e_lower_half_group << 10, y.v2); tmp = y.v1; // Rearranges the vector in correct order diff --git a/tpc_kernels_db/kernels/gaudi/customdiv_fwd_f32.c b/tpc_kernels_db/kernels/gaudi/customdiv_fwd_f32.c index 934cd2f..62056f9 100644 --- a/tpc_kernels_db/kernels/gaudi/customdiv_fwd_f32.c +++ b/tpc_kernels_db/kernels/gaudi/customdiv_fwd_f32.c @@ -4,114 +4,4 @@ * All Rights Reserved. * */ -float64 reciprocal_cephes_fast_f32(float64 input) -{ - float64 result, temp0, temp1, temp2; - const float a = 2.58586f; - const float b = -5.81818f; - const float c = 4.24242f; - - int64 significand = 0; - significand = v_i32_and_b(*((int64*)&input), 0x007fffff); - significand = v_i32_or_b(significand, 0x3f000000); - result = *((float64*)&significand); - - int64 exponent = 0; - exponent = v_i32_shr_b(*((int64*)&input), 23); - exponent = v_i32_and_b(exponent, 0x000000ff); - exponent -= 0x7e; - - temp0 = v_f32_mac_b(result, a, b); - temp1 = v_f32_mac_b(result, temp0, c); - temp2 = v_f32_mac_b(-result, temp1, 2); - temp2 *= temp1; - temp0 = v_f32_mac_b(-result, temp2, 2); - temp0 *= temp2; - - int64 exp = v_i32_shr_b(*((int64*)&temp0), 23); - exp = v_i32_and_b(exp, 0x000000ff); - exp = v_i32_add_b(exp, -exponent); - exp = v_i32_and_b(exp, 0xff); - result = v_f32_form_fp_num_ie_b((char256)exp, input, temp0, SW_EXP_IS_NUM); - - return result; -} - - -float64 reciprocal_cephes_f32(float64 input) -{ - float64 result = reciprocal_cephes_fast_f32(input); - - -// ==================================== -// Processing special values: denorm, +-0. +-inf, nan - float64 abs_x = v_f32_abs_b(input); - - const uint64 flt_max = 0x7f7fffff; - const float64 flt_max_fp32 = *((float64*)&flt_max); - - float64 fclass = v_f32_fclass_b(input); - result = v_f32_calc_fp_special_b(fclass, fclass, e_fp_recip, result); - result = v_f32_sel_geq_f32_b(abs_x, flt_max_fp32, 0.0f, result); -// ==================================== - - return result; -} - -void main(tensor input0, tensor input1, tensor output) -{ - const int depth = 0; - const int width = 1; - const int height = 2; - const int batch = 3; - - const int5 index_space_start = get_index_space_offset(); - const int5 index_space_end = get_index_space_size() + index_space_start; - - int5 coords = { 0, 0, 0, 0, 0 }; - - // DEPTH - const int depthStep = 64; - const int depthStart = index_space_start[depth] * depthStep; - const int depthEnd = index_space_end[depth] * depthStep; - - // WIDTH - const int widthStep = 1; - const int widthStart = index_space_start[width] * widthStep; - const int widthEnd = index_space_end[width] * widthStep; - - // HEIGHT - const int heightStep = 1; - const int heightStart = index_space_start[height]; - const int heightEnd = index_space_end[height]; - - // BATCH - const int batchStep = 1; - const int batchStart = index_space_start[batch]; - const int batchtEnd = index_space_end[batch]; - - for (int b = batchStart; b < batchtEnd; b += batchStep) - { - coords[batch] = b; - - for (int h = heightStart; h < heightEnd; h += heightStep) - { - coords[height] = h; - for (int d = depthStart; d < depthEnd; d += depthStep) - { - coords[depth] = d; - for (int w = widthStart; w < widthEnd; w += widthStep) - { - coords[width] = w; - - float64 x = v_f32_ld_tnsr_b(coords, input0); - float64 y = v_f32_ld_tnsr_b(coords, input1); - - float64 div_x_y = x * reciprocal_cephes_fast_f32(y); - - v_f32_st_tnsr(coords, output, div_x_y); - } - } - } - } -} +#include "customdiv_fwd_f32.h" \ No newline at end of file diff --git a/tpc_kernels_db/kernels/gaudi/filter_fwd_2d_bf16.c b/tpc_kernels_db/kernels/gaudi/filter_fwd_2d_bf16.c index 051a67c..5c13bff 100644 --- a/tpc_kernels_db/kernels/gaudi/filter_fwd_2d_bf16.c +++ b/tpc_kernels_db/kernels/gaudi/filter_fwd_2d_bf16.c @@ -48,10 +48,10 @@ void main(tensor ifm, 0}; bfloat128 filterVector = v_bf16_ld_tnsr_b(filterCoords, filter); bfloat128 ifmVector = v_bf16_ld_tnsr_b(ifmCoords, ifm); - accum = v_bf16_mac_acc32_b(filterVector, ifmVector, accum, (e_no_negation) << 1); + accum = v_bf16_mac_acc32_b(filterVector, ifmVector, accum, e_no_negation << 1); } } - bfloat128 out = v_convert_f32_to_bf16_all_b (accum); + bfloat128 out = v_convert_f32_to_bf16_all_b(accum); v_bf16_st_tnsr(output_coords, ofm, out); } } diff --git a/tpc_kernels_db/kernels/gaudi/leakyrelu_f32_gaudi.c b/tpc_kernels_db/kernels/gaudi/leakyrelu_f32_gaudi.c index 5c0640b..74579ca 100644 --- a/tpc_kernels_db/kernels/gaudi/leakyrelu_f32_gaudi.c +++ b/tpc_kernels_db/kernels/gaudi/leakyrelu_f32_gaudi.c @@ -53,7 +53,7 @@ void main(tensor input, tensor output, float alpha) float64 x = v_f32_ld_tnsr_b(coords, input); - bool256 cond = from_bool64(v_f32_cmp_grt_b(x, 0.0, 0, to_bool64((bool256){0}))); + bool256 cond = from_bool64(v_f32_cmp_grt_b(x, 0.0)); float64 y = v_f32_mul_vb(x, alpha, 0, x, to_bool64(cond), 1); diff --git a/tpc_kernels_db/kernels/gaudi/relu6_bwd_bf16.c b/tpc_kernels_db/kernels/gaudi/relu6_bwd_bf16.c index 8326c36..6b0e831 100644 --- a/tpc_kernels_db/kernels/gaudi/relu6_bwd_bf16.c +++ b/tpc_kernels_db/kernels/gaudi/relu6_bwd_bf16.c @@ -6,3 +6,4 @@ */ #define BFLOAT16 #include "relu6_bwd.h" +#undef BFLOAT16 \ No newline at end of file diff --git a/tpc_kernels_db/kernels/gaudi/relu6_bwd_f32.c b/tpc_kernels_db/kernels/gaudi/relu6_bwd_f32.c index 4edf932..53e302c 100644 --- a/tpc_kernels_db/kernels/gaudi/relu6_bwd_f32.c +++ b/tpc_kernels_db/kernels/gaudi/relu6_bwd_f32.c @@ -6,3 +6,4 @@ */ #define FLOAT32 #include "relu6_bwd.h" +#undef FLOAT32 \ No newline at end of file diff --git a/tpc_kernels_db/kernels/gaudi/relu6_fwd_bf16.c b/tpc_kernels_db/kernels/gaudi/relu6_fwd_bf16.c index 8a038e6..7d9b9fb 100644 --- a/tpc_kernels_db/kernels/gaudi/relu6_fwd_bf16.c +++ b/tpc_kernels_db/kernels/gaudi/relu6_fwd_bf16.c @@ -6,3 +6,4 @@ */ #define BFLOAT16 #include "relu6_fwd.h" +#undef BFLOAT16 diff --git a/tpc_kernels_db/kernels/gaudi/relu6_fwd_f32.c b/tpc_kernels_db/kernels/gaudi/relu6_fwd_f32.c index 79e81e4..545ad49 100644 --- a/tpc_kernels_db/kernels/gaudi/relu6_fwd_f32.c +++ b/tpc_kernels_db/kernels/gaudi/relu6_fwd_f32.c @@ -6,3 +6,4 @@ */ #define FLOAT32 #include "relu6_fwd.h" +#undef FLOAT32 \ No newline at end of file diff --git a/tpc_kernels_db/kernels/gaudi/softmax_fcd_bf16.c b/tpc_kernels_db/kernels/gaudi/softmax_fcd_bf16.c index ca78253..92e8747 100644 --- a/tpc_kernels_db/kernels/gaudi/softmax_fcd_bf16.c +++ b/tpc_kernels_db/kernels/gaudi/softmax_fcd_bf16.c @@ -40,7 +40,7 @@ void main( int5 ifmCoords = { depthStart, widthStart, heightStart, batchStart, 0 }; - bfloat128 zero_bf16 = v_bf16_mov_s(0.f); + bfloat128 zero_bf16 = 0.f; bfloat128 x; bfloat128 y; @@ -74,8 +74,8 @@ void main( y = v_convert_f32_to_bf16_all_b(yf32); // Move zero for out of bound co-ordinates - bool256 pred = from_bool128(v_u16_cmp_geq_b(d + V_LANE_ID_16, (unsigned)depthEnd, 0, to_bool128((bool256){0}))); - y = v_bf16_mov_vb(zero_bf16, 0, y, to_bool128(pred), 0); + bool256 pred = from_bool128(v_u16_cmp_geq_b(d + V_LANE_ID_16, (unsigned)depthEnd)); + y = v_bf16_mov_vb(zero_bf16, 0, y, to_bool128(pred)); // Sum up the values in a vector sum = sum + y; diff --git a/tpc_kernels_db/kernels/gaudi/softmax_non_fcd_bf16.c b/tpc_kernels_db/kernels/gaudi/softmax_non_fcd_bf16.c index cf35cc1..1c9b176 100644 --- a/tpc_kernels_db/kernels/gaudi/softmax_non_fcd_bf16.c +++ b/tpc_kernels_db/kernels/gaudi/softmax_non_fcd_bf16.c @@ -40,7 +40,7 @@ void main( int5 ifmCoords = { depthStart, widthStart, heightStart, batchStart, 0 }; - bfloat128 zero_bf16 = v_bf16_mov_s(0.f); + bfloat128 zero_bf16 = 0.f; bfloat128 x; bfloat128 y; @@ -74,8 +74,8 @@ void main( y = v_convert_f32_to_bf16_all_b(yf32); // Move zero for out of bound co-ordinates - bool256 pred = from_bool128(v_u16_cmp_geq_b(d + V_LANE_ID_16, (unsigned)depthEnd, 0, to_bool128((bool256){0}))); - y = v_bf16_mov_vb(zero_bf16, 0, y, to_bool128(pred), 0); + bool256 pred = from_bool128(v_u16_cmp_geq_b(d + V_LANE_ID_16, (unsigned)depthEnd)); + y = v_bf16_mov_vb(zero_bf16, 0, y, to_bool128(pred)); // Sum up the values in a vector sum = sum + y; diff --git a/tpc_kernels_db/kernels/gaudi/sparse_lengths_sum_bf16_2D_f32_embed.c b/tpc_kernels_db/kernels/gaudi/sparse_lengths_sum_bf16_2D_f32_embed.c index c92bf02..e5e3d5d 100644 --- a/tpc_kernels_db/kernels/gaudi/sparse_lengths_sum_bf16_2D_f32_embed.c +++ b/tpc_kernels_db/kernels/gaudi/sparse_lengths_sum_bf16_2D_f32_embed.c @@ -12,9 +12,9 @@ bfloat128_pair_t cast_bf16_to_32bits_lin_order(bfloat128 x) bfloat128 tmp; // 0..15, 32..47, 64..79, 96..111 - y.v1 = v_bf16_unpack_b(x, ((e_group_0) << 8) | ((e_every_second_element) << 9) | ((e_lower_half_group) << 10), y.v1); + y.v1 = v_bf16_unpack_b(x, e_group_0 << 8 | e_every_second_element << 9 | e_lower_half_group << 10, y.v1); // 16..31, 48..63, 80..95, 112..127 - y.v2 = v_bf16_unpack_b(x, ((e_group_1) << 8) | ((e_every_second_element) << 9) | ((e_lower_half_group) << 10), y.v2); + y.v2 = v_bf16_unpack_b(x, e_group_1 << 8 | e_every_second_element << 9 | e_lower_half_group << 10, y.v2); tmp = y.v1; // Rearranges the vector in correct order @@ -191,14 +191,14 @@ void main(tensor input_tensor, in_value_1_float_0 = v_convert_bf16_to_f32_all_b(in_value_1_bf16_av.v1); in_value_1_float_1 = v_convert_bf16_to_f32_all_b(in_value_1_bf16_av.v2); //application of scale and bias - in_value_1_float_0.v1 = v_f32_mac_b(in_value_1_float_0.v1, scale_1_v, neg_scale_x_bias_1_v, (e_no_negation) << 1); - in_value_1_float_1.v1 = v_f32_mac_b(in_value_1_float_1.v1, scale_1_v, neg_scale_x_bias_1_v, (e_no_negation) << 1); + in_value_1_float_0.v1 = v_f32_mac_b(in_value_1_float_0.v1, scale_1_v, neg_scale_x_bias_1_v, e_no_negation << 1); + in_value_1_float_1.v1 = v_f32_mac_b(in_value_1_float_1.v1, scale_1_v, neg_scale_x_bias_1_v, e_no_negation << 1); //conversion to f32 in_value_2_float_0 = v_convert_bf16_to_f32_all_b(in_value_2_bf16_av.v1); in_value_2_float_1 = v_convert_bf16_to_f32_all_b(in_value_2_bf16_av.v2); //application of scale and bias - in_value_2_float_0.v1 = v_f32_mac_b(in_value_2_float_0.v1, scale_2_v, neg_scale_x_bias_2_v, (e_no_negation) << 1); - in_value_2_float_1.v1 = v_f32_mac_b(in_value_2_float_1.v1, scale_2_v, neg_scale_x_bias_2_v, (e_no_negation) << 1); + in_value_2_float_0.v1 = v_f32_mac_b(in_value_2_float_0.v1, scale_2_v, neg_scale_x_bias_2_v, e_no_negation << 1); + in_value_2_float_1.v1 = v_f32_mac_b(in_value_2_float_1.v1, scale_2_v, neg_scale_x_bias_2_v, e_no_negation << 1); //next index coordinate idx_coord_1[0]++; @@ -217,10 +217,10 @@ void main(tensor input_tensor, in_value_1_bf16_av = cast_bf16_to_32bits_lin_order(in_value_1); in_value_2_bf16_av = cast_bf16_to_32bits_lin_order(in_value_2); //accumulating - out_value_1.v1 = v_f32_add_b(out_value_1.v1, in_value_1_float_0.v1, 0, out_value_1.v1, pred_1, 0); - out_value_1.v2 = v_f32_add_b(out_value_1.v2, in_value_1_float_1.v1, 0, out_value_1.v2, pred_1, 0); - out_value_2.v1 = v_f32_add_b(out_value_2.v1, in_value_2_float_0.v1, 0, out_value_2.v1, pred_2, 0); - out_value_2.v2 = v_f32_add_b(out_value_2.v2, in_value_2_float_1.v1, 0, out_value_2.v2, pred_2, 0); + out_value_1.v1 = v_f32_add_b(out_value_1.v1, in_value_1_float_0.v1, 0, out_value_1.v1, pred_1); + out_value_1.v2 = v_f32_add_b(out_value_1.v2, in_value_1_float_1.v1, 0, out_value_1.v2, pred_1); + out_value_2.v1 = v_f32_add_b(out_value_2.v1, in_value_2_float_0.v1, 0, out_value_2.v1, pred_2); + out_value_2.v2 = v_f32_add_b(out_value_2.v2, in_value_2_float_1.v1, 0, out_value_2.v2, pred_2); //scale is loaded from input tensor in the embedded version //loading the vector containing the scale and the zp @@ -270,18 +270,18 @@ void main(tensor input_tensor, in_value_1_float_0 = v_convert_bf16_to_f32_all_b(in_value_1_bf16_av.v1); in_value_1_float_1 = v_convert_bf16_to_f32_all_b(in_value_1_bf16_av.v2); - in_value_1_float_0.v1 = v_f32_mac_b(in_value_1_float_0.v1, scale_1_v, neg_scale_x_bias_1_v, (e_no_negation) << 1); - in_value_1_float_1.v1 = v_f32_mac_b(in_value_1_float_1.v1, scale_1_v, neg_scale_x_bias_1_v, (e_no_negation) << 1); + in_value_1_float_0.v1 = v_f32_mac_b(in_value_1_float_0.v1, scale_1_v, neg_scale_x_bias_1_v, e_no_negation << 1); + in_value_1_float_1.v1 = v_f32_mac_b(in_value_1_float_1.v1, scale_1_v, neg_scale_x_bias_1_v, e_no_negation << 1); in_value_2_float_0 = v_convert_bf16_to_f32_all_b(in_value_2_bf16_av.v1); in_value_2_float_1 = v_convert_bf16_to_f32_all_b(in_value_2_bf16_av.v2); - in_value_2_float_0.v1 = v_f32_mac_b(in_value_2_float_0.v1, scale_2_v, neg_scale_x_bias_2_v, (e_no_negation) << 1); - in_value_2_float_1.v1 = v_f32_mac_b(in_value_2_float_1.v1, scale_2_v, neg_scale_x_bias_2_v, (e_no_negation) << 1); + in_value_2_float_0.v1 = v_f32_mac_b(in_value_2_float_0.v1, scale_2_v, neg_scale_x_bias_2_v, e_no_negation << 1); + in_value_2_float_1.v1 = v_f32_mac_b(in_value_2_float_1.v1, scale_2_v, neg_scale_x_bias_2_v, e_no_negation << 1); - out_value_1.v1 = v_f32_add_b(out_value_1.v1, in_value_1_float_0.v1, 0, out_value_1.v1, pred_1, 0); - out_value_1.v2 = v_f32_add_b(out_value_1.v2, in_value_1_float_1.v1, 0, out_value_1.v2, pred_1, 0); - out_value_2.v1 = v_f32_add_b(out_value_2.v1, in_value_2_float_0.v1, 0, out_value_2.v1, pred_2, 0); - out_value_2.v2 = v_f32_add_b(out_value_2.v2, in_value_2_float_1.v1, 0, out_value_2.v2, pred_2, 0); + out_value_1.v1 = v_f32_add_b(out_value_1.v1, in_value_1_float_0.v1, 0, out_value_1.v1, pred_1); + out_value_1.v2 = v_f32_add_b(out_value_1.v2, in_value_1_float_1.v1, 0, out_value_1.v2, pred_1); + out_value_2.v1 = v_f32_add_b(out_value_2.v1, in_value_2_float_0.v1, 0, out_value_2.v1, pred_2); + out_value_2.v2 = v_f32_add_b(out_value_2.v2, in_value_2_float_1.v1, 0, out_value_2.v2, pred_2); //epilogue ends here //for next iteration, offset is calculated from the last segment of the current iteration diff --git a/tpc_kernels_db/kernels/gaudi2/customdiv_fwd_f32.c b/tpc_kernels_db/kernels/gaudi2/customdiv_fwd_f32.c new file mode 100644 index 0000000..62056f9 --- /dev/null +++ b/tpc_kernels_db/kernels/gaudi2/customdiv_fwd_f32.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: MIT + * + * Copyright 2016-2021 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ +#include "customdiv_fwd_f32.h" \ No newline at end of file diff --git a/tpc_kernels_db/kernels/gaudi2/relu_fwd_bf16.c b/tpc_kernels_db/kernels/gaudi2/relu_fwd_bf16.c new file mode 100644 index 0000000..7d9b9fb --- /dev/null +++ b/tpc_kernels_db/kernels/gaudi2/relu_fwd_bf16.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT + * + * Copyright 2016-2021 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ +#define BFLOAT16 +#include "relu6_fwd.h" +#undef BFLOAT16 diff --git a/tpc_kernels_db/kernels/include/customdiv_fwd_f32.h b/tpc_kernels_db/kernels/include/customdiv_fwd_f32.h new file mode 100644 index 0000000..934cd2f --- /dev/null +++ b/tpc_kernels_db/kernels/include/customdiv_fwd_f32.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: MIT + * + * Copyright 2016-2021 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ +float64 reciprocal_cephes_fast_f32(float64 input) +{ + float64 result, temp0, temp1, temp2; + const float a = 2.58586f; + const float b = -5.81818f; + const float c = 4.24242f; + + int64 significand = 0; + significand = v_i32_and_b(*((int64*)&input), 0x007fffff); + significand = v_i32_or_b(significand, 0x3f000000); + result = *((float64*)&significand); + + int64 exponent = 0; + exponent = v_i32_shr_b(*((int64*)&input), 23); + exponent = v_i32_and_b(exponent, 0x000000ff); + exponent -= 0x7e; + + temp0 = v_f32_mac_b(result, a, b); + temp1 = v_f32_mac_b(result, temp0, c); + temp2 = v_f32_mac_b(-result, temp1, 2); + temp2 *= temp1; + temp0 = v_f32_mac_b(-result, temp2, 2); + temp0 *= temp2; + + int64 exp = v_i32_shr_b(*((int64*)&temp0), 23); + exp = v_i32_and_b(exp, 0x000000ff); + exp = v_i32_add_b(exp, -exponent); + exp = v_i32_and_b(exp, 0xff); + result = v_f32_form_fp_num_ie_b((char256)exp, input, temp0, SW_EXP_IS_NUM); + + return result; +} + + +float64 reciprocal_cephes_f32(float64 input) +{ + float64 result = reciprocal_cephes_fast_f32(input); + + +// ==================================== +// Processing special values: denorm, +-0. +-inf, nan + float64 abs_x = v_f32_abs_b(input); + + const uint64 flt_max = 0x7f7fffff; + const float64 flt_max_fp32 = *((float64*)&flt_max); + + float64 fclass = v_f32_fclass_b(input); + result = v_f32_calc_fp_special_b(fclass, fclass, e_fp_recip, result); + result = v_f32_sel_geq_f32_b(abs_x, flt_max_fp32, 0.0f, result); +// ==================================== + + return result; +} + +void main(tensor input0, tensor input1, tensor output) +{ + const int depth = 0; + const int width = 1; + const int height = 2; + const int batch = 3; + + const int5 index_space_start = get_index_space_offset(); + const int5 index_space_end = get_index_space_size() + index_space_start; + + int5 coords = { 0, 0, 0, 0, 0 }; + + // DEPTH + const int depthStep = 64; + const int depthStart = index_space_start[depth] * depthStep; + const int depthEnd = index_space_end[depth] * depthStep; + + // WIDTH + const int widthStep = 1; + const int widthStart = index_space_start[width] * widthStep; + const int widthEnd = index_space_end[width] * widthStep; + + // HEIGHT + const int heightStep = 1; + const int heightStart = index_space_start[height]; + const int heightEnd = index_space_end[height]; + + // BATCH + const int batchStep = 1; + const int batchStart = index_space_start[batch]; + const int batchtEnd = index_space_end[batch]; + + for (int b = batchStart; b < batchtEnd; b += batchStep) + { + coords[batch] = b; + + for (int h = heightStart; h < heightEnd; h += heightStep) + { + coords[height] = h; + for (int d = depthStart; d < depthEnd; d += depthStep) + { + coords[depth] = d; + for (int w = widthStart; w < widthEnd; w += widthStep) + { + coords[width] = w; + + float64 x = v_f32_ld_tnsr_b(coords, input0); + float64 y = v_f32_ld_tnsr_b(coords, input1); + + float64 div_x_y = x * reciprocal_cephes_fast_f32(y); + + v_f32_st_tnsr(coords, output, div_x_y); + } + } + } + } +} diff --git a/tpc_kernels_db/kernels/include/kernel_config.h b/tpc_kernels_db/kernels/include/kernel_config.h index 1e71d85..4a5fe12 100644 --- a/tpc_kernels_db/kernels/include/kernel_config.h +++ b/tpc_kernels_db/kernels/include/kernel_config.h @@ -6,19 +6,19 @@ */ #if defined(FLOAT32) #define VECTOR float64 -#define v_ld_tnsr_i(a,b) v_f32_ld_tnsr_i(a,b) -#define v_sel_less_v_s_v_v(a,b,c,d) v_f32_sel_less_f32_b(a,b,c,d) -#define v_sel_geq_v_s_v_v(a,b,c,d) v_f32_sel_geq_f32_b(a,b,c,d) -#define v_sel_grt_v_s_v_v(a,b,c,d) v_f32_sel_grt_f32_b(a,b,c,d) -#define st_tnsr_i_v(a,b,c) f32_st_tnsr_i_v(a,b,c) +#define v_ld_tnsr_i(a,b) v_f32_ld_tnsr_b(a, b) +#define v_sel_less_v_s_v_v(a,b,c,d) v_f32_sel_less_f32_b(a, b, c, d) +#define v_sel_geq_v_s_v_v(a,b,c,d) v_f32_sel_geq_f32_b(a, b, c, d) +#define v_sel_grt_v_s_v_v(a,b,c,d) v_f32_sel_grt_f32_b(a, b, c, d) +#define st_tnsr_i_v(a,b,c) v_f32_st_tnsr(a, b, c) #endif #if defined(BFLOAT16) #define VECTOR bfloat128 -#define v_ld_tnsr_i(a,b) v_bf16_ld_tnsr_i(a,b) -#define v_sel_less_v_s_v_v(a,b,c,d) v_bf16_sel_less_bf16_b(a,b,c,d) -#define v_sel_geq_v_s_v_v(a,b,c,d) v_bf16_sel_geq_bf16_b(a,b,c,d) -#define v_sel_grt_v_s_v_v(a,b,c,d) v_bf16_sel_grt_bf16_b(a,b,c,d) -#define st_tnsr_i_v(a,b,c) bf16_st_tnsr_i_v(a,b,c) +#define v_ld_tnsr_i(a,b) v_bf16_ld_tnsr_b(a, b) +#define v_sel_less_v_s_v_v(a,b,c,d) v_bf16_sel_less_bf16_b(a, b, c, d) +#define v_sel_geq_v_s_v_v(a,b,c,d) v_bf16_sel_geq_bf16_b(a, b, c, d) +#define v_sel_grt_v_s_v_v(a,b,c,d) v_bf16_sel_grt_bf16_b(a, b, c, d) +#define st_tnsr_i_v(a,b,c) v_bf16_st_tnsr(a, b, c) #endif diff --git a/tpc_kernels_db/src/CMakeLists.txt b/tpc_kernels_db/src/CMakeLists.txt index ea5c357..4a4d758 100644 --- a/tpc_kernels_db/src/CMakeLists.txt +++ b/tpc_kernels_db/src/CMakeLists.txt @@ -35,7 +35,10 @@ separate_arguments(OPT_FLAG) # 4. Links the X86 elf into the executable # 5. Disassemble the file for debug purposes function(CompileTPCCWithClang TPC_C_SOURCES_TO_EMBED TPC_HEADERS deviceName) + set(OBJ_LIST ) foreach(SOURCE_FILE ${TPC_C_SOURCES_TO_EMBED}) + file(RELATIVE_PATH RELATIVE_FILE_PATH ${CMAKE_SOURCE_DIR} ${SOURCE_FILE}) + get_filename_component(RELATIVE_DIRECTORY ${RELATIVE_FILE_PATH} DIRECTORY) get_filename_component(SOURCE_NAME_NO_PATH_NO_SUFFIX ${SOURCE_FILE} NAME_WE) get_filename_component(SOURCE_FILE_NAME_NO_PATH ${SOURCE_FILE} NAME) if ("${CMAKE_BUILD_TYPE}" STREQUAL "Debug" AND "${SOURCE_FILE_NAME_NO_PATH}" STREQUAL "filter_2d_i8_w33_s11.c") @@ -43,16 +46,29 @@ function(CompileTPCCWithClang TPC_C_SOURCES_TO_EMBED TPC_HEADERS deviceName) elseif("${CMAKE_BUILD_TYPE}" STREQUAL "Debug") set (OPT_FLAG "-O0") endif() - add_custom_command(OUTPUT "${SOURCE_NAME_NO_PATH_NO_SUFFIX}_x86.o" + + # get prefix from relative path (for example: get "_gaudi2_spatial_pooling" from "kernels/gaudi2/spatial/pooling") + string(REGEX MATCHALL "/.*" WITHOUT_PARENT_DIR ${RELATIVE_DIRECTORY}) + string(REPLACE "/" "_" PATH_PREFIX ${WITHOUT_PARENT_DIR}) + + file(MAKE_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/${RELATIVE_DIRECTORY}) + + add_custom_command(OUTPUT "${RELATIVE_DIRECTORY}/${SOURCE_NAME_NO_PATH_NO_SUFFIX}_x86.o" DEPENDS ${SOURCE_FILE} ${TPC_COMPILER_PATH} ${TPC_HEADERS} - COMMAND cp ${SOURCE_FILE} ${CMAKE_CURRENT_BINARY_DIR} - COMMAND ${TPC_COMPILER_PATH} -Wall -Werror -march=${deviceName} ${OPT_FLAG} ${DEBUG_FLAG} -I${TPC_INCLUDE_DIR}/ -I${TPC_CURRENT_LIST_DIR} ./${SOURCE_FILE_NAME_NO_PATH} -c - COMMAND objcopy -I binary -O elf64-x86-64 -B i386:x86-64 ./${SOURCE_NAME_NO_PATH_NO_SUFFIX}.o "${SOURCE_NAME_NO_PATH_NO_SUFFIX}_x86.o" - COMMAND ${TPC_DISASSEMBLER_PATH} --triple tpc -d -j .text -no-show-raw-insn -no-leading-addr -mcpu=${deviceName} ./${RELATIVE_DIRECTORY}/${SOURCE_NAME_NO_PATH_NO_SUFFIX}.o > ${CMAKE_CURRENT_BINARY_DIR}/${RELATIVE_DIRECTORY}/${SOURCE_NAME_NO_PATH_NO_SUFFIX}.tpcasm) - add_library(${SOURCE_NAME_NO_PATH_NO_SUFFIX} STATIC "${SOURCE_NAME_NO_PATH_NO_SUFFIX}_x86.o") - set_target_properties( ${SOURCE_NAME_NO_PATH_NO_SUFFIX} PROPERTIES LINKER_LANGUAGE C) - target_link_libraries(${TPC_PERF_TARGET} ${SOURCE_NAME_NO_PATH_NO_SUFFIX}) + IMPLICIT_DEPENDS C ${SOURCE_FILE} + WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/${RELATIVE_DIRECTORY} + COMMAND cp ${SOURCE_FILE} ${CMAKE_CURRENT_BINARY_DIR}/${RELATIVE_FILE_PATH} + COMMAND ${TPC_COMPILER_PATH} -Wall -Werror -march=${deviceName} ${OPT_FLAG} ${DEBUG_FLAG} -I${TPC_INCLUDE_DIR}/ -I${TPC_CURRENT_LIST_DIR} ./${SOURCE_FILE_NAME_NO_PATH} -c + COMMAND objcopy -I binary -O elf64-x86-64 -B i386:x86-64 --prefix-symbols=${PATH_PREFIX} ./${SOURCE_NAME_NO_PATH_NO_SUFFIX}.o "${SOURCE_NAME_NO_PATH_NO_SUFFIX}_x86.o" + COMMAND ${TPC_DISASSEMBLER_PATH} --triple tpc -d -j .text --no-show-raw-insn --no-leading-addr --mcpu=${deviceName} ${SOURCE_NAME_NO_PATH_NO_SUFFIX}.o > ${SOURCE_NAME_NO_PATH_NO_SUFFIX}.tpcasm) + list(APPEND OBJ_LIST "${RELATIVE_DIRECTORY}/${SOURCE_NAME_NO_PATH_NO_SUFFIX}_x86.o") endforeach() + + add_library(${deviceName} STATIC ${OBJ_LIST}) + set_target_properties(${deviceName} PROPERTIES LINKER_LANGUAGE C) + target_include_directories(${deviceName} PRIVATE ${TPC_HEADERS}) + target_link_libraries(${TPC_PERF_TARGET} ${deviceName}) endfunction(CompileTPCCWithClang) CompileTPCCWithClang("${TPC_C_GAUDI_SOURCES_TO_EMBED}" "${TPC_GAUDI_HEADERS}" gaudi) +CompileTPCCWithClang("${TPC_C_GAUDI2_SOURCES_TO_EMBED}" "${TPC_GAUDI_HEADERS}" gaudi2) diff --git a/tpc_kernels_db/src/entry_points.cpp b/tpc_kernels_db/src/entry_points.cpp index fe32466..6fbe92d 100644 --- a/tpc_kernels_db/src/entry_points.cpp +++ b/tpc_kernels_db/src/entry_points.cpp @@ -53,13 +53,27 @@ gcapi::GlueCodeReturn_t GetKernelNames(_OUT_ char** names, Relu6BwdBF16Instance.GetKernelName(names[GAUDI_KERNEL_RELU6_BWD_BF16], Relu6All::bwd_bf16); } - + if (kernelCount != nullptr) { - // currently the library support 8 kernel. + // currently the library supports GAUDI_KERNEL_MAX_EXAMPLE_KERNEL kernels *kernelCount = GAUDI_KERNEL_MAX_EXAMPLE_KERNEL; } } + else if (deviceId == gcapi::DEVICE_ID_GAUDI2) + { + if (names != nullptr ) + { + CustomdivFwdF32 customdivFwdF32Instance; + customdivFwdF32Instance.GetKernelName(names[0]); + } + + if (kernelCount != nullptr) + { + // currently the library supports 1 kernel + *kernelCount = 1; + } + } else { if (kernelCount != nullptr) diff --git a/tpc_kernels_db/src/gaudi_src/batch_norm_f32.cpp b/tpc_kernels_db/src/gaudi_src/batch_norm_f32.cpp index 081c84a..dd1945f 100644 --- a/tpc_kernels_db/src/gaudi_src/batch_norm_f32.cpp +++ b/tpc_kernels_db/src/gaudi_src/batch_norm_f32.cpp @@ -6,8 +6,8 @@ */ #include "batch_norm_f32.hpp" -extern unsigned char _binary___batch_norm_fwd_f32_o_start; -extern unsigned char _binary___batch_norm_fwd_f32_o_end; +extern unsigned char _kernels_gaudi_binary___batch_norm_fwd_f32_o_start; +extern unsigned char _kernels_gaudi_binary___batch_norm_fwd_f32_o_end; gcapi::GlueCodeReturn_t BatchNormF32::GetKernelName( char kernelName [gcapi::MAX_NODE_NAME]) @@ -231,7 +231,7 @@ gcapi::GlueCodeReturn_t BatchNormF32::GetGcDefinitions( /************************************************************************************* * Stage V - Load ISA into the descriptor. **************************************************************************************/ - unsigned IsaSize = (&_binary___batch_norm_fwd_f32_o_end - &_binary___batch_norm_fwd_f32_o_start); + unsigned IsaSize = (&_kernels_gaudi_binary___batch_norm_fwd_f32_o_end - &_kernels_gaudi_binary___batch_norm_fwd_f32_o_start); unsigned givenBinarySize = out_defs->elfSize; out_defs->elfSize = IsaSize; @@ -239,7 +239,7 @@ gcapi::GlueCodeReturn_t BatchNormF32::GetGcDefinitions( { // copy binary out memcpy (out_defs->kernelElf , - &_binary___batch_norm_fwd_f32_o_start, + &_kernels_gaudi_binary___batch_norm_fwd_f32_o_start, IsaSize); } else diff --git a/tpc_kernels_db/src/gaudi_src/cast_gaudi.cpp b/tpc_kernels_db/src/gaudi_src/cast_gaudi.cpp index a7cc045..2d59b76 100644 --- a/tpc_kernels_db/src/gaudi_src/cast_gaudi.cpp +++ b/tpc_kernels_db/src/gaudi_src/cast_gaudi.cpp @@ -12,10 +12,10 @@ #include "cast_gaudi.hpp" -extern unsigned char _binary___cast_bf16_to_f32_o_start; -extern unsigned char _binary___cast_bf16_to_f32_o_end; -extern unsigned char _binary___cast_f32_to_bf16_o_start; -extern unsigned char _binary___cast_f32_to_bf16_o_end; +extern unsigned char _kernels_gaudi_binary___cast_bf16_to_f32_o_start; +extern unsigned char _kernels_gaudi_binary___cast_bf16_to_f32_o_end; +extern unsigned char _kernels_gaudi_binary___cast_f32_to_bf16_o_start; +extern unsigned char _kernels_gaudi_binary___cast_f32_to_bf16_o_end; gcapi::GlueCodeReturn_t CastGaudi::GetKernelName( char kernelName [gcapi::MAX_NODE_NAME], @@ -159,10 +159,10 @@ gcapi::GlueCodeReturn_t CastGaudi::GetGcDefinitions( /************************************************************************************* * Stage V - Load ISA into the descriptor. **************************************************************************************/ - unsigned IsaSize = (&_binary___cast_bf16_to_f32_o_end - &_binary___cast_bf16_to_f32_o_start); + unsigned IsaSize = (&_kernels_gaudi_binary___cast_bf16_to_f32_o_end - &_kernels_gaudi_binary___cast_bf16_to_f32_o_start); if (m_mode == 1) { - IsaSize = (&_binary___cast_f32_to_bf16_o_end - &_binary___cast_f32_to_bf16_o_start); + IsaSize = (&_kernels_gaudi_binary___cast_f32_to_bf16_o_end - &_kernels_gaudi_binary___cast_f32_to_bf16_o_start); } unsigned givenBinarySize = out_defs->elfSize; out_defs->elfSize = IsaSize; @@ -173,14 +173,14 @@ gcapi::GlueCodeReturn_t CastGaudi::GetGcDefinitions( { // copy binary out memcpy (out_defs->kernelElf , - &_binary___cast_bf16_to_f32_o_start, + &_kernels_gaudi_binary___cast_bf16_to_f32_o_start, IsaSize); } else { // copy binary out memcpy (out_defs->kernelElf , - &_binary___cast_f32_to_bf16_o_start, + &_kernels_gaudi_binary___cast_f32_to_bf16_o_start, IsaSize); } } diff --git a/tpc_kernels_db/src/gaudi_src/customdiv_fwd_f32.cpp b/tpc_kernels_db/src/gaudi_src/customdiv_fwd_f32.cpp index b9d0c51..086ff86 100644 --- a/tpc_kernels_db/src/gaudi_src/customdiv_fwd_f32.cpp +++ b/tpc_kernels_db/src/gaudi_src/customdiv_fwd_f32.cpp @@ -7,9 +7,16 @@ #include #include "customdiv_fwd_f32.hpp" +#define CUSTOM_DIV_START _kernels_gaudi_binary___customdiv_fwd_f32_o_start +#define CUSTOM_DIV_END _kernels_gaudi_binary___customdiv_fwd_f32_o_end + +extern unsigned char CUSTOM_DIV_START; +extern unsigned char CUSTOM_DIV_END; + +extern unsigned char _kernels_gaudi2_binary___customdiv_fwd_f32_o_start; +extern unsigned char _kernels_gaudi2_binary___customdiv_fwd_f32_o_end; + -extern unsigned char _binary___customdiv_fwd_f32_o_start; -extern unsigned char _binary___customdiv_fwd_f32_o_end; gcapi::GlueCodeReturn_t CustomdivFwdF32::GetKernelName( char kernelName [gcapi::MAX_NODE_NAME]) @@ -138,15 +145,35 @@ gcapi::GlueCodeReturn_t CustomdivFwdF32::GetGcDefinitions( /************************************************************************************* * Stage V - Load ISA into the descriptor. **************************************************************************************/ - unsigned IsaSize = (&_binary___customdiv_fwd_f32_o_end - &_binary___customdiv_fwd_f32_o_start); + + unsigned char* pStart = nullptr; + unsigned char* pEnd = nullptr; + + switch(params->deviceId) + { + case gcapi::DEVICE_ID_GAUDI: + { + pStart = &CUSTOM_DIV_START; + pEnd = &CUSTOM_DIV_END; + break; + } + case gcapi::DEVICE_ID_GAUDI2: + { + pStart = &_kernels_gaudi2_binary___customdiv_fwd_f32_o_start; + pEnd = &_kernels_gaudi2_binary___customdiv_fwd_f32_o_end; + break; + } + default: + return gcapi::GLUE_FAILED; + } + + unsigned IsaSize = (pEnd - pStart); unsigned givenBinarySize = kernel->elfSize; kernel->elfSize = IsaSize; if (givenBinarySize >= IsaSize) { - memcpy (kernel->kernelElf , - &_binary___customdiv_fwd_f32_o_start, - IsaSize); + memcpy (kernel->kernelElf, pStart, IsaSize); } else { diff --git a/tpc_kernels_db/src/gaudi_src/filter_fwd_2d_bf16.cpp b/tpc_kernels_db/src/gaudi_src/filter_fwd_2d_bf16.cpp index 3ddb1d9..a48f769 100644 --- a/tpc_kernels_db/src/gaudi_src/filter_fwd_2d_bf16.cpp +++ b/tpc_kernels_db/src/gaudi_src/filter_fwd_2d_bf16.cpp @@ -10,8 +10,8 @@ #include "filter_fwd_2d_bf16.hpp" -extern unsigned char _binary___filter_fwd_2d_bf16_o_start; -extern unsigned char _binary___filter_fwd_2d_bf16_o_end; +extern unsigned char _kernels_gaudi_binary___filter_fwd_2d_bf16_o_start; +extern unsigned char _kernels_gaudi_binary___filter_fwd_2d_bf16_o_end; gcapi::GlueCodeReturn_t FilterFwd2dBF16::GetKernelName( char kernelName [gcapi::MAX_NODE_NAME]) @@ -111,7 +111,7 @@ gcapi::GlueCodeReturn_t FilterFwd2dBF16::GetGcDefinitions( /************************************************************************************* * Stage V - Load ISA into the descriptor. **************************************************************************************/ - unsigned IsaSize = (&_binary___filter_fwd_2d_bf16_o_end - &_binary___filter_fwd_2d_bf16_o_start); + unsigned IsaSize = (&_kernels_gaudi_binary___filter_fwd_2d_bf16_o_end - &_kernels_gaudi_binary___filter_fwd_2d_bf16_o_start); unsigned givenBinarySize = out_defs->elfSize; out_defs->elfSize = IsaSize; @@ -119,7 +119,7 @@ gcapi::GlueCodeReturn_t FilterFwd2dBF16::GetGcDefinitions( { // copy binary out memcpy (out_defs->kernelElf, - &_binary___filter_fwd_2d_bf16_o_start, + &_kernels_gaudi_binary___filter_fwd_2d_bf16_o_start, IsaSize); } else diff --git a/tpc_kernels_db/src/gaudi_src/leakyrelu_f32_gaudi.cpp b/tpc_kernels_db/src/gaudi_src/leakyrelu_f32_gaudi.cpp index ca689b2..a8a50c9 100644 --- a/tpc_kernels_db/src/gaudi_src/leakyrelu_f32_gaudi.cpp +++ b/tpc_kernels_db/src/gaudi_src/leakyrelu_f32_gaudi.cpp @@ -8,8 +8,8 @@ #include "leakyrelu_f32_gaudi.hpp" -extern unsigned char _binary___leakyrelu_f32_gaudi_o_start; -extern unsigned char _binary___leakyrelu_f32_gaudi_o_end; +extern unsigned char _kernels_gaudi_binary___leakyrelu_f32_gaudi_o_start; +extern unsigned char _kernels_gaudi_binary___leakyrelu_f32_gaudi_o_end; gcapi::GlueCodeReturn_t LeakyReluF32Gaudi::GetKernelName( char kernelName [gcapi::MAX_NODE_NAME]) @@ -148,14 +148,14 @@ gcapi::GlueCodeReturn_t LeakyReluF32Gaudi::GetGcDefinitions( /************************************************************************************* * Stage V - Load ISA into the descriptor. **************************************************************************************/ - unsigned IsaSize = (&_binary___leakyrelu_f32_gaudi_o_end - &_binary___leakyrelu_f32_gaudi_o_start); + unsigned IsaSize = (&_kernels_gaudi_binary___leakyrelu_f32_gaudi_o_end - &_kernels_gaudi_binary___leakyrelu_f32_gaudi_o_start); unsigned givenBinarySize = kernel->elfSize; kernel->elfSize = IsaSize; if (givenBinarySize >= IsaSize) { memcpy (kernel->kernelElf , - &_binary___leakyrelu_f32_gaudi_o_start, + &_kernels_gaudi_binary___leakyrelu_f32_gaudi_o_start, IsaSize); } else diff --git a/tpc_kernels_db/src/gaudi_src/relu6_all.cpp b/tpc_kernels_db/src/gaudi_src/relu6_all.cpp index 87b876f..c880b89 100644 --- a/tpc_kernels_db/src/gaudi_src/relu6_all.cpp +++ b/tpc_kernels_db/src/gaudi_src/relu6_all.cpp @@ -7,14 +7,14 @@ #include #include "relu6_all.hpp" -extern unsigned char _binary___relu6_fwd_f32_o_start; -extern unsigned char _binary___relu6_fwd_f32_o_end; -extern unsigned char _binary___relu6_bwd_f32_o_start; -extern unsigned char _binary___relu6_bwd_f32_o_end; -extern unsigned char _binary___relu6_fwd_bf16_o_start; -extern unsigned char _binary___relu6_fwd_bf16_o_end; -extern unsigned char _binary___relu6_bwd_bf16_o_start; -extern unsigned char _binary___relu6_bwd_bf16_o_end; +extern unsigned char _kernels_gaudi_binary___relu6_fwd_f32_o_start; +extern unsigned char _kernels_gaudi_binary___relu6_fwd_f32_o_end; +extern unsigned char _kernels_gaudi_binary___relu6_bwd_f32_o_start; +extern unsigned char _kernels_gaudi_binary___relu6_bwd_f32_o_end; +extern unsigned char _kernels_gaudi_binary___relu6_fwd_bf16_o_start; +extern unsigned char _kernels_gaudi_binary___relu6_fwd_bf16_o_end; +extern unsigned char _kernels_gaudi_binary___relu6_bwd_bf16_o_start; +extern unsigned char _kernels_gaudi_binary___relu6_bwd_bf16_o_end; gcapi::GlueCodeReturn_t Relu6All::GetKernelName( char kernelName [gcapi::MAX_NODE_NAME], Relu6_mode_t mode) @@ -212,25 +212,25 @@ gcapi::GlueCodeReturn_t Relu6All::GetGcDefinitions( /************************************************************************************* * Stage V - Load ISA into the descriptor. **************************************************************************************/ - unsigned IsaSize = (&_binary___relu6_fwd_f32_o_end - &_binary___relu6_fwd_f32_o_start); + unsigned IsaSize = (&_kernels_gaudi_binary___relu6_fwd_f32_o_end - &_kernels_gaudi_binary___relu6_fwd_f32_o_start); unsigned char *binary_kernel; switch (m_mode) { case fwd_f32: - IsaSize = (&_binary___relu6_fwd_f32_o_end - &_binary___relu6_fwd_f32_o_start); - binary_kernel = &_binary___relu6_fwd_f32_o_start; + IsaSize = (&_kernels_gaudi_binary___relu6_fwd_f32_o_end - &_kernels_gaudi_binary___relu6_fwd_f32_o_start); + binary_kernel = &_kernels_gaudi_binary___relu6_fwd_f32_o_start; break; case bwd_f32: - IsaSize = (&_binary___relu6_bwd_f32_o_end - &_binary___relu6_bwd_f32_o_start); - binary_kernel = &_binary___relu6_bwd_f32_o_start; + IsaSize = (&_kernels_gaudi_binary___relu6_bwd_f32_o_end - &_kernels_gaudi_binary___relu6_bwd_f32_o_start); + binary_kernel = &_kernels_gaudi_binary___relu6_bwd_f32_o_start; break; case fwd_bf16: - IsaSize = (&_binary___relu6_fwd_bf16_o_end - &_binary___relu6_fwd_bf16_o_start); - binary_kernel = &_binary___relu6_fwd_bf16_o_start; + IsaSize = (&_kernels_gaudi_binary___relu6_fwd_bf16_o_end - &_kernels_gaudi_binary___relu6_fwd_bf16_o_start); + binary_kernel = &_kernels_gaudi_binary___relu6_fwd_bf16_o_start; break; case bwd_bf16: - IsaSize = (&_binary___relu6_bwd_bf16_o_end - &_binary___relu6_bwd_bf16_o_start); - binary_kernel = &_binary___relu6_bwd_bf16_o_start; + IsaSize = (&_kernels_gaudi_binary___relu6_bwd_bf16_o_end - &_kernels_gaudi_binary___relu6_bwd_bf16_o_start); + binary_kernel = &_kernels_gaudi_binary___relu6_bwd_bf16_o_start; break; default: break; diff --git a/tpc_kernels_db/src/gaudi_src/softmax_bf16.cpp b/tpc_kernels_db/src/gaudi_src/softmax_bf16.cpp index 94ea007..e1c5815 100644 --- a/tpc_kernels_db/src/gaudi_src/softmax_bf16.cpp +++ b/tpc_kernels_db/src/gaudi_src/softmax_bf16.cpp @@ -6,10 +6,10 @@ */ #include "softmax_bf16.hpp" -extern unsigned char _binary___softmax_fcd_bf16_o_start; -extern unsigned char _binary___softmax_fcd_bf16_o_end; -extern unsigned char _binary___softmax_non_fcd_bf16_o_start; -extern unsigned char _binary___softmax_non_fcd_bf16_o_end; +extern unsigned char _kernels_gaudi_binary___softmax_fcd_bf16_o_start; +extern unsigned char _kernels_gaudi_binary___softmax_fcd_bf16_o_end; +extern unsigned char _kernels_gaudi_binary___softmax_non_fcd_bf16_o_start; +extern unsigned char _kernels_gaudi_binary___softmax_non_fcd_bf16_o_end; gcapi::GlueCodeReturn_t SoftMaxBF16::GetKernelNameFcd( char kernelName [gcapi::MAX_NODE_NAME]) @@ -192,8 +192,8 @@ gcapi::GlueCodeReturn_t SoftMaxBF16::GetGcDefinitions( /************************************************************************************* * Stage V - Load ISA into the descriptor. **************************************************************************************/ - unsigned IsaSize1 = (&_binary___softmax_fcd_bf16_o_end - &_binary___softmax_fcd_bf16_o_start); - unsigned IsaSize2 = (&_binary___softmax_non_fcd_bf16_o_end - &_binary___softmax_non_fcd_bf16_o_start); + unsigned IsaSize1 = (&_kernels_gaudi_binary___softmax_fcd_bf16_o_end - &_kernels_gaudi_binary___softmax_fcd_bf16_o_start); + unsigned IsaSize2 = (&_kernels_gaudi_binary___softmax_non_fcd_bf16_o_end - &_kernels_gaudi_binary___softmax_non_fcd_bf16_o_start); unsigned givenBinarySize = kernel->elfSize; unsigned IsaSize = def->axis==0? IsaSize1:IsaSize2; @@ -205,14 +205,14 @@ gcapi::GlueCodeReturn_t SoftMaxBF16::GetGcDefinitions( { // copy binary out memcpy (kernel->kernelElf , - &_binary___softmax_fcd_bf16_o_start, + &_kernels_gaudi_binary___softmax_fcd_bf16_o_start, IsaSize); } else { // copy binary out memcpy (kernel->kernelElf , - &_binary___softmax_non_fcd_bf16_o_start, + &_kernels_gaudi_binary___softmax_non_fcd_bf16_o_start, IsaSize); } } diff --git a/tpc_kernels_db/src/gaudi_src/sparse_lengths_sum_bf16.cpp b/tpc_kernels_db/src/gaudi_src/sparse_lengths_sum_bf16.cpp index a586de4..eeeb717 100644 --- a/tpc_kernels_db/src/gaudi_src/sparse_lengths_sum_bf16.cpp +++ b/tpc_kernels_db/src/gaudi_src/sparse_lengths_sum_bf16.cpp @@ -6,8 +6,8 @@ */ #include "sparse_lengths_sum_bf16.hpp" -extern unsigned char _binary___sparse_lengths_sum_bf16_2D_f32_embed_o_start; -extern unsigned char _binary___sparse_lengths_sum_bf16_2D_f32_embed_o_end; +extern unsigned char _kernels_gaudi_binary___sparse_lengths_sum_bf16_2D_f32_embed_o_start; +extern unsigned char _kernels_gaudi_binary___sparse_lengths_sum_bf16_2D_f32_embed_o_end; gcapi::GlueCodeReturn_t SparseLengthsSumBF16::GetKernelName( char kernelName [gcapi::MAX_NODE_NAME]) @@ -145,7 +145,7 @@ gcapi::GlueCodeReturn_t SparseLengthsSumBF16::GetGcDefinitions( /************************************************************************************* * Stage V - Load ISA into the descriptor. **************************************************************************************/ - unsigned IsaSize = (&_binary___sparse_lengths_sum_bf16_2D_f32_embed_o_end - &_binary___sparse_lengths_sum_bf16_2D_f32_embed_o_start); + unsigned IsaSize = (&_kernels_gaudi_binary___sparse_lengths_sum_bf16_2D_f32_embed_o_end - &_kernels_gaudi_binary___sparse_lengths_sum_bf16_2D_f32_embed_o_start); unsigned givenBinarySize = kernel->elfSize; kernel->elfSize = IsaSize; @@ -153,7 +153,7 @@ gcapi::GlueCodeReturn_t SparseLengthsSumBF16::GetGcDefinitions( { // copy binary out memcpy (kernel->kernelElf , - &_binary___sparse_lengths_sum_bf16_2D_f32_embed_o_start, + &_kernels_gaudi_binary___sparse_lengths_sum_bf16_2D_f32_embed_o_start, IsaSize); } else