Cadence verilog compiler doesn't seem to like the parameter declared after usage

[Sundarapandian]

Cadence verilog compiler causes the following error

file: /tst/ibex_soc/data/ibex_soc_lib/ibex_super_system/rtl/system/dm_top.sv
  input  logic [BusWidth-1:0]   slave_addr_i,
                       |
xmvlog: *E,UNDIDN (/tst/ibex_soc/data/ibex_soc_lib/ibex_super_system/rtl/system/dm_top.sv,32|23): 'BusWidth': undeclared identifier [12.5(IEEE)].
  input  logic [BusWidth/8-1:0] slave_be_i,
                       |
xmvlog: *E,UNDIDN (/tst/ibex_soc/data/ibex_soc_lib/ibex_super_system/rtl/system/dm_top.sv,33|23): 'BusWidth': undeclared identifier [12.5(IEEE)].
  input  logic [BusWidth-1:0]   slave_wdata_i,
                       |
xmvlog: *E,UNDIDN (/tst/ibex_soc/data/ibex_soc_lib/ibex_super_system/rtl/system/dm_top.sv,34|23): 'BusWidth': undeclared identifier [12.5(IEEE)].
  output logic [BusWidth-1:0]   slave_rdata_o,
                       |
xmvlog: *E,UNDIDN (/tst/ibex_soc/data/ibex_soc_lib/ibex_super_system/rtl/system/dm_top.sv,35|23): 'BusWidth': undeclared identifier [12.5(IEEE)].
  output logic [BusWidth-1:0]   master_add_o,
                       |
xmvlog: *E,UNDIDN (/tst/ibex_soc/data/ibex_soc_lib/ibex_super_system/rtl/system/dm_top.sv,39|23): 'BusWidth': undeclared identifier [12.5(IEEE)].
  output logic [BusWidth-1:0]   master_wdata_o,
                       |
xmvlog: *E,UNDIDN (/tst/ibex_soc/data/ibex_soc_lib/ibex_super_system/rtl/system/dm_top.sv,41|23): 'BusWidth': undeclared identifier [12.5(IEEE)].
  output logic [BusWidth/8-1:0] master_be_o,
                       |
xmvlog: *E,UNDIDN (/tst/ibex_soc/data/ibex_soc_lib/ibex_super_system/rtl/system/dm_top.sv,42|23): 'BusWidth': undeclared identifier [12.5(IEEE)].
  input  logic [BusWidth-1:0]   master_r_rdata_i
                       |
xmvlog: *E,UNDIDN (/tst/ibex_soc/data/ibex_soc_lib/ibex_super_system/rtl/system/dm_top.sv,45|23): 'BusWidth': undeclared identifier [12.5(IEEE)].

The following seems to fix it

diff --git a/rtl/system/dm_top.sv b/rtl/system/dm_top.sv
index 23e3ce6..4d26daa 100644
--- a/rtl/system/dm_top.sv
+++ b/rtl/system/dm_top.sv
@@ -14,7 +14,8 @@
 
 module dm_top #(
   parameter int              NrHarts = 1,
-  parameter logic [31:0]     IdcodeValue = 32'h 0000_0001
+  parameter logic [31:0]     IdcodeValue = 32'h 0000_0001,
+  parameter int              BusWidth = 32
 ) (
   input  logic               clk_i,       // clock
   input  logic               rst_ni,      // asynchronous reset active low, connect PoR
@@ -47,7 +48,7 @@ module dm_top #(
 
   `ASSERT_INIT(paramCheckNrHarts, NrHarts > 0)
 
-  localparam int BusWidth = 32;
+//  localparam int BusWidth = 32;
   // all harts have contiguous IDs
   localparam logic [NrHarts-1:0] SelectableHarts = {NrHarts{1'b1}};

[Sundarapandian]

Looks like it was already fixed in the source repo "https://github.com/pulp-platform/riscv-dbg/blob/master/src/dm_top.sv"

[GregAC]

Thanks for letting me know. I've had a go at revendoring the latest version of riscv-dbg but due to some changes the patches I need on top of it (principally to switch out some primitives to use OpenTitan ones rather than PULP ones) won't apply cleanly. It's a bit of work (potentially involving extending the OpenTitan primitives) to fix this which I won't do right away. I'll leave this issue open to track.