Does ddisasm work for Risc-V binaries?

[SaiVK]

Hello Everyone
Can ddisasm be applied to Risc-V binaries to generate relocatable-assembly code and perform CFG analysis etc...?

Thanking you
Sai

[eschulte]

We do not have any support for Risc-V binaries yet.

But we are open to contributions and Capstone does support Risc-V so the external dependency for Risc-V is satisfied.

[SaiVK]

Hello @eschulte
Is there any docs or any pointers to extend ddisasm? Also, does GTIRB support Risc-V backend?

Thanking you
Sai

[eschulte]

The changes on the GTIRB side should be minimal, basically just adding RISC-V to the ISA enum in our protobuf module definition and to the corresponding ISA enums in our Python, Java, and Common Lisp APIs. That part should be trivial.

On the DDisasm side I'd look under src/datalog/arch and src/gtirb-decoder/arch and then mimic what you see for another ISA, e.g. arm64. We try to keep the ddisasm code largely segregated by ISA so each ISA's implementation is in its own file. Probably @kwarrick would have more advice here.

Also, if you're considering this (which would be awesome!), do be aware of our code of conduct and the fact that we ask all contributors to DDisasm to sign our contributor license agreement which give GrammaTech rights to your contributions to DDisasm so that we can maintain our GPL.

[SaiVK]

Thank you @eschulte. I will probably start working on some small binary rewriting examples w.r.t x86 backend to get accustomed to ddisasm. And then try looking into RiscV backend.

-Sai

[aeflores]

@SaiVK you will probably want to extend gtirb-pprinter (https://github.com/grammatech/gtirb-pprinter) as well, so it can print RISC-V gtirb files. Similarly to ddisasm, you might want to look at how other ISAs are implemented there, such as ARM64 https://github.com/GrammaTech/gtirb-pprinter/blob/master/src/gtirb_pprinter/Arm64PrettyPrinter.cpp to get an idea of what is needed.

[SaiVK]

Thanks, @aeflores for the pointers. I will look into it.

-Sai