Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

build and run our system in software simulation using non-Verilator hardware simulators #89

Open
3 tasks
kiniry opened this issue Feb 18, 2022 · 0 comments
Labels
ENHANCEMENT New feature or request hardware Q/A Quality assurance issue; validation, testing, and formal assurance. Someday Issues that are not required by our current contract, but we'd like to attend to someday.

Comments

@kiniry
Copy link
Member

kiniry commented Feb 18, 2022

In particular, it would be great to demonstrate portability of our SoC and methodology across:

  1. A standard commercial simulator that is used mainly for ASIC design like Siemens EDA's ModelSim or Questa simulators, Synopsys VCS, and Cadence's NC-Verilog.
  2. A standard commercial simulator that is used mainly for FPGA-based designs like Xilinx's VSim.
  3. An open source physics simulator like Xyce and LTspice.

Note that this work is not part of our SoW, it is just a nice to have later, and may get funded by other projects.

@kiniry kiniry added ENHANCEMENT New feature or request hardware Q/A Quality assurance issue; validation, testing, and formal assurance. labels Feb 18, 2022
@kiniry kiniry added the Someday Issues that are not required by our current contract, but we'd like to attend to someday. label Apr 18, 2022
@kiniry kiniry added this to the Second Polishing Release milestone May 22, 2023
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
ENHANCEMENT New feature or request hardware Q/A Quality assurance issue; validation, testing, and formal assurance. Someday Issues that are not required by our current contract, but we'd like to attend to someday.
Projects
None yet
Development

No branches or pull requests

1 participant