Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

get all NERV SoC smoketests (single core and three core) up and running reliably #55

Open
2 tasks
kiniry opened this issue Jan 5, 2022 · 5 comments
Open
2 tasks
Assignees
Labels
BLOCKED This issue is blocked on some other task, issue, merge request, or person. BUG Something isn't working build system Issues that relate to our build system, both on development systems as well as in continuous integra feature model hardware Lando/Lobot Issues related to our Lando or Lobot specifications. Someday Issues that are not required by our current contract, but we'd like to attend to someday. WiP
Milestone

Comments

@kiniry
Copy link
Member

kiniry commented Jan 5, 2022

  • in the Bluespec simulator and
  • via the Verilator backend build
@kiniry kiniry added BUG Something isn't working hardware WiP BLOCKED This issue is blocked on some other task, issue, merge request, or person. build system Issues that relate to our build system, both on development systems as well as in continuous integra feature model Lando/Lobot Issues related to our Lando or Lobot specifications. labels Jan 5, 2022
@kiniry
Copy link
Member Author

kiniry commented Apr 18, 2022

What is the status on this @podhrmic? Do they all run, but only in Verilator or a proprietary simulator?

@podhrmic
Copy link
Collaborator

I am pretty sure Bluesim doesn't simulate imported verilog files (such as Nerv.sv). The SoC is running self-tests in Verilator. Are there any other tests that should be running?

@kiniry
Copy link
Member Author

kiniry commented Apr 20, 2022

You are correct about Bluesim. The only way we could support it down the road is if we were using a full BSV-based SoC.

Wrt the Verilator question, I was just wondering if you had attempted to run the emitted Verilog SoC in any Verilog simulator besides Verilator.

And finally, I just wanted to double-check that all existing tests in the harness as well as self-test were passing.

@podhrmic
Copy link
Collaborator

Wrt the Verilator question, I was just wondering if you had attempted to run the emitted Verilog SoC in any Verilog simulator besides Verilator.

Only Verilator. IIRC iverilog doesn't properly support SystemVerilog files (nerv.sv), another issue might be the C function imports. Is there any other simulator that we should be trying?

And finally, I just wanted to double-check that all existing tests in the harness as well as self-test were passing.

I am doing a pass on it today, so I will report back. We had the self-tests passing, the goal is to run the scenario tests as well (identical to the SW only simulation)

@kiniry
Copy link
Member Author

kiniry commented Apr 20, 2022

Wrt the Verilator question, I was just wondering if you had attempted to run the emitted Verilog SoC in any Verilog simulator besides Verilator.

Only Verilator. IIRC iverilog doesn't properly support SystemVerilog files (nerv.sv), another issue might be the C function imports. Is there any other simulator that we should be trying?

There are two commercial simulators we commonly have available to us: Xilinx's XSim and ISim and Siemens EDA's ModelSim and Questa simulators. We also used to have access to the Cadence and Synopsys simulators, but those licenses are now at Niobium. I have to renew our Siemens EDA licenses, so the only thing we have in-hand right now is Xilinx's.

The other simulator we have/use is, of course, Berkeley's FireSim, which we used for FETT and runs in AWS.

And finally, I just wanted to double-check that all existing tests in the harness as well as self-test were passing.

I am doing a pass on it today, so I will report back. We had the self-tests passing, the goal is to run the scenario tests as well (identical to the SW only simulation)

Exactly. Thanks for the update.

@kiniry kiniry added the Someday Issues that are not required by our current contract, but we'd like to attend to someday. label Oct 28, 2022
@kiniry kiniry removed this from the Task 2: Validation and Verification milestone Oct 28, 2022
@kiniry kiniry added this to the SoC milestone May 22, 2023
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
BLOCKED This issue is blocked on some other task, issue, merge request, or person. BUG Something isn't working build system Issues that relate to our build system, both on development systems as well as in continuous integra feature model hardware Lando/Lobot Issues related to our Lando or Lobot specifications. Someday Issues that are not required by our current contract, but we'd like to attend to someday. WiP
Projects
None yet
Development

No branches or pull requests

2 participants